mirror of
https://github.com/cloud-hypervisor/cloud-hypervisor.git
synced 2026-08-05 02:19:16 +00:00
8b67298ad8
This commit moves the code that generates the DSDT data for the PCI bus into PciSegment making no functional changes to the generated AML. Signed-off-by: Rob Bradford <robert.bradford@intel.com>
399 lines
14 KiB
Rust
399 lines
14 KiB
Rust
// Portions Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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//
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// Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE-BSD-3-Clause file.
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//
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// Copyright © 2019 - 2021 Intel Corporation
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//
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// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
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//
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use crate::device_manager::{AddressManager, DeviceManagerError, DeviceManagerResult};
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#[cfg(feature = "acpi")]
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use acpi_tables::aml::{self, Aml};
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use arch::layout;
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use pci::{DeviceRelocation, PciBus, PciConfigMmio, PciRoot};
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#[cfg(target_arch = "x86_64")]
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use pci::{PciConfigIo, PCI_CONFIG_IO_PORT, PCI_CONFIG_IO_PORT_SIZE};
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use std::sync::{Arc, Mutex};
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#[cfg(feature = "acpi")]
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use uuid::Uuid;
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use vm_device::BusDevice;
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pub(crate) struct PciSegment {
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id: u16,
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pub(crate) pci_bus: Arc<Mutex<PciBus>>,
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pub(crate) pci_config_mmio: Arc<Mutex<PciConfigMmio>>,
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mmio_config_address: u64,
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#[cfg(target_arch = "x86_64")]
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pub(crate) pci_config_io: Option<Arc<Mutex<PciConfigIo>>>,
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// Bitmap of PCI devices to hotplug.
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pub(crate) pci_devices_up: u32,
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// Bitmap of PCI devices to hotunplug.
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pub(crate) pci_devices_down: u32,
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// List of allocated IRQs for each PCI slot.
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pub(crate) pci_irq_slots: [u8; 32],
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// Device memory covered by this segment
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pub(crate) start_of_device_area: u64,
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pub(crate) end_of_device_area: u64,
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}
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impl PciSegment {
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pub(crate) fn new_default_segment(
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address_manager: &Arc<AddressManager>,
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start_of_device_area: u64,
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end_of_device_area: u64,
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) -> DeviceManagerResult<PciSegment> {
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let pci_root = PciRoot::new(None);
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let pci_bus = Arc::new(Mutex::new(PciBus::new(
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pci_root,
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Arc::clone(address_manager) as Arc<dyn DeviceRelocation>,
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)));
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let pci_config_mmio = Arc::new(Mutex::new(PciConfigMmio::new(Arc::clone(&pci_bus))));
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address_manager
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.mmio_bus
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.insert(
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Arc::clone(&pci_config_mmio) as Arc<Mutex<dyn BusDevice>>,
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arch::layout::PCI_MMCONFIG_START.0,
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arch::layout::PCI_MMCONFIG_SIZE,
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)
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.map_err(DeviceManagerError::BusError)?;
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#[cfg(target_arch = "x86_64")]
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let pci_config_io = Arc::new(Mutex::new(PciConfigIo::new(Arc::clone(&pci_bus))));
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#[cfg(target_arch = "x86_64")]
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address_manager
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.io_bus
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.insert(
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pci_config_io.clone(),
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PCI_CONFIG_IO_PORT,
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PCI_CONFIG_IO_PORT_SIZE,
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)
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.map_err(DeviceManagerError::BusError)?;
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let mut segment = PciSegment {
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id: 0,
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pci_bus,
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pci_config_mmio,
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mmio_config_address: arch::layout::PCI_MMCONFIG_START.0,
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pci_devices_up: 0,
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pci_devices_down: 0,
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pci_irq_slots: [0; 32],
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#[cfg(target_arch = "x86_64")]
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pci_config_io: Some(pci_config_io),
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start_of_device_area,
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end_of_device_area,
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};
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// Reserve some IRQs for PCI devices in case they need to support INTx.
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segment.reserve_legacy_interrupts_for_pci_devices(address_manager)?;
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info!(
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"Adding PCI segment: id={}, PCI MMIO config address: 0x{:x}, device area [0x{:x}-0x{:x}",
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segment.id, segment.mmio_config_address, segment.start_of_device_area, segment.end_of_device_area
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);
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Ok(segment)
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}
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pub(crate) fn next_device_bdf(&self) -> DeviceManagerResult<u32> {
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// We need to shift the device id since the 3 first bits
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// are dedicated to the PCI function, and we know we don't
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// do multifunction. Also, because we only support one PCI
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// bus, the bus 0, we don't need to add anything to the
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// global device ID.
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Ok(self
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.pci_bus
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.lock()
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.unwrap()
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.next_device_id()
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.map_err(DeviceManagerError::NextPciDeviceId)?
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<< 3)
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}
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fn reserve_legacy_interrupts_for_pci_devices(
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&mut self,
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address_manager: &Arc<AddressManager>,
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) -> DeviceManagerResult<()> {
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// Reserve 8 IRQs which will be shared across all PCI devices.
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let num_irqs = 8;
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let mut irqs: Vec<u8> = Vec::new();
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for _ in 0..num_irqs {
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irqs.push(
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address_manager
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.allocator
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.lock()
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.unwrap()
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.allocate_irq()
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.ok_or(DeviceManagerError::AllocateIrq)? as u8,
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);
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}
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// There are 32 devices on the PCI bus, let's assign them an IRQ.
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for i in 0..32 {
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self.pci_irq_slots[i] = irqs[(i % num_irqs) as usize];
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}
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Ok(())
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}
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}
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#[cfg(feature = "acpi")]
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struct PciDevSlot {
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device_id: u8,
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}
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#[cfg(feature = "acpi")]
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impl Aml for PciDevSlot {
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fn to_aml_bytes(&self) -> Vec<u8> {
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let sun = self.device_id;
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let adr: u32 = (self.device_id as u32) << 16;
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aml::Device::new(
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format!("S{:03}", self.device_id).as_str().into(),
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vec![
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&aml::Name::new("_SUN".into(), &sun),
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&aml::Name::new("_ADR".into(), &adr),
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&aml::Method::new(
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"_EJ0".into(),
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1,
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true,
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vec![&aml::MethodCall::new(
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"\\_SB_.PHPR.PCEJ".into(),
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vec![&aml::Path::new("_SUN")],
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)],
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),
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],
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)
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.to_aml_bytes()
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}
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}
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#[cfg(feature = "acpi")]
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struct PciDevSlotNotify {
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device_id: u8,
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}
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#[cfg(feature = "acpi")]
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impl Aml for PciDevSlotNotify {
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fn to_aml_bytes(&self) -> Vec<u8> {
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let device_id_mask: u32 = 1 << self.device_id;
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let object = aml::Path::new(&format!("S{:03}", self.device_id));
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let mut bytes = aml::And::new(&aml::Local(0), &aml::Arg(0), &device_id_mask).to_aml_bytes();
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bytes.extend_from_slice(
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&aml::If::new(
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&aml::Equal::new(&aml::Local(0), &device_id_mask),
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vec![&aml::Notify::new(&object, &aml::Arg(1))],
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)
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.to_aml_bytes(),
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);
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bytes
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}
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}
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#[cfg(feature = "acpi")]
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struct PciDevSlotMethods {}
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#[cfg(feature = "acpi")]
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impl Aml for PciDevSlotMethods {
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fn to_aml_bytes(&self) -> Vec<u8> {
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let mut device_notifies = Vec::new();
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for device_id in 0..32 {
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device_notifies.push(PciDevSlotNotify { device_id });
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}
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let mut device_notifies_refs: Vec<&dyn aml::Aml> = Vec::new();
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for device_notify in device_notifies.iter() {
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device_notifies_refs.push(device_notify);
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}
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let mut bytes =
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aml::Method::new("DVNT".into(), 2, true, device_notifies_refs).to_aml_bytes();
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bytes.extend_from_slice(
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&aml::Method::new(
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"PCNT".into(),
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0,
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true,
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vec![
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&aml::MethodCall::new(
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"DVNT".into(),
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vec![&aml::Path::new("\\_SB_.PHPR.PCIU"), &aml::ONE],
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),
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&aml::MethodCall::new(
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"DVNT".into(),
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vec![&aml::Path::new("\\_SB_.PHPR.PCID"), &3usize],
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),
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],
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)
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.to_aml_bytes(),
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);
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bytes
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}
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}
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#[cfg(feature = "acpi")]
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struct PciDsmMethod {}
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#[cfg(feature = "acpi")]
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impl Aml for PciDsmMethod {
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fn to_aml_bytes(&self) -> Vec<u8> {
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// Refer to ACPI spec v6.3 Ch 9.1.1 and PCI Firmware spec v3.3 Ch 4.6.1
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// _DSM (Device Specific Method), the following is the implementation in ASL.
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/*
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Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
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{
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If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
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{
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If ((Arg2 == Zero))
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{
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Return (Buffer (One) { 0x21 })
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}
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If ((Arg2 == 0x05))
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{
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Return (Zero)
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}
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}
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Return (Buffer (One) { 0x00 })
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}
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*/
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/*
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* As per ACPI v6.3 Ch 19.6.142, the UUID is required to be in mixed endian:
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* Among the fields of a UUID:
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* {d1 (8 digits)} - {d2 (4 digits)} - {d3 (4 digits)} - {d4 (16 digits)}
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* d1 ~ d3 need to be little endian, d4 be big endian.
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* See https://en.wikipedia.org/wiki/Universally_unique_identifier#Encoding .
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*/
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let uuid = Uuid::parse_str("E5C937D0-3553-4D7A-9117-EA4D19C3434D").unwrap();
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let (uuid_d1, uuid_d2, uuid_d3, uuid_d4) = uuid.as_fields();
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let mut uuid_buf = vec![];
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uuid_buf.extend(&uuid_d1.to_le_bytes());
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uuid_buf.extend(&uuid_d2.to_le_bytes());
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uuid_buf.extend(&uuid_d3.to_le_bytes());
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uuid_buf.extend(uuid_d4);
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aml::Method::new(
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"_DSM".into(),
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4,
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false,
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vec![
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&aml::If::new(
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&aml::Equal::new(&aml::Arg(0), &aml::Buffer::new(uuid_buf)),
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vec![
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&aml::If::new(
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&aml::Equal::new(&aml::Arg(2), &aml::ZERO),
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vec![&aml::Return::new(&aml::Buffer::new(vec![0x21]))],
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),
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&aml::If::new(
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&aml::Equal::new(&aml::Arg(2), &0x05u8),
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vec![&aml::Return::new(&aml::ZERO)],
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),
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],
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),
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&aml::Return::new(&aml::Buffer::new(vec![0])),
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],
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)
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.to_aml_bytes()
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}
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}
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#[cfg(feature = "acpi")]
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impl Aml for PciSegment {
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fn to_aml_bytes(&self) -> Vec<u8> {
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let mut pci_dsdt_inner_data: Vec<&dyn aml::Aml> = Vec::new();
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let hid = aml::Name::new("_HID".into(), &aml::EisaName::new("PNP0A08"));
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pci_dsdt_inner_data.push(&hid);
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let cid = aml::Name::new("_CID".into(), &aml::EisaName::new("PNP0A03"));
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pci_dsdt_inner_data.push(&cid);
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let adr = aml::Name::new("_ADR".into(), &aml::ZERO);
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pci_dsdt_inner_data.push(&adr);
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let seg = aml::Name::new("_SEG".into(), &aml::ZERO);
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pci_dsdt_inner_data.push(&seg);
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let uid = aml::Name::new("_UID".into(), &aml::ZERO);
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pci_dsdt_inner_data.push(&uid);
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let cca = aml::Name::new("_CCA".into(), &aml::ONE);
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pci_dsdt_inner_data.push(&cca);
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let supp = aml::Name::new("SUPP".into(), &aml::ZERO);
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pci_dsdt_inner_data.push(&supp);
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// Since Cloud Hypervisor supports only one PCI bus, it can be tied
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// to the NUMA node 0. It's up to the user to organize the NUMA nodes
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// so that the PCI bus relates to the expected vCPUs and guest RAM.
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let proximity_domain = 0u32;
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let pxm_return = aml::Return::new(&proximity_domain);
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let pxm = aml::Method::new("_PXM".into(), 0, false, vec![&pxm_return]);
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pci_dsdt_inner_data.push(&pxm);
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let pci_dsm = PciDsmMethod {};
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pci_dsdt_inner_data.push(&pci_dsm);
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let crs = aml::Name::new(
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"_CRS".into(),
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&aml::ResourceTemplate::new(vec![
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&aml::AddressSpace::new_bus_number(0x0u16, 0x0u16),
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#[cfg(target_arch = "x86_64")]
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&aml::Io::new(0xcf8, 0xcf8, 1, 0x8),
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#[cfg(target_arch = "aarch64")]
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&aml::Memory32Fixed::new(
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true,
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layout::PCI_MMCONFIG_START.0 as u32,
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layout::PCI_MMCONFIG_SIZE as u32,
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),
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&aml::AddressSpace::new_memory(
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aml::AddressSpaceCachable::NotCacheable,
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true,
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layout::MEM_32BIT_DEVICES_START.0 as u32,
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(layout::MEM_32BIT_DEVICES_START.0 + layout::MEM_32BIT_DEVICES_SIZE - 1) as u32,
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),
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&aml::AddressSpace::new_memory(
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aml::AddressSpaceCachable::NotCacheable,
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true,
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self.start_of_device_area,
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self.end_of_device_area,
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),
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#[cfg(target_arch = "x86_64")]
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&aml::AddressSpace::new_io(0u16, 0x0cf7u16),
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#[cfg(target_arch = "x86_64")]
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&aml::AddressSpace::new_io(0x0d00u16, 0xffffu16),
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]),
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);
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pci_dsdt_inner_data.push(&crs);
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let mut pci_devices = Vec::new();
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for device_id in 0..32 {
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let pci_device = PciDevSlot { device_id };
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pci_devices.push(pci_device);
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}
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for pci_device in pci_devices.iter() {
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pci_dsdt_inner_data.push(pci_device);
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}
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let pci_device_methods = PciDevSlotMethods {};
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pci_dsdt_inner_data.push(&pci_device_methods);
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// Build PCI routing table, listing IRQs assigned to PCI devices.
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let prt_package_list: Vec<(u32, u32)> = self
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.pci_irq_slots
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.iter()
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.enumerate()
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.map(|(i, irq)| (((((i as u32) & 0x1fu32) << 16) | 0xffffu32), *irq as u32))
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.collect();
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let prt_package_list: Vec<aml::Package> = prt_package_list
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.iter()
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.map(|(bdf, irq)| aml::Package::new(vec![bdf, &0u8, &0u8, irq]))
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.collect();
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let prt_package_list: Vec<&dyn Aml> = prt_package_list
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.iter()
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.map(|item| item as &dyn Aml)
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.collect();
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let prt = aml::Name::new("_PRT".into(), &aml::Package::new(prt_package_list));
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pci_dsdt_inner_data.push(&prt);
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aml::Device::new("_SB_.PCI0".into(), pci_dsdt_inner_data).to_aml_bytes()
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}
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}
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