mirror of
https://github.com/cloud-hypervisor/cloud-hypervisor.git
synced 2026-08-05 02:19:16 +00:00
Sebastien Boeuf
a423bf13ad
The new virtio-queue version introduced some breaking changes which need to be addressed so that Cloud Hypervisor can still work with this version. The most important change is about removing a handle to the guest memory from the Queue, meaning the caller has to provide the guest memory handle for multiple methods from the QueueT trait. One interesting aspect is that QueueT has been widely extended to provide every getter and setter we need to access and update the Queue structure without having direct access to its internal fields. This patch ports all the virtio and vhost-user devices to this new crate definition. It also updates both vhost-user-block and vhost-user-net backends based on the updated vhost-user-backend crate. It also updates the fuzz directory. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
424 lines
16 KiB
Rust
424 lines
16 KiB
Rust
// Copyright 2018 The Chromium OS Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE-BSD-3-Clause file.
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//
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// Copyright © 2019 Intel Corporation
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//
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// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
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use crate::VirtioDevice;
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use byteorder::{ByteOrder, LittleEndian};
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use std::sync::atomic::{AtomicU16, Ordering};
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use std::sync::{Arc, Mutex};
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use versionize::{VersionMap, Versionize, VersionizeResult};
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use versionize_derive::Versionize;
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use virtio_queue::{Queue, QueueT};
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use vm_migration::{MigratableError, Pausable, Snapshot, Snapshottable, VersionMapped};
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use vm_virtio::AccessPlatform;
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#[derive(Clone, Versionize)]
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pub struct VirtioPciCommonConfigState {
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pub driver_status: u8,
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pub config_generation: u8,
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pub device_feature_select: u32,
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pub driver_feature_select: u32,
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pub queue_select: u16,
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pub msix_config: u16,
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pub msix_queues: Vec<u16>,
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}
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impl VersionMapped for VirtioPciCommonConfigState {}
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/// Contains the data for reading and writing the common configuration structure of a virtio PCI
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/// device.
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///
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/// * Registers:
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/// ** About the whole device.
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/// le32 device_feature_select; // 0x00 // read-write
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/// le32 device_feature; // 0x04 // read-only for driver
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/// le32 driver_feature_select; // 0x08 // read-write
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/// le32 driver_feature; // 0x0C // read-write
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/// le16 msix_config; // 0x10 // read-write
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/// le16 num_queues; // 0x12 // read-only for driver
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/// u8 device_status; // 0x14 // read-write (driver_status)
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/// u8 config_generation; // 0x15 // read-only for driver
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/// ** About a specific virtqueue.
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/// le16 queue_select; // 0x16 // read-write
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/// le16 queue_size; // 0x18 // read-write, power of 2, or 0.
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/// le16 queue_msix_vector; // 0x1A // read-write
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/// le16 queue_enable; // 0x1C // read-write (Ready)
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/// le16 queue_notify_off; // 0x1E // read-only for driver
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/// le64 queue_desc; // 0x20 // read-write
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/// le64 queue_avail; // 0x28 // read-write
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/// le64 queue_used; // 0x30 // read-write
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pub struct VirtioPciCommonConfig {
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pub access_platform: Option<Arc<dyn AccessPlatform>>,
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pub driver_status: u8,
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pub config_generation: u8,
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pub device_feature_select: u32,
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pub driver_feature_select: u32,
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pub queue_select: u16,
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pub msix_config: Arc<AtomicU16>,
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pub msix_queues: Arc<Mutex<Vec<u16>>>,
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}
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impl VirtioPciCommonConfig {
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fn state(&self) -> VirtioPciCommonConfigState {
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VirtioPciCommonConfigState {
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driver_status: self.driver_status,
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config_generation: self.config_generation,
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device_feature_select: self.device_feature_select,
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driver_feature_select: self.driver_feature_select,
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queue_select: self.queue_select,
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msix_config: self.msix_config.load(Ordering::Acquire),
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msix_queues: self.msix_queues.lock().unwrap().clone(),
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}
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}
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fn set_state(&mut self, state: &VirtioPciCommonConfigState) {
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self.driver_status = state.driver_status;
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self.config_generation = state.config_generation;
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self.device_feature_select = state.device_feature_select;
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self.driver_feature_select = state.driver_feature_select;
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self.queue_select = state.queue_select;
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self.msix_config.store(state.msix_config, Ordering::Release);
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*(self.msix_queues.lock().unwrap()) = state.msix_queues.clone();
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}
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pub fn read(
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&mut self,
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offset: u64,
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data: &mut [u8],
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queues: &mut [Queue],
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device: Arc<Mutex<dyn VirtioDevice>>,
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) {
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assert!(data.len() <= 8);
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match data.len() {
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1 => {
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let v = self.read_common_config_byte(offset);
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data[0] = v;
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}
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2 => {
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let v = self.read_common_config_word(offset, queues);
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LittleEndian::write_u16(data, v);
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}
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4 => {
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let v = self.read_common_config_dword(offset, device);
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LittleEndian::write_u32(data, v);
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}
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8 => {
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let v = self.read_common_config_qword(offset);
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LittleEndian::write_u64(data, v);
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}
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_ => error!("invalid data length for virtio read: len {}", data.len()),
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}
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}
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pub fn write(
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&mut self,
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offset: u64,
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data: &[u8],
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queues: &mut [Queue],
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device: Arc<Mutex<dyn VirtioDevice>>,
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) {
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assert!(data.len() <= 8);
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match data.len() {
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1 => self.write_common_config_byte(offset, data[0]),
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2 => self.write_common_config_word(offset, LittleEndian::read_u16(data), queues),
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4 => {
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self.write_common_config_dword(offset, LittleEndian::read_u32(data), queues, device)
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}
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8 => self.write_common_config_qword(offset, LittleEndian::read_u64(data), queues),
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_ => error!("invalid data length for virtio write: len {}", data.len()),
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}
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}
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fn read_common_config_byte(&self, offset: u64) -> u8 {
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debug!("read_common_config_byte: offset 0x{:x}", offset);
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// The driver is only allowed to do aligned, properly sized access.
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match offset {
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0x14 => self.driver_status,
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0x15 => self.config_generation,
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_ => {
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warn!("invalid virtio config byte read: 0x{:x}", offset);
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0
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}
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}
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}
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fn write_common_config_byte(&mut self, offset: u64, value: u8) {
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debug!("write_common_config_byte: offset 0x{:x}", offset);
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match offset {
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0x14 => self.driver_status = value,
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_ => {
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warn!("invalid virtio config byte write: 0x{:x}", offset);
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}
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}
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}
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fn read_common_config_word(&self, offset: u64, queues: &[Queue]) -> u16 {
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debug!("read_common_config_word: offset 0x{:x}", offset);
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match offset {
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0x10 => self.msix_config.load(Ordering::Acquire),
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0x12 => queues.len() as u16, // num_queues
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0x16 => self.queue_select,
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0x18 => self.with_queue(queues, |q| q.size()).unwrap_or(0),
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0x1a => self.msix_queues.lock().unwrap()[self.queue_select as usize],
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0x1c => {
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if self.with_queue(queues, |q| q.ready()).unwrap_or(false) {
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1
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} else {
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0
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}
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}
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0x1e => self.queue_select, // notify_off
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_ => {
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warn!("invalid virtio register word read: 0x{:x}", offset);
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0
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}
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}
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}
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fn write_common_config_word(&mut self, offset: u64, value: u16, queues: &mut [Queue]) {
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debug!("write_common_config_word: offset 0x{:x}", offset);
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match offset {
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0x10 => self.msix_config.store(value, Ordering::Release),
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0x16 => self.queue_select = value,
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0x18 => self.with_queue_mut(queues, |q| q.set_size(value)),
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0x1a => self.msix_queues.lock().unwrap()[self.queue_select as usize] = value,
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0x1c => self.with_queue_mut(queues, |q| {
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let ready = value == 1;
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q.set_ready(ready);
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// Translate address of descriptor table and vrings.
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if let Some(access_platform) = &self.access_platform {
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if ready {
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let desc_table = access_platform.translate_gva(q.desc_table(), 0).unwrap();
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let avail_ring = access_platform.translate_gva(q.avail_ring(), 0).unwrap();
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let used_ring = access_platform.translate_gva(q.used_ring(), 0).unwrap();
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q.set_desc_table_address(
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Some((desc_table & 0xffff_ffff) as u32),
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Some((desc_table >> 32) as u32),
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);
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q.set_avail_ring_address(
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Some((avail_ring & 0xffff_ffff) as u32),
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Some((avail_ring >> 32) as u32),
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);
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q.set_used_ring_address(
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Some((used_ring & 0xffff_ffff) as u32),
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Some((used_ring >> 32) as u32),
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);
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}
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}
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}),
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_ => {
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warn!("invalid virtio register word write: 0x{:x}", offset);
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}
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}
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}
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fn read_common_config_dword(&self, offset: u64, device: Arc<Mutex<dyn VirtioDevice>>) -> u32 {
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debug!("read_common_config_dword: offset 0x{:x}", offset);
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match offset {
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0x00 => self.device_feature_select,
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0x04 => {
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let locked_device = device.lock().unwrap();
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// Only 64 bits of features (2 pages) are defined for now, so limit
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// device_feature_select to avoid shifting by 64 or more bits.
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if self.device_feature_select < 2 {
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(locked_device.features() >> (self.device_feature_select * 32)) as u32
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} else {
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0
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}
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}
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0x08 => self.driver_feature_select,
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_ => {
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warn!("invalid virtio register dword read: 0x{:x}", offset);
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0
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}
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}
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}
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fn write_common_config_dword(
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&mut self,
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offset: u64,
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value: u32,
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queues: &mut [Queue],
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device: Arc<Mutex<dyn VirtioDevice>>,
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) {
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debug!("write_common_config_dword: offset 0x{:x}", offset);
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match offset {
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0x00 => self.device_feature_select = value,
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0x08 => self.driver_feature_select = value,
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0x0c => {
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if self.driver_feature_select < 2 {
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let mut locked_device = device.lock().unwrap();
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locked_device
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.ack_features(u64::from(value) << (self.driver_feature_select * 32));
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} else {
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warn!(
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"invalid ack_features (page {}, value 0x{:x})",
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self.driver_feature_select, value
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);
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}
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}
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0x20 => self.with_queue_mut(queues, |q| q.set_desc_table_address(Some(value), None)),
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0x24 => self.with_queue_mut(queues, |q| q.set_desc_table_address(None, Some(value))),
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0x28 => self.with_queue_mut(queues, |q| q.set_avail_ring_address(Some(value), None)),
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0x2c => self.with_queue_mut(queues, |q| q.set_avail_ring_address(None, Some(value))),
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0x30 => self.with_queue_mut(queues, |q| q.set_used_ring_address(Some(value), None)),
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0x34 => self.with_queue_mut(queues, |q| q.set_used_ring_address(None, Some(value))),
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_ => {
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warn!("invalid virtio register dword write: 0x{:x}", offset);
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}
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}
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}
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fn read_common_config_qword(&self, _offset: u64) -> u64 {
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debug!("read_common_config_qword: offset 0x{:x}", _offset);
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0 // Assume the guest has no reason to read write-only registers.
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}
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fn write_common_config_qword(&mut self, offset: u64, value: u64, queues: &mut [Queue]) {
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debug!("write_common_config_qword: offset 0x{:x}", offset);
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let low = Some((value & 0xffff_ffff) as u32);
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let high = Some((value >> 32) as u32);
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match offset {
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0x20 => self.with_queue_mut(queues, |q| q.set_desc_table_address(low, high)),
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0x28 => self.with_queue_mut(queues, |q| q.set_avail_ring_address(low, high)),
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0x30 => self.with_queue_mut(queues, |q| q.set_used_ring_address(low, high)),
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_ => {
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warn!("invalid virtio register qword write: 0x{:x}", offset);
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}
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}
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}
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fn with_queue<U, F>(&self, queues: &[Queue], f: F) -> Option<U>
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where
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F: FnOnce(&Queue) -> U,
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{
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queues.get(self.queue_select as usize).map(f)
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}
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fn with_queue_mut<F: FnOnce(&mut Queue)>(&self, queues: &mut [Queue], f: F) {
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if let Some(queue) = queues.get_mut(self.queue_select as usize) {
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f(queue);
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}
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}
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}
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impl Pausable for VirtioPciCommonConfig {}
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impl Snapshottable for VirtioPciCommonConfig {
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fn id(&self) -> String {
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String::from("virtio_pci_common_config")
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}
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fn snapshot(&mut self) -> std::result::Result<Snapshot, MigratableError> {
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Snapshot::new_from_versioned_state(&self.id(), &self.state())
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}
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fn restore(&mut self, snapshot: Snapshot) -> std::result::Result<(), MigratableError> {
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self.set_state(&snapshot.to_versioned_state(&self.id())?);
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Ok(())
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}
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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use crate::GuestMemoryMmap;
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use crate::{ActivateResult, VirtioInterrupt};
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use std::sync::Arc;
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use virtio_queue::Queue;
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use vm_memory::GuestMemoryAtomic;
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use vmm_sys_util::eventfd::EventFd;
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struct DummyDevice(u32);
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const QUEUE_SIZE: u16 = 256;
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const QUEUE_SIZES: &[u16] = &[QUEUE_SIZE];
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const DUMMY_FEATURES: u64 = 0x5555_aaaa;
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impl VirtioDevice for DummyDevice {
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fn device_type(&self) -> u32 {
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self.0
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}
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fn queue_max_sizes(&self) -> &[u16] {
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QUEUE_SIZES
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}
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fn activate(
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&mut self,
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_mem: GuestMemoryAtomic<GuestMemoryMmap>,
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_interrupt_evt: Arc<dyn VirtioInterrupt>,
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_queues: Vec<(usize, Queue, EventFd)>,
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) -> ActivateResult {
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Ok(())
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}
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fn features(&self) -> u64 {
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DUMMY_FEATURES
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}
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fn ack_features(&mut self, _value: u64) {}
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fn read_config(&self, _offset: u64, _data: &mut [u8]) {}
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fn write_config(&mut self, _offset: u64, _data: &[u8]) {}
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}
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#[test]
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fn write_base_regs() {
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let mut regs = VirtioPciCommonConfig {
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access_platform: None,
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driver_status: 0xaa,
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config_generation: 0x55,
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device_feature_select: 0x0,
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driver_feature_select: 0x0,
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queue_select: 0xff,
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msix_config: Arc::new(AtomicU16::new(0)),
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msix_queues: Arc::new(Mutex::new(vec![0; 3])),
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};
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let dev = Arc::new(Mutex::new(DummyDevice(0)));
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let mut queues = Vec::new();
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// Can set all bits of driver_status.
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regs.write(0x14, &[0x55], &mut queues, dev.clone());
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let mut read_back = vec![0x00];
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regs.read(0x14, &mut read_back, &mut queues, dev.clone());
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assert_eq!(read_back[0], 0x55);
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// The config generation register is read only.
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regs.write(0x15, &[0xaa], &mut queues, dev.clone());
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let mut read_back = vec![0x00];
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regs.read(0x15, &mut read_back, &mut queues, dev.clone());
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assert_eq!(read_back[0], 0x55);
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// Device features is read-only and passed through from the device.
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regs.write(0x04, &[0, 0, 0, 0], &mut queues, dev.clone());
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let mut read_back = vec![0, 0, 0, 0];
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regs.read(0x04, &mut read_back, &mut queues, dev.clone());
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assert_eq!(LittleEndian::read_u32(&read_back), DUMMY_FEATURES as u32);
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// Feature select registers are read/write.
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regs.write(0x00, &[1, 2, 3, 4], &mut queues, dev.clone());
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let mut read_back = vec![0, 0, 0, 0];
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regs.read(0x00, &mut read_back, &mut queues, dev.clone());
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assert_eq!(LittleEndian::read_u32(&read_back), 0x0403_0201);
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regs.write(0x08, &[1, 2, 3, 4], &mut queues, dev.clone());
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let mut read_back = vec![0, 0, 0, 0];
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regs.read(0x08, &mut read_back, &mut queues, dev.clone());
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assert_eq!(LittleEndian::read_u32(&read_back), 0x0403_0201);
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// 'queue_select' can be read and written.
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regs.write(0x16, &[0xaa, 0x55], &mut queues, dev.clone());
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let mut read_back = vec![0x00, 0x00];
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regs.read(0x16, &mut read_back, &mut queues, dev);
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assert_eq!(read_back[0], 0xaa);
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assert_eq!(read_back[1], 0x55);
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}
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}
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