mirror of
https://github.com/cloud-hypervisor/cloud-hypervisor.git
synced 2026-08-05 02:19:16 +00:00
5c25d82f59
When SVE is enabled, KVM replaces the FPSIMD V-registers with wider SVE Z-registers. Attempting to access the old FPSIMD offsets returns EINVAL. Fix by classifying each register from KVM_GET_REG_LIST as core, system, or extended. Extended registers (currently SVE only) are saved as generic `ExtendedReg` entries split into `pre_finalize_regs` (registers like SVE VLS that must be written before `vcpu_finalize`) and `extended_regs`. FPSIMD registers are only accessed when SVE is absent. Unrecognized register families error immediately so future extensions like SME fail clearly rather than silently losing state. The snapshot is deserialized before vCPU init to make pre-finalize register state available for the init -> VLS -> finalize ordering required by KVM. Signed-off-by: Ruben Hakobyan <hruben@meta.com>
496 lines
14 KiB
Rust
496 lines
14 KiB
Rust
// Copyright © 2024 Institute of Software, CAS. All rights reserved.
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//
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// Copyright © 2019 Intel Corporation
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//
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// SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause
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//
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// Copyright © 2020, Microsoft Corporation
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//
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// Copyright 2018-2019 CrowdStrike, Inc.
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//
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//
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//! A generic abstraction around hypervisor functionality
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//!
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//! This crate offers a trait abstraction for underlying hypervisors
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//!
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//! # Platform support
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//!
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//! - x86_64
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//! - arm64
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//! - riscv64 (experimental)
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//!
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/// Architecture specific definitions
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#[macro_use]
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pub mod arch;
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#[cfg(feature = "kvm")]
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/// KVM implementation module
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pub mod kvm;
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/// Microsoft Hypervisor implementation module
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#[cfg(feature = "mshv")]
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pub mod mshv;
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/// Hypervisor related module
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mod hypervisor;
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/// Vm related module
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mod vm;
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/// CPU related module
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mod cpu;
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/// Device related module
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mod device;
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use std::sync::Arc;
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use anyhow::anyhow;
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use concat_idents::concat_idents;
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#[cfg(target_arch = "x86_64")]
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pub use cpu::CpuVendor;
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pub use cpu::{HypervisorCpuError, Vcpu, VmExit};
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pub use device::HypervisorDeviceError;
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#[cfg(all(feature = "kvm", target_arch = "aarch64"))]
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pub use kvm::aarch64;
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#[cfg(all(feature = "kvm", target_arch = "riscv64"))]
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pub use kvm::{AiaState, riscv64};
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pub use vm::{
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DataMatch, HypervisorVmError, InterruptSourceConfig, LegacyIrqSourceConfig, MsiIrqSourceConfig,
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Vm, VmOps,
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};
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pub use crate::hypervisor::{Hypervisor, HypervisorError};
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#[derive(Debug, Copy, Clone, PartialEq)]
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pub enum HypervisorType {
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#[cfg(feature = "kvm")]
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Kvm,
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#[cfg(feature = "mshv")]
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Mshv,
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}
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pub fn new() -> std::result::Result<Arc<dyn Hypervisor>, HypervisorError> {
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#[cfg(feature = "kvm")]
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if kvm::KvmHypervisor::is_available()? {
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return kvm::KvmHypervisor::new();
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}
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#[cfg(feature = "mshv")]
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if mshv::MshvHypervisor::is_available()? {
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return mshv::MshvHypervisor::new();
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}
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Err(HypervisorError::HypervisorCreate(anyhow!(
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"no supported hypervisor"
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)))
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}
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// Returns a `Vec<T>` with a size in bytes at least as large as `size_in_bytes`.
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fn vec_with_size_in_bytes<T: Default>(size_in_bytes: usize) -> Vec<T> {
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let rounded_size = size_in_bytes.div_ceil(size_of::<T>());
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let mut v = Vec::with_capacity(rounded_size);
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v.resize_with(rounded_size, T::default);
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v
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}
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// The kvm API has many structs that resemble the following `Foo` structure:
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//
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// ```
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// #[repr(C)]
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// struct Foo {
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// some_data: u32
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// entries: __IncompleteArrayField<__u32>,
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// }
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// ```
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//
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// In order to allocate such a structure, `size_of::<Foo>()` would be too small because it would not
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// include any space for `entries`. To make the allocation large enough while still being aligned
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// for `Foo`, a `Vec<Foo>` is created. Only the first element of `Vec<Foo>` would actually be used
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// as a `Foo`. The remaining memory in the `Vec<Foo>` is for `entries`, which must be contiguous
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// with `Foo`. This function is used to make the `Vec<Foo>` with enough space for `count` entries.
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use std::mem::size_of;
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pub fn vec_with_array_field<T: Default, F>(count: usize) -> Vec<T> {
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let element_space = count * size_of::<F>();
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let vec_size_bytes = size_of::<T>() + element_space;
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vec_with_size_in_bytes(vec_size_bytes)
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}
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/// User memory region structure
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#[derive(Debug, Default, Eq, PartialEq)]
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pub struct UserMemoryRegion {
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pub slot: u32,
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pub guest_phys_addr: u64,
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pub memory_size: u64,
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pub userspace_addr: u64,
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pub flags: u32,
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pub guest_memfd: Option<u32>,
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pub guest_memfd_offset: Option<u64>,
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}
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/// Flags for user memory region
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pub const USER_MEMORY_REGION_READ: u32 = 1;
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pub const USER_MEMORY_REGION_WRITE: u32 = 1 << 1;
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pub const USER_MEMORY_REGION_EXECUTE: u32 = 1 << 2;
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pub const USER_MEMORY_REGION_LOG_DIRTY: u32 = 1 << 3;
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pub const USER_MEMORY_REGION_ADJUSTABLE: u32 = 1 << 4;
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pub const USER_MEMORY_REGION_GUEST_MEMFD: u32 = 1 << 5;
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#[derive(Debug)]
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pub enum MpState {
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#[cfg(feature = "kvm")]
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Kvm(kvm_bindings::kvm_mp_state),
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#[cfg(feature = "mshv")]
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Mshv, /* MSHV does not support MpState yet */
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}
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#[derive(Debug, Clone, Copy)]
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pub enum IoEventAddress {
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Pio(u64),
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Mmio(u64),
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}
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#[derive(Clone, serde::Serialize, serde::Deserialize)]
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#[allow(clippy::large_enum_variant)]
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pub enum CpuState {
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#[cfg(feature = "kvm")]
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Kvm(kvm::VcpuKvmState),
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#[cfg(feature = "mshv")]
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Mshv(mshv::VcpuMshvState),
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}
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#[cfg(target_arch = "aarch64")]
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impl CpuState {
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pub fn pre_finalize_regs(&self) -> &[arch::aarch64::ExtendedReg] {
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match self {
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#[cfg(feature = "kvm")]
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CpuState::Kvm(state) => &state.pre_finalize_regs,
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#[cfg(feature = "mshv")]
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CpuState::Mshv(_) => &[],
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}
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}
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}
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#[derive(Debug, Clone, Copy, serde::Serialize, serde::Deserialize)]
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#[cfg(target_arch = "x86_64")]
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pub enum ClockData {
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#[cfg(feature = "kvm")]
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Kvm(kvm_bindings::kvm_clock_data),
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#[cfg(feature = "mshv")]
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Mshv(mshv::MshvClockData),
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}
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#[cfg(target_arch = "x86_64")]
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impl ClockData {
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pub fn reset_flags(&mut self) {
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match self {
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#[cfg(feature = "kvm")]
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ClockData::Kvm(s) => s.flags = 0,
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#[allow(unreachable_patterns)]
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_ => {}
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}
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}
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}
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#[derive(Debug, Clone, Copy, Default, PartialEq, Eq)]
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pub struct HypervisorVmConfig {
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#[cfg(feature = "tdx")]
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pub tdx_enabled: bool,
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#[cfg(feature = "sev_snp")]
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pub sev_snp_enabled: bool,
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#[cfg(feature = "sev_snp")]
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pub mem_size: u64,
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#[cfg(feature = "sev_snp")]
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pub vmsa_features: u64,
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pub nested: bool,
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pub smt_enabled: bool,
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}
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#[derive(Copy, Clone)]
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pub enum IrqRoutingEntry {
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#[cfg(feature = "kvm")]
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Kvm(kvm_bindings::kvm_irq_routing_entry),
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#[cfg(feature = "mshv")]
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Mshv(mshv_bindings::mshv_user_irq_entry),
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}
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#[derive(Debug, Clone, Copy, PartialEq, serde::Serialize, serde::Deserialize)]
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pub enum VcpuInit {
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#[cfg(all(feature = "kvm", target_arch = "aarch64"))]
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Kvm(kvm_bindings::kvm_vcpu_init),
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#[cfg(all(feature = "mshv", target_arch = "aarch64"))]
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Mshv(mshv_bindings::MshvVcpuInit),
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}
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#[derive(Debug, Clone, PartialEq)]
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pub enum RegList {
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#[cfg(all(feature = "kvm", any(target_arch = "aarch64", target_arch = "riscv64")))]
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Kvm(kvm_bindings::RegList),
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#[cfg(all(feature = "mshv", target_arch = "aarch64"))]
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Mshv(mshv_bindings::MshvRegList),
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}
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pub enum Register {
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#[cfg(feature = "kvm")]
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Kvm(kvm_bindings::kvm_one_reg),
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}
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#[allow(clippy::large_enum_variant)]
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#[derive(Debug, Clone, Copy, PartialEq, serde::Serialize, serde::Deserialize)]
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pub enum StandardRegisters {
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#[cfg(all(feature = "kvm", not(target_arch = "riscv64")))]
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Kvm(kvm_bindings::kvm_regs),
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#[cfg(all(feature = "kvm", target_arch = "riscv64"))]
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Kvm(kvm_bindings::kvm_riscv_core),
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#[cfg(any(feature = "mshv", feature = "mshv_emulator"))]
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Mshv(mshv_bindings::StandardRegisters),
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}
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macro_rules! set_x86_64_reg {
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($reg_name:ident) => {
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concat_idents!(method_name = "set_", $reg_name {
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#[cfg(target_arch = "x86_64")]
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impl StandardRegisters {
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pub fn method_name(&mut self, val: u64) {
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match self {
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#[cfg(feature = "kvm")]
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StandardRegisters::Kvm(s) => s.$reg_name = val,
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#[cfg(any(feature = "mshv", feature = "mshv_emulator"))]
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StandardRegisters::Mshv(s) => s.$reg_name = val,
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#[allow(unreachable_patterns)]
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_ => { let _ = val; unreachable!("no x86_64 register backend available") },
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}
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}
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}
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});
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}
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}
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macro_rules! get_x86_64_reg {
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($reg_name:ident) => {
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concat_idents!(method_name = "get_", $reg_name {
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#[cfg(target_arch = "x86_64")]
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impl StandardRegisters {
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pub fn method_name(&self) -> u64 {
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match self {
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#[cfg(feature = "kvm")]
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StandardRegisters::Kvm(s) => s.$reg_name,
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#[cfg(any(feature = "mshv", feature = "mshv_emulator"))]
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StandardRegisters::Mshv(s) => s.$reg_name,
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#[allow(unreachable_patterns)]
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_ => unreachable!("no x86_64 register backend available"),
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}
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}
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}
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});
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}
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}
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set_x86_64_reg!(rax);
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set_x86_64_reg!(rbx);
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set_x86_64_reg!(rcx);
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set_x86_64_reg!(rdx);
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set_x86_64_reg!(rsi);
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set_x86_64_reg!(rdi);
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set_x86_64_reg!(rsp);
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set_x86_64_reg!(rbp);
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set_x86_64_reg!(r8);
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set_x86_64_reg!(r9);
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set_x86_64_reg!(r10);
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set_x86_64_reg!(r11);
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set_x86_64_reg!(r12);
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set_x86_64_reg!(r13);
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set_x86_64_reg!(r14);
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set_x86_64_reg!(r15);
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set_x86_64_reg!(rip);
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set_x86_64_reg!(rflags);
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get_x86_64_reg!(rax);
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get_x86_64_reg!(rbx);
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get_x86_64_reg!(rcx);
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get_x86_64_reg!(rdx);
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get_x86_64_reg!(rsi);
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get_x86_64_reg!(rdi);
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get_x86_64_reg!(rsp);
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get_x86_64_reg!(rbp);
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get_x86_64_reg!(r8);
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get_x86_64_reg!(r9);
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get_x86_64_reg!(r10);
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get_x86_64_reg!(r11);
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get_x86_64_reg!(r12);
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get_x86_64_reg!(r13);
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get_x86_64_reg!(r14);
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get_x86_64_reg!(r15);
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get_x86_64_reg!(rip);
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get_x86_64_reg!(rflags);
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macro_rules! set_aarch64_reg {
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($reg_name:ident, $type:ty) => {
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concat_idents!(method_name = "set_", $reg_name {
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#[cfg(target_arch = "aarch64")]
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impl StandardRegisters {
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pub fn method_name(&mut self, val: $type) {
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match self {
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#[cfg(feature = "kvm")]
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StandardRegisters::Kvm(s) => s.regs.$reg_name = val,
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#[cfg(feature = "mshv")]
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StandardRegisters::Mshv(s) => s.$reg_name = val,
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}
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}
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}
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});
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}
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}
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macro_rules! get_aarch64_reg {
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($reg_name:ident, $type:ty) => {
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concat_idents!(method_name = "get_", $reg_name {
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#[cfg(target_arch = "aarch64")]
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impl StandardRegisters {
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pub fn method_name(&self) -> $type {
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match self {
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#[cfg(feature = "kvm")]
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StandardRegisters::Kvm(s) => s.regs.$reg_name,
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#[cfg(feature = "mshv")]
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StandardRegisters::Mshv(s) => s.$reg_name,
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}
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}
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}
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});
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}
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}
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set_aarch64_reg!(regs, [u64; 31usize]);
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set_aarch64_reg!(sp, u64);
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set_aarch64_reg!(pc, u64);
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set_aarch64_reg!(pstate, u64);
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get_aarch64_reg!(regs, [u64; 31usize]);
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get_aarch64_reg!(sp, u64);
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get_aarch64_reg!(pc, u64);
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get_aarch64_reg!(pstate, u64);
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macro_rules! set_riscv64_reg {
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(mode) => {
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#[cfg(target_arch = "riscv64")]
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impl StandardRegisters {
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pub fn set_mode(&mut self, val: u64) {
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match self {
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#[cfg(feature = "kvm")]
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StandardRegisters::Kvm(s) => s.mode = val,
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}
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}
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}
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};
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($reg_name:ident) => {
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concat_idents!(method_name = "set_", $reg_name {
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#[cfg(target_arch = "riscv64")]
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impl StandardRegisters {
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pub fn method_name(&mut self, val: u64) {
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match self {
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#[cfg(feature = "kvm")]
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StandardRegisters::Kvm(s) => s.regs.$reg_name = val,
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}
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}
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}
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});
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}
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}
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macro_rules! get_riscv64_reg {
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(mode) => {
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#[cfg(target_arch = "riscv64")]
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impl StandardRegisters {
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pub fn get_mode(&self) -> u64 {
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match self {
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#[cfg(feature = "kvm")]
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StandardRegisters::Kvm(s) => s.mode,
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}
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}
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}
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};
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($reg_name:ident) => {
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concat_idents!(method_name = "get_", $reg_name {
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#[cfg(target_arch = "riscv64")]
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impl StandardRegisters {
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pub fn method_name(&self) -> u64 {
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match self {
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#[cfg(feature = "kvm")]
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StandardRegisters::Kvm(s) => s.regs.$reg_name,
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}
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}
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}
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});
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}
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}
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set_riscv64_reg!(pc);
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set_riscv64_reg!(ra);
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set_riscv64_reg!(sp);
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set_riscv64_reg!(gp);
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set_riscv64_reg!(tp);
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set_riscv64_reg!(t0);
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set_riscv64_reg!(t1);
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set_riscv64_reg!(t2);
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set_riscv64_reg!(s0);
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set_riscv64_reg!(s1);
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set_riscv64_reg!(a0);
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set_riscv64_reg!(a1);
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set_riscv64_reg!(a2);
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set_riscv64_reg!(a3);
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set_riscv64_reg!(a4);
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set_riscv64_reg!(a5);
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set_riscv64_reg!(a6);
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set_riscv64_reg!(a7);
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set_riscv64_reg!(s2);
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set_riscv64_reg!(s3);
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set_riscv64_reg!(s4);
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set_riscv64_reg!(s5);
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set_riscv64_reg!(s6);
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set_riscv64_reg!(s7);
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set_riscv64_reg!(s8);
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set_riscv64_reg!(s9);
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set_riscv64_reg!(s10);
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set_riscv64_reg!(s11);
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set_riscv64_reg!(t3);
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set_riscv64_reg!(t4);
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set_riscv64_reg!(t5);
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set_riscv64_reg!(t6);
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set_riscv64_reg!(mode);
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get_riscv64_reg!(pc);
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get_riscv64_reg!(ra);
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get_riscv64_reg!(sp);
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get_riscv64_reg!(gp);
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get_riscv64_reg!(tp);
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get_riscv64_reg!(t0);
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|
get_riscv64_reg!(t1);
|
|
get_riscv64_reg!(t2);
|
|
get_riscv64_reg!(s0);
|
|
get_riscv64_reg!(s1);
|
|
get_riscv64_reg!(a0);
|
|
get_riscv64_reg!(a1);
|
|
get_riscv64_reg!(a2);
|
|
get_riscv64_reg!(a3);
|
|
get_riscv64_reg!(a4);
|
|
get_riscv64_reg!(a5);
|
|
get_riscv64_reg!(a6);
|
|
get_riscv64_reg!(a7);
|
|
get_riscv64_reg!(s2);
|
|
get_riscv64_reg!(s3);
|
|
get_riscv64_reg!(s4);
|
|
get_riscv64_reg!(s5);
|
|
get_riscv64_reg!(s6);
|
|
get_riscv64_reg!(s7);
|
|
get_riscv64_reg!(s8);
|
|
get_riscv64_reg!(s9);
|
|
get_riscv64_reg!(s10);
|
|
get_riscv64_reg!(s11);
|
|
get_riscv64_reg!(t3);
|
|
get_riscv64_reg!(t4);
|
|
get_riscv64_reg!(t5);
|
|
get_riscv64_reg!(t6);
|
|
get_riscv64_reg!(mode);
|