mirror of
https://github.com/cloud-hypervisor/cloud-hypervisor.git
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a072b9a356
For ARM64 guests we need to set three important partition property: 1) PPI interrupt ID for timer interrupt 2) PPI interrupt ID for PMU interrupts. 3) Hiding LPI support from the guest because MSHV does emulate ITS for the guest. Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
229 lines
6.7 KiB
Rust
229 lines
6.7 KiB
Rust
// SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause
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//
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// Copyright © 2025, Microsoft Corporation
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//
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use bitfield_struct::bitfield;
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use open_enum::open_enum;
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use zerocopy::{FromBytes, IntoBytes};
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/// ESR_EL2, exception syndrome register.
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#[bitfield(u64)]
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#[derive(IntoBytes, FromBytes)]
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pub struct EsrEl2 {
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#[bits(25)]
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pub iss: u32,
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pub il: bool,
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#[bits(6)]
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pub ec: u8,
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#[bits(5)]
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pub iss2: u8,
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#[bits(27)]
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_rsvd: u32,
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}
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#[open_enum]
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#[derive(Debug)]
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#[repr(u8)]
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pub enum FaultStatusCode {
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ADDRESS_SIZE_FAULT_LEVEL0 = 0b000000,
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ADDRESS_SIZE_FAULT_LEVEL1 = 0b000001,
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ADDRESS_SIZE_FAULT_LEVEL2 = 0b000010,
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ADDRESS_SIZE_FAULT_LEVEL3 = 0b000011,
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TRANSLATION_FAULT_LEVEL0 = 0b000100,
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TRANSLATION_FAULT_LEVEL1 = 0b000101,
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TRANSLATION_FAULT_LEVEL2 = 0b000110,
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TRANSLATION_FAULT_LEVEL3 = 0b000111,
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ACCESS_FLAG_FAULT_LEVEL0 = 0b001000,
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ACCESS_FLAG_FAULT_LEVEL1 = 0b001001,
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ACCESS_FLAG_FAULT_LEVEL2 = 0b001010,
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ACCESS_FLAG_FAULT_LEVEL3 = 0b001011,
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PERMISSION_FAULT_LEVEL0 = 0b001100,
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PERMISSION_FAULT_LEVEL1 = 0b001101,
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PERMISSION_FAULT_LEVEL2 = 0b001110,
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PERMISSION_FAULT_LEVEL3 = 0b001111,
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SYNCHRONOUS_EXTERNAL_ABORT = 0b010000,
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SYNC_TAG_CHECK_FAULT = 0b010001,
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SEA_TTW_LEVEL_NEG1 = 0b010011,
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SEA_TTW_LEVEL0 = 0b010100,
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SEA_TTW_LEVEL1 = 0b010101,
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SEA_TTW_LEVEL2 = 0b010110,
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SEA_TTW_LEVEL3 = 0b010111,
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ECC_PARITY = 0b011000,
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ECC_PARITY_TTW_LEVEL_NEG1 = 0b011011,
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ECC_PARITY_TTW_LEVEL0 = 0b011100,
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ECC_PARITY_TTW_LEVEL1 = 0b011101,
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ECC_PARITY_TTW_LEVEL2 = 0b011110,
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ECC_PARITY_TTW_LEVEL3 = 0b011111,
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/// Valid only for data fault.
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ALIGNMENT_FAULT = 0b100001,
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/// Valid only for instruction fault.
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GRANULE_PROTECTION_FAULT_LEVEL_NEG = 0b100011,
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/// Valid only for instruction fault.
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GRANULE_PROTECTION_FAULT_LEVEL0 = 0b100100,
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/// Valid only for instruction fault.
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GRANULE_PROTECTION_FAULT_LEVEL1 = 0b100101,
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/// Valid only for instruction fault.
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GRANULE_PROTECTION_FAULT_LEVEL2 = 0b100110,
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/// Valid only for instruction fault.
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GRANULE_PROTECTION_FAULT_LEVEL3 = 0b100111,
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ADDRESS_SIZE_FAULT_LEVEL_NEG1 = 0b101001,
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TRANSLATION_FAULT_LEVEL_NEG1 = 0b101011,
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TLB_CONFLICT_ABORT = 0b110000,
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UNSUPPORTED_HW_UPDATE_FAULT = 0b110001,
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}
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/// Support for embedding within IssDataAbort/IssInstructionAbort
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impl FaultStatusCode {
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const fn from_bits(bits: u32) -> Self {
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FaultStatusCode((bits & 0x3f) as u8)
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}
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const fn into_bits(self) -> u32 {
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self.0 as u32
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}
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}
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#[bitfield(u32)]
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pub struct IssDataAbort {
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#[bits(6)]
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pub dfsc: FaultStatusCode,
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// Write operation (write not read)
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pub wnr: bool,
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pub s1ptw: bool,
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pub cm: bool,
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pub ea: bool,
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/// FAR not valid
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pub fnv: bool,
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#[bits(2)]
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pub set: u8,
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pub vncr: bool,
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/// Acquire/release
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pub ar: bool,
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/// (ISV==1) 64-bit, (ISV==0) FAR is approximate
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pub sf: bool,
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#[bits(5)]
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/// Register index.
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pub srt: u8,
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/// Sign extended.
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pub sse: bool,
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#[bits(2)]
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/// access width log2
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pub sas: u8,
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/// Valid ESREL2 iss field.
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pub isv: bool,
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#[bits(7)]
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_unused: u8,
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}
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#[open_enum]
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#[repr(u8)]
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pub enum ExceptionClass {
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UNKNOWN = 0b000000,
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WFI = 0b000001,
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MCR_MRC_COPROC_15 = 0b000011,
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MCRR_MRRC_COPROC_15 = 0b000100,
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MCR_MRC_COPROC_14 = 0b000101,
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LDC_STC = 0b000110,
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FP_OR_SIMD = 0b000111,
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VMRS = 0b001000,
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POINTER_AUTH_HCR_OR_SCR = 0b001001,
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LS64 = 0b001010,
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MRRC_COPROC_14 = 0b001100,
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BRANCH_TARGET = 0b001101,
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ILLEGAL_STATE = 0b001110,
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SVC32 = 0b010001,
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HVC32 = 0b010010,
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SMC32 = 0b010011,
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SVC = 0b010101,
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HVC = 0b010110,
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SMC = 0b010111,
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SYSTEM = 0b011000,
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SVE = 0b011001,
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ERET = 0b011010,
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TSTART = 0b011011,
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POINTER_AUTH = 0b011100,
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SME = 0b011101,
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INSTRUCTION_ABORT_LOWER = 0b100000,
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INSTRUCTION_ABORT = 0b100001,
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PC_ALIGNMENT = 0b100010,
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DATA_ABORT_LOWER = 0b100100,
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DATA_ABORT = 0b100101,
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SP_ALIGNMENT_FAULT = 0b100110,
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MEMORY_OP = 0b100111,
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FP_EXCEPTION_32 = 0b101000,
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FP_EXCEPTION_64 = 0b101100,
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SERROR = 0b101111,
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BREAKPOINT_LOWER = 0b110000,
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BREAKPOINT = 0b110001,
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STEP_LOWER = 0b110010,
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STEP = 0b110011,
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WATCHPOINT_LOWER = 0b110100,
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WATCHPOINT = 0b110101,
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BRK32 = 0b111000,
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VECTOR_CATCH_32 = 0b111010,
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BRK = 0b111100,
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}
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#[allow(non_upper_case_globals)]
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// PSR (Processor State Register) bits.
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// Taken from arch/arm64/include/uapi/asm/ptrace.h.
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const PSR_MODE_EL1h: u64 = 0x0000_0005;
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const PSR_F_BIT: u64 = 0x0000_0040;
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const PSR_I_BIT: u64 = 0x0000_0080;
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const PSR_A_BIT: u64 = 0x0000_0100;
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const PSR_D_BIT: u64 = 0x0000_0200;
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// Taken from arch/arm64/kvm/inject_fault.c.
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pub const PSTATE_FAULT_BITS_64: u64 = PSR_MODE_EL1h | PSR_A_BIT | PSR_F_BIT | PSR_I_BIT | PSR_D_BIT;
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// AArch64 system register encoding:
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// See https://developer.arm.com/documentation/ddi0487 (chapter D12)
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//
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// 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
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// +----------+---+-----+-----+-----+-----+-----+----+
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// |1101010100| L | op0 | op1 | CRn | CRm | op2 | Rt |
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// +----------+---+-----+-----+-----+-----+-----+----+
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//
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// Notes:
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// - L and Rt are reserved as implementation defined fields, ignored.
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const SYSREG_HEAD: u32 = 0b1101010100u32 << 22;
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const SYSREG_OP0_SHIFT: u32 = 19;
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const SYSREG_OP0_MASK: u32 = 0b11u32 << 19;
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const SYSREG_OP1_SHIFT: u32 = 16;
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const SYSREG_OP1_MASK: u32 = 0b111u32 << 16;
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const SYSREG_CRN_SHIFT: u32 = 12;
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const SYSREG_CRN_MASK: u32 = 0b1111u32 << 12;
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const SYSREG_CRM_SHIFT: u32 = 8;
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const SYSREG_CRM_MASK: u32 = 0b1111u32 << 8;
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const SYSREG_OP2_SHIFT: u32 = 5;
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const SYSREG_OP2_MASK: u32 = 0b111u32 << 5;
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/// Define the ID of system registers
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#[macro_export]
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macro_rules! arm64_sys_reg {
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($name: tt, $op0: tt, $op1: tt, $crn: tt, $crm: tt, $op2: tt) => {
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pub const $name: u32 = SYSREG_HEAD
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| ((($op0 as u32) << SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK as u32)
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| ((($op1 as u32) << SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK as u32)
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| ((($crn as u32) << SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK as u32)
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| ((($crm as u32) << SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK as u32)
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| ((($op2 as u32) << SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK as u32);
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};
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}
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arm64_sys_reg!(MPIDR_EL1, 3, 0, 0, 0, 5);
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arm64_sys_reg!(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0);
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arm64_sys_reg!(TTBR1_EL1, 3, 0, 2, 0, 1);
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arm64_sys_reg!(TCR_EL1, 3, 0, 2, 0, 2);
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pub const AARCH64_ARCH_TIMER_PHYS_SECURE_IRQ: u32 = 13;
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pub const AARCH64_ARCH_TIMER_PHYS_NONSECURE_IRQ: u32 = 14;
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pub const AARCH64_ARCH_TIMER_VIRT_IRQ: u32 = 11;
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pub const AARCH64_ARCH_TIMER_HYP_IRQ: u32 = 10;
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// PMU PPI interrupt number
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pub const AARCH64_PMU_IRQ: u32 = 7;
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pub const AARCH64_MIN_PPI_IRQ: u32 = 16;
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