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https://github.com/cloud-hypervisor/cloud-hypervisor.git
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42522a88c0
To ensure that struct sizes are the same on 32-bit and 64-bit, various kernel APIs use __u64 (Rust u64) to represent userspace pointers. Userspace is expected to cast pointers to __u64 before passing them to the kernel, and cast kernel-provided __u64 to a pointer before using them. However, various safe APIs in Cloud Hypervisor took caller-provided u64 values and passed them to syscalls that interpret them as userspace addresses. Therefore, passing bad u64 values would cause memory disclosure or corruption. Fix the bug by using usize and pointer types as appropriate. To make soundness of the code easier to reason about, the PCI code gains a new MmapRegion abstraction that ensures the validity of pointers. The rest of the code already has an MmapRegion abstraction it can use. To avoid having to reason about whether something is keeping the MmapRegion alive, reference counting is added. MmapRegion cannot hold references to other objects, so the reference counting cannot introduce cycles. Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>
73 lines
1.6 KiB
Rust
73 lines
1.6 KiB
Rust
// Copyright © 2020 Intel Corporation
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//
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// SPDX-License-Identifier: Apache-2.0
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//
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use std::sync::Arc;
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use serde::{Deserialize, Serialize};
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use vm_memory::bitmap::AtomicBitmap;
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use vm_memory::{GuestAddress, MmapRegion};
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mod bus;
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pub mod dma_mapping;
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pub mod interrupt;
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pub use self::bus::{Bus, BusDevice, BusDeviceSync, Error as BusError};
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/// Type of Message Signalled Interrupt
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#[derive(Copy, Clone, Debug, PartialEq, Eq, Serialize, Deserialize)]
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pub enum MsiIrqType {
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/// PCI MSI IRQ numbers.
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PciMsi,
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/// PCI MSIx IRQ numbers.
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PciMsix,
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/// Generic MSI IRQ numbers.
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GenericMsi,
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}
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#[derive(Copy, Clone, PartialEq, Eq, Serialize, Deserialize, Debug)]
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pub enum PciBarType {
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Io,
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Mmio32,
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Mmio64,
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}
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/// Enumeration for device resources.
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#[allow(missing_docs)]
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#[derive(Clone, Debug, Serialize, Deserialize)]
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pub enum Resource {
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/// IO Port address range.
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PioAddressRange { base: u16, size: u16 },
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/// Memory Mapped IO address range.
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MmioAddressRange { base: u64, size: u64 },
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/// PCI BAR
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PciBar {
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index: usize,
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base: u64,
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size: u64,
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type_: PciBarType,
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prefetchable: bool,
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},
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/// Legacy IRQ number.
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LegacyIrq(u32),
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/// Message Signaled Interrupt
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MsiIrq {
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ty: MsiIrqType,
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base: u32,
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size: u32,
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},
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/// Network Interface Card MAC address.
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MacAddress(String),
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/// KVM memslot index.
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KvmMemSlot(u32),
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}
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#[derive(Clone)]
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pub struct UserspaceMapping {
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pub mem_slot: u32,
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pub addr: GuestAddress,
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pub mapping: Arc<MmapRegion<AtomicBitmap>>,
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pub mergeable: bool,
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}
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