diff --git a/cpumf/Makefile b/cpumf/Makefile index e97f20d3..2b581132 100644 --- a/cpumf/Makefile +++ b/cpumf/Makefile @@ -1,67 +1,30 @@ -#!/usr/bin/make -f - include ../common.mak +TESTS := tests/ -CPUMF_DATADIR = $(TOOLS_DATADIR)/cpumf -DATA_FILES = cpum-cf-hw-counter.map \ - cpum-cf-cfvn-1.ctr cpum-cf-cfvn-3.ctr \ - cpum-cf-csvn-12345.ctr cpum-cf-csvn-6.ctr \ - cpum-cf-extended-z10.ctr cpum-cf-extended-z196.ctr \ - cpum-cf-extended-zEC12.ctr cpum-sf-modes.ctr \ - cpum-cf-extended-z13.ctr cpum-cf-extended-z14.ctr \ - cpum-cf-extended-z15.ctr -LIB_FILES = bin/cpumf_helper -USRBIN_SCRIPTS = bin/lscpumf -USRSBIN_SCRIPTS = bin/chcpumf +BIN_FILES = lscpumf chcpumf MAN_FILES = lscpumf.1 chcpumf.8 -all: +all: $(BIN_FILES) -scripts: $(USRBIN_SCRIPTS) $(USRSBIN_SCRIPTS) $(LIB_FILES) - chmod +x $(USRBIN_SCRIPTS) $(USRSBIN_SCRIPTS) $(LIB_FILES) +libs = $(rootdir)/libutil/libutil.a -check: +lscpumf: lscpumf.o $(libs) +chcpumf: chcpumf.o $(libs) -install: scripts install-man - for prg in $(USRBIN_SCRIPTS); do \ - $(INSTALL) -g $(GROUP) -o $(OWNER) -m 755 $$prg $(DESTDIR)$(USRBINDIR) ; \ - done - for prg in $(USRSBIN_SCRIPTS); do \ - $(INSTALL) -g $(GROUP) -o $(OWNER) -m 755 $$prg $(DESTDIR)$(USRSBINDIR) ; \ - done - test -d $(DESTDIR)$(CPUMF_DATADIR) || mkdir -p $(DESTDIR)$(CPUMF_DATADIR) - for lib in $(LIB_FILES); do \ - $(INSTALL) -g $(GROUP) -o $(OWNER) -m 755 $$lib $(DESTDIR)$(TOOLS_LIBDIR) ; \ - done - for data in $(DATA_FILES); do \ - $(INSTALL) -g $(GROUP) -o $(OWNER) -m 644 data/$$data $(DESTDIR)$(CPUMF_DATADIR) ; \ +install: all install-man + $(INSTALL) -d -m 755 $(DESTDIR)$(BINDIR) $(DESTDIR)$(MANDIR)/man8 + for binf in $(BIN_FILES); do \ + $(INSTALL) -g $(GROUP) -o $(OWNER) -m 755 $$binf $(DESTDIR)$(BINDIR); \ done +clean: + rm -f *.o *~ $(BIN_FILES) core + install-man: for man in $(MAN_FILES); do \ msection=`echo $$man |sed 's/.*\.\([1-9]\)$$/man\1/'` ; \ $(INSTALL) -g $(GROUP) -o $(OWNER) -m 644 -D man/$$man $(DESTDIR)$(MANDIR)/$$msection/$$man ; \ done -man2pdf: - for man in $(MAN_FILES); do \ - man -t man/$$man |ps2pdf -sPAPERSIZE=a4 - man/$${man}.pdf ; \ - done -man2text: - for man in $(MAN_FILES); do \ - MANWIDTH=80 LANG=C man man/$$man |col -b |expand > man/$${man}.txt ; \ - done - -clean: - rm -f $(LIB_FILES) $(USRBIN_SCRIPTS) $(USRSBIN_SCRIPTS) - -%: %.in - real_libdir=$(TOOLS_LIBDIR); \ - real_cpumfdatadir=$(CPUMF_DATADIR); \ - $(SED) -e "s#@lib_path@#$$real_libdir#g" \ - -e "s#@cpumfdata_path@#$$real_cpumfdatadir#g" \ - -e 's#@S390_TOOLS_RELEASE@#$(S390_TOOLS_RELEASE)#g' \ - < $< > $@ - -.PHONY: all scripts install install-man man2pdf man2text clean +.PHONY: all install clean diff --git a/cpumf/bin/chcpumf.in b/cpumf/bin/chcpumf.in deleted file mode 100644 index f1ff3171..00000000 --- a/cpumf/bin/chcpumf.in +++ /dev/null @@ -1,182 +0,0 @@ -#!/usr/bin/perl -W -# -# chcpumf - Control CPU-measurement facilities -# -# Copyright IBM Corp. 2014, 2017 -# -# s390-tools is free software; you can redistribute it and/or modify -# it under the terms of the MIT license. See LICENSE for details. -# -use strict; -use warnings; -use File::Basename qw/fileparse/; -use Data::Dumper; -use Getopt::Long qw/:config no_ignore_case/; - -# Global constants -my $CPUMF_HELPER = '@lib_path@/cpumf_helper'; -my $CPUM_SFB_SIZE = '/sys/module/kernel/parameters/cpum_sfb_size'; - -# Prototypes -sub main(); -sub show_help(); -sub show_version(); -sub do_set_sfb_size($); -sub cpumf_set_sfb_size($); -sub invoke_cpumf_helper($); - -sub main() -{ - my $config = { - # Internal data - cpumf => {}, # CPU-MF information hash - }; - - unless (GetOptions( - # General options for help, version, verbose,... - "h|help" => \&show_help, - "v|version" => \&show_version, - "V|verbose+" => \$config->{verbose}, - # Change specific options - "m|min=i" => \$config->{min}, - "x|max=i" => \$config->{max}, - )) { - print STDERR "One or more options are not valid\n"; - print STDERR "Try '" . fileparse($0) . - " --help' for more information\n"; - exit 1; - } - - # Collect CPU-MF information - $config->{cpumf} = invoke_cpumf_helper("-i"); - die "Failed to collect CPU-MF information: $!\n" unless $config->{cpumf}; - - # Process parameters - my $exitval = 5; - if (defined($config->{min}) || defined($config->{max})) { - $exitval = do_set_sfb_size($config); - } else { - print STDERR "You must specify a valid option\n"; - exit 1; - } - - exit($exitval); -} - -sub show_help() -{ - my $prog = fileparse($0); - - print <<"EoHelp"; -Usage: chcpumf -h|-v - chcpumf -m - chcpumf -x - -Options: - -m Specifies the initial size of the sampling buffer. - A sample-data-block (SDB) consumes about 4 kilobytes. - -x Specifies the maximum size of the sampling buffer. - A sample-data-block (SDB) consumes about 4 kilobytes. - -h Displays help information, then exits. - -v Displays version information, then exits. - -For more help information, issue 'man $prog'. -EoHelp - exit 0; -} - -sub show_version() -{ - print <<'EoVersion'; -CPU-measurement facility utilities, version @S390_TOOLS_RELEASE@ -Copyright IBM Corp. 2014, 2017 - -EoVersion - exit 0; -} - -sub cpumf_set_sfb_size($) -{ - my @size = @{shift()}; - my $val = join ',', @size[0,1]; - my ($SFBSIZE, $rc); - - return undef unless open($SFBSIZE, '>', $CPUM_SFB_SIZE); - # Check the return code of print and close to detect error conditions - # reported by the device driver. Because perl might buffer data, print - # might be successful, but close might then report the error condition. - # So check the return code of both functions and always close the file - # handle. - $rc = print { $SFBSIZE } "$val\n"; - unless ($rc) { - close($SFBSIZE); - return $rc; - } - return close($SFBSIZE); -} - -sub do_set_sfb_size($) -{ - my $c = shift(); - my $size; - - # Check if sampling facility is available - unless (exists $c->{cpumf}->{sf}) { - print STDERR "No CPU-measurement sampling facility detected\n"; - return 2; - } - # Check if perf support is available - unless (exists $c->{cpumf}->{sf}->{perf}) { - print STDERR "No perf support for the CPU-measurement" . - " sampling facility availalble\n"; - return 2; - } - - # Optionally, change the sampling buffer sizes - if (defined($c->{min}) || defined($c->{max})) { - $size = invoke_cpumf_helper("--sfb-size"); - # Use current size value for zero min/max specifications - $size->[0] = $c->{min} if defined($c->{min}); - $size->[1] = $c->{max} if defined($c->{max}); - # Validate new settings - if ($size->[0] < 1 || $size->[1] < 1) { - die "The specified number(s) are not valid\n"; - } - if ($size->[0] >= $size->[1]) { - die "The specified maximum must be greater " . - "than the minimum\n"; - } - # Set new sampling buffer sizes - unless (cpumf_set_sfb_size($size)) { - die "Failed to change sampling buffer size: $!\n"; - } - } - - # Finally, show sampling buffer sizes - if ($c->{verbose}) { - $size = invoke_cpumf_helper("--sfb-size"); - print "Sampling buffer sizes:\n"; - printf " Minimum: %6u sample-data-blocks\n", $size->[0]; - printf " Maximum: %6u sample-data-blocks\n", $size->[1]; - } - - return 0; -} - -sub invoke_cpumf_helper($) -{ - my $parms = shift(); - my $result; - - # Call helper module - my $output = qx"$CPUMF_HELPER $parms"; - die "Failed to run helper module for '$parms'\n" if $? >> 8; - $result = eval "$output"; - die "Failed to parse helper module data\n" if $@; - - return $result; -} - -&main(); -__DATA__ -__END__ diff --git a/cpumf/bin/cpumf_helper.in b/cpumf/bin/cpumf_helper.in deleted file mode 100755 index 988f2dee..00000000 --- a/cpumf/bin/cpumf_helper.in +++ /dev/null @@ -1,489 +0,0 @@ -#!/usr/bin/perl -W -# -# cpumf_helper - Helper module for managing CPU-measurement facilities (CPU-MF) -# -# Copyright IBM Corp. 2014, 2017 -# -# s390-tools is free software; you can redistribute it and/or modify -# it under the terms of the MIT license. See LICENSE for details. -# -use strict; -use warnings; -use Carp qw/croak/; -use Data::Dumper; -use Getopt::Long qw/:config no_ignore_case/; - -# Global constants -my $SERVICE_LEVELS = '/proc/service_levels'; -my $CPUMF_DATA_DIR = '@cpumfdata_path@'; -my $CPUM_SFB_SIZE = '/sys/module/kernel/parameters/cpum_sfb_size'; -my $CPUM_SF_DBF='/sys/kernel/debug/s390dbf/cpum_sf'; - -# Counter set bits (according to QUERY COUNTER INFORMATION) -my $BASIC_SET = 0x0002; -my $PROBLEM_STATE_SET = 0x0004; -my $CRYPTO_SET = 0x0008; -my $EXTENTED_SET = 0x0001; -my $MT_DIAG_SET = 0x0020; -my $COPROC_GRP_SET = 0x8000; - - -# Public prototypes -sub cpumf_collect_data(); -sub cpumf_get_sfb_size(); -sub cpumf_set_sfb_size($); -sub cpumf_parse_ctrdef($;$); -sub cpumf_load_ctrdef($;$); -sub cpumf_get_counter_set($); -sub cpumf_counter_set_names(); -sub cpumf_counter_set_ids(); -sub cpumf_hardware_counter_map(); - -# Internal prototypes -sub cpumf_parse_cf($$); -sub cpumf_parse_sf($$); - - -sub cpumf_get_sfb_size() -{ - my $val = "0,0"; - my $SFBSIZE; - - if (open($SFBSIZE, '<', $CPUM_SFB_SIZE)) { - $val = <$SFBSIZE>; - chomp($val); - close($SFBSIZE); - } - - return [split /,/, $val]; -} - -sub cpumf_set_sfb_size($) -{ - my @size = @{shift()}; - my $val = join ',', @size[0,1]; - my ($SFBSIZE, $rc); - - return undef unless open($SFBSIZE, '>', $CPUM_SFB_SIZE); - # Check the return code of print and close to detect error conditions - # reported by the device driver. Because perl might buffer data, print - # might be successful, but close might then report the error condition. - # So check the return code of both functions and always close the file - # handle. - $rc = print { $SFBSIZE } "$val\n"; - unless ($rc) { - close($SFBSIZE); - return $rc; - } - return close($SFBSIZE); -} - - -sub cpumf_parse_cf($$) -{ - my ($ent, $data) = @_; - - if ($ent =~ /version=([0-9.]+) authorization=([[:xdigit:]]+)/) { - $data->{cf} = { version => $1, auth => hex($2) }; - } -} - -sub cpumf_parse_sf($$) -{ - my ($ent, $data) = @_; - - # Parse common sampling facility entry - if ($ent =~ /min_rate=(\d+) max_rate=(\d+) cpu_speed=(\d+)/) { - $data->{sf} = { - min_sampl_interval => $1, - max_sampl_interval => $2, - cpu_speed => $3, - # This contains a list of authorized sampling modes, for - # example, basic - modes => {}, - }; - } - - # Parse sampling facility mode entries - if ($ent =~ /mode=(\w+) sample_size=(\d+)/) { - $data->{sf}->{modes}->{$1}->{sample_size} = $2; - } -} - -sub cpumf_collect_data() -{ - my $SL; - - # Collect CPU-MF information from /proc/service_levels - return undef unless open($SL, '<', $SERVICE_LEVELS); - my @sl = <$SL>; - chomp(@sl); - close($SL); - - # Process CPU-MF information and build data hash - my $data = {}; - foreach my $ent (@sl) { - $ent =~ s/^CPU-MF: // or next; - cpumf_parse_cf($ent, $data) if $ent =~ s/Counter facility: //; - cpumf_parse_sf($ent, $data) if $ent =~ s/Sampling facility: //; - } - - # Collect perf support for available facilities - if (-e '/sys/bus/event_source/devices/cpum_cf') { - $data->{cf}->{perf} = "cpum_cf" if exists $data->{cf}; - } - if (-e '/sys/bus/event_source/devices/cpum_sf') { - $data->{sf}->{perf} = "cpum_sf" if exists $data->{sf}; - } - - return $data; -} - -# Parse the specified counter definition file and returns a hash containing -# the parsed counter definition. The optional argument specifies a hash -# reference to which the new definitions are added. This reference is returned. -sub cpumf_parse_ctrdef($;$) -{ - my $ctrdef = shift(); - my $h = @_ ? shift() : {}; - my $CTRDEF; - - return undef unless open($CTRDEF, '<', "$CPUMF_DATA_DIR/$ctrdef"); - my ($ctr, $name); - while (my $line = <$CTRDEF>) { - next if $line =~ /^#/; - chomp($line); - - # Parse start of counter definition entry - if ($line =~ m/^Counter:\s*(0x[[:xdigit:]]+|\d+) - \s+Name:\s*([[:alnum:]_]+)$/x) { - ($ctr, $name) = ($1, $2); - $ctr = hex($ctr) if $ctr =~ /^0x/; - unless (length($ctr)) { - print STDERR "Found invalid entry in counter " . - "definition: line $.\n"; - } - $h->{$ctr} = { name => $name || "" }; - } - - # At this point, a counter must be defined - next unless defined($ctr); - - # Parse short description (optional) - if ($line =~ m/^Short-Description:\s*(\S.*)?$/) { - $h->{$ctr}->{shortdesc} = $1 || ""; - - # Parse start of counter description - } elsif ($line =~ m/^Description:\s*(\S.*)?$/) { - $h->{$ctr}->{desc} = $1 || ""; - - # Parse end of counter description - } elsif ($line =~ m/^\.$/) { - # Complete the counter definition - $h->{$ctr}->{set} = cpumf_get_counter_set($ctr); - # Trim whitespaces - $h->{$ctr}->{shortdesc} =~ s/^\s+|\s+$//g if $h->{$ctr}->{shortdesc}; - $h->{$ctr}->{desc} =~ s/^\s+|\s+$//g if $h->{$ctr}->{desc}; - # Finally, reset counter for next entry - $ctr = undef; - - # Line is part of counter description (if $ctr_num is set) - } else { - $h->{$ctr}->{desc} .= " $line"; - } - } - close($CTRDEF); - - return $h; -} - -# IBM System z hardware with CPU-M counter facility support -my $system_z_hwtype_map = { - # Machine type Description - '' => 'Unknown hardware model', - 2097 => 'IBM System z10 EC', - 2098 => 'IBM System z10 BC', - 2817 => 'IBM zEnterprise 196', - 2818 => 'IBM zEnterprise 114', - 2827 => 'IBM zEnterprise EC12', - 2828 => 'IBM zEnterprise BC12', - 2964 => 'IBM z13', - 2965 => 'IBM z13s', - 3906 => 'IBM z14', - 3907 => 'IBM z14 ZR1', - 8561 => 'IBM z15', -}; - -sub get_hardware_type() -{ - my $type = ""; - my $SYSINFO; - - return undef unless open($SYSINFO, '<', '/proc/sysinfo'); - while (my $line = <$SYSINFO>) { - if ($line =~ m/^Type:\s*(\d+)\s*$/) { - $type = $1; - last; - } - } - close($SYSINFO); - return $type; -} - -sub get_cpum_cf_version() -{ - my $SL; - - my $v = { - cfvn => 0, - csvn => 0, - }; - - return $v unless open($SL, '<', $SERVICE_LEVELS); - while (my $line = <$SL>) { - # CPU-MF: Counter facility: version=3.5 - if ($line =~ m/^CPU-MF: Counter facility: version=(\d+)\.(\d+)/) { - $v->{cfvn} = $1; # Counter First Version Number - $v->{csvn} = $2; # Counter Second Version Number - last; - } - } - close($SL); - return $v -} - -sub cpumf_load_ctrdef($;$) -{ - my $hw_type = shift(); - my $authorized = @_ ? shift() : 0xffff; # Counter Set authorization - - my $ctrmap = cpumf_hardware_counter_map(); - return unless $ctrmap; - - # Obtain CPU-MF counter facility versions - my $version = get_cpum_cf_version(); - - # List of "generic" counter sets - my @def = (); - push @def, "cfvn-" . $version->{cfvn}; - if ($version->{csvn} >= 1 && $version->{csvn} <= 6) { - push @def, "csvn-12345"; - } - if ($version->{csvn} == 6) { - push @def, "csvn-6"; - } - - my $h = {}; - # Load counter set definition - foreach my $ent (@def) { - cpumf_parse_ctrdef($ctrmap->{$ent}, $h) or - croak "Failed to read counter definition for $ent: $!\n"; - } - # Load hardware model specific counter set(s) - if ($hw_type && $ctrmap->{$hw_type}) { - # Hardware-model specific counter sets are: - # - Extended Counter Set - # - MT-diagnostic Counter Set - cpumf_parse_ctrdef($ctrmap->{$hw_type}, $h) or - croak "Failed to read hardware-model counter definition: $!\n"; - } - - # Remove counter sets that miss authorizations - my @no_auth_list = (); - foreach my $ctr (sort keys %$h) { - push @no_auth_list, $ctr unless $h->{$ctr}->{set} & $authorized; - } - delete $h->{$_} foreach (@no_auth_list); - - return $h; -} - - -sub cpumf_get_counter_set($) -{ - my $ctr = shift(); - - return $BASIC_SET if $ctr < 32; - return $PROBLEM_STATE_SET if $ctr < 64; - return $CRYPTO_SET if $ctr < 128; - # - # The extended counter set ranges from - # 128 to - # 159 for csvn == 1 - # 175 for csvn == 2 - # 255 for csvn > 2 - # Tolerate any future counters up to - # the MT-diagnostic counter set. - return $EXTENTED_SET if $ctr < 448; - # - # The MT-diagnostic counter set ranges from - # 448 to - # 495 for cvsn > 3 - return $MT_DIAG_SET if $ctr <= 495; - return 0; -} - -sub cpumf_counter_set_names() -{ - return { - # Identifier Name - $BASIC_SET => 'Basic Counter Set', - $PROBLEM_STATE_SET => 'Problem-State Counter Set', - $CRYPTO_SET => 'Crypto-Activity Counter Set', - $EXTENTED_SET => 'Extended Counter Set', - $MT_DIAG_SET => 'MT-diagnostic Counter Set', - $COPROC_GRP_SET => 'Coprocessor Group Counter Set', - }; -} - -sub cpumf_counter_set_ids() -{ - return [$BASIC_SET, $PROBLEM_STATE_SET, $CRYPTO_SET, $EXTENTED_SET, - $MT_DIAG_SET, $COPROC_GRP_SET]; -} - -sub cpumf_hardware_counter_map() -{ - my $map = do "$CPUMF_DATA_DIR/cpum-cf-hw-counter.map"; - croak "Failed to parse mapfile: $@" if $@; - croak "Failed to read mapfile: $!" unless defined $map; - return $map; -} - -my $cpumf_helper_str = <<'END_MESSAGE'; - -cpumf_helper - Helper module for managing CPU-Measurement Facilities (CPU-MF) - -Options: --i, --info: - Displays detailed information about installed and available - CPU-measurement facilities and the related Linux support. - --c, --counter authorization_value - Displays counter information for the current System z hardware. - The authorization value provides information about the authorized - counter sets. The value must be specified in decimal format. - - To display all supported counters, specify C<65535> (FFFF hex). - - To display supported counters for a particular System z hardware, - use the --ctr-def option and specify the System z hardware type. - ---hardware-type - Displays the System z hardware type. - ---ctr-def ctr-definition - Displays detailed information about the specified counter definition. - Valid counter definitions start with C or followed by - the counter first/second version number of the CPU-Measurement Counter - Facility. To display counter information of model-specific counter - sets, specify the System z hardware type for I. - ---ctr-set-names - Displays the mapping of counter set IDs to counter set names. - The counter set IDs are numbers that are used in counter definitions. - ---ctr-set-ids - Displays the counter set IDs. The counter set IDs are numbers that - match the authorization bits (see QUERY COUNTER INFORMATION). - The output format is a list. To get the ID for a particular counter - set, use an index number as follows: - - 0: Basic Counter Set - 1: Problem-State Counter Set - 2: Crypto-Activity Counter Set - 3: Extended Counter Set - 4: MT-diagnostic Counter Set - 5: Coprocessor Group Counter Set - ---ctr-sf - Displays the counter definitions for the sampling facility support. - These counter definitions are specific to Linux perf infrastructure. - ---sfb-size - Displays the size of the sampling facility buffer (SFB). The minimum - and maximum numbers are measured in units of sample-data-blocks. A - sample-data-block uses about 4 kilobytes. - -END_MESSAGE - -sub cpumf_helper_main() -{ - # Configuration settings and options - my $conf = { - }; - - # Parse command line option - GetOptions( - "i|info" => \$conf->{opt_info}, - "c|counter=i" => \$conf->{opt_ctr}, - "ctr-def=s" => \$conf->{opt_ctrdef}, - "hardware-type" => \$conf->{opt_hwtype}, - "ctr-set-names" => \$conf->{opt_ctrset_names}, - "ctr-set-ids" => \$conf->{opt_ctrset_ids}, - "sfb-size" => \$conf->{opt_sfb_size}, - "ctr-sf" => \$conf->{opt_sf_ctr}, - ) or die("One or more options are not valid\n" . $cpumf_helper_str); - - - # Setting up Data::Dumper to create parseable Perl output - local $Data::Dumper::Purity = 1; - local $Data::Dumper::Sortkeys = 1; - local $Data::Dumper::Terse = 1; - - ###print STDERR "CONF: " . Dumper($conf) . "\n"; - - # Process command line options - my $exitval = 0; - my $result; - if (defined($conf->{opt_info})) { - $result = cpumf_collect_data(); - - # Display System z hardware type - } elsif (defined($conf->{opt_hwtype})) { - my $type = get_hardware_type(); - $result = [$type, $system_z_hwtype_map->{$type} || ""]; - - # Display counters for current System z hardware - } elsif (defined($conf->{opt_ctr})) { - my $type = get_hardware_type(); - $type = 0 unless $type; - $result = cpumf_load_ctrdef($type, $conf->{opt_ctr}); - - # Display counters for a particular System z hardware type - } elsif (defined($conf->{opt_ctrdef})) { - my $m = cpumf_hardware_counter_map(); - if (exists $m->{$conf->{opt_ctrdef}}) { - $result = cpumf_parse_ctrdef($m->{$conf->{opt_ctrdef}}); - } else { - printf STDERR "Invalid counter definition\n"; - $exitval = 2; - } - # Display the size of the sampling facility buffer (sfb) - } elsif (defined($conf->{opt_sfb_size})) { - $result = cpumf_get_sfb_size(); - - # Display counter definitions for the sampling facility support (perf) - } elsif (defined($conf->{opt_sf_ctr})) { - $result = cpumf_parse_ctrdef('cpum-sf-modes.ctr'); - - # Display mapping of counter set IDs to counter set names - } elsif (defined($conf->{opt_ctrset_names})) { - $result = cpumf_counter_set_names(); - - # Display counter set IDs - } elsif (defined($conf->{opt_ctrset_ids})) { - $result = cpumf_counter_set_ids(); - - } else { - die("No option specified\n" . $cpumf_helper_str); - } - - # Display result - print Dumper($result) if $result; - exit $exitval; -} - -&cpumf_helper_main(); -__DATA__ -__END__ diff --git a/cpumf/bin/lscpumf.in b/cpumf/bin/lscpumf.in deleted file mode 100644 index c7058657..00000000 --- a/cpumf/bin/lscpumf.in +++ /dev/null @@ -1,387 +0,0 @@ -#!/usr/bin/perl -W -# -# lscpumf - Display information about CPU-measurement facilities -# -# Copyright IBM Corp. 2014, 2017 -# -# s390-tools is free software; you can redistribute it and/or modify -# it under the terms of the MIT license. See LICENSE for details. -# -use strict; -use warnings; -use Data::Dumper; -use File::Basename qw/fileparse/; -use Getopt::Long qw/:config no_ignore_case/; - -# Global constants -my $CPUMF_HELPER = '@lib_path@/cpumf_helper'; - -# Prototypes -sub main(); -sub show_help(); -sub show_version(); -sub do_show_info($); -sub do_show_cf($); -sub do_show_sf($); -sub do_show_ctr($;$); -sub do_show_sf_events($); -sub invoke_cpumf_helper($); - - -sub main() -{ - my $config = { - # Internal data - cpumf => {}, # CPU-MF information hash - }; - - unless (GetOptions( - # General options for help, version,... - "h|help" => \&show_help, - "v|version" => \&show_version, - # Display options - "i|info" => \$config->{opt_info}, - "c|list-counters" => \$config->{opt_ctr}, - "C|list-all-counters" => \$config->{opt_ctr_all}, - "s|list-sampling-events" => \$config->{opt_ctr_sf}, - )) { - print STDERR "One or more options are not valid\n"; - print STDERR "Try '" . fileparse($0) . - " --help' for more information\n"; - exit 1; - } - - # Collect CPU-MF information - $config->{cpumf} = invoke_cpumf_helper("-i"); - die "Failed to collect CPU-MF information: $!\n" unless $config->{cpumf}; - - # Process parameters - my $exitval = 5; - if (defined($config->{opt_info})) { - do_show_cf($config); - do_show_sf($config); - $exitval = 0; - - } elsif (defined($config->{opt_ctr})) { - $exitval = do_show_ctr($config); - } elsif (defined($config->{opt_ctr_all})) { - $exitval = do_show_ctr($config, "all") - } elsif (defined($config->{opt_ctr_sf})) { - $exitval = do_show_sf_events($config); - } else { - $exitval = do_show_info($config); - } - - exit($exitval); -} - -sub show_help() -{ - my $prog = fileparse($0); - - print <<"EoHelp"; -Usage: lscpumf -h|-v - lscpumf [-i] - lscpumf -c|-C - -Options: - -i Displays detailed information. - -c Lists counters for which the LPAR is authorized. - -C Lists counters regardless of LPAR authorization. - -s Lists perf raw events that activate the sampling facility. - -h Displays help information, then exits. - -v Displays version information, then exits. - -For more help information, issue 'man $prog'. -EoHelp - exit 0; -} - -sub show_version() -{ - print <<'EoVersion'; -CPU-measurement facility utilities, version @S390_TOOLS_RELEASE@ -Copyright IBM Corp. 2014, 2017 - -EoVersion - exit 0; -} - -sub do_show_info($) -{ - my $c = shift(); - my $cpumf = $c->{cpumf}; - my @f = (); - - push @f, "CPU-measurement Counter Facility" if exists $cpumf->{cf}; - push @f, "CPU-measurement Sampling Facility" if exists $cpumf->{sf}; - - if (@f) { - print((join "\n", @f) . "\n"); - } else { - print STDERR "No CPU-measurement facilities detected\n"; - return 2; - } - return 0; -} - -sub do_show_cf($) -{ - my $c = shift(); - - # Check if counter facility is available - unless (exists $c->{cpumf}->{cf}) { - print STDERR "No CPU-measurement counter facility detected\n"; - return 2; - } - - # Retrieve counter facility information - my $cf = $c->{cpumf}->{cf}; - - # Create list of authorized counter sets - my @sets = (); - push @sets, "None" unless $cf->{auth}; - push @sets, "Crypto-Activity counter set" if $cf->{auth} & 0x8; - push @sets, "Problem-State counter set" if $cf->{auth} & 0x4; - push @sets, "Basic counter set" if $cf->{auth} & 0x2; - push @sets, "Extented counter set" if $cf->{auth} & 0x1; - push @sets, "MT-diagnostic counter set" if $cf->{auth} & 0x20; - - print "CPU-measurement counter facility\n"; - print "-" x 74 . "\n"; - # TODO Display additional information about available conters depending - # on the version information - print "Version: " . $cf->{version} . "\n"; - print "\n"; - print "Authorized counter sets:\n"; - print " $_\n" foreach (sort @sets); - printf "\nLinux perf event support: %s\n\n", - exists $cf->{perf} ? "Yes (PMU: $cf->{perf})" : "No"; - - return 0; -} - -sub div_ceil($$) -{ - my ($a, $b) = @_; - return int(($a + $b - 1) / $b); -} - -sub humanize_bytes($;$) -{ - my $bytes = shift(); - my @units = split //, " KMGTPEZY"; - - my $u = @_ ? shift() : 0; - while ($bytes >= 1024 && $u <= $#units) { - $bytes /= 1024; - $u++; - } - return sprintf "%.f%sB", $bytes, $units[$u]; -} - -sub get_sfb_details($) -{ - my $n_sdb = shift(); - - # Calculate sampling buffer structure - my $n_sdbt = div_ceil($n_sdb, 511); - my $n_pages = $n_sdb + $n_sdbt; - return [ - $n_sdb, # number of sample-data-blocks - $n_sdbt, # number of sample-data-block-tables - $n_pages, # number of 4K pages - $n_pages * 4096, # size in bytes - ]; -} - -sub do_show_sf($) -{ - my $c = shift(); - - # Check if sampling facility is available - unless (exists $c->{cpumf}->{sf}) { - print STDERR "No CPU-measurement sampling facility detected\n"; - return 2; - } - my $sf = $c->{cpumf}->{sf}; - my $size = invoke_cpumf_helper("--sfb-size"); - - # Sampling facility information - print "CPU-measurement sampling facility\n"; - print "-" x 74 . "\n"; - print "Sampling Interval:\n"; - printf " Minimum: %10u cycles (approx. %8u Hz)\n", - $sf->{min_sampl_interval}, - 1000000 * $sf->{cpu_speed} / $sf->{min_sampl_interval}; - printf " Maximum: %10u cycles (approx. %8u Hz)\n", - $sf->{max_sampl_interval}, - 1000000 * $sf->{cpu_speed} / $sf->{max_sampl_interval}; - print "\n"; - print "Authorized sampling modes:\n"; - foreach my $m (sort keys %{$sf->{modes}}) { - printf " %-10s (sample size: %3u bytes)\n", $m, - $sf->{modes}->{$m}->{sample_size}; - } - print "\n"; - printf "\nLinux perf event support: %s\n\n", - exists $sf->{perf} ? "Yes (PMU: $sf->{perf})" : "No"; - - # Sampling buffer settings for cpum_sf - goto out unless exists $sf->{perf}; - - print "Current sampling buffer settings for $sf->{perf}:\n"; - printf " Basic-sampling mode\n"; - my $s = get_sfb_details($size->[0]); - printf " Minimum: %6u sample-data-blocks (%6s)\n", - $s->[0], humanize_bytes($s->[3]); - $s = get_sfb_details($size->[1]); - printf " Maximum: %6u sample-data-blocks (%6s)\n", - $s->[0], humanize_bytes($s->[3]); - unless (exists $sf->{modes}->{diagnostic}) { - goto out; - } - - # Sampling buffer setting specific to diagnostic-sampling mode - my $f_diag = div_ceil($sf->{modes}->{diagnostic}->{sample_size}, - $sf->{modes}->{basic}->{sample_size}); - print "\n"; - printf " Diagnostic-sampling mode (including basic-sampling)\n"; - $s = get_sfb_details($size->[0] * $f_diag); - printf " Minimum: %6u sample-data-blocks (%6s)\n", - $s->[0], humanize_bytes($s->[3]); - $s = get_sfb_details($size->[1] * $f_diag); - printf " Maximum: %6u sample-data-blocks (%6s)\n", - $s->[0], humanize_bytes($s->[3]); - printf " Size factor: %2u\n", $f_diag; -out: - return 0; -} - -sub print_counters($$) -{ - my ($ctrdef, $header) = @_; - my $set_name_map = invoke_cpumf_helper('--ctr-set-names'); - my $out = []; - - my ($ctr_perf, $ctr_num, $set, $name, $desc); - format PERF_CTR_FORM = -r@<<<< @<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< -$ctr_perf, $name - - ^<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< - $desc - ^<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< ~~ - $desc - @<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< - $set - -. - print $header; - $~ = "PERF_CTR_FORM"; - foreach my $ctr (sort { $a <=> $b } keys %$ctrdef) { - $ctr_perf = sprintf "%x", $ctr; - $ctr_num = $ctr < (1 << 16) ? $ctr : ""; - $name = $ctrdef->{$ctr}->{name}; - $desc = $ctrdef->{$ctr}->{shortdesc} ? - $ctrdef->{$ctr}->{shortdesc} - : $ctrdef->{$ctr}->{desc}; - $desc .= "."; - $set = $set_name_map->{$ctrdef->{$ctr}->{set}}; - if ($set) { - $set = "Counter $ctr_num / $set."; - } else { - $set = "This event is not associated with a counter set."; - } - write; - } -} - -sub do_show_ctr($;$) -{ - my $c = shift(); - - # Check if counter facility is available - unless (exists $c->{cpumf}->{cf}) { - print STDERR "No CPU-measurement counter facility detected\n"; - return 2; - } - - # Retrieve counter authorization ("all" or authorized counters only) - my $auth = @_ ? hex("0xFFFF") : $c->{cpumf}->{cf}->{auth}; - - # Retrieve counter information - my $ctrs = invoke_cpumf_helper("-c $auth"); - unless ($ctrs) { - print STDERR "No counters are available or authorized\n"; - return 3; - } - - # Retrieve hardware type - my $hwtype = invoke_cpumf_helper("--hardware-type"); - my $model = length $hwtype->[1] ? "for $hwtype->[1]" : ""; - my $header = <<"EoHeader"; -Perf event counter list $model -============================================================================== - -Raw -event Name Description ------------------------------------------------------------------------------- -EoHeader - print_counters($ctrs, $header); - - return 0; -} - -sub do_show_sf_events($) -{ - my $c = shift(); - - # Check if sampling facility is available - unless (exists $c->{cpumf}->{sf}) { - print STDERR "No CPU-measurement sampling facility detected\n"; - return 2; - } - my $sf = $c->{cpumf}->{sf}; - my $events = invoke_cpumf_helper("--ctr-sf"); - - # Remove events with missing authorization - delete $events->{0xB0000} unless exists $sf->{modes}->{basic}; - delete $events->{0xBD000} unless exists $sf->{modes}->{diagnostic}; - - unless ($events) { - print STDERR "Sampling facility is not authorized\n"; - return 3; - } - - # Display sampling facility events (aka. counters) - my $header = <<"EoHeader"; -Perf events for activating the sampling facility -============================================================================== - -Raw -event Name Description ------------------------------------------------------------------------------- -EoHeader - print_counters($events, $header); - - return 0; -} - -sub invoke_cpumf_helper($) -{ - my $parms = shift(); - my $result; - - # Call helper module - my $output = qx"$CPUMF_HELPER $parms"; - die "Failed to run helper module for '$parms'\n" if $? >> 8; - $result = eval "$output"; - die "Failed to parse helper module data\n" if $@; - - return $result; -} - -&main(); -__DATA__ -__END__ diff --git a/cpumf/chcpumf.c b/cpumf/chcpumf.c new file mode 100644 index 00000000..561c121d --- /dev/null +++ b/cpumf/chcpumf.c @@ -0,0 +1,214 @@ +/* + * chcpumf - Change CPU Measurement Facility Characteristics + * + * Copyright IBM Corp. 2020 + * + * s390-tools is free software; you can redistribute it and/or modify + * it under the terms of the MIT license. See LICENSE for details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "lib/util_opt.h" +#include "lib/util_prg.h" +#include "lib/util_base.h" + +#include "defines.h" + +static int verbose; +static unsigned long min_sdb, max_sdb; + +static struct util_opt opt_vec[] = { + UTIL_OPT_SECTION("OPTIONS"), + { + .option = { "min", required_argument, NULL, 'm' }, + .argument = "num_sdb", + .desc = "Specifies the initial size of the sampling buffer.\n" + "A sample-data-block (SDB) consumes about 4 kilobytes.", + }, + { + .option = { "max", required_argument, NULL, 'x' }, + .argument = "num_sdb", + .desc = "Specifies the maximum size of the sampling buffer.\n" + "A sample-data-block (SDB) consumes about 4 kilobytes.", + }, + { + .option = { "verbose", no_argument, NULL, 'V' }, + .desc = "Verbose, display new sample-data-block values.", + }, + UTIL_OPT_HELP, + UTIL_OPT_VERSION, + UTIL_OPT_END +}; + +static const struct util_prg prg = { + .desc = "Change CPU Measurement facility charactertics", + .copyright_vec = { + { + .owner = "IBM Corp.", + .pub_first = 2020, + .pub_last = 2020, + }, + UTIL_PRG_COPYRIGHT_END + } +}; + +/* Parse tool parameters. Fill in global variables keep_case, buffersize and + * command according to parameters. Return VMCP_OK on success, VMCP_OPT + * in case of parameter errors. In case of --help or --version, print + * respective text to stdout and exit. */ +static long parse_buffersize(char *string) +{ + char *suffix; + long bytes; + + bytes = strtol(string, &suffix, 10); + if (strlen(suffix) > 1) + return -1; + switch (*suffix) { + case 'k': + case 'K': + bytes *= 1024; + break; + case 'm': + case 'M': + bytes *= 1048576; + break; + case '\0': + break; + default: + return 0; + } + return bytes; +} + +static int read_sfb(unsigned long *min, unsigned long *max) +{ + int rc = EXIT_SUCCESS; + FILE *fp; + + fp = fopen(PERF_SFB_SIZE, "r"); + if (fp == NULL) { + linux_error(PERF_SFB_SIZE); + return EXIT_FAILURE; + } + if (fscanf(fp, "%ld,%ld", min, max) != 2) { + fprintf(stderr, "Error: Can not parse file " PERF_SFB_SIZE); + rc = EXIT_FAILURE; + } + fclose(fp); + return rc; +} + +static int write_sfb(unsigned long min, unsigned long max) +{ + int rc = EXIT_SUCCESS; + char text[64]; + size_t len; + FILE *fp; + + fp = fopen(PERF_SFB_SIZE, "w"); + if (fp == NULL) { + linux_error(PERF_SFB_SIZE); + return EXIT_FAILURE; + } + snprintf(text, sizeof text, "%ld,%ld", min, max); + len = strlen(text) + 1; + if (fwrite(text, 1, len, fp) != len) { + linux_error(PERF_SFB_SIZE); + rc = EXIT_FAILURE; + } + if (fclose(fp)) { + linux_error(PERF_SFB_SIZE); + rc = EXIT_FAILURE; + } + if (verbose) + fprintf(stderr, "Sampling buffer sizes:\n" + " Minimum:%7ld sample-data-blocks\n" + " Maximum:%7ld sample-data-blocks\n", + min, max); + return rc; +} + +static int parse_args(int argc, char **argv) +{ + int opt, action = 0; + long new; + + while ((opt = util_opt_getopt_long(argc, argv)) != -1) { + switch (opt) { + case 'h': + util_prg_print_help(); + util_opt_print_help(); + exit(EXIT_SUCCESS); + case 'v': + util_prg_print_version(); + exit(EXIT_SUCCESS); + case 'x': + new = parse_buffersize(optarg); + if (new < 1) { + fprintf(stderr, "The specified number(s)" + " are not valid\n"); + exit(EXIT_FAILURE); + } + max_sdb = new; + action = 1; + break; + case 'm': + new = parse_buffersize(optarg); + if (new < 1) { + fprintf(stderr, "The specified number(s)" + " are not valid\n"); + exit(EXIT_FAILURE); + } + min_sdb = new; + action = 1; + break; + case 'V': + verbose = 1; + break; + case '?': + fprintf(stderr, "One or more options are not valid\n"); + fprintf(stderr, "Try 'chcpumf --help' for more" + " information\n"); + exit(EXIT_FAILURE); + } + } + if (!action) { + fprintf(stderr, "You must specify a valid option\n"); + exit(EXIT_FAILURE); + } + return action; +} + +int main(int argc, char **argv) +{ + int ret = EXIT_FAILURE; + struct stat sbuf; + + util_prg_init(&prg); + util_opt_init(opt_vec, NULL); + + if (stat(PERF_PATH PERF_SF, &sbuf) != 0) { + fprintf(stderr, + "No CPU-measurement sampling facility detected\n"); + return ret; + } + if (read_sfb(&min_sdb, &max_sdb)) + return ret; + /* Overwrite min_sdb and/or max_sdb */ + parse_args(argc, argv); + if (min_sdb >= max_sdb) { + fprintf(stderr, "The specified maximum must be greater " + "than the minimum\n"); + return ret; + } + return write_sfb(min_sdb, max_sdb); +} diff --git a/cpumf/data/cpum-cf-cfvn-1.ctr b/cpumf/data/cpum-cf-cfvn-1.ctr deleted file mode 100644 index ed38d27b..00000000 --- a/cpumf/data/cpum-cf-cfvn-1.ctr +++ /dev/null @@ -1,60 +0,0 @@ -Counter: 0 Name:CPU_CYCLES -Short-Description:CPU Cycles -Description: -Cycle Count -. -Counter: 1 Name:INSTRUCTIONS -Short-Description:Instructions -Description: -Instruction Count -. -Counter: 2 Name:L1I_DIR_WRITES -Short-Description:L1I Directory Writes -Description: -Level-1 I-Cache Directory Write Count -. -Counter: 3 Name:L1I_PENALTY_CYCLES -Short-Description:L1I Penalty Cycles -Description: -Level-1 I-Cache Penalty Cycle Count -. -Counter: 4 Name:L1D_DIR_WRITES -Short-Description:L1D Directory Writes -Description: -Level-1 D-Cache Directory Write Count -. -Counter: 5 Name:L1D_PENALTY_CYCLES -Short-Description:L1D Penalty Cycles -Description: -Level-1 D-Cache Penalty Cycle Count -. -Counter: 32 Name:PROBLEM_STATE_CPU_CYCLES -Short-Description:Problem-State CPU Cycles -Description: -Problem-State Cycle Count -. -Counter: 33 Name:PROBLEM_STATE_INSTRUCTIONS -Short-Description:Problem-State Instructions -Description: -Problem-State Instruction Count -. -Counter: 34 Name:PROBLEM_STATE_L1I_DIR_WRITES -Short-Description:Problem-State L1I Directory Writes -Description: -Problem-State Level-1 I-Cache Directory Write Count -. -Counter: 35 Name:PROBLEM_STATE_L1I_PENALTY_CYCLES -Short-Description:Problem-State L1I Penalty Cycles -Description: -Problem-State Level-1 I-Cache Penalty Cycle Count -. -Counter: 36 Name:PROBLEM_STATE_L1D_DIR_WRITES -Short-Description:Problem-State L1D Directory Writes -Description: -Problem-State Level-1 D-Cache Directory Write Count -. -Counter: 37 Name:PROBLEM_STATE_L1D_PENALTY_CYCLES -Short-Description:Problem-State L1D Penalty Cycles -Description: -Problem-State Level-1 D-Cache Penalty Cycle Count -. diff --git a/cpumf/data/cpum-cf-cfvn-3.ctr b/cpumf/data/cpum-cf-cfvn-3.ctr deleted file mode 100644 index df10cba0..00000000 --- a/cpumf/data/cpum-cf-cfvn-3.ctr +++ /dev/null @@ -1,40 +0,0 @@ -Counter: 0 Name:CPU_CYCLES -Short-Description:CPU Cycles -Description: -Cycle Count -. -Counter: 1 Name:INSTRUCTIONS -Short-Description:Instructions -Description: -Instruction Count -. -Counter: 2 Name:L1I_DIR_WRITES -Short-Description:L1I Directory Writes -Description: -Level-1 I-Cache Directory Write Count -. -Counter: 3 Name:L1I_PENALTY_CYCLES -Short-Description:L1I Penalty Cycles -Description: -Level-1 I-Cache Penalty Cycle Count -. -Counter: 4 Name:L1D_DIR_WRITES -Short-Description:L1D Directory Writes -Description: -Level-1 D-Cache Directory Write Count -. -Counter: 5 Name:L1D_PENALTY_CYCLES -Short-Description:L1D Penalty Cycles -Description: -Level-1 D-Cache Penalty Cycle Count -. -Counter: 32 Name:PROBLEM_STATE_CPU_CYCLES -Short-Description:Problem-State CPU Cycles -Description: -Problem-State Cycle Count -. -Counter: 33 Name:PROBLEM_STATE_INSTRUCTIONS -Short-Description:Problem-State Instructions -Description: -Problem-State Instruction Count -. diff --git a/cpumf/data/cpum-cf-csvn-12345.ctr b/cpumf/data/cpum-cf-csvn-12345.ctr deleted file mode 100644 index bbf99d72..00000000 --- a/cpumf/data/cpum-cf-csvn-12345.ctr +++ /dev/null @@ -1,100 +0,0 @@ -Counter: 64 Name:PRNG_FUNCTIONS -Short-Description:PRNG Functions -Description: -Total number of the PRNG functions issued by the CPU -. -Counter: 65 Name:PRNG_CYCLES -Short-Description:PRNG Cycles -Description: -Total number of CPU cycles when the DEA/AES coprocessor is busy -performing PRNG functions issued by the CPU -. -Counter: 66 Name:PRNG_BLOCKED_FUNCTIONS -Short-Description:PRNG Blocked Functions -Description: -Total number of the PRNG functions that are issued by the CPU and are -blocked because the DEA/AES coprocessor is busy performing a function -issued by another CPU -. -Counter: 67 Name:PRNG_BLOCKED_CYCLES -Short-Description:PRNG Blocked Cycles -Description: -Total number of CPU cycles blocked for the PRNG functions issued by -the CPU because the DEA/AES coprocessor is busy performing a function -issued by another CPU -. -Counter: 68 Name:SHA_FUNCTIONS -Short-Description:SHA Functions -Description: -Total number of SHA functions issued by the CPU -. -Counter: 69 Name:SHA_CYCLES -Short-Description:SHA Cycles -Description: -Total number of CPU cycles when the SHA coprocessor is busy performing -the SHA functions issued by the CPU -. -Counter: 70 Name:SHA_BLOCKED_FUNCTIONS -Short-Description:SHA Blocked Functions -Description: -Total number of the SHA functions that are issued by the CPU and are -blocked because the SHA coprocessor is busy performing a function issued -by another CPU -. -Counter: 71 Name:SHA_BLOCKED_CYCLES -Short-Description:SHA Bloced Cycles -Description: -Total number of CPU cycles blocked for the SHA functions issued by the -CPU because the SHA coprocessor is busy performing a function issued -by another CPU -. -Counter: 72 Name:DEA_FUNCTIONS -Short-Description:DEA Functions -Description: -Total number of the DEA functions issued by the CPU -. -Counter: 73 Name:DEA_CYCLES -Short-Description:DEA Cycles -Description: -Total number of CPU cycles when the DEA/AES coprocessor is busy -performing the DEA functions issued by the CPU -. -Counter: 74 Name:DEA_BLOCKED_FUNCTIONS -Short-Description:DEA Blocked Functions -Description: -Total number of the DEA functions that are issued by the CPU and are -blocked because the DEA/AES coprocessor is busy performing a function -issued by another CPU -. -Counter: 75 Name:DEA_BLOCKED_CYCLES -Short-Description:DEA Blocked Cycles -Description: -Total number of CPU cycles blocked for the DEA functions issued by the -CPU because the DEA/AES coprocessor is busy performing a function issued -by another CPU -. -Counter: 76 Name:AES_FUNCTIONS -Short-Description:AES Functions -Description: -Total number of AES functions issued by the CPU -. -Counter: 77 Name:AES_CYCLES -Short-Description:AES Cycles -Description: -Total number of CPU cycles when the DEA/AES coprocessor is busy -performing the AES functions issued by the CPU -. -Counter: 78 Name:AES_BLOCKED_FUNCTIONS -Short-Description:AES Blocked Functions -Description: -Total number of AES functions that are issued by the CPU and are blocked -because the DEA/AES coprocessor is busy performing a function issued -by another CPU -. -Counter: 79 Name:AES_BLOCKED_CYCLES -Short-Description:AES Blocked Cycles -Description: -Total number of CPU cycles blocked for the AES functions issued by the -CPU because the DEA/AES coprocessor is busy performing a function issued -by another CPU -. diff --git a/cpumf/data/cpum-cf-csvn-6.ctr b/cpumf/data/cpum-cf-csvn-6.ctr deleted file mode 100644 index 4ea3b447..00000000 --- a/cpumf/data/cpum-cf-csvn-6.ctr +++ /dev/null @@ -1,33 +0,0 @@ -Counter: 80 Name:ECC_FUNCTION_COUNT -Short-Description:ECC Function Count -Description: -This counter counts the -total number of the elliptic-curve cryptography (ECC) -functions issued by the CPU. -. -Counter: 81 Name:ECC_CYCLES_COUNT -Short-Description:ECC Cycles Count -Description: -This counter counts the total -number of CPU cycles when the ECC coprocessor is -busy performing the elliptic-curve cryptography -(ECC) functions issued by the CPU. -. -Counter: 82 Name:ECC_BLOCKED_FUNCTION_COUNT -Short-Description:Ecc Blocked Function Count -Description: -This counter -counts the total number of the elliptic-curve -cryptography (ECC) functions that are issued by the CPU -and are blocked because the ECC coprocessor is -busy performing a function issued by another CPU. -. -Counter: 83 Name:ECC_BLOCKED_CYCLES_COUNT -Short-Description:ECC Blocked Cycles Count -Description: -This counter counts -the total number of CPU cycles blocked for the elliptic-curve -cryptography (ECC) functions issued by the -CPU because the ECC coprocessor is busy perform- -ing a function issued by another CPU. -. diff --git a/cpumf/data/cpum-cf-extended-z10.ctr b/cpumf/data/cpum-cf-extended-z10.ctr deleted file mode 100644 index c4676e4e..00000000 --- a/cpumf/data/cpum-cf-extended-z10.ctr +++ /dev/null @@ -1,114 +0,0 @@ -Counter: 128 Name:L1I_L2_SOURCED_WRITES -Short-Description:L1I L2 Sourced Writes -Description: -A directory write to the Level-1 I-Cache directory where the returned -cache line was sourced from the Level-2 (L1.5) cache -. -Counter: 129 Name:L1D_L2_SOURCED_WRITES -Short-Description:L1D L2 Sourced Writes -Description: -A directory write to the Level-1 D-Cache directory where the installed -cache line was sourced from the Level-2 (L1.5) cache -. -Counter: 130 Name:L1I_L3_LOCAL_WRITES -Short-Description:L1I L3 Local Writes -Description: -A directory write to the Level-1 I-Cache directory where the installed -cache line was sourced from the Level-3 cache that is on the same book -as the Instruction cache (Local L2 cache) -. -Counter: 131 Name:L1D_L3_LOCAL_WRITES -Short-Description:L1D L3 Local Writes -Description: -A directory write to the Level-1 D-Cache directory where the installtion -cache line was source from the Level-3 cache that is on the same book -as the Data cache (Local L2 cache) -. -Counter: 132 Name:L1I_L3_REMOTE_WRITES -Short-Description:L1I L3 Remote Writes -Description: -A directory write to the Level-1 I-Cache directory where the installed -cache line was sourced from a Level-3 cache that is not on the same -book as the Instruction cache (Remote L2 cache) -. -Counter: 133 Name:L1D_L3_REMOTE_WRITES -Short-Description:L1D L3 Remote Writes -Description: -A directory write to the Level-1 D-Cache directory where the installed -cache line was sourced from a Level-3 cache that is not on the same -book as the Data cache (Remote L2 cache) -. -Counter: 134 Name:L1D_LMEM_SOURCED_WRITES -Short-Description:L1D Local Memory Sourced Writes -Description: -A directory write to the Level-1 D-Cache directory where the installed -cache line was sourced from memory that is attached to the same book -as the Data cache (Local Memory) -. -Counter: 135 Name:L1I_LMEM_SOURCED_WRITES -Short-Description:L1I Local Memory Sourced Writes -Description: -A directory write to the Level-1 I-Cache where the installed cache -line was sourced from memory that is attached to the s ame book as the -Instruction cache (Local Memory) -. -Counter: 136 Name:L1D_RO_EXCL_WRITES -Short-Description:L1D Read-only Exclusive Writes -Description: -A directory write to the Level-1 D-Cache where the line was originally -in a Read-Only state in the cache but has been updated to be in the -Exclusive state that allows stores to the cache line -. -Counter: 137 Name:L1I_CACHELINE_INVALIDATES -Short-Description:L1I Cacheline Invalidates -Description: -A cache line in the Level-1 I-Cache has been invalidated by a store on -the same CPU as the Level-1 I-Cache -. -Counter: 138 Name:ITLB1_WRITES -Short-Description:ITLB1 Writes -Description: -A translation entry has been written into the Level-1 Instruction -Translation Lookaside Buffer -. -Counter: 139 Name:DTLB1_WRITES -Short-Description:DTLB1 Writes -Description: -A translation entry has been written to the Level-1 Data Translation -Lookaside Buffer -. -Counter: 140 Name:TLB2_PTE_WRITES -Short-Description:TLB2 PTE Writes -Description: -A translation entry has been written to the Level-2 TLB Page Table -Entry arrays -. -Counter: 141 Name:TLB2_CRSTE_WRITES -Short-Description:TLB2 CRSTE Writes -Description: -A translation entry has been written to the Level-2 TLB Common Region -Segment Table Entry arrays -. -Counter: 142 Name:TLB2_CRSTE_HPAGE_WRITES -Short-Description:TLB2 CRSTE One-Megabyte Page Writes -Description: -A translation entry has been written to the Level-2 TLB Common Region -Segment Table Entry arrays for a one-megabyte large page translation -. -Counter: 145 Name:ITLB1_MISSES -Short-Description:ITLB1 Misses -Description: -Level-1 Instruction TLB miss in progress. Incremented by one for every -cycle an ITLB1 miss is in progress -. -Counter: 146 Name:DTLB1_MISSES -Short-Description:DTLB1 Misses -Description: -Level-1 Data TLB miss in progress. Incremented by one for every cycle -an DTLB1 miss is in progress -. -Counter: 147 Name:L2C_STORES_SENT -Short-Description:L2C Stores Sent -Description: -Incremented by one for every store sent to Level-2 (L1.5) cache -. diff --git a/cpumf/data/cpum-cf-extended-z13.ctr b/cpumf/data/cpum-cf-extended-z13.ctr deleted file mode 100644 index 52cffa5e..00000000 --- a/cpumf/data/cpum-cf-extended-z13.ctr +++ /dev/null @@ -1,373 +0,0 @@ -# Counter decriptions for the -# IBM z13 extended counter and MT-diagnostic counter set -# -# Notes for transactional-execution mode symbolic names: -# TX .. transactional-execution mode -# NC .. nonconstrained -# C .. constrained -# -# Undefined counters in the extended counter set: -# 142 -# 180-217 -# 221-225 -# Undefined counters in the MT-diagnostic counter set: -# 450-495 -# -# -# Extended Counter Set -# --------------------------------------------------------------------- -Counter:128 Name:L1D_RO_EXCL_WRITES -Short-Description:L1D Read-only Exclusive Writes -Description: -A directory write to the Level-1 Data cache where the line was -originally in a Read-Only state in the cache but has been updated -to be in the Exclusive state that allows stores to the cache line. -. -Counter:129 Name:DTLB1_WRITES -Short-Description:DTLB1 Writes -Description: -A translation entry has been written to the Level-1 Data Translation -Lookaside Buffer -. -Counter:130 Name:DTLB1_MISSES -Short-Description:DTLB1 Misses -Description: -Level-1 Data TLB miss in progress. Incremented by one for every cycle -a DTLB1 miss is in progress. -. -Counter:131 Name:DTLB1_HPAGE_WRITES -Short-Description:DTLB1 One-Megabyte Page Writes -Description: -A translation entry has been written to the Level-1 Data Translation -Lookaside Buffer for a one-megabyte page -. -Counter:132 Name:DTLB1_GPAGE_WRITES -Short-Description:DTLB1 Two-Gigabyte Page Writes -A translation entry has been written to the Level-1 Data Translation -Lookaside Buffer for a two-gigabyte page. -. -Counter:133 Name:L1D_L2D_SOURCED_WRITES -Short-Description:L1D L2D Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from the Level-2 Data cache -. -Counter:134 Name:ITLB1_WRITES -Short-Description:ITLB1 Writes -Description: -A translation entry has been written to the Level-1 Instruction -Translation Lookaside Buffer -. -Counter:135 Name:ITLB1_MISSES -Short-Description:ITLB1 Misses -Description: -Level-1 Instruction TLB miss in progress. Incremented by one for every -cycle an ITLB1 miss is in progress -. -Counter:136 Name:L1I_L2I_SOURCED_WRITES -Short-Description:L1I L2I Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from the Level-2 Instruction cache -. -Counter:137 Name:TLB2_PTE_WRITES -Short-Description:TLB2 PTE Writes -Description: -A translation entry has been written to the Level-2 TLB Page Table -Entry arrays -. -Counter:138 Name:TLB2_CRSTE_HPAGE_WRITES -Short-Description:TLB2 CRSTE One-Megabyte Page Writes -Description: -A translation entry has been written to the Level-2 TLB Combined Region -Segment Table Entry arrays for a one-megabyte large page translation -. -Counter:139 Name:TLB2_CRSTE_WRITES -Short-Description:TLB2 CRSTE Writes -Description: -A translation entry has been written to the Level-2 TLB Combined Region -Segment Table Entry arrays -. -Counter:140 Name:TX_C_TEND -Short-Description:Completed TEND instructions in constrained TX mode -Description: -A TEND instruction has completed in a constrained transactional-execution -mode -. -Counter:141 Name:TX_NC_TEND -Short-Description:Completed TEND instructions in non-constrained TX mode -Description: -A TEND instruction has completed in a non-constrained -transactional-execution mode -. -Counter:143 Name:L1C_TLB1_MISSES -Short-Description:L1C TLB1 Misses -Description: -Increments by one for any cycle where a Level-1 cache or Level-1 TLB miss -is in progress. -. -Counter:144 Name:L1D_ONCHIP_L3_SOURCED_WRITES -Short-Description:L1D On-Chip L3 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an On-Chip Level-3 cache without intervention -. -Counter:145 Name:L1D_ONCHIP_L3_SOURCED_WRITES_IV -Short-Description:L1D On-Chip L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an On-Chip Level-3 cache with intervention -. -Counter:146 Name:L1D_ONNODE_L4_SOURCED_WRITES -Short-Description:L1D On-Node L4 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an On-Node Level-4 cache -. -Counter:147 Name:L1D_ONNODE_L3_SOURCED_WRITES_IV -Short-Description:L1D On-Node L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an On-Node Level-3 cache with intervention -. -Counter:148 Name:L1D_ONNODE_L3_SOURCED_WRITES -Short-Description:L1D On-Node L3 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an On-Node Level-3 cache without intervention -. -Counter:149 Name:L1D_ONDRAWER_L4_SOURCED_WRITES -Short-Description:L1D On-Drawer L4 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an On-Drawer Level-4 cache -. -Counter:150 Name:L1D_ONDRAWER_L3_SOURCED_WRITES_IV -Short-Description:L1D On-Drawer L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an On-Drawer Level-3 cache with intervention -. -Counter:151 Name:L1D_ONDRAWER_L3_SOURCED_WRITES -Short-Description:L1D On-Drawer L3 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an On-Drawer Level-3 cache without intervention -. -Counter:152 Name:L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES -Short-Description:L1D Off-Drawer Same-Column L4 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an Off-Drawer Same-Column Level-4 cache -. -Counter:153 Name:L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV -Short-Description:L1D Off-Drawer Same-Column L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an Off-Drawer Same-Column Level-3 cache with -intervention -. -Counter:154 Name:L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES -Short-Description:L1D Off-Drawer Same-Column L3 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an Off-Drawer Same-Column Level-3 cache -without intervention -. -Counter:155 Name:L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES -Short-Description:L1D Off-Drawer Far-Column L3 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an Off-Drawer Far-Column Level-4 cache -. -Counter:156 Name:L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV -Short-Description:L1D Off-Drawer Far-Column L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an Off-Drawer Far-Column Level-3 cache with -intervention -. -Counter:157 Name:L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES -Short-Description:L1D Off-Drawer Far-Column L3 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an Off-Drawer Far-Column Level-3 cache -without intervention -. -Counter:158 Name:L1D_ONNODE_MEM_SOURCED_WRITES -Short-Description:L1D On-Node Memory Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from On-Node memory -. -Counter:159 Name:L1D_ONDRAWER_MEM_SOURCED_WRITES -Short-Description:L1D On-Drawer Memory Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from On-Drawer memory -. -Counter:160 Name:L1D_OFFDRAWER_MEM_SOURCED_WRITES -Short-Description:L1D Off-Drawer Memory Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from On-Drawer memory -. -Counter:161 Name:L1D_ONCHIP_MEM_SOURCED_WRITES -Short-Description:L1D On-Chip Memory Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from On-Chip memory -. -Counter:162 Name:L1I_ONCHIP_L3_SOURCED_WRITES -Short-Description:L1I On-Chip L3 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an On-Chip Level-3 cache without -intervention -. -Counter:163 Name:L1I_ONCHIP_L3_SOURCED_WRITES_IV -Short-Description:L1I On-Chip L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an On Chip Level-3 cache with -intervention -. -Counter:164 Name:L1I_ONNODE_L4_SOURCED_WRITES -Short-Description:L1I On-Chip L4 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an On-Node Level-4 cache -. -Counter:165 Name:L1I_ONNODE_L3_SOURCED_WRITES_IV -Short-Description:L1I On-Node L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Instruction cache directory where -the returned cache line was sourced from an On-Node Level-3 cache -with intervention -. -Counter:166 Name:L1I_ONNODE_L3_SOURCED_WRITES -Short-Description:L1I On-Node L3 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where -the returned cache line was sourced from an On-Node Level-3 cache -without intervention -. -Counter:167 Name:L1I_ONDRAWER_L4_SOURCED_WRITES -Short-Description:L1I On-Drawer L4 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where -the returned cache line was sourced from an On-Drawer Level-4 cache -. -Counter:168 Name:L1I_ONDRAWER_L3_SOURCED_WRITES_IV -Short-Description:L1I On-Drawer L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Instruction cache directory where -the returned cache line was sourced from an On-Drawer Level-3 cache -with intervention -. -Counter:169 Name:L1I_ONDRAWER_L3_SOURCED_WRITES -Short-Description:L1I On-Drawer L3 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where -the returned cache line was sourced from an On-Drawer Level-3 cache -without intervention -. -Counter:170 Name:L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES -Short-Description:L1I Off-Drawer Same-Column L4 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where -the returned cache line was sourced from an Off-Drawer Same-Column -Level-4 cache -. -Counter:171 Name:L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV -Short-Description:L1I Off-Drawer Same-Column L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Instruction cache directory where -the returned cache line was sourced from an Off-Drawer Same-Column -Level-3 cache with intervention -. -Counter:172 Name:L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES -Short-Description:L1I Off-Drawer Same-Column L3 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where -the returned cache line was sourced from an Off-Drawer Same-Column -Level-3 cache without intervention -. -Counter:173 Name:L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES -Short-Description:L1I Off-Drawer Far-Column L4 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where -the returned cache line was sourced from an Off-Drawer Far-Column -Level-4 cache -. -Counter:174 Name:L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV -Short-Description:L1I Off-Drawer Far-Column L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Instruction cache directory where -the returned cache line was sourced from an Off-Drawer Far-Column -Level-3 cache with intervention -. -Counter:175 Name:L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES -Short-Description:L1I Off-Drawer Far-Column L3 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where -the returned cache line was sourced from an Off-Drawer Far-Column -Level-3 cache without intervention -. -Counter:176 Name:L1I_ONNODE_MEM_SOURCED_WRITES -Short-Description:L1I On-Node Memory Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where -the returned cache line was sourced from On-Node memory -. -Counter:177 Name:L1I_ONDRAWER_MEM_SOURCED_WRITES -Short-Description:L1I On-Drawer Memory Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where -the returned cache line was sourced from On-Drawer memory -. -Counter:178 Name:L1I_OFFDRAWER_MEM_SOURCED_WRITES -Short-Description:L1I Off-Drawer Memory Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where -the returned cache line was sourced from On-Drawer memory -. -Counter:179 Name:L1I_ONCHIP_MEM_SOURCED_WRITES -Short-Description:L1I On-Chip Memory Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where -the returned cache line was sourced from On-Chip memory -. -Counter:218 Name:TX_NC_TABORT -Short-Description:Aborted transactions in non-constrained TX mode -Description: -A transaction abort has occurred in a non-constrained -transactional-execution mode -. -Counter:219 Name:TX_C_TABORT_NO_SPECIAL -Short-Description:Aborted transactions in constrained TX mode not using special completion logic -Description: -A transaction abort has occurred in a constrained transactional-execution -mode and the CPU is not using any special logic to allow the transaction -to complete -. -Counter:220 Name:TX_C_TABORT_SPECIAL -Short-Description:Aborted transactions in constrained TX mode using special completion logic -Description: -A transaction abort has occurred in a constrained transactional-execution -mode and the CPU is using special logic to allow the transaction to -complete -. -# -# MT-diagnostic counter set -# --------------------------------------------------------------------- -Counter:448 Name:MT_DIAG_CYCLES_ONE_THR_ACTIVE -Short-Description:Cycle count with one thread active -Description: -Cycle count with one thread active -. -Counter:449 Name:MT_DIAG_CYCLES_TWO_THR_ACTIVE -Short-Description:Cycle count with two threads active -Description: -Cycle count with two threads active -. diff --git a/cpumf/data/cpum-cf-extended-z14.ctr b/cpumf/data/cpum-cf-extended-z14.ctr deleted file mode 100644 index e9e3f925..00000000 --- a/cpumf/data/cpum-cf-extended-z14.ctr +++ /dev/null @@ -1,357 +0,0 @@ -# Counter decriptions for the -# IBM z14 extended counter and MT-diagnostic counter set -# -# Notes for transactional-execution mode symbolic names: -# TX .. transactional-execution mode -# NC .. nonconstrained -# C .. constrained -# -# Undefined counters in the extended counter set: -# 142 -# 158-161 -# 176-223 -# 227-231 -# 233-242 -# 246-255 -# Undefined counters in the MT-diagnostic counter set: -# 450-495 -# -# -# Extended Counter Set -# --------------------------------------------------------------------- -Counter:128 Name:L1D_RO_EXCL_WRITES -Short-Description:L1D Read-only Exclusive Writes -Description: -A directory write to the Level-1 Data cache where the line was -originally in a Read-Only state in the cache but has been updated -to be in the Exclusive state that allows stores to the cache line -. -Counter:129 Name:DTLB2_WRITES -Short-Description:DTLB2 Writes -Description: -A translation has been written into The Translation Lookaside -Buffer 2 (TLB2) and the request was made by the data cache -. -Counter:130 Name:DTLB2_MISSES -Short-Description:DTLB2 Misses -Description: -A TLB2 miss is in progress for a request made by the data cache. -Incremented by one for every TLB2 miss in progress for the Level-1 -Data cache on this cycle -. -Counter:131 Name:DTLB2_HPAGE_WRITES -Short-Description:DTLB2 One-Megabyte Page Writes -Description: -A translation entry was written into the Combined Region and Segment -Table Entry array in the Level-2 TLB for a one-megabyte page or a -Last Host Translation was done -. -Counter:132 Name:DTLB2_GPAGE_WRITES -Short-Description:DTLB2 Two-Gigabyte Page Writes -Description: -A translation entry for a two-gigabyte page was written into the -Level-2 TLB -. -Counter:133 Name:L1D_L2D_SOURCED_WRITES -Short-Description:L1D L2D Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the -returned cache line was sourced from the Level-2 Data cache -. -Counter:134 Name:ITLB2_WRITES -Short-Description:ITLB2 Writes -Description: -A translation entry has been written into the Translation Lookaside -Buffer 2 (TLB2) and the request was made by the instruction cache -. -Counter:135 Name:ITLB2_MISSES -Short-Description:ITLB2 Misses -Description: -A TLB2 miss is in progress for a request made by the instruction cache. -Incremented by one for every TLB2 miss in progress for the Level-1 -Instruction cache in a cycle -. -Counter:136 Name:L1I_L2I_SOURCED_WRITES -Short-Description:L1I L2I Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from the Level-2 Instruction cache -. -Counter:137 Name:TLB2_PTE_WRITES -Short-Description:TLB2 PTE Writes -Description: -A translation entry was written into the Page Table Entry array in the -Level-2 TLB -. -Counter:138 Name:TLB2_CRSTE_WRITES -Short-Description:TLB2 CRSTE Writes -Description: -Translation entries were written into the Combined Region and Segment -Table Entry array and the Page Table Entry array in the Level-2 TLB -. -Counter:139 Name:TLB2_ENGINES_BUSY -Short-Description:TLB2 Engines Busy -Description: -The number of Level-2 TLB translation engines busy in a cycle -. -Counter:140 Name:TX_C_TEND -Short-Description:Completed TEND instructions in constrained TX mode -Description: -A TEND instruction has completed in a constrained transactional-execution -mode -. -Counter:141 Name:TX_NC_TEND -Short-Description:Completed TEND instructions in non-constrained TX mode -Description: -A TEND instruction has completed in a non-constrained -transactional-execution mode -. -Counter:143 Name:L1C_TLB2_MISSES -Short-Description:L1C TLB2 Misses -Description: -Increments by one for any cycle where a level-1 cache or level-2 TLB miss -is in progress -. -Counter:144 Name:L1D_ONCHIP_L3_SOURCED_WRITES -Short-Description:L1D On-Chip L3 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an On-Chip Level-3 cache without intervention -. -Counter:145 Name:L1D_ONCHIP_MEMORY_SOURCED_WRITES -Short-Description:L1D On-Chip Memory Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from On-Chip memory -. -Counter:146 Name:L1D_ONCHIP_L3_SOURCED_WRITES_IV -Short-Description:L1D On-Chip L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an On-Chip Level-3 cache with intervention -. -Counter:147 Name:L1D_ONCLUSTER_L3_SOURCED_WRITES -Short-Description:L1D On-Cluster L3 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from On-Cluster Level-3 cache withountervention -. -Counter:148 Name:L1D_ONCLUSTER_MEMORY_SOURCED_WRITES -Short-Description:L1D On-Cluster Memory Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an On-Cluster memory -. -Counter:149 Name:L1D_ONCLUSTER_L3_SOURCED_WRITES_IV -Short-Description:L1D On-Cluster L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an On-Cluster Level-3 cache with intervention -. -Counter:150 Name:L1D_OFFCLUSTER_L3_SOURCED_WRITES -Short-Description:L1D Off-Cluster L3 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an Off-Cluster Level-3 cache without -intervention -. -Counter:151 Name:L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES -Short-Description:L1D Off-Cluster Memory Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from Off-Cluster memory -. -Counter:152 Name:L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV -Short-Description:L1D Off-Cluster L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an Off-Cluster Level-3 cache with intervention -. -Counter:153 Name:L1D_OFFDRAWER_L3_SOURCED_WRITES -Short-Description:L1D Off-Drawer L3 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an Off-Drawer Level-3 cache without -intervention -. -Counter:154 Name:L1D_OFFDRAWER_MEMORY_SOURCED_WRITES -Short-Description:L1D Off-Drawer Memory Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from Off-Drawer memory -. -Counter:155 Name:L1D_OFFDRAWER_L3_SOURCED_WRITES_IV -Short-Description:L1D Off-Drawer L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an Off-Drawer Level-3 cache with intervention -. -Counter:156 Name:L1D_ONDRAWER_L4_SOURCED_WRITES -Short-Description:L1D On-Drawer L4 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from On-Drawer Level-4 cache -. -Counter:157 Name:L1D_OFFDRAWER_L4_SOURCED_WRITES -Short-Description:L1D Off-Drawer L4 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from Off-Drawer Level-4 cache -. -Counter:158 Name:L1D_ONCHIP_L3_SOURCED_WRITES_RO -Short-Description:L1D On-Chip L3 Sourced Writes read-only -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from On-Chip L3 but a read-only invalidate was -done to remove other copies of the cache line -. -Counter:162 Name:L1I_ONCHIP_L3_SOURCED_WRITES -Short-Description:L1I On-Chip L3 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache ine was sourced from an On-Chip Level-3 cache without -intervention -. -Counter:163 Name:L1I_ONCHIP_MEMORY_SOURCED_WRITES -Short-Description:L1I On-Chip Memory Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache ine was sourced from On-Chip memory -. -Counter:164 Name:L1I_ONCHIP_L3_SOURCED_WRITES_IV -Short-Description:L1I On-Chip L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache ine was sourced from an On-Chip Level-3 cache with -intervention -. -Counter:165 Name:L1I_ONCLUSTER_L3_SOURCED_WRITES -Short-Description:L1I On-Cluster L3 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an On-Cluster Level-3 cache without -intervention -. -Counter:166 Name:L1I_ONCLUSTER_MEMORY_SOURCED_WRITES -Short-Description:L1I On-Cluster Memory Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an On-Cluster memory -. -Counter:167 Name:L1I_ONCLUSTER_L3_SOURCED_WRITES_IV -Short-Description:L1I On-Cluster L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from On-Cluster Level-3 cache with -intervention -. -Counter:168 Name:L1I_OFFCLUSTER_L3_SOURCED_WRITES -Short-Description:L1I Off-Cluster L3 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an Off-Cluster Level-3 cache without -intervention -. -Counter:169 Name:L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES -Short-Description:L1I Off-Cluster Memory Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from Off-Cluster memory -. -Counter:170 Name:L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV -Short-Description:L1I Off-Cluster L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an Off-Cluster Level-3 cache with -intervention -. -Counter:171 Name:L1I_OFFDRAWER_L3_SOURCED_WRITES -Short-Description:L1I Off-Drawer L3 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an Off-Drawer Level-3 cache without -intervention -. -Counter:172 Name:L1I_OFFDRAWER_MEMORY_SOURCED_WRITES -Short-Description:L1I Off-Drawer Memory Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from Off-Drawer memory -. -Counter:173 Name:L1I_OFFDRAWER_L3_SOURCED_WRITES_IV -Short-Description:L1I Off-Drawer L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an Off-Drawer Level-3 cache with -intervention -. -Counter:174 Name:L1I_ONDRAWER_L4_SOURCED_WRITES -Short-Description:L1I On-Drawer L4 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from On-Drawer Level-4 cache -. -Counter:175 Name:L1I_OFFDRAWER_L4_SOURCED_WRITES -Short-Description:L1I Off-Drawer L4 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from Off-Drawer Level-4 cache -. -Counter:224 Name:BCD_DFP_EXECUTION_SLOTS -Short-Description:BCD DFP Execution Slots -Description: -Count of floating point execution slots used for finished Binary Coded -Decimal to Decimal Floating Point conversions. Instructions: CDZT, -CXZT, CZDT, CZXT -. -Counter:225 Name:VX_BCD_EXECUTION_SLOTS -Short-Description:VX BCD Execution Slots -Description: -Count of floating point execution slots used for finished vector arithmetic -Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP, -VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG -. -Counter:226 Name:DECIMAL_INSTRUCTIONS -Short-Description:Decimal Instructions -Description: -Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, -EDMK, MP, SRP, SP, ZAP -. -Counter:232 Name:LAST_HOST_TRANSLATIONS -Short-Description:Last host translation done -Description: -Last Host Translation done -. -Counter:243 Name:TX_NC_TABORT -Short-Description:Aborted transactions in non-constrained TX mode -Description: -A transaction abort has occurred in a non-constrained -transactional-execution mode -. -Counter:244 Name:TX_C_TABORT_NO_SPECIAL -Short-Description:Aborted transactions in constrained TX mode not using special completion logic -Description: -A transaction abort has occurred in a constrained transactional-execution -mode and the CPU is not using any special logic to allow the transaction -to complete -. -Counter:245 Name:TX_C_TABORT_SPECIAL -Short-Description:Aborted transactions in constrained TX mode using special completion logic -Description: -A transaction abort has occurred in a constrained transactional-execution -mode and the CPU is using special logic to allow the transaction to -complete -. -# -# MT-diagnostic counter set -# --------------------------------------------------------------------- -Counter:448 Name:MT_DIAG_CYCLES_ONE_THR_ACTIVE -Short-Description:Cycle count with one thread active -Description: -Cycle count with one thread active -. -Counter:449 Name:MT_DIAG_CYCLES_TWO_THR_ACTIVE -Short-Description:Cycle count with two threads active -Description: -Cycle count with two threads active -. diff --git a/cpumf/data/cpum-cf-extended-z15.ctr b/cpumf/data/cpum-cf-extended-z15.ctr deleted file mode 100644 index 0fc935c0..00000000 --- a/cpumf/data/cpum-cf-extended-z15.ctr +++ /dev/null @@ -1,376 +0,0 @@ -# Counter decriptions for the -# IBM z14 extended counter and MT-diagnostic counter set -# -# Notes for transactional-execution mode symbolic names: -# TX .. transactional-execution mode -# NC .. nonconstrained -# C .. constrained -# -# Undefined counters in the extended counter set: -# 142 -# 158-161 -# 176-223 -# 227-231 -# 233-242 -# 246-255 -# Undefined counters in the MT-diagnostic counter set: -# 450-495 -# -# -# Extended Counter Set -# --------------------------------------------------------------------- -Counter:128 Name:L1D_RO_EXCL_WRITES -Short-Description:L1D Read-only Exclusive Writes -Description: -A directory write to the Level-1 Data cache where the line was -originally in a Read-Only state in the cache but has been updated -to be in the Exclusive state that allows stores to the cache line -. -Counter:129 Name:DTLB2_WRITES -Short-Description:DTLB2 Writes -Description: -A translation has been written into The Translation Lookaside -Buffer 2 (TLB2) and the request was made by the data cache -. -Counter:130 Name:DTLB2_MISSES -Short-Description:DTLB2 Misses -Description: -A TLB2 miss is in progress for a request made by the data cache. -Incremented by one for every TLB2 miss in progress for the Level-1 -Data cache on this cycle -. -Counter:131 Name:DTLB2_HPAGE_WRITES -Short-Description:DTLB2 One-Megabyte Page Writes -Description: -A translation entry was written into the Combined Region and Segment -Table Entry array in the Level-2 TLB for a one-megabyte page -. -Counter:132 Name:DTLB2_GPAGE_WRITES -Short-Description:DTLB2 Two-Gigabyte Page Writes -Description: -A translation entry for a two-gigabyte page was written into the -Level-2 TLB -. -Counter:133 Name:L1D_L2D_SOURCED_WRITES -Short-Description:L1D L2D Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the -returned cache line was sourced from the Level-2 Data cache -. -Counter:134 Name:ITLB2_WRITES -Short-Description:ITLB2 Writes -Description: -A translation entry has been written into the Translation Lookaside -Buffer 2 (TLB2) and the request was made by the instruction cache -. -Counter:135 Name:ITLB2_MISSES -Short-Description:ITLB2 Misses -Description: -A TLB2 miss is in progress for a request made by the instruction cache. -Incremented by one for every TLB2 miss in progress for the Level-1 -Instruction cache in a cycle -. -Counter:136 Name:L1I_L2I_SOURCED_WRITES -Short-Description:L1I L2I Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from the Level-2 Instruction cache -. -Counter:137 Name:TLB2_PTE_WRITES -Short-Description:TLB2 PTE Writes -Description: -A translation entry was written into the Page Table Entry array in the -Level-2 TLB -. -Counter:138 Name:TLB2_CRSTE_WRITES -Short-Description:TLB2 CRSTE Writes -Description: -Translation entries were written into the Combined Region and Segment -Table Entry array and the Page Table Entry array in the Level-2 TLB -. -Counter:139 Name:TLB2_ENGINES_BUSY -Short-Description:TLB2 Engines Busy -Description: -The number of Level-2 TLB translation engines busy in a cycle -. -Counter:140 Name:TX_C_TEND -Short-Description:Completed TEND instructions in constrained TX mode -Description: -A TEND instruction has completed in a constrained transactional-execution -mode -. -Counter:141 Name:TX_NC_TEND -Short-Description:Completed TEND instructions in non-constrained TX mode -Description: -A TEND instruction has completed in a non-constrained -transactional-execution mode -. -Counter:143 Name:L1C_TLB2_MISSES -Short-Description:L1C TLB2 Misses -Description: -Increments by one for any cycle where a level-1 cache or level-2 TLB miss -is in progress -. -Counter:144 Name:L1D_ONCHIP_L3_SOURCED_WRITES -Short-Description:L1D On-Chip L3 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an On-Chip Level-3 cache without intervention -. -Counter:145 Name:L1D_ONCHIP_MEMORY_SOURCED_WRITES -Short-Description:L1D On-Chip Memory Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from On-Chip memory -. -Counter:146 Name:L1D_ONCHIP_L3_SOURCED_WRITES_IV -Short-Description:L1D On-Chip L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an On-Chip Level-3 cache with intervention -. -Counter:147 Name:L1D_ONCLUSTER_L3_SOURCED_WRITES -Short-Description:L1D On-Cluster L3 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from On-Cluster Level-3 cache withountervention -. -Counter:148 Name:L1D_ONCLUSTER_MEMORY_SOURCED_WRITES -Short-Description:L1D On-Cluster Memory Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an On-Cluster memory -. -Counter:149 Name:L1D_ONCLUSTER_L3_SOURCED_WRITES_IV -Short-Description:L1D On-Cluster L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an On-Cluster Level-3 cache with intervention -. -Counter:150 Name:L1D_OFFCLUSTER_L3_SOURCED_WRITES -Short-Description:L1D Off-Cluster L3 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an Off-Cluster Level-3 cache without -intervention -. -Counter:151 Name:L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES -Short-Description:L1D Off-Cluster Memory Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from Off-Cluster memory -. -Counter:152 Name:L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV -Short-Description:L1D Off-Cluster L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an Off-Cluster Level-3 cache with intervention -. -Counter:153 Name:L1D_OFFDRAWER_L3_SOURCED_WRITES -Short-Description:L1D Off-Drawer L3 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an Off-Drawer Level-3 cache without -intervention -. -Counter:154 Name:L1D_OFFDRAWER_MEMORY_SOURCED_WRITES -Short-Description:L1D Off-Drawer Memory Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from Off-Drawer memory -. -Counter:155 Name:L1D_OFFDRAWER_L3_SOURCED_WRITES_IV -Short-Description:L1D Off-Drawer L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an Off-Drawer Level-3 cache with intervention -. -Counter:156 Name:L1D_ONDRAWER_L4_SOURCED_WRITES -Short-Description:L1D On-Drawer L4 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from On-Drawer Level-4 cache -. -Counter:157 Name:L1D_OFFDRAWER_L4_SOURCED_WRITES -Short-Description:L1D Off-Drawer L4 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from Off-Drawer Level-4 cache -. -Counter:158 Name:L1D_ONCHIP_L3_SOURCED_WRITES_RO -Short-Description:L1D On-Chip L3 Sourced Writes read-only -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from On-Chip L3 but a read-only invalidate was -done to remove other copies of the cache line -. -Counter:162 Name:L1I_ONCHIP_L3_SOURCED_WRITES -Short-Description:L1I On-Chip L3 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache ine was sourced from an On-Chip Level-3 cache without -intervention -. -Counter:163 Name:L1I_ONCHIP_MEMORY_SOURCED_WRITES -Short-Description:L1I On-Chip Memory Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache ine was sourced from On-Chip memory -. -Counter:164 Name:L1I_ONCHIP_L3_SOURCED_WRITES_IV -Short-Description:L1I On-Chip L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache ine was sourced from an On-Chip Level-3 cache with -intervention -. -Counter:165 Name:L1I_ONCLUSTER_L3_SOURCED_WRITES -Short-Description:L1I On-Cluster L3 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an On-Cluster Level-3 cache without -intervention -. -Counter:166 Name:L1I_ONCLUSTER_MEMORY_SOURCED_WRITES -Short-Description:L1I On-Cluster Memory Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an On-Cluster memory -. -Counter:167 Name:L1I_ONCLUSTER_L3_SOURCED_WRITES_IV -Short-Description:L1I On-Cluster L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from On-Cluster Level-3 cache with -intervention -. -Counter:168 Name:L1I_OFFCLUSTER_L3_SOURCED_WRITES -Short-Description:L1I Off-Cluster L3 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an Off-Cluster Level-3 cache without -intervention -. -Counter:169 Name:L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES -Short-Description:L1I Off-Cluster Memory Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from Off-Cluster memory -. -Counter:170 Name:L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV -Short-Description:L1I Off-Cluster L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an Off-Cluster Level-3 cache with -intervention -. -Counter:171 Name:L1I_OFFDRAWER_L3_SOURCED_WRITES -Short-Description:L1I Off-Drawer L3 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an Off-Drawer Level-3 cache without -intervention -. -Counter:172 Name:L1I_OFFDRAWER_MEMORY_SOURCED_WRITES -Short-Description:L1I Off-Drawer Memory Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from Off-Drawer memory -. -Counter:173 Name:L1I_OFFDRAWER_L3_SOURCED_WRITES_IV -Short-Description:L1I Off-Drawer L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an Off-Drawer Level-3 cache with -intervention -. -Counter:174 Name:L1I_ONDRAWER_L4_SOURCED_WRITES -Short-Description:L1I On-Drawer L4 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from On-Drawer Level-4 cache -. -Counter:175 Name:L1I_OFFDRAWER_L4_SOURCED_WRITES -Short-Description:L1I Off-Drawer L4 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from Off-Drawer Level-4 cache -. -Counter:224 Name:BCD_DFP_EXECUTION_SLOTS -Short-Description:BCD DFP Execution Slots -Description: -Count of floating point execution slots used for finished Binary Coded -Decimal to Decimal Floating Point conversions. Instructions: CDZT, -CXZT, CZDT, CZXT -. -Counter:225 Name:VX_BCD_EXECUTION_SLOTS -Short-Description:VX BCD Execution Slots -Description: -Count of floating point execution slots used for finished vector arithmetic -Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP, -VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG -. -Counter:226 Name:DECIMAL_INSTRUCTIONS -Short-Description:Decimal Instructions -Description: -Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, -EDMK, MP, SRP, SP, ZAP -. -Counter:232 Name:LAST_HOST_TRANSLATIONS -Short-Description:Last host translation done -Description: -Last Host Translation done -. -Counter:243 Name:TX_NC_TABORT -Short-Description:Aborted transactions in non-constrained TX mode -Description: -A transaction abort has occurred in a non-constrained -transactional-execution mode -. -Counter:244 Name:TX_C_TABORT_NO_SPECIAL -Short-Description:Aborted transactions in constrained TX mode not using special completion logic -Description: -A transaction abort has occurred in a constrained transactional-execution -mode and the CPU is not using any special logic to allow the transaction -to complete -. -Counter:245 Name:TX_C_TABORT_SPECIAL -Short-Description:Aborted transactions in constrained TX mode using special completion logic -Description: -A transaction abort has occurred in a constrained transactional-execution -mode and the CPU is using special logic to allow the transaction to -complete -. -Counter:247 Name:DFLT_ACCESS -Short-Description:Cycles CPU spent obtaining access to Deflate unit -Description: -Cycles CPU spent obtaining access to Deflate unit -. -Counter:252 Name:DFLT_CYCLES -Short-Description:Cycles CPU is using Deflate unit -Description: -Cycles CPU is using Deflate unit -. -Counter:264 Name:DFLT_CC -Short-Description:Increments by one for every DEFLATE CONVERSION CALL instruction executed -Description: -Increments by one for every DEFLATE CONVERSION CALL instruction executed -. -Counter:265 Name:DFLT_CCERROR -Short-Description:Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2 -Description: -Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2 -. -# -# MT-diagnostic counter set -# --------------------------------------------------------------------- -Counter:448 Name:MT_DIAG_CYCLES_ONE_THR_ACTIVE -Short-Description:Cycle count with one thread active -Description: -Cycle count with one thread active -. -Counter:449 Name:MT_DIAG_CYCLES_TWO_THR_ACTIVE -Short-Description:Cycle count with two threads active -Description: -Cycle count with two threads active -. diff --git a/cpumf/data/cpum-cf-extended-z196.ctr b/cpumf/data/cpum-cf-extended-z196.ctr deleted file mode 100644 index f24df5cc..00000000 --- a/cpumf/data/cpum-cf-extended-z196.ctr +++ /dev/null @@ -1,146 +0,0 @@ -Counter: 128 Name:L1D_L2_SOURCED_WRITES -Short-Description:L1D L2 Sourced Writes -Description: -A directory write to the Level-1 D-Cache directory where the returned -cache line was sourced from the Level-2 cache -. -Counter: 129 Name:L1I_L2_SOURCED_WRITES -Short-Description:L1I L2 Sourced Writes -Description: -A directory write to the Level-1 I-Cache directory where the returned -cache line was sourced from the Level-2 cache -. -Counter: 130 Name:DTLB1_MISSES -Short-Description:DTLB1 Misses -Description: -Level-1 Data TLB miss in progress. Incremented by one for every cycle -a DTLB1 miss is in progress. -. -Counter: 131 Name:ITLB1_MISSES -Short-Description:ITLB1 Misses -Description: -Level-1 Instruction TLB miss in progress. Incremented by one for every -cycle a ITLB1 miss is in progress. -. -Counter: 133 Name:L2C_STORES_SENT -Short-Description:L2C Stores Sent -Description: -Incremented by one for every store sent to Level-2 cache -. -Counter: 134 Name:L1D_OFFBOOK_L3_SOURCED_WRITES -Short-Description:L1D Off-Book L3 Sourced Writes -Description: -A directory write to the Level-1 D-Cache directory where the returned -cache line was sourced from an Off Book Level-3 cache -. -Counter: 135 Name:L1D_ONBOOK_L4_SOURCED_WRITES -Short-Description:L1D On-Book L4 Sourced Writes -Description: -A directory write to the Level-1 D-Cache directory where the returned -cache line was sourced from an On Book Level-4 cache -. -Counter: 136 Name:L1I_ONBOOK_L4_SOURCED_WRITES -Short-Description:L1I On-Book L4 Sourced Writes -Description: -A directory write to the Level-1 I-Cache directory where the returned -cache line was sourced from an On Book Level-4 cache -. -Counter: 137 Name:L1D_RO_EXCL_WRITES -Short-Description:L1D Read-only Exclusive Writes -Description: -A directory write to the Level-1 D-Cache where the line was originally -in a Read-Only state in the cache but has been updated to be in the -Exclusive state that allows stores to the cache line -. -Counter: 138 Name:L1D_OFFBOOK_L4_SOURCED_WRITES -Short-Description:L1D Off-Book L4 Sourced Writes -Description: -A directory write to the Level-1 D-Cache directory where the returned -cache line was sourced from an Off Book Level-4 cache -. -Counter: 139 Name:L1I_OFFBOOK_L4_SOURCED_WRITES -Short-Description:L1I Off-Book L4 Sourced Writes -Description: -A directory write to the Level-1 I-Cache directory where the returned -cache line was sourced from an Off Book Level-4 cache -. -Counter: 140 Name:DTLB1_HPAGE_WRITES -Short-Description:DTLB1 One-Megabyte Page Writes -Description: -A translation entry has been written to the Level-1 Data Translation -Lookaside Buffer for a one-megabyte page -. -Counter: 141 Name:L1D_LMEM_SOURCED_WRITES -Short-Description:L1D Local Memory Sourced Writes -Description: -A directory write to the Level-1 D-Cache where the installed cache line -was sourced from memory that is attached to the same book as the Data -cache (Local Memory) -. -Counter: 142 Name:L1I_LMEM_SOURCED_WRITES -Short-Description:L1I Local Memory Sourced Writes -Description: -A directory write to the Level-1 I-Cache where the installed cache -line was sourced from memory that is attached to the same book as the -Instruction cache (Local Memory) -. -Counter: 143 Name:L1I_OFFBOOK_L3_SOURCED_WRITES -Short-Description:L1I Off-Book L3 Sourced Writes -Description: -A directory write to the Level-1 I-Cache directory where the returned -cache line was sourced from an Off Book Level-3 cache -. -Counter: 144 Name:DTLB1_WRITES -Short-Description:DTLB1 Writes -Description: -A translation entry has been written to the Level-1 Data Translation -Lookaside Buffer -. -Counter: 145 Name:ITLB1_WRITES -Short-Description:ITLB1 Writes -Description: -A translation entry has been written to the Level-1 Instruction -Translation Lookaside Buffer -. -Counter: 146 Name:TLB2_PTE_WRITES -Short-Description:TLB2 PTE Writes -Description: -A translation entry has been written to the Level-2 TLB Page Table -Entry arrays -. -Counter: 147 Name:TLB2_CRSTE_HPAGE_WRITES -Short-Description:TLB2 CRSTE One-Megabyte Page Writes -Description: -A translation entry has been written to the Level-2 TLB Common Region -Segment Table Entry arrays for a one-megabyte large page translation -. -Counter: 148 Name:TLB2_CRSTE_WRITES -Short-Description:TLB2 CRSTE Writes -Description: -A translation entry has been written to the Level-2 TLB Common Region -Segment Table Entry arrays -. -Counter: 150 Name:L1D_ONCHIP_L3_SOURCED_WRITES -Short-Description:L1D On-Chip L3 Sourced Writes -Description: -A directory write to the Level-1 D-Cache directory where the returned -cache line was sourced from an On Chip Level-3 cache -. -Counter: 152 Name:L1D_OFFCHIP_L3_SOURCED_WRITES -Short-Description:L1D Off-Chip L3 Sourced Writes -Description: -A directory write to the Level-1 D-Cache directory where the returned -cache line was sourced from an Off Chip/On Book Level-3 cache -. -Counter: 153 Name:L1I_ONCHIP_L3_SOURCED_WRITES -Short-Description:L1I On-Chip L3 Sourced Writes -Description: -A directory write to the Level-1 I-Cache directory where the returned -cache line was sourced from an On Chip Level-3 cache -. -Counter: 155 Name:L1I_OFFCHIP_L3_SOURCED_WRITES -Short-Description:L1I Off-Chip L3 Sourced Writes -Description: -A directory write to the Level-1 I-Cache directory where the returned -cache line was sourced from an Off Chip/On Book Level-3 cache -. diff --git a/cpumf/data/cpum-cf-extended-zEC12.ctr b/cpumf/data/cpum-cf-extended-zEC12.ctr deleted file mode 100644 index 576cb71d..00000000 --- a/cpumf/data/cpum-cf-extended-zEC12.ctr +++ /dev/null @@ -1,230 +0,0 @@ -Counter: 128 Name:DTLB1_MISSES -Short-Description:DTLB1 Misses -Description: -Level-1 Data TLB miss in progress. Incremented by one for every cycle -a DTLB1 miss is in progress. -. -Counter:129 Name:ITLB1_MISSES -Short-Description:ITLB1 Misses -Description: -Level-1 Instruction TLB miss in progress. Incremented by one for every -cycle a ITLB1 miss is in progress. -. -Counter:130 Name:L1D_L2I_SOURCED_WRITES -Short-Description:L1D L2I Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from the Level-2 Instruction cache -. -Counter:131 Name:L1I_L2I_SOURCED_WRITES -Short-Description:L1I L2I Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from the Level-2 Instruction cache -. -Counter:132 Name:L1D_L2D_SOURCED_WRITES -Short-Description:L1D L2D Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from the Level-2 Data cache -. -Counter:133 Name:DTLB1_WRITES -Short-Description:DTLB1 Writes -Description: -A translation entry has been written to the Level-1 Data Translation -Lookaside Buffer -. -Counter:135 Name:L1D_LMEM_SOURCED_WRITES -Short-Description:L1D Local Memory Sourced Writes -Description: -A directory write to the Level-1 Data cache where the installed cache line -was sourced from memory that is attached to the same book as the Data -cache (Local Memory) -. -Counter:137 Name:L1I_LMEM_SOURCED_WRITES -Short-Description:L1I Local Memory Sourced Writes -Description: -A directory write to the Level-1 Instruction cache where the installed cache -line was sourced from memory that is attached to the same book as the -Instruction cache (Local Memory) -. -Counter:138 Name:L1D_RO_EXCL_WRITES -Short-Description:L1D Read-only Exclusive Writes -Description: -A directory write to the Level-1 D-Cache where the line was originally -in a Read-Only state in the cache but has been updated to be in the -Exclusive state that allows stores to the cache line -. -Counter:139 Name:DTLB1_HPAGE_WRITES -Short-Description:DTLB1 One-Megabyte Page Writes -Description: -A translation entry has been written to the Level-1 Data Translation -Lookaside Buffer for a one-megabyte page -. -Counter:140 Name:ITLB1_WRITES -Short-Description:ITLB1 Writes -Description: -A translation entry has been written to the Level-1 Instruction -Translation Lookaside Buffer -. -Counter:141 Name:TLB2_PTE_WRITES -Short-Description:TLB2 PTE Writes -Description: -A translation entry has been written to the Level-2 TLB Page Table -Entry arrays -. -Counter:142 Name:TLB2_CRSTE_HPAGE_WRITES -Short-Description:TLB2 CRSTE One-Megabyte Page Writes -Description: -A translation entry has been written to the Level-2 TLB Common Region -Segment Table Entry arrays for a one-megabyte large page translation -. -Counter:143 Name:TLB2_CRSTE_WRITES -Short-Description:TLB2 CRSTE Writes -Description: -A translation entry has been written to the Level-2 TLB Common Region -Segment Table Entry arrays -. -Counter:144 Name:L1D_ONCHIP_L3_SOURCED_WRITES -Short-Description:L1D On-Chip L3 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an On Chip Level-3 cache without intervention -. -Counter:145 Name:L1D_OFFCHIP_L3_SOURCED_WRITES -Short-Description:L1D Off-Chip L3 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an Off Chip/On Book Level-3 cache without -intervention -. -Counter:146 Name:L1D_OFFBOOK_L3_SOURCED_WRITES -Short-Description:L1D Off-Book L3 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an Off Book Level-3 cache without intervention -. -Counter:147 Name:L1D_ONBOOK_L4_SOURCED_WRITES -Short-Description:L1D On-Book L4 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an On Book Level-4 cache -. -Counter:148 Name:L1D_OFFBOOK_L4_SOURCED_WRITES -Short-Description:L1D Off-Book L4 Sourced Writes -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an Off Book Level-4 cache -. -# -# Notes for the transactional-execution mode notations: -# TX .. transactional-execution mode -# NC .. nonconstrained -# C .. constrained -# -Counter:149 Name:TX_NC_TEND -Short-Description:Completed TEND instructions in non-constrained TX mode -Description: -A TEND instruction has completed in a nonconstrained -transactional-execution mode -. -Counter:150 Name:L1D_ONCHIP_L3_SOURCED_WRITES_IV -Short-Description:L1D On-Chip L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from a On Chip Level-3 cache with intervention -. -Counter:151 Name:L1D_OFFCHIP_L3_SOURCED_WRITES_IV -Short-Description:L1D Off-Chip L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an Off Chip/On Book Level-3 cache with -intervention -. -# XXX Remove SOURCED from L1D_OFFBOOK_L3_SOURCED_WRITES... -Counter:152 Name:L1D_OFFBOOK_L3_SOURCED_WRITES_IV -Short-Description:L1D Off-Book L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Data cache directory where the returned -cache line was sourced from an Off Book Level-3 cache with intervention -. -Counter:153 Name:L1I_ONCHIP_L3_SOURCED_WRITES -Short-Description:L1I On-Chip L3 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an On Chip Level-3 cache without -intervention -. -Counter:154 Name:L1I_OFFCHIP_L3_SOURCED_WRITES -Short-Description:L1I Off-Chip L3 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an Off Chip/On Book Level-3 cache -without intervention -. -Counter:155 Name:L1I_OFFBOOK_L3_SOURCED_WRITES -Short-Description:L1I Off-Book L3 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an Off Book Level-3 cache without -intervention -. -Counter:156 Name:L1I_ONBOOK_L4_SOURCED_WRITES -Short-Description:L1I On-Book L4 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an On Book Level-4 cache -. -Counter:157 Name:L1I_OFFBOOK_L4_SOURCED_WRITES -Short-Description:L1I Off-Book L4 Sourced Writes -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an Off Book Level-4 cache -. -Counter:158 Name:TX_C_TEND -Short-Description:Completed TEND instructions in constrained TX mode -Description: -A TEND instruction has completed in a constrained transactional-execution -mode -. -Counter:159 Name:L1I_ONCHIP_L3_SOURCED_WRITES_IV -Short-Description:L1I On-Chip L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an On Chip Level-3 cache with -intervention -. -Counter:160 Name:L1I_OFFCHIP_L3_SOURCED_WRITES_IV -Short-Description:L1I Off-Chip L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an Off Chip/On Book Level-3 cache -with intervention -. -Counter:161 Name:L1I_OFFBOOK_L3_SOURCED_WRITES_IV -Short-Description:L1I Off-Book L3 Sourced Writes with Intervention -Description: -A directory write to the Level-1 Instruction cache directory where the -returned cache line was sourced from an Off Book Level-3 cache with -intervention -. -Counter:177 Name:TX_NC_TABORT -Short-Description:Aborted transactions in non-constrained TX mode -Description: -A transaction abort has occurred in a nonconstrained -transactional-execution mode -. -Counter:178 Name:TX_C_TABORT_NO_SPECIAL -Short-Description:Aborted transactions in constrained TX mode not using special completion logic -Description: -A transaction abort has occurred in a constrained transactional-execution -mode and the CPU is not using any special logic to allow the transaction -to complete -. -Counter:179 Name:TX_C_TABORT_SPECIAL -Short-Description:Aborted transactions in constrained TX mode using special completion logic -Description: -A transaction abort has occurred in a constrained transactional-execution -mode and the CPU is using special logic to allow the transaction to -complete -. diff --git a/cpumf/data/cpum-cf-hw-counter.map b/cpumf/data/cpum-cf-hw-counter.map deleted file mode 100644 index fec8048a..00000000 --- a/cpumf/data/cpum-cf-hw-counter.map +++ /dev/null @@ -1,33 +0,0 @@ -# CPU-measurement facilities -# -# Mapping of: -# 1. CPU-MF counter first/second version numbers to "generic" counter -# definitions -# 2. IBM z Systems hardware to respective extended counter set definitions -# -# -{ - # Definition # File name - - # CFVN - 'cfvn-1' => 'cpum-cf-cfvn-1.ctr', - 'cfvn-3' => 'cpum-cf-cfvn-3.ctr', - - # CSVN - 'csvn-12345' => 'cpum-cf-csvn-12345.ctr', - 'csvn-6' => 'cpum-cf-csvn-6.ctr', - - # Extended counters - 2097 => 'cpum-cf-extended-z10.ctr', - 2098 => 'cpum-cf-extended-z10.ctr', - 2817 => 'cpum-cf-extended-z196.ctr', - 2818 => 'cpum-cf-extended-z196.ctr', - 2827 => 'cpum-cf-extended-zEC12.ctr', - 2828 => 'cpum-cf-extended-zEC12.ctr', - 2964 => 'cpum-cf-extended-z13.ctr', - 2965 => 'cpum-cf-extended-z13.ctr', - 3906 => 'cpum-cf-extended-z14.ctr', - 3907 => 'cpum-cf-extended-z14.ctr', - 8561 => 'cpum-cf-extended-z15.ctr', - 8562 => 'cpum-cf-extended-z15.ctr', -}; diff --git a/cpumf/data/cpum-sf-modes.ctr b/cpumf/data/cpum-sf-modes.ctr deleted file mode 100644 index bc6d2bad..00000000 --- a/cpumf/data/cpum-sf-modes.ctr +++ /dev/null @@ -1,15 +0,0 @@ -# Perf raw event counter definitions for the -# CPU-measurment sampling facility -# -# Basic-sampling mode -Counter: 0xB0000 Name:SF_CYCLES_BASIC -Short-Description:Sample CPU Cycles Using Basic-sampling Mode -Description: -Sample CPU cycles using basic-sampling mode -. -# Diagnostic-sampling mode (includes basic-sampling) -Counter: 0xBD000 Name:SF_CYCLES_BASIC_DIAG -Short-Description:Sample CPU Cycle Using Diagnostic-sampling Mode (not for ordinary use) -Description: -Sample CPU cycle using diagnostic-sampling mode (not for ordinary use) -. diff --git a/cpumf/defines.h b/cpumf/defines.h new file mode 100644 index 00000000..c50b9f66 --- /dev/null +++ b/cpumf/defines.h @@ -0,0 +1,23 @@ +/* + * Defines for CPU Measurement Facility Characteristics + * + * Copyright IBM Corp. 2020 + * + * s390-tools is free software; you can redistribute it and/or modify + * it under the terms of the MIT license. See LICENSE for details. + */ + +#ifndef DEFINES_H +#define DEFINES_H + +#define PERF_SFB_SIZE "/sys/module/kernel/parameters/cpum_sfb_size" +#define PERF_PATH "/sys/bus/event_source/devices/" +#define PERF_SF "cpum_sf" +#define PERF_CF "cpum_cf" + +static inline void linux_error(const char *message) +{ + fprintf(stderr, "Error: %s: %s\n", message, strerror(errno)); +} + +#endif diff --git a/cpumf/lscpumf.c b/cpumf/lscpumf.c new file mode 100644 index 00000000..21e9d466 --- /dev/null +++ b/cpumf/lscpumf.c @@ -0,0 +1,3095 @@ +/* + * lscpumf - Show CPU Measurement Facility Characteristics + * + * Copyright IBM Corp. 2020 + * + * s390-tools is free software; you can redistribute it and/or modify + * it under the terms of the MIT license. See LICENSE for details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "lib/util_opt.h" +#include "lib/util_prg.h" +#include "lib/util_base.h" + +#include "defines.h" + +#define ACTION_NONE 0 +#define ACTION_INFO 1 +#define ACTION_CNT 2 +#define ACTION_CNTALL 3 +#define ACTION_SAMPLE 4 +static bool actions[ACTION_SAMPLE + 1]; /* Specified command line options */ + +/* This defines the number of pages a Sample Data Buffer Table (SDBT) can hold + * as payload data. Each SDBT is one PAGE (4096 bytes) and continas 512 eight + * byte data pointers to Sample Data Buffers (SDB). The last entry of a SDBT + * points to another SDBT and can not store payload. + */ +#define PER_SDBT_SIZE 511 + +/* File names to read data from */ +#define SERVICELEVEL "/proc/service_levels" +#define CPUMF_CF_TYPE "/sys/devices/cpum_cf/type" +#define CPUMF_SF_TYPE "/sys/devices/cpum_sf/type" + +static struct util_opt opt_vec[] = { + UTIL_OPT_SECTION("OPTIONS"), + { + .option = { "list-counters", no_argument, NULL, 'c' }, + .desc = "Lists counters for which the LPAR is authorized.", + }, + { + .option = { "list-all-counters", no_argument, NULL, 'C' }, + .desc = "Lists counters regardless of LPAR authorization.", + }, + { + .option = { "name", no_argument, NULL, 'n' }, + .desc = "Displays counter names.", + }, + { + .option = { "info", no_argument, NULL, 'i' }, + .desc = "Displays detailed information.", + }, + { + .option = { "list-sampling-events", no_argument, NULL, 's' }, + .desc = "Lists sampling events for which the LPAR is authorized.", + }, + UTIL_OPT_HELP, + UTIL_OPT_VERSION, + UTIL_OPT_END +}; + +static const struct util_prg prg = { + .desc = "List CPU Measurement facility charactertics", + .copyright_vec = { + { + .owner = "IBM Corp.", + .pub_first = 2020, + .pub_last = 2020, + }, + UTIL_PRG_COPYRIGHT_END + } +}; + +static char prefix[32]; /* Counter prefix */ +static bool show_names; + +static struct cpumf_info { + unsigned int first_vn; /* Counter facility first version nr */ + unsigned int second_vn; /* Counter facility second version nr */ + unsigned int authorization; /* Counter facility authorization */ + float version; + unsigned long min_rate; /* Minimum sampling rate */ + unsigned long max_rate; /* Maximum sampling rate */ + unsigned long cpu_speed; /* CPU Cycles per micro second */ + unsigned int basic_sample_sz; /* # of Bytes per basic sample */ + unsigned int diag_sample_sz; /* # of bytes per diagnostic sample */ + unsigned char have_counter; /* CPUM counter facility detected */ + unsigned char have_samples; /* CPUM sampling facility detected */ + unsigned int min_sfb; /* Minimum sampling buffer size */ + unsigned int max_sfb; /* Maximum sampling buffer size */ + unsigned short machine_type; /* Machine Type */ +} cpumf; + + +/* + * Samples definition are identical on all machines. No versioning. + */ +static struct samples { /* Sample definition for all machines */ + unsigned long counter; /* Sample number */ + char *name; /* Counter name see SA23-2261 */ + char *desc; /* Short description */ + char *longdesc; /* Long description */ +} def_samples[] = { + { + .counter = 0xB0000, + .name = "SF_CYCLES_BASIC", + .desc = "Sample CPU Cycles Using Basic-sampling Mode.", + .longdesc = "Sample CPU Cycles Using Basic-sampling Mode." + }, + { + .counter = 0xBD000, + .name = "SF_CYCLES_BASIC_DIAG", + .desc = "Sample CPU Cycle Using Diagnostic-sampling Mode\n" + " (not for ordinary use).", + .longdesc = "Sample CPU Cycle Using Diagnostic-sampling Mode\n" + " (not for ordinary use).", + } +}; + +/* + * For exact details and clarifications see document SA23-2260-06 and + * SA23-2261-06 (January 2020). + * + * Counter definitions vary, depending on machine and version numbering. + * The CPU Measurement facility has a first and second version number. + * + * The first version number governs basic counter set and the + * problem state counter set. Currently used are first verion numbers 1 and 3. + * The counter numbers are identifical for version number 1 and 3, but + * have different purpose and description. + * + * The second version number governs the crypto counter set. Currently used + * are numbers 1, 2, 3, 4, 5 and 6. Numbers 1 to 5 use the same counter numbers + * and definitions. Number 6 adds 4 more deflate counters but leaves + * the other counters in this counter set unchanged. + * + * The second version number also governs the extended counter set range. + * The definition of each extended counter set is machine specific and + * determined by machine number. Extended counter set ranges are: + * Second version number and range: + * Second version number: 1 Range 128 to 159 inclusive (32 counters) + * Second version number: 2 Range 128 to 175 inclusive (48 counters) + * Second version number: 3,4,5 Range 128 to 255 inclusive (128 counters) + * Second version number: 6 Range 128 to 287 inclusive (160 counters) + * + * The second version number also governs the MT-diagnostic counter set range. + * Second version number: 1,2,3 none installed + * Second version number: >3 Range 448 to 495 inclusive (48 counters) + */ + +#define CPUMF_CTRSET_NONE 0 +#define CPUMF_CTRSET_BASIC 2 +#define CPUMF_CTRSET_PROBLEM_STATE 4 +#define CPUMF_CTRSET_CRYPTO 8 +#define CPUMF_CTRSET_EXTENDED 1 +#define CPUMF_CTRSET_MT_DIAG 32 + +struct counters { + int ctrnum; + int ctrset; + char *name; + char *desc; +}; + +static struct counters cpumcf_fvn1_counters[] = { + { + .ctrnum = 0, + .ctrset = CPUMF_CTRSET_BASIC, + .name = "CPU_CYCLES", + .desc = "Cycle Count", + }, + { + .ctrnum = 1, + .ctrset = CPUMF_CTRSET_BASIC, + .name = "INSTRUCTIONS", + .desc = "Instruction Count", + }, + { + .ctrnum = 2, + .ctrset = CPUMF_CTRSET_BASIC, + .name = "L1I_DIR_WRITES", + .desc = "Level-1 I-Cache Directory Write Count", + }, + { + .ctrnum = 3, + .ctrset = CPUMF_CTRSET_BASIC, + .name = "L1I_PENALTY_CYCLES", + .desc = "Level-1 I-Cache Penalty Cycle Count", + }, + { + .ctrnum = 4, + .ctrset = CPUMF_CTRSET_BASIC, + .name = "L1D_DIR_WRITES", + .desc = "Level-1 D-Cache Directory Write Count", + }, + { + .ctrnum = 5, + .ctrset = CPUMF_CTRSET_BASIC, + .name = "L1D_PENALTY_CYCLES", + .desc = "Level-1 D-Cache Penalty Cycle Count", + }, + { + .ctrnum = 32, + .ctrset = CPUMF_CTRSET_PROBLEM_STATE, + .name = "PROBLEM_STATE_CPU_CYCLES", + .desc = "Problem-State Cycle Count", + }, + { + .ctrnum = 33, + .ctrset = CPUMF_CTRSET_PROBLEM_STATE, + .name = "PROBLEM_STATE_INSTRUCTIONS", + .desc = "Problem-State Instruction Count", + }, + { + .ctrnum = 34, + .ctrset = CPUMF_CTRSET_PROBLEM_STATE, + .name = "PROBLEM_STATE_L1I_DIR_WRITES", + .desc = "Problem-State Level-1 I-Cache Directory Write Count", + }, + { + .ctrnum = 35, + .ctrset = CPUMF_CTRSET_PROBLEM_STATE, + .name = "PROBLEM_STATE_L1I_PENALTY_CYCLES", + .desc = "Problem-State Level-1 I-Cache Penalty Cycle Count", + }, + { + .ctrnum = 36, + .ctrset = CPUMF_CTRSET_PROBLEM_STATE, + .name = "PROBLEM_STATE_L1D_DIR_WRITES", + .desc = "Problem-State Level-1 D-Cache Directory Write Count", + }, + { + .ctrnum = 37, + .ctrset = CPUMF_CTRSET_PROBLEM_STATE, + .name = "PROBLEM_STATE_L1D_PENALTY_CYCLES", + .desc = "Problem-State Level-1 D-Cache Penalty Cycle Count", + }, +}; + +static struct counters cpumcf_fvn3_counters[] = { + { + .ctrnum = 0, + .ctrset = CPUMF_CTRSET_BASIC, + .name = "CPU_CYCLES", + .desc = "Cycle Count", + }, + { + .ctrnum = 1, + .ctrset = CPUMF_CTRSET_BASIC, + .name = "INSTRUCTIONS", + .desc = "Instruction Count", + }, + { + .ctrnum = 2, + .ctrset = CPUMF_CTRSET_BASIC, + .name = "L1I_DIR_WRITES", + .desc = "Level-1 I-Cache Directory Write Count", + }, + { + .ctrnum = 3, + .ctrset = CPUMF_CTRSET_BASIC, + .name = "L1I_PENALTY_CYCLES", + .desc = "Level-1 I-Cache Penalty Cycle Count", + }, + { + .ctrnum = 4, + .ctrset = CPUMF_CTRSET_BASIC, + .name = "L1D_DIR_WRITES", + .desc = "Level-1 D-Cache Directory Write Count", + }, + { + .ctrnum = 5, + .ctrset = CPUMF_CTRSET_BASIC, + .name = "L1D_PENALTY_CYCLES", + .desc = "Level-1 D-Cache Penalty Cycle Count", + }, + { + .ctrnum = 32, + .ctrset = CPUMF_CTRSET_PROBLEM_STATE, + .name = "PROBLEM_STATE_CPU_CYCLES", + .desc = "Problem-State Cycle Count", + }, + { + .ctrnum = 33, + .ctrset = CPUMF_CTRSET_PROBLEM_STATE, + .name = "PROBLEM_STATE_INSTRUCTIONS", + .desc = "Problem-State Instruction Count", + }, +}; + +static struct counters cpumcf_svn_12345_counters[] = { + { + .ctrnum = 64, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "PRNG_FUNCTIONS", + .desc = "Total number of the PRNG functions issued by the" + "\n\t\tCPU", + }, + { + .ctrnum = 65, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "PRNG_CYCLES", + .desc = "Total number of CPU cycles when the DEA/AES" + "\n\t\tcoprocessor is busy performing PRNG functions" + "\n\t\tissued by the CPU", + }, + { + .ctrnum = 66, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "PRNG_BLOCKED_FUNCTIONS", + .desc = "Total number of the PRNG functions that are issued" + "\n\t\tby the CPU and are blocked because the DEA/AES" + "\n\t\tcoprocessor is busy performing a function issued by" + "\n\t\tanother CPU", + }, + { + .ctrnum = 67, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "PRNG_BLOCKED_CYCLES", + .desc = "Total number of CPU cycles blocked for the PRNG" + "\n\t\tfunctions issued by the CPU because the DEA/AES" + "\n\t\tcoprocessor is busy performing a function issued by" + "\n\t\tanother CPU", + }, + { + .ctrnum = 68, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "SHA_FUNCTIONS", + .desc = "Total number of SHA functions issued by the CPU", + }, + { + .ctrnum = 69, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "SHA_CYCLES", + .desc = "Total number of CPU cycles when the SHA coprocessor" + "\n\t\tis busy performing the SHA functions issued by the" + "\n\t\tCPU", + }, + { + .ctrnum = 70, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "SHA_BLOCKED_FUNCTIONS", + .desc = "Total number of the SHA functions that are issued" + "\n\t\tby the CPU and are blocked because the SHA" + "\n\t\tcoprocessor is busy performing a function issued by" + "\n\t\tanother CPU", + }, + { + .ctrnum = 71, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "SHA_BLOCKED_CYCLES", + .desc = "Total number of CPU cycles blocked for the SHA" + "\n\t\tfunctions issued by the CPU because the SHA" + "\n\t\tcoprocessor is busy performing a function issued by" + "\n\t\tanother CPU", + }, + { + .ctrnum = 72, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "DEA_FUNCTIONS", + .desc = "Total number of the DEA functions issued by the CPU", + }, + { + .ctrnum = 73, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "DEA_CYCLES", + .desc = "Total number of CPU cycles when the DEA/AES" + "\n\t\tcoprocessor is busy performing the DEA functions" + "\n\t\tissued by the CPU", + }, + { + .ctrnum = 74, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "DEA_BLOCKED_FUNCTIONS", + .desc = "Total number of the DEA functions that are issued" + "\n\t\tby the CPU and are blocked because the DEA/AES" + "\n\t\tcoprocessor is busy performing a function issued by" + "\n\t\tanother CPU", + }, + { + .ctrnum = 75, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "DEA_BLOCKED_CYCLES", + .desc = "Total number of CPU cycles blocked for the DEA" + "\n\t\tfunctions issued by the CPU because the DEA/AES" + "\n\t\tcoprocessor is busy performing a function issued by" + "\n\t\tanother CPU", + }, + { + .ctrnum = 76, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "AES_FUNCTIONS", + .desc = "Total number of AES functions issued by the CPU", + }, + { + .ctrnum = 77, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "AES_CYCLES", + .desc = "Total number of CPU cycles when the DEA/AES" + "\n\t\tcoprocessor is busy performing the AES functions" + "\n\t\tissued by the CPU", + }, + { + .ctrnum = 78, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "AES_BLOCKED_FUNCTIONS", + .desc = "Total number of AES functions that are issued by" + "\n\t\tthe CPU and are blocked because the DEA/AES" + "\n\t\tcoprocessor is busy performing a function issued by" + "\n\t\tanother CPU", + }, + { + .ctrnum = 79, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "AES_BLOCKED_CYCLES", + .desc = "Total number of CPU cycles blocked for the AES" + "\n\t\tfunctions issued by the CPU because the DEA/AES" + "\n\t\tcoprocessor is busy performing a function issued by" + "\n\t\tanother CPU", + }, +}; + +static struct counters cpumcf_svn_6_counters[] = { + { + .ctrnum = 64, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "PRNG_FUNCTIONS", + .desc = "Total number of the PRNG functions issued by the" + "\n\t\tCPU", + }, + { + .ctrnum = 65, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "PRNG_CYCLES", + .desc = "Total number of CPU cycles when the DEA/AES" + "\n\t\tcoprocessor is busy performing PRNG functions" + "\n\t\tissued by the CPU", + }, + { + .ctrnum = 66, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "PRNG_BLOCKED_FUNCTIONS", + .desc = "Total number of the PRNG functions that are issued" + "\n\t\tby the CPU and are blocked because the DEA/AES" + "\n\t\tcoprocessor is busy performing a function issued by" + "\n\t\tanother CPU", + }, + { + .ctrnum = 67, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "PRNG_BLOCKED_CYCLES", + .desc = "Total number of CPU cycles blocked for the PRNG" + "\n\t\tfunctions issued by the CPU because the DEA/AES" + "\n\t\tcoprocessor is busy performing a function issued by" + "\n\t\tanother CPU", + }, + { + .ctrnum = 68, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "SHA_FUNCTIONS", + .desc = "Total number of SHA functions issued by the CPU", + }, + { + .ctrnum = 69, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "SHA_CYCLES", + .desc = "Total number of CPU cycles when the SHA coprocessor" + "\n\t\tis busy performing the SHA functions issued by the" + "\n\t\tCPU", + }, + { + .ctrnum = 70, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "SHA_BLOCKED_FUNCTIONS", + .desc = "Total number of the SHA functions that are issued" + "\n\t\tby the CPU and are blocked because the SHA" + "\n\t\tcoprocessor is busy performing a function issued by" + "\n\t\tanother CPU", + }, + { + .ctrnum = 71, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "SHA_BLOCKED_CYCLES", + .desc = "Total number of CPU cycles blocked for the SHA" + "\n\t\tfunctions issued by the CPU because the SHA" + "\n\t\tcoprocessor is busy performing a function issued by" + "\n\t\tanother CPU", + }, + { + .ctrnum = 72, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "DEA_FUNCTIONS", + .desc = "Total number of the DEA functions issued by the CPU", + }, + { + .ctrnum = 73, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "DEA_CYCLES", + .desc = "Total number of CPU cycles when the DEA/AES" + "\n\t\tcoprocessor is busy performing the DEA functions" + "\n\t\tissued by the CPU", + }, + { + .ctrnum = 74, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "DEA_BLOCKED_FUNCTIONS", + .desc = "Total number of the DEA functions that are issued" + "\n\t\tby the CPU and are blocked because the DEA/AES" + "\n\t\tcoprocessor is busy performing a function issued by" + "\n\t\tanother CPU", + }, + { + .ctrnum = 75, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "DEA_BLOCKED_CYCLES", + .desc = "Total number of CPU cycles blocked for the DEA" + "\n\t\tfunctions issued by the CPU because the DEA/AES" + "\n\t\tcoprocessor is busy performing a function issued by" + "\n\t\tanother CPU", + }, + { + .ctrnum = 76, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "AES_FUNCTIONS", + .desc = "Total number of AES functions issued by the CPU", + }, + { + .ctrnum = 77, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "AES_CYCLES", + .desc = "Total number of CPU cycles when the DEA/AES" + "\n\t\tcoprocessor is busy performing the AES functions" + "\n\t\tissued by the CPU", + }, + { + .ctrnum = 78, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "AES_BLOCKED_FUNCTIONS", + .desc = "Total number of AES functions that are issued by" + "\n\t\tthe CPU and are blocked because the DEA/AES" + "\n\t\tcoprocessor is busy performing a function issued by" + "\n\t\tanother CPU", + }, + { + .ctrnum = 79, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "AES_BLOCKED_CYCLES", + .desc = "Total number of CPU cycles blocked for the AES" + "\n\t\tfunctions issued by the CPU because the DEA/AES" + "\n\t\tcoprocessor is busy performing a function issued by" + "\n\t\tanother CPU", + }, + { + .ctrnum = 80, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "ECC_FUNCTION_COUNT", + .desc = "This counter counts the total number of the" + "\n\t\telliptic-curve cryptography (ECC) functions issued" + "\n\t\tby the CPU.", + }, + { + .ctrnum = 81, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "ECC_CYCLES_COUNT", + .desc = "This counter counts the total number of CPU cycles" + "\n\t\twhen the ECC coprocessor is busy performing the" + "\n\t\telliptic-curve cryptography (ECC) functions issued" + "\n\t\tby the CPU.", + }, + { + .ctrnum = 82, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "ECC_BLOCKED_FUNCTION_COUNT", + .desc = "This counter counts the total number of the" + "\n\t\telliptic-curve cryptography (ECC) functions that" + "\n\t\tare issued by the CPU and are blocked because the" + "\n\t\tECC coprocessor is busy performing a function" + "\n\t\tissued by another CPU.", + }, + { + .ctrnum = 83, + .ctrset = CPUMF_CTRSET_CRYPTO, + .name = "ECC_BLOCKED_CYCLES_COUNT", + .desc = "This counter counts the total number of CPU cycles" + "\n\t\tblocked for the elliptic-curve cryptography (ECC)" + "\n\t\tfunctions issued by the CPU because the ECC" + "\n\t\tcoprocessor is busy perform- ing a function issued" + "\n\t\tby another CPU.", + }, +}; + +static struct counters cpumcf_z10_counters[] = { + { + .ctrnum = 128, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_L2_SOURCED_WRITES", + .desc = "A directory write to the Level-1 I-Cache directory" + "\n\t\twhere the returned cache line was sourced from the" + "\n\t\tLevel-2 (L1.5) cache", + }, + { + .ctrnum = 129, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_L2_SOURCED_WRITES", + .desc = "A directory write to the Level-1 D-Cache directory" + "\n\t\twhere the installed cache line was sourced from the" + "\n\t\tLevel-2 (L1.5) cache", + }, + { + .ctrnum = 130, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_L3_LOCAL_WRITES", + .desc = "A directory write to the Level-1 I-Cache directory" + "\n\t\twhere the installed cache line was sourced from the" + "\n\t\tLevel-3 cache that is on the same book as the" + "\n\t\tInstruction cache (Local L2 cache)", + }, + { + .ctrnum = 131, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_L3_LOCAL_WRITES", + .desc = "A directory write to the Level-1 D-Cache directory" + "\n\t\twhere the installtion cache line was source from" + "\n\t\tthe Level-3 cache that is on the same book as the" + "\n\t\tData cache (Local L2 cache)", + }, + { + .ctrnum = 132, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_L3_REMOTE_WRITES", + .desc = "A directory write to the Level-1 I-Cache directory" + "\n\t\twhere the installed cache line was sourced from a" + "\n\t\tLevel-3 cache that is not on the same book as the" + "\n\t\tInstruction cache (Remote L2 cache)", + }, + { + .ctrnum = 133, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_L3_REMOTE_WRITES", + .desc = "A directory write to the Level-1 D-Cache directory" + "\n\t\twhere the installed cache line was sourced from a" + "\n\t\tLevel-3 cache that is not on the same book as the" + "\n\t\tData cache (Remote L2 cache)", + }, + { + .ctrnum = 134, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_LMEM_SOURCED_WRITES", + .desc = "A directory write to the Level-1 D-Cache directory" + "\n\t\twhere the installed cache line was sourced from" + "\n\t\tmemory that is attached to the same book as the" + "\n\t\tData cache (Local Memory)", + }, + { + .ctrnum = 135, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_LMEM_SOURCED_WRITES", + .desc = "A directory write to the Level-1 I-Cache where the" + "\n\t\tinstalled cache line was sourced from memory that" + "\n\t\tis attached to the s ame book as the Instruction" + "\n\t\tcache (Local Memory)", + }, + { + .ctrnum = 136, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_RO_EXCL_WRITES", + .desc = "A directory write to the Level-1 D-Cache where the" + "\n\t\tline was originally in a Read-Only state in the" + "\n\t\tcache but has been updated to be in the Exclusive" + "\n\t\tstate that allows stores to the cache line", + }, + { + .ctrnum = 137, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_CACHELINE_INVALIDATES", + .desc = "A cache line in the Level-1 I-Cache has been" + "\n\t\tinvalidated by a store on the same CPU as the Level-" + "\n\t\t1 I-Cache", + }, + { + .ctrnum = 138, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "ITLB1_WRITES", + .desc = "A translation entry has been written into the Level-" + "\n\t\t1 Instruction Translation Lookaside Buffer", + }, + { + .ctrnum = 139, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DTLB1_WRITES", + .desc = "A translation entry has been written to the Level-1" + "\n\t\tData Translation Lookaside Buffer", + }, + { + .ctrnum = 140, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TLB2_PTE_WRITES", + .desc = "A translation entry has been written to the Level-2" + "\n\t\tTLB Page Table Entry arrays", + }, + { + .ctrnum = 141, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TLB2_CRSTE_WRITES", + .desc = "A translation entry has been written to the Level-2" + "\n\t\tTLB Common Region Segment Table Entry arrays", + }, + { + .ctrnum = 142, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TLB2_CRSTE_HPAGE_WRITES", + .desc = "A translation entry has been written to the Level-2" + "\n\t\tTLB Common Region Segment Table Entry arrays for a" + "\n\t\tone-megabyte large page translation", + }, + { + .ctrnum = 145, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "ITLB1_MISSES", + .desc = "Level-1 Instruction TLB miss in progress." + "\n\t\tIncremented by one for every cycle an ITLB1 miss is" + "\n\t\tin progress", + }, + { + .ctrnum = 146, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DTLB1_MISSES", + .desc = "Level-1 Data TLB miss in progress. Incremented by" + "\n\t\tone for every cycle an DTLB1 miss is in progress", + }, + { + .ctrnum = 147, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L2C_STORES_SENT", + .desc = "Incremented by one for every store sent to Level-2" + "\n\t\t(L1.5) cache", + }, +}; + +static struct counters cpumcf_z196_counters[] = { + { + .ctrnum = 128, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_L2_SOURCED_WRITES", + .desc = "A directory write to the Level-1 D-Cache directory" + "\n\t\twhere the returned cache line was sourced from the" + "\n\t\tLevel-2 cache", + }, + { + .ctrnum = 129, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_L2_SOURCED_WRITES", + .desc = "A directory write to the Level-1 I-Cache directory" + "\n\t\twhere the returned cache line was sourced from the" + "\n\t\tLevel-2 cache", + }, + { + .ctrnum = 130, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DTLB1_MISSES", + .desc = "Level-1 Data TLB miss in progress. Incremented by" + "\n\t\tone for every cycle a DTLB1 miss is in progress.", + }, + { + .ctrnum = 131, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "ITLB1_MISSES", + .desc = "Level-1 Instruction TLB miss in progress." + "\n\t\tIncremented by one for every cycle a ITLB1 miss is" + "\n\t\tin progress.", + }, + { + .ctrnum = 133, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L2C_STORES_SENT", + .desc = "Incremented by one for every store sent to Level-2" + "\n\t\tcache", + }, + { + .ctrnum = 134, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFBOOK_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 D-Cache directory" + "\n\t\twhere the returned cache line was sourced from an" + "\n\t\tOff Book Level-3 cache", + }, + { + .ctrnum = 135, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONBOOK_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 D-Cache directory" + "\n\t\twhere the returned cache line was sourced from an" + "\n\t\tOn Book Level-4 cache", + }, + { + .ctrnum = 136, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONBOOK_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 I-Cache directory" + "\n\t\twhere the returned cache line was sourced from an" + "\n\t\tOn Book Level-4 cache", + }, + { + .ctrnum = 137, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_RO_EXCL_WRITES", + .desc = "A directory write to the Level-1 D-Cache where the" + "\n\t\tline was originally in a Read-Only state in the" + "\n\t\tcache but has been updated to be in the Exclusive" + "\n\t\tstate that allows stores to the cache line", + }, + { + .ctrnum = 138, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFBOOK_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 D-Cache directory" + "\n\t\twhere the returned cache line was sourced from an" + "\n\t\tOff Book Level-4 cache", + }, + { + .ctrnum = 139, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFBOOK_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 I-Cache directory" + "\n\t\twhere the returned cache line was sourced from an" + "\n\t\tOff Book Level-4 cache", + }, + { + .ctrnum = 140, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DTLB1_HPAGE_WRITES", + .desc = "A translation entry has been written to the Level-1" + "\n\t\tData Translation Lookaside Buffer for a one-" + "\n\t\tmegabyte page", + }, + { + .ctrnum = 141, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_LMEM_SOURCED_WRITES", + .desc = "A directory write to the Level-1 D-Cache where the" + "\n\t\tinstalled cache line was sourced from memory that" + "\n\t\tis attached to the same book as the Data cache" + "\n\t\t(Local Memory)", + }, + { + .ctrnum = 142, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_LMEM_SOURCED_WRITES", + .desc = "A directory write to the Level-1 I-Cache where the" + "\n\t\tinstalled cache line was sourced from memory that" + "\n\t\tis attached to the same book as the Instruction" + "\n\t\tcache (Local Memory)", + }, + { + .ctrnum = 143, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFBOOK_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 I-Cache directory" + "\n\t\twhere the returned cache line was sourced from an" + "\n\t\tOff Book Level-3 cache", + }, + { + .ctrnum = 144, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DTLB1_WRITES", + .desc = "A translation entry has been written to the Level-1" + "\n\t\tData Translation Lookaside Buffer", + }, + { + .ctrnum = 145, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "ITLB1_WRITES", + .desc = "A translation entry has been written to the Level-1" + "\n\t\tInstruction Translation Lookaside Buffer", + }, + { + .ctrnum = 146, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TLB2_PTE_WRITES", + .desc = "A translation entry has been written to the Level-2" + "\n\t\tTLB Page Table Entry arrays", + }, + { + .ctrnum = 147, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TLB2_CRSTE_HPAGE_WRITES", + .desc = "A translation entry has been written to the Level-2" + "\n\t\tTLB Common Region Segment Table Entry arrays for a" + "\n\t\tone-megabyte large page translation", + }, + { + .ctrnum = 148, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TLB2_CRSTE_WRITES", + .desc = "A translation entry has been written to the Level-2" + "\n\t\tTLB Common Region Segment Table Entry arrays", + }, + { + .ctrnum = 150, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONCHIP_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 D-Cache directory" + "\n\t\twhere the returned cache line was sourced from an" + "\n\t\tOn Chip Level-3 cache", + }, + { + .ctrnum = 152, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFCHIP_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 D-Cache directory" + "\n\t\twhere the returned cache line was sourced from an" + "\n\t\tOff Chip/On Book Level-3 cache", + }, + { + .ctrnum = 153, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONCHIP_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 I-Cache directory" + "\n\t\twhere the returned cache line was sourced from an" + "\n\t\tOn Chip Level-3 cache", + }, + { + .ctrnum = 155, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFCHIP_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 I-Cache directory" + "\n\t\twhere the returned cache line was sourced from an" + "\n\t\tOff Chip/On Book Level-3 cache", + }, +}; + +static struct counters cpumcf_zec12_counters[] = { + { + .ctrnum = 128, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DTLB1_MISSES", + .desc = "Level-1 Data TLB miss in progress. Incremented by" + "\n\t\tone for every cycle a DTLB1 miss is in progress.", + }, + { + .ctrnum = 129, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "ITLB1_MISSES", + .desc = "Level-1 Instruction TLB miss in progress." + "\n\t\tIncremented by one for every cycle a ITLB1 miss is" + "\n\t\tin progress.", + }, + { + .ctrnum = 130, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_L2I_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom the Level-2 Instruction cache", + }, + { + .ctrnum = 131, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_L2I_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom the Level-2 Instruction cache", + }, + { + .ctrnum = 132, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_L2D_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom the Level-2 Data cache", + }, + { + .ctrnum = 133, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DTLB1_WRITES", + .desc = "A translation entry has been written to the Level-1" + "\n\t\tData Translation Lookaside Buffer", + }, + { + .ctrnum = 135, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_LMEM_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache where" + "\n\t\tthe installed cache line was sourced from memory" + "\n\t\tthat is attached to the same book as the Data cache" + "\n\t\t(Local Memory)", + }, + { + .ctrnum = 137, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_LMEM_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\twhere the installed cache line was sourced from" + "\n\t\tmemory that is attached to the same book as the" + "\n\t\tInstruction cache (Local Memory)", + }, + { + .ctrnum = 138, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_RO_EXCL_WRITES", + .desc = "A directory write to the Level-1 D-Cache where the" + "\n\t\tline was originally in a Read-Only state in the" + "\n\t\tcache but has been updated to be in the Exclusive" + "\n\t\tstate that allows stores to the cache line", + }, + { + .ctrnum = 139, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DTLB1_HPAGE_WRITES", + .desc = "A translation entry has been written to the Level-1" + "\n\t\tData Translation Lookaside Buffer for a one-" + "\n\t\tmegabyte page", + }, + { + .ctrnum = 140, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "ITLB1_WRITES", + .desc = "A translation entry has been written to the Level-1" + "\n\t\tInstruction Translation Lookaside Buffer", + }, + { + .ctrnum = 141, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TLB2_PTE_WRITES", + .desc = "A translation entry has been written to the Level-2" + "\n\t\tTLB Page Table Entry arrays", + }, + { + .ctrnum = 142, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TLB2_CRSTE_HPAGE_WRITES", + .desc = "A translation entry has been written to the Level-2" + "\n\t\tTLB Common Region Segment Table Entry arrays for a" + "\n\t\tone-megabyte large page translation", + }, + { + .ctrnum = 143, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TLB2_CRSTE_WRITES", + .desc = "A translation entry has been written to the Level-2" + "\n\t\tTLB Common Region Segment Table Entry arrays", + }, + { + .ctrnum = 144, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONCHIP_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On Chip Level-3 cache without intervention", + }, + { + .ctrnum = 145, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFCHIP_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off Chip/On Book Level-3 cache without" + "\n\t\tintervention", + }, + { + .ctrnum = 146, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFBOOK_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off Book Level-3 cache without intervention", + }, + { + .ctrnum = 147, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONBOOK_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On Book Level-4 cache", + }, + { + .ctrnum = 148, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFBOOK_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off Book Level-4 cache", + }, + { + .ctrnum = 149, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TX_NC_TEND", + .desc = "A TEND instruction has completed in a" + "\n\t\tnonconstrained transactional-execution mode", + }, + { + .ctrnum = 150, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONCHIP_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom a On Chip Level-3 cache with intervention", + }, + { + .ctrnum = 151, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFCHIP_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off Chip/On Book Level-3 cache with" + "\n\t\tintervention", + }, + { + .ctrnum = 152, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFBOOK_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off Book Level-3 cache with intervention", + }, + { + .ctrnum = 153, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONCHIP_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On Chip Level-3 cache without intervention", + }, + { + .ctrnum = 154, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFCHIP_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off Chip/On Book Level-3 cache without" + "\n\t\tintervention", + }, + { + .ctrnum = 155, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFBOOK_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off Book Level-3 cache without intervention", + }, + { + .ctrnum = 156, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONBOOK_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On Book Level-4 cache", + }, + { + .ctrnum = 157, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFBOOK_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off Book Level-4 cache", + }, + { + .ctrnum = 158, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TX_C_TEND", + .desc = "A TEND instruction has completed in a constrained" + "\n\t\ttransactional-execution mode", + }, + { + .ctrnum = 159, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONCHIP_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On Chip Level-3 cache with intervention", + }, + { + .ctrnum = 160, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFCHIP_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off Chip/On Book Level-3 cache with" + "\n\t\tintervention", + }, + { + .ctrnum = 161, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFBOOK_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off Book Level-3 cache with intervention", + }, + { + .ctrnum = 177, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TX_NC_TABORT", + .desc = "A transaction abort has occurred in a" + "\n\t\tnonconstrained transactional-execution mode", + }, + { + .ctrnum = 178, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TX_C_TABORT_NO_SPECIAL", + .desc = "A transaction abort has occurred in a constrained" + "\n\t\ttransactional-execution mode and the CPU is not" + "\n\t\tusing any special logic to allow the transaction to" + "\n\t\tcomplete", + }, + { + .ctrnum = 179, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TX_C_TABORT_SPECIAL", + .desc = "A transaction abort has occurred in a constrained" + "\n\t\ttransactional-execution mode and the CPU is using" + "\n\t\tspecial logic to allow the transaction to complete", + }, +}; + +static struct counters cpumcf_z13_counters[] = { + { + .ctrnum = 128, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_RO_EXCL_WRITES", + .desc = "A directory write to the Level-1 Data cache where" + "\n\t\tthe line was originally in a Read-Only state in the" + "\n\t\tcache but has been updated to be in the Exclusive" + "\n\t\tstate that allows stores to the cache line.", + }, + { + .ctrnum = 129, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DTLB1_WRITES", + .desc = "A translation entry has been written to the Level-1" + "\n\t\tData Translation Lookaside Buffer", + }, + { + .ctrnum = 130, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DTLB1_MISSES", + .desc = "Level-1 Data TLB miss in progress. Incremented by" + "\n\t\tone for every cycle a DTLB1 miss is in progress.", + }, + { + .ctrnum = 131, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DTLB1_HPAGE_WRITES", + .desc = "A translation entry has been written to the Level-1" + "\n\t\tData Translation Lookaside Buffer for a one-" + "\n\t\tmegabyte page", + }, + { + .ctrnum = 132, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DTLB1_GPAGE_WRITES", + .desc = "A translation entry has been written to the Level-1" + "\n\t\tData Translation Lookaside Buffer for a two-" + "\n\t\tgigabyte page.", + }, + { + .ctrnum = 133, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_L2D_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom the Level-2 Data cache", + }, + { + .ctrnum = 134, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "ITLB1_WRITES", + .desc = "A translation entry has been written to the Level-1" + "\n\t\tInstruction Translation Lookaside Buffer", + }, + { + .ctrnum = 135, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "ITLB1_MISSES", + .desc = "Level-1 Instruction TLB miss in progress." + "\n\t\tIncremented by one for every cycle an ITLB1 miss is" + "\n\t\tin progress", + }, + { + .ctrnum = 136, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_L2I_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom the Level-2 Instruction cache", + }, + { + .ctrnum = 137, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TLB2_PTE_WRITES", + .desc = "A translation entry has been written to the Level-2" + "\n\t\tTLB Page Table Entry arrays", + }, + { + .ctrnum = 138, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TLB2_CRSTE_HPAGE_WRITES", + .desc = "A translation entry has been written to the Level-2" + "\n\t\tTLB Combined Region Segment Table Entry arrays for" + "\n\t\ta one-megabyte large page translation", + }, + { + .ctrnum = 139, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TLB2_CRSTE_WRITES", + .desc = "A translation entry has been written to the Level-2" + "\n\t\tTLB Combined Region Segment Table Entry arrays", + }, + { + .ctrnum = 140, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TX_C_TEND", + .desc = "A TEND instruction has completed in a constrained" + "\n\t\ttransactional-execution mode", + }, + { + .ctrnum = 141, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TX_NC_TEND", + .desc = "A TEND instruction has completed in a non-" + "\n\t\tconstrained transactional-execution mode", + }, + { + .ctrnum = 143, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1C_TLB1_MISSES", + .desc = "Increments by one for any cycle where a Level-1" + "\n\t\tcache or Level-1 TLB miss is in progress.", + }, + { + .ctrnum = 144, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONCHIP_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Chip Level-3 cache without intervention", + }, + { + .ctrnum = 145, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONCHIP_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Chip Level-3 cache with intervention", + }, + { + .ctrnum = 146, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONNODE_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Node Level-4 cache", + }, + { + .ctrnum = 147, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONNODE_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Node Level-3 cache with intervention", + }, + { + .ctrnum = 148, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONNODE_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Node Level-3 cache without intervention", + }, + { + .ctrnum = 149, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONDRAWER_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Drawer Level-4 cache", + }, + { + .ctrnum = 150, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONDRAWER_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Drawer Level-3 cache with intervention", + }, + { + .ctrnum = 151, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONDRAWER_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Drawer Level-3 cache without" + "\n\t\tintervention", + }, + { + .ctrnum = 152, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Drawer Same-Column Level-4 cache", + }, + { + .ctrnum = 153, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Drawer Same-Column Level-3 cache with" + "\n\t\tintervention", + }, + { + .ctrnum = 154, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Drawer Same-Column Level-3 cache" + "\n\t\twithout intervention", + }, + { + .ctrnum = 155, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Drawer Far-Column Level-4 cache", + }, + { + .ctrnum = 156, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Drawer Far-Column Level-3 cache with" + "\n\t\tintervention", + }, + { + .ctrnum = 157, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Drawer Far-Column Level-3 cache without" + "\n\t\tintervention", + }, + { + .ctrnum = 158, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONNODE_MEM_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom On-Node memory", + }, + { + .ctrnum = 159, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONDRAWER_MEM_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom On-Drawer memory", + }, + { + .ctrnum = 160, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFDRAWER_MEM_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom On-Drawer memory", + }, + { + .ctrnum = 161, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONCHIP_MEM_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom On-Chip memory", + }, + { + .ctrnum = 162, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONCHIP_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Chip Level-3 cache without intervention", + }, + { + .ctrnum = 163, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONCHIP_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On Chip Level-3 cache with intervention", + }, + { + .ctrnum = 164, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONNODE_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Node Level-4 cache", + }, + { + .ctrnum = 165, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONNODE_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Node Level-3 cache with intervention", + }, + { + .ctrnum = 166, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONNODE_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Node Level-3 cache without intervention", + }, + { + .ctrnum = 167, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONDRAWER_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Drawer Level-4 cache", + }, + { + .ctrnum = 168, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONDRAWER_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Drawer Level-3 cache with intervention", + }, + { + .ctrnum = 169, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONDRAWER_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Drawer Level-3 cache without" + "\n\t\tintervention", + }, + { + .ctrnum = 170, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Drawer Same-Column Level-4 cache", + }, + { + .ctrnum = 171, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Drawer Same-Column Level-3 cache with" + "\n\t\tintervention", + }, + { + .ctrnum = 172, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Drawer Same-Column Level-3 cache" + "\n\t\twithout intervention", + }, + { + .ctrnum = 173, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Drawer Far-Column Level-4 cache", + }, + { + .ctrnum = 174, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Drawer Far-Column Level-3 cache with" + "\n\t\tintervention", + }, + { + .ctrnum = 175, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Drawer Far-Column Level-3 cache without" + "\n\t\tintervention", + }, + { + .ctrnum = 176, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONNODE_MEM_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom On-Node memory", + }, + { + .ctrnum = 177, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONDRAWER_MEM_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom On-Drawer memory", + }, + { + .ctrnum = 178, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFDRAWER_MEM_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom On-Drawer memory", + }, + { + .ctrnum = 179, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONCHIP_MEM_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom On-Chip memory", + }, + { + .ctrnum = 218, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TX_NC_TABORT", + .desc = "A transaction abort has occurred in a non-" + "\n\t\tconstrained transactional-execution mode", + }, + { + .ctrnum = 219, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TX_C_TABORT_NO_SPECIAL", + .desc = "A transaction abort has occurred in a constrained" + "\n\t\ttransactional-execution mode and the CPU is not" + "\n\t\tusing any special logic to allow the transaction to" + "\n\t\tcomplete", + }, + { + .ctrnum = 220, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TX_C_TABORT_SPECIAL", + .desc = "A transaction abort has occurred in a constrained" + "\n\t\ttransactional-execution mode and the CPU is using" + "\n\t\tspecial logic to allow the transaction to complete", + }, + { + .ctrnum = 448, + .ctrset = CPUMF_CTRSET_MT_DIAG, + .name = "MT_DIAG_CYCLES_ONE_THR_ACTIVE", + .desc = "Cycle count with one thread active", + }, + { + .ctrnum = 449, + .ctrset = CPUMF_CTRSET_MT_DIAG, + .name = "MT_DIAG_CYCLES_TWO_THR_ACTIVE", + .desc = "Cycle count with two threads active", + }, +}; + +static struct counters cpumcf_z14_counters[] = { + { + .ctrnum = 128, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_RO_EXCL_WRITES", + .desc = "A directory write to the Level-1 Data cache where" + "\n\t\tthe line was originally in a Read-Only state in the" + "\n\t\tcache but has been updated to be in the Exclusive" + "\n\t\tstate that allows stores to the cache line", + }, + { + .ctrnum = 129, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DTLB2_WRITES", + .desc = "A translation has been written into The Translation" + "\n\t\tLookaside Buffer 2 (TLB2) and the request was made" + "\n\t\tby the data cache", + }, + { + .ctrnum = 130, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DTLB2_MISSES", + .desc = "A TLB2 miss is in progress for a request made by" + "\n\t\tthe data cache. Incremented by one for every TLB2" + "\n\t\tmiss in progress for the Level-1 Data cache on this" + "\n\t\tcycle", + }, + { + .ctrnum = 131, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DTLB2_HPAGE_WRITES", + .desc = "A translation entry was written into the Combined" + "\n\t\tRegion and Segment Table Entry array in the Level-2" + "\n\t\tTLB for a one-megabyte page or a Last Host" + "\n\t\tTranslation was done", + }, + { + .ctrnum = 132, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DTLB2_GPAGE_WRITES", + .desc = "A translation entry for a two-gigabyte page was" + "\n\t\twritten into the Level-2 TLB", + }, + { + .ctrnum = 133, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_L2D_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom the Level-2 Data cache", + }, + { + .ctrnum = 134, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "ITLB2_WRITES", + .desc = "A translation entry has been written into the" + "\n\t\tTranslation Lookaside Buffer 2 (TLB2) and the" + "\n\t\trequest was made by the instruction cache", + }, + { + .ctrnum = 135, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "ITLB2_MISSES", + .desc = "A TLB2 miss is in progress for a request made by" + "\n\t\tthe instruction cache. Incremented by one for every" + "\n\t\tTLB2 miss in progress for the Level-1 Instruction" + "\n\t\tcache in a cycle", + }, + { + .ctrnum = 136, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_L2I_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom the Level-2 Instruction cache", + }, + { + .ctrnum = 137, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TLB2_PTE_WRITES", + .desc = "A translation entry was written into the Page Table" + "\n\t\tEntry array in the Level-2 TLB", + }, + { + .ctrnum = 138, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TLB2_CRSTE_WRITES", + .desc = "Translation entries were written into the Combined" + "\n\t\tRegion and Segment Table Entry array and the Page" + "\n\t\tTable Entry array in the Level-2 TLB", + }, + { + .ctrnum = 139, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TLB2_ENGINES_BUSY", + .desc = "The number of Level-2 TLB translation engines busy" + "\n\t\tin a cycle", + }, + { + .ctrnum = 140, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TX_C_TEND", + .desc = "A TEND instruction has completed in a constrained" + "\n\t\ttransactional-execution mode", + }, + { + .ctrnum = 141, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TX_NC_TEND", + .desc = "A TEND instruction has completed in a non-" + "\n\t\tconstrained transactional-execution mode", + }, + { + .ctrnum = 143, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1C_TLB2_MISSES", + .desc = "Increments by one for any cycle where a level-1" + "\n\t\tcache or level-2 TLB miss is in progress", + }, + { + .ctrnum = 144, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONCHIP_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Chip Level-3 cache without intervention", + }, + { + .ctrnum = 145, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONCHIP_MEMORY_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom On-Chip memory", + }, + { + .ctrnum = 146, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONCHIP_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Chip Level-3 cache with intervention", + }, + { + .ctrnum = 147, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONCLUSTER_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom On-Cluster Level-3 cache withountervention", + }, + { + .ctrnum = 148, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONCLUSTER_MEMORY_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Cluster memory", + }, + { + .ctrnum = 149, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONCLUSTER_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Cluster Level-3 cache with intervention", + }, + { + .ctrnum = 150, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFCLUSTER_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Cluster Level-3 cache without" + "\n\t\tintervention", + }, + { + .ctrnum = 151, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom Off-Cluster memory", + }, + { + .ctrnum = 152, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Cluster Level-3 cache with intervention", + }, + { + .ctrnum = 153, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFDRAWER_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Drawer Level-3 cache without" + "\n\t\tintervention", + }, + { + .ctrnum = 154, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFDRAWER_MEMORY_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom Off-Drawer memory", + }, + { + .ctrnum = 155, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFDRAWER_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Drawer Level-3 cache with intervention", + }, + { + .ctrnum = 156, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONDRAWER_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom On-Drawer Level-4 cache", + }, + { + .ctrnum = 157, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFDRAWER_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom Off-Drawer Level-4 cache", + }, + { + .ctrnum = 158, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONCHIP_L3_SOURCED_WRITES_RO", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom On-Chip L3 but a read-only invalidate was done" + "\n\t\tto remove other copies of the cache line", + }, + { + .ctrnum = 162, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONCHIP_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache ine was sourced" + "\n\t\tfrom an On-Chip Level-3 cache without intervention", + }, + { + .ctrnum = 163, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONCHIP_MEMORY_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache ine was sourced" + "\n\t\tfrom On-Chip memory", + }, + { + .ctrnum = 164, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONCHIP_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache ine was sourced" + "\n\t\tfrom an On-Chip Level-3 cache with intervention", + }, + { + .ctrnum = 165, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONCLUSTER_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Cluster Level-3 cache without" + "\n\t\tintervention", + }, + { + .ctrnum = 166, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONCLUSTER_MEMORY_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Cluster memory", + }, + { + .ctrnum = 167, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONCLUSTER_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom On-Cluster Level-3 cache with intervention", + }, + { + .ctrnum = 168, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFCLUSTER_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Cluster Level-3 cache without" + "\n\t\tintervention", + }, + { + .ctrnum = 169, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom Off-Cluster memory", + }, + { + .ctrnum = 170, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Cluster Level-3 cache with intervention", + }, + { + .ctrnum = 171, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFDRAWER_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Drawer Level-3 cache without" + "\n\t\tintervention", + }, + { + .ctrnum = 172, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFDRAWER_MEMORY_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom Off-Drawer memory", + }, + { + .ctrnum = 173, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFDRAWER_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Drawer Level-3 cache with intervention", + }, + { + .ctrnum = 174, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONDRAWER_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom On-Drawer Level-4 cache", + }, + { + .ctrnum = 175, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFDRAWER_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom Off-Drawer Level-4 cache", + }, + { + .ctrnum = 224, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "BCD_DFP_EXECUTION_SLOTS", + .desc = "Count of floating point execution slots used for" + "\n\t\tfinished Binary Coded Decimal to Decimal Floating" + "\n\t\tPoint conversions. Instructions: CDZT, CXZT, CZDT," + "\n\t\tCZXT", + }, + { + .ctrnum = 225, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "VX_BCD_EXECUTION_SLOTS", + .desc = "Count of floating point execution slots used for" + "\n\t\tfinished vector arithmetic Binary Coded Decimal" + "\n\t\tinstructions. Instructions: VAP, VSP, VMPVMSP, VDP," + "\n\t\tVSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ," + "\n\t\tVCVB, VCVBG, VCVDVCVDG", + }, + { + .ctrnum = 226, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DECIMAL_INSTRUCTIONS", + .desc = "Decimal instructions dispatched. Instructions: CVB," + "\n\t\tCVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP", + }, + { + .ctrnum = 232, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "LAST_HOST_TRANSLATIONS", + .desc = "Last Host Translation done", + }, + { + .ctrnum = 243, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TX_NC_TABORT", + .desc = "A transaction abort has occurred in a non-" + "\n\t\tconstrained transactional-execution mode", + }, + { + .ctrnum = 244, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TX_C_TABORT_NO_SPECIAL", + .desc = "A transaction abort has occurred in a constrained" + "\n\t\ttransactional-execution mode and the CPU is not" + "\n\t\tusing any special logic to allow the transaction to" + "\n\t\tcomplete", + }, + { + .ctrnum = 245, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TX_C_TABORT_SPECIAL", + .desc = "A transaction abort has occurred in a constrained" + "\n\t\ttransactional-execution mode and the CPU is using" + "\n\t\tspecial logic to allow the transaction to complete", + }, + { + .ctrnum = 448, + .ctrset = CPUMF_CTRSET_MT_DIAG, + .name = "MT_DIAG_CYCLES_ONE_THR_ACTIVE", + .desc = "Cycle count with one thread active", + }, + { + .ctrnum = 449, + .ctrset = CPUMF_CTRSET_MT_DIAG, + .name = "MT_DIAG_CYCLES_TWO_THR_ACTIVE", + .desc = "Cycle count with two threads active", + }, +}; + +static struct counters cpumcf_z15_counters[] = { + { + .ctrnum = 128, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_RO_EXCL_WRITES", + .desc = "A directory write to the Level-1 Data cache where" + "\n\t\tthe line was originally in a Read-Only state in the" + "\n\t\tcache but has been updated to be in the Exclusive" + "\n\t\tstate that allows stores to the cache line", + }, + { + .ctrnum = 129, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DTLB2_WRITES", + .desc = "A translation has been written into The Translation" + "\n\t\tLookaside Buffer 2 (TLB2) and the request was made" + "\n\t\tby the data cache", + }, + { + .ctrnum = 130, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DTLB2_MISSES", + .desc = "A TLB2 miss is in progress for a request made by" + "\n\t\tthe data cache. Incremented by one for every TLB2" + "\n\t\tmiss in progress for the Level-1 Data cache on this" + "\n\t\tcycle", + }, + { + .ctrnum = 131, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DTLB2_HPAGE_WRITES", + .desc = "A translation entry was written into the Combined" + "\n\t\tRegion and Segment Table Entry array in the Level-2" + "\n\t\tTLB for a one-megabyte page", + }, + { + .ctrnum = 132, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DTLB2_GPAGE_WRITES", + .desc = "A translation entry for a two-gigabyte page was" + "\n\t\twritten into the Level-2 TLB", + }, + { + .ctrnum = 133, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_L2D_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom the Level-2 Data cache", + }, + { + .ctrnum = 134, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "ITLB2_WRITES", + .desc = "A translation entry has been written into the" + "\n\t\tTranslation Lookaside Buffer 2 (TLB2) and the" + "\n\t\trequest was made by the instruction cache", + }, + { + .ctrnum = 135, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "ITLB2_MISSES", + .desc = "A TLB2 miss is in progress for a request made by" + "\n\t\tthe instruction cache. Incremented by one for every" + "\n\t\tTLB2 miss in progress for the Level-1 Instruction" + "\n\t\tcache in a cycle", + }, + { + .ctrnum = 136, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_L2I_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom the Level-2 Instruction cache", + }, + { + .ctrnum = 137, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TLB2_PTE_WRITES", + .desc = "A translation entry was written into the Page Table" + "\n\t\tEntry array in the Level-2 TLB", + }, + { + .ctrnum = 138, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TLB2_CRSTE_WRITES", + .desc = "Translation entries were written into the Combined" + "\n\t\tRegion and Segment Table Entry array and the Page" + "\n\t\tTable Entry array in the Level-2 TLB", + }, + { + .ctrnum = 139, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TLB2_ENGINES_BUSY", + .desc = "The number of Level-2 TLB translation engines busy" + "\n\t\tin a cycle", + }, + { + .ctrnum = 140, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TX_C_TEND", + .desc = "A TEND instruction has completed in a constrained" + "\n\t\ttransactional-execution mode", + }, + { + .ctrnum = 141, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TX_NC_TEND", + .desc = "A TEND instruction has completed in a non-" + "\n\t\tconstrained transactional-execution mode", + }, + { + .ctrnum = 143, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1C_TLB2_MISSES", + .desc = "Increments by one for any cycle where a level-1" + "\n\t\tcache or level-2 TLB miss is in progress", + }, + { + .ctrnum = 144, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONCHIP_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Chip Level-3 cache without intervention", + }, + { + .ctrnum = 145, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONCHIP_MEMORY_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom On-Chip memory", + }, + { + .ctrnum = 146, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONCHIP_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Chip Level-3 cache with intervention", + }, + { + .ctrnum = 147, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONCLUSTER_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom On-Cluster Level-3 cache withountervention", + }, + { + .ctrnum = 148, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONCLUSTER_MEMORY_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Cluster memory", + }, + { + .ctrnum = 149, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONCLUSTER_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Cluster Level-3 cache with intervention", + }, + { + .ctrnum = 150, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFCLUSTER_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Cluster Level-3 cache without" + "\n\t\tintervention", + }, + { + .ctrnum = 151, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom Off-Cluster memory", + }, + { + .ctrnum = 152, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Cluster Level-3 cache with intervention", + }, + { + .ctrnum = 153, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFDRAWER_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Drawer Level-3 cache without" + "\n\t\tintervention", + }, + { + .ctrnum = 154, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFDRAWER_MEMORY_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom Off-Drawer memory", + }, + { + .ctrnum = 155, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFDRAWER_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Drawer Level-3 cache with intervention", + }, + { + .ctrnum = 156, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONDRAWER_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom On-Drawer Level-4 cache", + }, + { + .ctrnum = 157, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_OFFDRAWER_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom Off-Drawer Level-4 cache", + }, + { + .ctrnum = 158, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1D_ONCHIP_L3_SOURCED_WRITES_RO", + .desc = "A directory write to the Level-1 Data cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom On-Chip L3 but a read-only invalidate was done" + "\n\t\tto remove other copies of the cache line", + }, + { + .ctrnum = 162, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONCHIP_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache ine was sourced" + "\n\t\tfrom an On-Chip Level-3 cache without intervention", + }, + { + .ctrnum = 163, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONCHIP_MEMORY_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache ine was sourced" + "\n\t\tfrom On-Chip memory", + }, + { + .ctrnum = 164, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONCHIP_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache ine was sourced" + "\n\t\tfrom an On-Chip Level-3 cache with intervention", + }, + { + .ctrnum = 165, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONCLUSTER_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Cluster Level-3 cache without" + "\n\t\tintervention", + }, + { + .ctrnum = 166, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONCLUSTER_MEMORY_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an On-Cluster memory", + }, + { + .ctrnum = 167, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONCLUSTER_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom On-Cluster Level-3 cache with intervention", + }, + { + .ctrnum = 168, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFCLUSTER_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Cluster Level-3 cache without" + "\n\t\tintervention", + }, + { + .ctrnum = 169, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom Off-Cluster memory", + }, + { + .ctrnum = 170, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Cluster Level-3 cache with intervention", + }, + { + .ctrnum = 171, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFDRAWER_L3_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Drawer Level-3 cache without" + "\n\t\tintervention", + }, + { + .ctrnum = 172, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFDRAWER_MEMORY_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom Off-Drawer memory", + }, + { + .ctrnum = 173, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFDRAWER_L3_SOURCED_WRITES_IV", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom an Off-Drawer Level-3 cache with intervention", + }, + { + .ctrnum = 174, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_ONDRAWER_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom On-Drawer Level-4 cache", + }, + { + .ctrnum = 175, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "L1I_OFFDRAWER_L4_SOURCED_WRITES", + .desc = "A directory write to the Level-1 Instruction cache" + "\n\t\tdirectory where the returned cache line was sourced" + "\n\t\tfrom Off-Drawer Level-4 cache", + }, + { + .ctrnum = 224, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "BCD_DFP_EXECUTION_SLOTS", + .desc = "Count of floating point execution slots used for" + "\n\t\tfinished Binary Coded Decimal to Decimal Floating" + "\n\t\tPoint conversions. Instructions: CDZT, CXZT, CZDT," + "\n\t\tCZXT", + }, + { + .ctrnum = 225, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "VX_BCD_EXECUTION_SLOTS", + .desc = "Count of floating point execution slots used for" + "\n\t\tfinished vector arithmetic Binary Coded Decimal" + "\n\t\tinstructions. Instructions: VAP, VSP, VMPVMSP, VDP," + "\n\t\tVSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ," + "\n\t\tVCVB, VCVBG, VCVDVCVDG", + }, + { + .ctrnum = 226, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DECIMAL_INSTRUCTIONS", + .desc = "Decimal instructions dispatched. Instructions: CVB," + "\n\t\tCVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP", + }, + { + .ctrnum = 232, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "LAST_HOST_TRANSLATIONS", + .desc = "Last Host Translation done", + }, + { + .ctrnum = 243, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TX_NC_TABORT", + .desc = "A transaction abort has occurred in a non-" + "\n\t\tconstrained transactional-execution mode", + }, + { + .ctrnum = 244, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TX_C_TABORT_NO_SPECIAL", + .desc = "A transaction abort has occurred in a constrained" + "\n\t\ttransactional-execution mode and the CPU is not" + "\n\t\tusing any special logic to allow the transaction to" + "\n\t\tcomplete", + }, + { + .ctrnum = 245, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "TX_C_TABORT_SPECIAL", + .desc = "A transaction abort has occurred in a constrained" + "\n\t\ttransactional-execution mode and the CPU is using" + "\n\t\tspecial logic to allow the transaction to complete", + }, + { + .ctrnum = 247, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DFLT_ACCESS", + .desc = "Cycles CPU spent obtaining access to Deflate unit", + }, + { + .ctrnum = 252, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DFLT_CYCLES", + .desc = "Cycles CPU is using Deflate unit", + }, + { + .ctrnum = 264, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DFLT_CC", + .desc = "Increments by one for every DEFLATE CONVERSION CALL" + "\n\t\tinstruction executed", + }, + { + .ctrnum = 265, + .ctrset = CPUMF_CTRSET_EXTENDED, + .name = "DFLT_CCERROR", + .desc = "Increments by one for every DEFLATE CONVERSION CALL" + "\n\t\tinstruction executed that ended in Condition Codes" + "\n\t\t0, 1 or 2", + }, + { + .ctrnum = 448, + .ctrset = CPUMF_CTRSET_MT_DIAG, + .name = "MT_DIAG_CYCLES_ONE_THR_ACTIVE", + .desc = "Cycle count with one thread active", + }, + { + .ctrnum = 449, + .ctrset = CPUMF_CTRSET_MT_DIAG, + .name = "MT_DIAG_CYCLES_TWO_THR_ACTIVE", + .desc = "Cycle count with two threads active", + }, +}; + +static const char *machine_name(void) +{ + switch (cpumf.machine_type) { + case 2097: return "IBM System z10 EC"; + case 2098: return "IBM System z10 BC"; + case 2817: return "IBM zEnterprise 196"; + case 2818: return "IBM zEnterprise 114"; + case 2827: return "IBM zEnterprise EC12"; + case 2828: return "IBM zEnterprise BC12"; + case 2964: return "IBM z13"; + case 2965: return "IBM z13s"; + case 3906: return "IBM z14"; + case 3907: return "IBM z14 ZR1"; + case 8561: return "IBM z15"; + } + return "Unknown hardware model"; +} + +/* Return the type number of the CPU Measurement facility from the sysfs file. + * If the type number is equal to PERF_TYPE_RAW, then the prefix is 'r' to + * specify the raw counter number by the perf tool. + * If perf_pmu_register() kernel function assigned any other (higher) type + * number, set the prefix to : + */ +static int read_cpumf_type(const char *filename, const char *type) +{ + int nr, rc = EXIT_FAILURE; + FILE *fp = fopen(filename, "r"); + + if (fp == NULL) { + fprintf(stderr, "No CPU-measurement %s facility detected\n", + type); + return rc; + } + if (fscanf(fp, "%d", &nr) != 1) + fprintf(stderr, "Can not parse file %s\n", filename); + else { + rc = EXIT_SUCCESS; + if (nr == PERF_TYPE_RAW) + strcat(prefix, "r"); + else + snprintf(prefix, sizeof prefix, "%d:", nr); + } + fclose(fp); + return rc; +} + +/* Parse tool parameters. In case of --help or --version, print + * respective text to stdout and exit. + * Only handle one option and simulate behavior of previous tool. + */ +static int parse_args(int argc, char **argv) +{ + int opt; + + actions[ACTION_NONE] = true; + while ((opt = util_opt_getopt_long(argc, argv)) != EOF) { + switch (opt) { + case 'h': + util_prg_print_help(); + util_opt_print_help(); + exit(EXIT_SUCCESS); + case 'v': + util_prg_print_version(); + exit(EXIT_SUCCESS); + case 'i': + actions[ACTION_INFO] = true; + break; + case 'n': + show_names = true; + break; + case 's': + actions[ACTION_SAMPLE] = true; + break; + case 'c': + actions[ACTION_CNT] = true; + break; + case 'C': + actions[ACTION_CNTALL] = true; + break; + case '?': + fprintf(stderr, "One or more options are not valid\n"); + fprintf(stderr, "Try 'lscpumf --help' for more" + " information.\n"); + exit(EXIT_FAILURE); + } + } + if (actions[ACTION_INFO]) + return ACTION_INFO; + else if (actions[ACTION_CNT]) + return ACTION_CNT; + else if (actions[ACTION_CNTALL]) + return ACTION_CNTALL; + else if (actions[ACTION_SAMPLE]) + return ACTION_SAMPLE; + + return ACTION_NONE; +} + +static unsigned long tohz(unsigned long value, unsigned long cpuspeed) +{ + return 1000000 * cpuspeed / value; +} + +static void human(char *buffer, size_t buffer_len, unsigned long bytes) +{ + const char bu[] = " KMGTPEZY"; + size_t unit = 0; + + while (bytes >= 1024 && unit < strlen(bu)) { + bytes /= 1024; + ++unit; + } + snprintf(buffer, buffer_len, "%ld%cB", bytes, bu[unit]); +} + +static unsigned long div_ceil(unsigned long a, unsigned long b) +{ + return (a + b - 1) / b; +} + +static void show_info(struct cpumf_info *p, int details) +{ + struct stat sbuf; + + if (!p->have_counter && !p->have_samples) { + fprintf(stderr, "No CPU-measurement facilities detected\n"); + return; + } + if (p->have_counter) { + printf("CPU-measurement Counter Facility\n"); + if (details) { + printf("----------------------------------------------" + "----------------------------\n"); + printf("Version: %3.1f\n\n", p->version); + printf("Authorized counter sets:\n"); + if (!p->authorization) + printf(" None\n"); + if (0x2 & p->authorization) + printf(" Basic counter Set\n"); + if (0x8 & p->authorization) + printf(" Crypto-Activity counter Set\n"); + if (0x1 & p->authorization) + printf(" Extended counter Set\n"); + if (0x20 & p->authorization) + printf(" MT-diagnostic counter Set\n"); + if (0x4 & p->authorization) + printf(" Problem-State counter Set\n"); + if (0x8000 & p->authorization) + printf(" Coprocessor Group counter Set\n"); + printf("\nLinux perf event support: %s\n\n", + (stat(PERF_PATH PERF_CF, &sbuf) != 0) ? "No" : + "Yes (PMU: " PERF_CF ")"); + + } + } else + fprintf(stderr, + "No CPU-measurement counter facility detected\n"); + if (p->have_samples) { + unsigned long total, fdiag; + char text[32]; + + printf("CPU-measurement Sampling Facility\n"); + if (details) { + printf("----------------------------------------------" + "----------------------------\n"); + printf("Sampling Interval:\n"); + printf(" Minimum: %10ld cycles" + " (approx. %9ld Hz)\n", p->min_rate, + tohz(p->min_rate, p->cpu_speed)); + printf(" Maximum: %10ld cycles" + " (approx. %9ld Hz)\n", p->max_rate, + tohz(p->max_rate, p->cpu_speed)); + printf("\n"); + printf("Authorized sampling modes:\n"); + printf(" basic: (sample size: %3d bytes)\n", + p->basic_sample_sz); + printf(" diagnostic: (sample size: %3d bytes)\n", + p->diag_sample_sz); + + printf("\nLinux perf event support: %s\n\n", + (stat(PERF_PATH PERF_SF, &sbuf) != 0) ? "No" : + "Yes (PMU: " PERF_SF ")"); + + printf("Current sampling buffer settings for %s:\n", + PERF_SF); + printf(" Basic-sampling mode\n"); + total = p->min_sfb + div_ceil(p->min_sfb, PER_SDBT_SIZE); + human(text, sizeof text, PAGE_SIZE * total); + printf(" Minimum: %6d" + " sample-data-blocks (%6s)\n", p->min_sfb, text); + total = p->max_sfb + div_ceil(p->max_sfb, PER_SDBT_SIZE); + human(text, sizeof text, PAGE_SIZE * total); + printf(" Maximum: %6d" + " sample-data-blocks (%6s)\n\n", p->max_sfb, + text); + + printf(" Diagnostic-sampling mode" + " (including basic-sampling)\n"); + fdiag = div_ceil(p->diag_sample_sz, p->basic_sample_sz); + total = fdiag * p->min_sfb + + div_ceil(p->min_sfb, PER_SDBT_SIZE); + human(text, sizeof text, PAGE_SIZE * total); + printf(" Minimum: %6ld" + " sample-data-blocks (%6s)\n", + fdiag * p->min_sfb, text); + total = fdiag * p->max_sfb + + div_ceil(p->max_sfb * fdiag, PER_SDBT_SIZE); + human(text, sizeof text, PAGE_SIZE * total); + printf(" Maximum: %6ld" + " sample-data-blocks (%6s)\n", fdiag * p->max_sfb, + text); + printf(" Size factor: %2ld\n", fdiag); + } + } else + fprintf(stderr, + "No CPU-measurement sampling facility detected\n"); +} + +/* Funktion to read machine type */ +#define SYSINFO "/proc/sysinfo" +#define MACH_TYPE "Type:" + +static int read_machine(unsigned short *mt) +{ + int rc = EXIT_FAILURE; + char *linep = NULL; + size_t line_sz; + ssize_t nbytes; + FILE *fp; + + fp = fopen(SYSINFO, "r"); + if (fp == NULL) { + linux_error(SYSINFO); + return rc; + } + while ((nbytes = getline(&linep, &line_sz, fp)) != EOF) { + if (!strncmp(linep, MACH_TYPE, sizeof MACH_TYPE - 1)) { + int rc_scan = sscanf(linep, MACH_TYPE "%hd", mt); + if (rc_scan != 1) + fprintf(stderr, "Can not parse line %s", linep); + else + rc = EXIT_SUCCESS; + break; + } + } + fclose(fp); + free(linep); + return rc; +} + +/* Read CPU Measurement sampling facility device driver minimum and maximum + * buffer size + */ +static int read_sfb(struct cpumf_info *p) +{ + FILE *fp; + int rc = EXIT_SUCCESS; + + fp = fopen(PERF_SFB_SIZE, "r"); + if (fp == NULL) { + linux_error(PERF_SFB_SIZE); + return EXIT_FAILURE; + } + if (fscanf(fp, "%d,%d", &p->min_sfb, &p->max_sfb) != 2) { + fprintf(stderr, "Can not parse %s\n", PERF_SFB_SIZE); + rc = EXIT_FAILURE; + } + fclose(fp); + return rc; +} + +/* Read allnecessary information from /sysfs file /proc/service_levels */ +static int read_info(void) +{ + char *linep = NULL; + size_t line_sz; + ssize_t nbytes; + FILE *slp; + int rc; + + memset(&cpumf, 0, sizeof cpumf); + slp = fopen(SERVICELEVEL, "r"); + if (slp == NULL) { + linux_error(SERVICELEVEL); + return EXIT_FAILURE; + } + + while ((nbytes = getline(&linep, &line_sz, slp)) != EOF) { + if (!strncmp(linep, "CPU-MF: Counter facility:", 25)) { + rc = sscanf(linep, "CPU-MF: Counter facility:" + " version=%f authorization=%x", + &cpumf.version, &cpumf.authorization); + if (rc != 2) { + fprintf(stderr, "Can not parse line %s", linep); + rc = EXIT_FAILURE; + goto out; + } + cpumf.have_counter = 1; + cpumf.first_vn = (int)cpumf.version; + cpumf.second_vn = ((int)(10 * cpumf.version) % 10); + } + if (!strncmp(linep, "CPU-MF: Sampling facility: min", 30)) { + rc = sscanf(linep, "CPU-MF: Sampling facility:" + " min_rate=%ld max_rate=%ld cpu_speed=%ld", + &cpumf.min_rate, &cpumf.max_rate, + &cpumf.cpu_speed); + if (rc != 3) { + fprintf(stderr, "Can not parse line %s", linep); + rc = EXIT_FAILURE; + goto out; + } + cpumf.have_samples = 1; + } + if (!strncmp(linep, "CPU-MF: Sampling facility: mode=basic", 37)) { + rc = sscanf(linep, "CPU-MF: Sampling facility:" + " mode=basic sample_size=%u", + &cpumf.basic_sample_sz); + if (rc != 1) { + fprintf(stderr, "Can not parse line %s", linep); + rc = EXIT_FAILURE; + goto out; + } + } + if (!strncmp(linep, "CPU-MF: Sampling facility: mode=diag", 36)) { + rc = sscanf(linep, "CPU-MF: Sampling facility:" + " mode=diagnostic sample_size=%u", + &cpumf.diag_sample_sz); + if (rc != 1) { + fprintf(stderr, "Can not parse line %s", linep); + rc = EXIT_FAILURE; + goto out; + } + } + } + if (cpumf.have_samples) { + rc = read_sfb(&cpumf); + if (rc == EXIT_FAILURE) + goto out; + } + rc = read_machine(&cpumf.machine_type); + if (rc == EXIT_FAILURE) + goto out; + rc = EXIT_SUCCESS; +out: + fclose(slp); + free(linep); + + return rc; +} + +static void show_hdr(void) +{ + printf("================================================" + "==============================\n\n" + "Raw\n" + "event Name Description\n" + "---------------------------" + "---------------------------------------------------\n"); +} + +#define FORMATS "%s%5lx\t%s\n\n %s\n %s\n\n" +#define FORMATC "%s%d%s\n\n %s\n %s %d / %s\n\n" + +static void show_sample(void) +{ + printf("Perf events for activating the sampling facility\n"); + show_hdr(); + for (unsigned int i = 0; i < ARRAY_SIZE(def_samples); ++i) { + printf(FORMATS, prefix, def_samples[i].counter, + def_samples[i].name, def_samples[i].desc, + "This event is not associated with a counter set."); + } +} + +static const char *name_counterset(int snr) +{ + switch (snr) { + case CPUMF_CTRSET_BASIC: return "Basic Counter Set."; + case CPUMF_CTRSET_PROBLEM_STATE: return "Problem-State Counter Set."; + case CPUMF_CTRSET_CRYPTO: return "Crypto-Activity Counter Set."; + case CPUMF_CTRSET_EXTENDED: return "Extended Counter Set."; + case CPUMF_CTRSET_MT_DIAG: return "MT-diagnostic Counter Set."; + default: return "Unknown Counter Set."; + } +} + +/* Check if counter set this counter belongs to has been authorized. */ +static bool auth_counterset(struct counters *cp) +{ + if (cp->ctrset == CPUMF_CTRSET_BASIC && (cpumf.authorization & 2)) + return true; + if (cp->ctrset == CPUMF_CTRSET_PROBLEM_STATE && (cpumf.authorization & 4)) + return true; + if (cp->ctrset == CPUMF_CTRSET_CRYPTO && (cpumf.authorization & 8)) + return true; + if (cp->ctrset == CPUMF_CTRSET_EXTENDED && (cpumf.authorization & 1)) + return true; + if (cp->ctrset == CPUMF_CTRSET_MT_DIAG && (cpumf.authorization & 0x20)) + return true; + return false; +} + +/* Return pointer to counter set and size. */ +static struct counters *get_counter(int ctrset, size_t *len) +{ + struct counters *cp = NULL; + + *len = 0; + switch (ctrset) { + case CPUMF_CTRSET_BASIC: + if (cpumf.first_vn == 1) { + cp = cpumcf_fvn1_counters; + *len = ARRAY_SIZE(cpumcf_fvn1_counters); + } else { + cp = cpumcf_fvn3_counters; + *len = ARRAY_SIZE(cpumcf_fvn3_counters); + } + break; + case CPUMF_CTRSET_CRYPTO: + if (cpumf.second_vn <= 5) { + cp = cpumcf_svn_12345_counters; + *len = ARRAY_SIZE(cpumcf_svn_12345_counters); + } else { + cp = cpumcf_svn_6_counters; + *len = ARRAY_SIZE(cpumcf_svn_6_counters); + } + break; + case CPUMF_CTRSET_EXTENDED: + switch (cpumf.machine_type) { + case 2097: + case 2098: + cp = cpumcf_z10_counters; + *len = ARRAY_SIZE(cpumcf_z10_counters); + break; + case 2817: + case 2818: + cp = cpumcf_z196_counters; + *len = ARRAY_SIZE(cpumcf_z196_counters); + break; + case 2827: + case 2828: + cp = cpumcf_zec12_counters; + *len = ARRAY_SIZE(cpumcf_zec12_counters); + break; + case 2964: + case 2965: + cp = cpumcf_z13_counters; + *len = ARRAY_SIZE(cpumcf_z13_counters); + break; + case 3906: + case 3907: + cp = cpumcf_z14_counters; + *len = ARRAY_SIZE(cpumcf_z14_counters); + break; + case 8561: + case 8562: + cp = cpumcf_z15_counters; + *len = ARRAY_SIZE(cpumcf_z15_counters); + break; + } + break; + } + return cp; +} + +static void show_counterset(bool all, struct counters *cp, size_t cp_cnt) +{ + char cnt_name[128]; + + for (size_t i = 0; i < cp_cnt; ++i, ++cp) { + if (!all && !auth_counterset(cp)) + continue; + if (show_names) + snprintf(cnt_name, sizeof cnt_name, "/name=%s/", + cp->name); + else + snprintf(cnt_name, sizeof cnt_name, "\t%s", + cp->name); + printf(FORMATC, prefix, cp->ctrnum, cnt_name, + cp->desc, "Counter", cp->ctrnum, + name_counterset(cp->ctrset)); + } +} + +static void show_counter(bool all) +{ + struct counters *cp; + size_t cp_cnt; + + printf("perf event counter list for %s\n", machine_name()); + show_hdr(); + /* Basic counter set */ + cp = get_counter(CPUMF_CTRSET_BASIC, &cp_cnt); + show_counterset(all, cp, cp_cnt); + /* Crypto counter set */ + cp = get_counter(CPUMF_CTRSET_CRYPTO, &cp_cnt); + show_counterset(all, cp, cp_cnt); + /* Extended counter set */ + cp = get_counter(CPUMF_CTRSET_EXTENDED, &cp_cnt); + show_counterset(all, cp, cp_cnt); +} + +int main(int argc, char **argv) +{ + bool all = false; + int ret; + + util_prg_init(&prg); + util_opt_init(opt_vec, NULL); + + ret = read_info(); + if (ret == EXIT_FAILURE) + return ret; + + switch ((ret = parse_args(argc, argv))) { + case ACTION_CNT: + case ACTION_CNTALL: + all = ret == ACTION_CNTALL; + ret = read_cpumf_type(CPUMF_CF_TYPE, "counter"); + if (ret == EXIT_SUCCESS) + show_counter(all); + break; + case ACTION_SAMPLE: + ret = read_cpumf_type(CPUMF_SF_TYPE, "sampling"); + if (ret == EXIT_SUCCESS) + show_sample(); + break; + case ACTION_NONE: + case ACTION_INFO: + show_info(&cpumf, ret == ACTION_INFO); + break; + } + return ret; +} diff --git a/cpumf/man/lscpumf.1 b/cpumf/man/lscpumf.1 index fd87a32e..871218b7 100644 --- a/cpumf/man/lscpumf.1 +++ b/cpumf/man/lscpumf.1 @@ -1,11 +1,11 @@ \" lscpumf.1 .\" .\" -.\" Copyright IBM Corp. 2014, 2017 +.\" Copyright IBM Corp. 2014, 2020 .\" s390-tools is free software; you can redistribute it and/or modify .\" it under the terms of the MIT license. See LICENSE for details. .\" ---------------------------------------------------------------------- -.TH lscpumf "1" "February 2014" "s390-tools" "CPU-MF management programs" +.TH lscpumf "1" "May 2020" "s390-tools" "CPU-MF management programs" . .ds c \fBlscpumf\fP . @@ -19,8 +19,8 @@ lscpumf \- display information about CPU-measurement facilities .RB [ \-i | \-\-info ] .br .B lscpumf -.RB [ \-c | \-\-list\-counters ] -.RB [ \-C | \-\-list\-all\-counters ] +.RB [ \-c | \-\-list\-counters ] [ \-n ] +.RB [ \-C | \-\-list\-all\-counters ] [ \-n ] .RB [ \-s | \-\-list\-sampling\-events ] .br .B lscpumf @@ -46,12 +46,25 @@ facilities. Lists counters that are provided by the CPU-measurement facility, omitting counters for which the LPAR is not authorized. For counter measurements with the perf program, the raw event identifier is displayed. +For linux version 5.5 and later the raw event identifier is +displayed as :, where type is the number the CPU Measurement +counter facility device driver was assigned to by the kernel. +For earlier linux versions the raw event identifier is displayed as r. . .TP .BR \-C ", " \-\-list\-all\-counters Lists all counters that are provided by the CPU-measurement counter facility, regardless of LPAR authorization. To list only those counters for which the LPAR is authorized, use the -c option. +For linux version 5.5 and later the raw event identifier is +displayed as :, where type is the number the CPU Measurement +counter facility device driver was assigned to by the kernel. +For earlier linux versions the raw event identifier is displayed as r. +. +.TP +.BR \-n ", " \-\-name +. +Display the counter name together with the raw event identifier. . .TP .BR \-s ", " \-\-list\-sampling\-events