From 4762e65acbc4efe7142ccb5fd2ef86073737ebd8 Mon Sep 17 00:00:00 2001 From: Philipp Rudo Date: Wed, 6 Nov 2019 13:00:55 +0100 Subject: [PATCH] zipl: Consolidate STAGE{2,3} macros MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Increase consistency with the other macros by moving and renaming the STAGE{2,3} macros in zipl.h. Signed-off-by: Philipp Rudo Reviewed-by: Stefan Haberland Signed-off-by: Jan Höppner --- zipl/include/zipl.h | 8 ++++---- zipl/src/boot.c | 4 ++-- zipl/src/bootmap.c | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/zipl/include/zipl.h b/zipl/include/zipl.h index e2cb1e97..b7721d4e 100644 --- a/zipl/include/zipl.h +++ b/zipl/include/zipl.h @@ -19,13 +19,12 @@ #define ZIPL_MAGIC_SIZE 4 #define DISK_LAYOUT_ID 0x00000001 +#define STAGE3_ENTRY 0xa000UL #define IMAGE_ENTRY 0x10000UL #define IMAGE_ENTRY_KDUMP 0x10010UL -#define ZIPL_STAGE2_LOAD_ADDRESS 0x2000UL -#define ZIPL_STAGE3_ENTRY_ADDRESS 0xa000UL -#define DEFAULT_STAGE3_ADDRESS 0xa000UL -#define DEFAULT_STAGE3_PARAMS_ADDRESS 0x9000UL +#define STAGE2_LOAD_ADDRESS 0x2000UL +#define STAGE3_LOAD_ADDRESS 0xa000UL #define IMAGE_LOAD_ADDRESS IMAGE_ENTRY #define ADDRESS_LIMIT 0x80000000UL @@ -38,6 +37,7 @@ #define STAGE3_HEAP_ADDRESS 0x2000UL #define STAGE3_STACK_SIZE 0x1000UL #define STAGE3_STACK_ADDRESS 0xF000UL +#define STAGE3_PARAMS_ADDRESS 0x9000UL #define PSW_ADDRESS_MASK 0x000000007fffffffUL #define PSW_LOAD 0x0008000080000000UL diff --git a/zipl/src/boot.c b/zipl/src/boot.c index 74ce61f4..9ce31412 100644 --- a/zipl/src/boot.c +++ b/zipl/src/boot.c @@ -195,7 +195,7 @@ boot_init_fba_stage1b(struct boot_fba_stage1b *stage1b, stage1b->locdata[i].blocknr = (uint32_t) stage2_list[i].linear.block; stage1b->locread[i].read.address_lo = - ZIPL_STAGE2_LOAD_ADDRESS + i * FBA_BLK_SIZE; + STAGE2_LOAD_ADDRESS + i * FBA_BLK_SIZE; } /* Terminate CCW chain */ stage1b->locread[i - 1].read.flags &= ~CCW_FLAG_CC; @@ -220,7 +220,7 @@ boot_init_eckd_stage1b(struct boot_eckd_stage1b *stage1b, stage1b->seek[i].head = stage2_list[i].chs.head | ((stage2_list[i].chs.cyl >> 12) & 0xfff0); stage1b->seek[i].sec = stage2_list[i].chs.sec; - stage1b->ssrt[i].read.address_lo = ZIPL_STAGE2_LOAD_ADDRESS + + stage1b->ssrt[i].read.address_lo = STAGE2_LOAD_ADDRESS + i * stage2_list[i].chs.size; stage1b->ssrt[i].read.flags = CCW_FLAG_CC | CCW_FLAG_SLI; } diff --git a/zipl/src/bootmap.c b/zipl/src/bootmap.c index b208bbd9..06c2c58a 100644 --- a/zipl/src/bootmap.c +++ b/zipl/src/bootmap.c @@ -627,7 +627,7 @@ add_ipl_program(int fd, struct job_ipl_data* ipl, disk_blockptr_t* program, } /* Add stage 3 loader to bootmap */ - rc = add_component_file(fd, ZIPL_STAGE3_PATH, DEFAULT_STAGE3_ADDRESS, + rc = add_component_file(fd, ZIPL_STAGE3_PATH, STAGE3_LOAD_ADDRESS, signature_size, VOID_ADD(table, offset), 1, info, target, &comp_loc[comp_nr]); if (rc) { @@ -654,7 +654,7 @@ add_ipl_program(int fd, struct job_ipl_data* ipl, disk_blockptr_t* program, } rc = add_component_buffer(fd, stage3_params, stage3_params_size, (component_data) (uint64_t) - DEFAULT_STAGE3_PARAMS_ADDRESS, + STAGE3_PARAMS_ADDRESS, VOID_ADD(table, offset), info, &comp_loc[comp_nr], component_load); free(stage3_params); @@ -792,7 +792,7 @@ add_ipl_program(int fd, struct job_ipl_data* ipl, disk_blockptr_t* program, create_component_entry(VOID_ADD(table, offset), NULL, component_execute, (component_data) (uint64_t) - (ZIPL_STAGE3_ENTRY_ADDRESS | PSW_LOAD), + (STAGE3_ENTRY | PSW_LOAD), info); /* Write component table */ rc = disk_write_block_aligned(fd, table, info->phy_block_size,