From 8688d47e3df1b6460d7fea32c5edc23b1bb203e0 Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Tue, 20 Mar 2018 08:06:06 +0000 Subject: [PATCH] cpumf: Add short description for z13 extended counter set MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a short description to the z13 extended counter set definition file. Signed-off-by: Thomas Richter Reviewed-by: Hendrik Brueckner Signed-off-by: Jan Höppner --- cpumf/data/cpum-cf-extended-z13.ctr | 56 +++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/cpumf/data/cpum-cf-extended-z13.ctr b/cpumf/data/cpum-cf-extended-z13.ctr index 6330387c..7b8a34a7 100644 --- a/cpumf/data/cpum-cf-extended-z13.ctr +++ b/cpumf/data/cpum-cf-extended-z13.ctr @@ -17,288 +17,342 @@ # Extended Counter Set # --------------------------------------------------------------------- Counter:128 Name:L1D_RO_EXCL_WRITES +Short-Description:L1D RO Exclusive Writes Description: A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line. . Counter:129 Name:DTLB1_WRITES +Short-Description:DTLB1 Writes Description: A translation entry has been written to the Level-1 Data Translation Lookaside Buffer . Counter:130 Name:DTLB1_MISSES +Short-Description:DTLB1 Misses Description: Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress. . Counter:131 Name:DTLB1_HPAGE_WRITES +Short-Description:DTLB1 One-Megabyte Page Writes Description: A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page . Counter:132 Name:DTLB1_GPAGE_WRITES +Short-Description:DTLB1 Two-Gigabyte Page Writes A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a two-gigabyte page. . Counter:133 Name:L1D_L2D_SOURCED_WRITES +Short-Description:L1D L2D Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache . Counter:134 Name:ITLB1_WRITES +Short-Description:ITLB1 Writes Description: A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer . Counter:135 Name:ITLB1_MISSES +Short-Description:ITLB1 Misses Description: Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress . Counter:136 Name:L1I_L2I_SOURCED_WRITES +Short-Description:L1I L2I Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache . Counter:137 Name:TLB2_PTE_WRITES +Short-Description:TLB2 PTE Writes Description: A translation entry has been written to the Level-2 TLB Page Table Entry arrays . Counter:138 Name:TLB2_CRSTE_HPAGE_WRITES +Short-Description:TLB2 CRSTE One-Megabate Page Writes Description: A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays for a one-megabyte large page translation . Counter:139 Name:TLB2_CRSTE_WRITES +Short-Description:TLB2 CRSTE Writes Description: A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays . Counter:140 Name:TX_C_TEND +Short-Description:Completed TEND instructions in constrained TX mode Description: A TEND instruction has completed in a constrained transactional-execution mode . Counter:141 Name:TX_NC_TEND +Short-Description:Completed TEND instructions in non constrained TX mode Description: A TEND instruction has completed in a non-constrained transactional-execution mode . Counter:143 Name:L1C_TLB1_MISSES +Short-Description:L1C TLB1 Misses Description: Increments by one for any cycle where a Level-1 cache or Level-1 TLB miss is in progress. . Counter:144 Name:L1D_ONCHIP_L3_SOURCED_WRITES +Short-Description:L1D On-Chip L3 Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention . Counter:145 Name:L1D_ONCHIP_L3_SOURCED_WRITES_IV +Short-Description:L1D On-Chip L3 Sourced Writes with Intervention Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention . Counter:146 Name:L1D_ONNODE_L4_SOURCED_WRITES +Short-Description:L1D On-Node L4 Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-4 cache . Counter:147 Name:L1D_ONNODE_L3_SOURCED_WRITES_IV +Short-Description:L1D On-Node L3 Sourced Writes with Intervention Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention . Counter:148 Name:L1D_ONNODE_L3_SOURCED_WRITES +Short-Description:L1D On-Node L3 Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention . Counter:149 Name:L1D_ONDRAWER_L4_SOURCED_WRITES +Short-Description:L1D On-Drawer L4 Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache . Counter:150 Name:L1D_ONDRAWER_L3_SOURCED_WRITES_IV +Short-Description:L1D On-Drawer L3 Sourced Writes with Intervention Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention . Counter:151 Name:L1D_ONDRAWER_L3_SOURCED_WRITES +Short-Description:L1D On-Drawer L3 Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention . Counter:152 Name:L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES +Short-Description:L1D Off-Drawer Same-Column L4 Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache . Counter:153 Name:L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV +Short-Description:L1D Off-Drawer Same-Column L3 Sourced Writes with Intervention Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention . Counter:154 Name:L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES +Short-Description:L1D Off-Drawer Same-Column L3 Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention . Counter:155 Name:L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES +Short-Description:L1D Off-Drawer Far-Column L3 Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache . Counter:156 Name:L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV +Short-Description:L1D Off-Drawer Far-Column L3 Sourced Writes with Intervention Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention . Counter:157 Name:L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES +Short-Description:L1D Off-Drawer Far-Column L3 Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention . Counter:158 Name:L1D_ONNODE_MEM_SOURCED_WRITES +Short-Description:L1D On-Node Memory Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Node memory . Counter:159 Name:L1D_ONDRAWER_MEM_SOURCED_WRITES +Short-Description:L1D On-Drawer Memory Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory . Counter:160 Name:L1D_OFFDRAWER_MEM_SOURCED_WRITES +Short-Description:L1D Off-Drawer Memory Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory . Counter:161 Name:L1D_ONCHIP_MEM_SOURCED_WRITES +Short-Description:L1D On-Chip Memory Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory . Counter:162 Name:L1I_ONCHIP_L3_SOURCED_WRITES +Short-Description:L1I On-Chip L3 Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention . Counter:163 Name:L1I_ONCHIP_L3_SOURCED_WRITES_IV +Short-Description:L1I On-Chip L3 Sourced Writes with Intervention Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention . Counter:164 Name:L1I_ONNODE_L4_SOURCED_WRITES +Short-Description:L1I On-Chip L4 Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-4 cache . Counter:165 Name:L1I_ONNODE_L3_SOURCED_WRITES_IV +Short-Description:L1I On-Node L3 Sourced Writes with Intervention Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention . Counter:166 Name:L1I_ONNODE_L3_SOURCED_WRITES +Short-Description:L1I On-Node L3 Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention . Counter:167 Name:L1I_ONDRAWER_L4_SOURCED_WRITES +Short-Description:L1I On-Drawer L4 Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache . Counter:168 Name:L1I_ONDRAWER_L3_SOURCED_WRITES_IV +Short-Description:L1I On-Drawer L3 Sourced Writes with Intervention Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention . Counter:169 Name:L1I_ONDRAWER_L3_SOURCED_WRITES +Short-Description:L1I On-Drawer L3 Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention . Counter:170 Name:L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES +Short-Description:L1I Off-Drawer Same-Column L4 Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache . Counter:171 Name:L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV +Short-Description:L1I Off-Drawer Same-Column L3 Sourced Writes with Intervention Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention . Counter:172 Name:L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES +Short-Description:L1I Off-Drawer Same-Column L3 Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention . Counter:173 Name:L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES +Short-Description:L1I Off-Drawer Far-Column L4 Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache . Counter:174 Name:L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV +Short-Description:L1I Off-Drawer Far-Column L3 Sourced Writes with Intervention Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention . Counter:175 Name:L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES +Short-Description:L1I Off-Drawer Far-Column L3 Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention . Counter:176 Name:L1I_ONNODE_MEM_SOURCED_WRITES +Short-Description:L1I On-Node Memory Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Node memory . Counter:177 Name:L1I_ONDRAWER_MEM_SOURCED_WRITES +Short-Description:L1I On-Drawer Memory Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory . Counter:178 Name:L1I_OFFDRAWER_MEM_SOURCED_WRITES +Short-Description:L1I Off-Drawer Memory Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory . Counter:179 Name:L1I_ONCHIP_MEM_SOURCED_WRITES +Short-Description:L1I On-Chip Memory Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory . Counter:218 Name:TX_NC_TABORT +Short-Description:Aborted transaction in non constrained TX mode Description: A transaction abort has occurred in a non-constrained transactional-execution mode . Counter:219 Name:TX_C_TABORT_NO_SPECIAL +Short-Description:Aborted transactions in constrained TX mode not using special completion logic Description: A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete . Counter:220 Name:TX_C_TABORT_SPECIAL +Short-Description:Aborted transactions in constrained TX mode using special completion logic Description: A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to @@ -308,10 +362,12 @@ complete # MT-diagnostic counter set # --------------------------------------------------------------------- Counter:448 Name:MT_DIAG_CYCLES_ONE_THR_ACTIVE +Short-Description:Cycle count with one thread active Description: Cycle count with one thread active . Counter:449 Name:MT_DIAG_CYCLES_TWO_THR_ACTIVE +Short-Description:cycle count with two threads active Description: Cycle count with two threads active .