diff --git a/cpumf/data/cpum-cf-extended-z14.ctr b/cpumf/data/cpum-cf-extended-z14.ctr index 12f9d0dc..fd78ef52 100644 --- a/cpumf/data/cpum-cf-extended-z14.ctr +++ b/cpumf/data/cpum-cf-extended-z14.ctr @@ -20,272 +20,323 @@ # Extended Counter Set # --------------------------------------------------------------------- Counter:128 Name:L1D_RO_EXCL_WRITES +Short-Description:L1D Read-only Exclusive Writes Description: A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line . Counter:129 Name:DTLB2_WRITES +Short-Description:DTLB2 Writes Description: A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache . Counter:130 Name:DTLB2_MISSES +Short-Description:DTLB2 Misses Description: A TLB2 miss is in progress for a request made by the data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle . Counter:131 Name:DTLB2_HPAGE_WRITES +Short-Description:DTLB2 One-Megabyte Page Writes Description: A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page or a Last Host Translation was done . Counter:132 Name:DTLB2_GPAGE_WRITES +Short-Description:DTLB2 Two-Gigabye Page Writes Description: A translation entry for a two-gigabyte page was written into the Level-2 TLB . Counter:133 Name:L1D_L2D_SOURCED_WRITES +Short-Description:L1D L2D SOURCED Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache . Counter:134 Name:ITLB2_WRITES +Short-Description:ITLB2 Writes Description: A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache . Counter:135 Name:ITLB2_MISSES +Short-Description:ITLB2 Misses Description: A TLB2 miss is in progress for a request made by the instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle . Counter:136 Name:L1I_L2I_SOURCED_WRITES +Short-Description:L1I L2I Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache . Counter:137 Name:TLB2_PTE_WRITES +Short-Description:TLB2 PTE Writes Description: A translation entry was written into the Page Table Entry array in the Level-2 TLB . Counter:138 Name:TLB2_CRSTE_WRITES +Short-Description:TLB2 CRSTE Writes Description: Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB . Counter:139 Name:TLB2_ENGINES_BUSY +Short-Description:TLB2 Engines Busy Description: The number of Level-2 TLB translation engines busy in a cycle . Counter:140 Name:TX_C_TEND +Short-Description:Completed TEND instructions in constrained TX mode Description: A TEND instruction has completed in a constrained transactional-execution mode . Counter:141 Name:TX_NC_TEND +Short-Description:Completed TEND instructions in non constrained TX mode Description: A TEND instruction has completed in a non-constrained transactional-execution mode . Counter:143 Name:L1C_TLB2_MISSES +Short-Description:L1C TLB2 Misses Description: Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress . Counter:144 Name:L1D_ONCHIP_L3_SOURCED_WRITES +Short-Description:L1D On-Chip L3 Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention . Counter:145 Name:L1D_ONCHIP_MEMORY_SOURCED_WRITES +Short-Description:L1D On-Chip Memory Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory . Counter:146 Name:L1D_ONCHIP_L3_SOURCED_WRITES_IV +Short-Description:L1D On-Chip L3 Sourced Writes with intervention Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention . Counter:147 Name:L1D_ONCLUSTER_L3_SOURCED_WRITES +Short-Description:L1D On-Cluster L3 Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Cluster Level-3 cache withountervention . Counter:148 Name:L1D_ONCLUSTER_MEMORY_SOURCED_WRITES +Short-Description:L1D On-Cluster Memory Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster memory . Counter:149 Name:L1D_ONCLUSTER_L3_SOURCED_WRITES_IV +Short-Description:L1D On-Cluster L3 Sourced Writes with intervention Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache with intervention . Counter:150 Name:L1D_OFFCLUSTER_L3_SOURCED_WRITES +Short-Description:L1D Off-Cluster L3 Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention . Counter:151 Name:L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES +Short-Description:L1D Off-Cluster Memory Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Cluster memory . Counter:152 Name:L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV +Short-Description:L1D Off-Cluster L3 Sourced Writes with intervention Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention . Counter:153 Name:L1D_OFFDRAWER_L3_SOURCED_WRITES +Short-Description:L1D Off-Drawer L3 Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention . Counter:154 Name:L1D_OFFDRAWER_MEMORY_SOURCED_WRITES +Short-Description:L1D Off-Drawer Memory Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory . Counter:155 Name:L1D_OFFDRAWER_L3_SOURCED_WRITES_IV +Short-Description:L1D Off-Drawer L3 Sourced Writes with intervention Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention . Counter:156 Name:L1D_ONDRAWER_L4_SOURCED_WRITES +Short-Description:L1D On-Drawer L4 Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer Level-4 cache . Counter:157 Name:L1D_OFFDRAWER_L4_SOURCED_WRITES +Short-Description:L1D Off-Drawer L4 Sourced Writes Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache . Counter:158 Name:L1D_ONCHIP_L3_SOURCED_WRITES_RO +Short-Description:L1D On-Chip L3 Sourced Writes RO Description: A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip L3 but a read-only invalidate was done to remove other copies of the cache line . Counter:162 Name:L1I_ONCHIP_L3_SOURCED_WRITES +Short-Description:L1I On-Chip L3 Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache without intervention . Counter:163 Name:L1I_ONCHIP_MEMORY_SOURCED_WRITES +Short-Description:L1I On-Chip Memory Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from On-Chip memory . Counter:164 Name:L1I_ONCHIP_L3_SOURCED_WRITES_IV +Short-Description:L1I On-Chip L3 Sourced Writes with intervention Description: A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache with intervention . Counter:165 Name:L1I_ONCLUSTER_L3_SOURCED_WRITES +Short-Description:L1I On-Cluster L3 Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache without intervention . Counter:166 Name:L1I_ONCLUSTER_MEMORY_SOURCED_WRITES +Short-Description:L1I On-Cluster Memory Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster memory . Counter:167 Name:L1I_ONCLUSTER_L3_SOURCED_WRITES_IV +Short-Description:L1I On-Cluster L3 Sourced Writes with intervention Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Cluster Level-3 cache with intervention . Counter:168 Name:L1I_OFFCLUSTER_L3_SOURCED_WRITES +Short-Description:L1I Off-Cluster L3 Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention . Counter:169 Name:L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES +Short-Description:L1I Off-Cluster Memory Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Cluster memory . Counter:170 Name:L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV +Short-Description:L1I Off-Cluster L3 Sourced Writes with intervention Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention . Counter:171 Name:L1I_OFFDRAWER_L3_SOURCED_WRITES +Short-Description:L1I Off-Drawer L3 Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention . Counter:172 Name:L1I_OFFDRAWER_MEMORY_SOURCED_WRITES +Short-Description:L1I Off-Drawer Memory Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory . Counter:173 Name:L1I_OFFDRAWER_L3_SOURCED_WRITES_IV +Short-Description:L1I Off-Drawer L3 Sourced Writes with intervention Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention . Counter:174 Name:L1I_ONDRAWER_L4_SOURCED_WRITES +Short-Description:L1I On-Drawer L4 Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer Level-4 cache . Counter:175 Name:L1I_OFFDRAWER_L4_SOURCED_WRITES +Short-Description:L1I Off-Drawer L4 Sourced Writes Description: A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache . Counter:224 Name:BCD_DFP_EXECUTION_SLOTS +Short-Description:BCD DFP Execution Slots Description: Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT . Counter:225 Name:VX_BCD_EXECUTION_SLOTS +Short-Description:VX BCD Execution Slots Description: Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG . Counter:226 Name:DECIMAL_INSTRUCTIONS +Short-Description:Decimal Instructions Description: Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP . Counter:232 Name:LAST_HOST_TRANSLATIONS +Short-Description:Last host translation done Description: Last Host Translation done . Counter:243 Name:TX_NC_TABORT +Short-Description:Aborted transaction in non constrained TX mode Description: A transaction abort has occurred in a non-constrained transactional-execution mode . Counter:244 Name:TX_C_TABORT_NO_SPECIAL +Short-Description:Aborted transactions in constrained TX mode not using special completion logic Description: A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete . Counter:245 Name:TX_C_TABORT_SPECIAL +Short-Description:Aborted transactions in constrained TX mode using special completion logic Description: A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to @@ -295,10 +346,12 @@ complete # MT-diagnostic counter set # --------------------------------------------------------------------- Counter:448 Name:MT_DIAG_CYCLES_ONE_THR_ACTIVE +Short-Description:Cycle count with one thread active Description: Cycle count with one thread active . Counter:449 Name:MT_DIAG_CYCLES_TWO_THR_ACTIVE +Short-Description:Cycle count with two threads active Description: Cycle count with two threads active .