mirror of
https://github.com/ibm-s390-linux/s390-tools.git
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b627b8d8e1
This commit is based on the s390-tools-1.39.0 version. Changes on top of s390-tools-1.39.0: - Add MIT license to all source files - Add LICENSE file - Transform REAMDE to README.md (markdown) - Add AUTHORS.md file - Add CONTRIBUTING.md file - Move changelog from README to CHANGELOG.md file Reviewed-by: Stefan Haberland <sth@linux.vnet.ibm.com> Signed-off-by: Michael Holzheu <holzheu@linux.vnet.ibm.com>
97 lines
3.2 KiB
Plaintext
97 lines
3.2 KiB
Plaintext
Counter: 128 Name:L1I_L2_SOURCED_WRITES
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Description:
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A directory write to the Level-1 I-Cache directory where the returned
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cache line was sourced from the Level-2 (L1.5) cache
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.
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Counter: 129 Name:L1D_L2_SOURCED_WRITES
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Description:
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A directory write to the Level-1 D-Cache directory where the installed
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cache line was sourced from the Level-2 (L1.5) cache
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.
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Counter: 130 Name:L1I_L3_LOCAL_WRITES
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Description:
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A directory write to the Level-1 I-Cache directory where the installed
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cache line was sourced from the Level-3 cache that is on the same book
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as the Instruction cache (Local L2 cache)
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.
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Counter: 131 Name:L1D_L3_LOCAL_WRITES
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Description:
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A directory write to the Level-1 D-Cache directory where the installtion
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cache line was source from the Level-3 cache that is on the same book
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as the Data cache (Local L2 cache)
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.
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Counter: 132 Name:L1I_L3_REMOTE_WRITES
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Description:
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A directory write to the Level-1 I-Cache directory where the installed
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cache line was sourced from a Level-3 cache that is not on the same
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book as the Instruction cache (Remote L2 cache)
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.
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Counter: 133 Name:L1D_L3_REMOTE_WRITES
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Description:
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A directory write to the Level-1 D-Cache directory where the installed
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cache line was sourced from a Level-3 cache that is not on the same
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book as the Data cache (Remote L2 cache)
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.
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Counter: 134 Name:L1D_LMEM_SOURCED_WRITES
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Description:
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A directory write to the Level-1 D-Cache directory where the installed
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cache line was sourced from memory that is attached to the same book
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as the Data cache (Local Memory)
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.
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Counter: 135 Name:L1I_LMEM_SOURCED_WRITES
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Description:
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A directory write to the Level-1 I-Cache where the installed cache
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line was sourced from memory that is attached to the s ame book as the
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Instruction cahe (local Memory)
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.
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Counter: 136 Name:L1D_RO_EXCL_WRITES
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Description:
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A directory write to the Level-1 D-Cache where the line was originally
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in a Read-Only state in the cache but has been updated to be in the
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Exclusive state that allows stores to the cache line
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.
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Counter: 137 Name:L1I_CACHELINE_INVALIDATES
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Description:
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A cache line in the Level-1 I-Cache has been invalidated by a store on
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the same CPU as the Level-1 I-Cache
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.
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Counter: 138 Name:ITLB1_WRITES
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Description:
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A translation entry has been written into the Level-1 Instruction
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Translation Lookaside Buffer
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.
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Counter: 139 Name:DTLB1_WRITES
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Description:
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A translation entry has been written to the Level-1 Data Translation
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Lookaside Buffer
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Counter: 140 Name:TLB2_PTE_WRITES
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Description:
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A translation entry has been written to the Level-2 TLB Page Table
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Entry arrays
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Counter: 141 Name:TLB2_CRSTE_WRITES
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Description:
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A translation entry has been written to the Level-2 TLB Common Region
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Segment Table Entry arrays
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Counter: 142 Name:TLB2_CRSTE_HPAGE_WRITES
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Description:
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A translation entry has been written to the Level-2 TLB Common Region
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Segment Table Entry arrays for a one-megabyte large page translation
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Counter: 145 Name:ITLB1_MISSES
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Description:
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Level-1 Instruction TLB miss in progress. Incremented by one for every
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cycle an ITLB1 miss is in progress
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.
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Counter: 146 Name:DTLB1_MISSES
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Description:
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Level-1 Data TLB miss in progress. Incremented by one for every cycle
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an DTLB1 miss is in progress
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.
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Counter: 147 Name:L2C_STORES_SENT
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Description:
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Incremented by one for every store sent to Level-2 (L1.5) cache
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.
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