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b627b8d8e1
This commit is based on the s390-tools-1.39.0 version. Changes on top of s390-tools-1.39.0: - Add MIT license to all source files - Add LICENSE file - Transform REAMDE to README.md (markdown) - Add AUTHORS.md file - Add CONTRIBUTING.md file - Move changelog from README to CHANGELOG.md file Reviewed-by: Stefan Haberland <sth@linux.vnet.ibm.com> Signed-off-by: Michael Holzheu <holzheu@linux.vnet.ibm.com>
317 lines
11 KiB
Plaintext
317 lines
11 KiB
Plaintext
# Counter decriptions for the
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# IBM z13 extended counter and MT-diagnostic counter set
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#
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# Notes for transactional-execution mode symbolic names:
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# TX .. transactional-execution mode
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# NC .. nonconstrained
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# C .. constrained
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#
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# Undefined counters in the extended counter set:
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# 142
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# 180-217
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# 221-225
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# Undefined counters in the MT-diagnostic counter set:
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# 450-495
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#
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#
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# Extended Counter Set
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# ---------------------------------------------------------------------
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Counter:128 Name:L1D_WRITES_RO_EXCL
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A directory write to the Level-1 Data cache where the line was
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originally in a Read-Only state in the cache but has been updated
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to be in the Exclusive state that allows stores to the cache line.
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.
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Counter:129 Name:DTLB1_WRITES
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Description:
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A translation entry has been written to the Level-1 Data Translation
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Lookaside Buffer
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.
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Counter:130 Name:DTLB1_MISSES
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Description:
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Level-1 Data TLB miss in progress. Incremented by one for every cycle
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a DTLB1 miss is in progress.
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.
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Counter:131 Name:DTLB1_HPAGE_WRITES
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Description:
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A translation entry has been written to the Level-1 Data Translation
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Lookaside Buffer for a one-megabyte page
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.
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Counter:132 Name:DTLB1_GPAGE_WRITES
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A translation entry has been written to the Level-1 Data Translation
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Lookaside Buffer for a two-gigabyte page.
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.
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Counter:133 Name:L1D_L2D_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from the Level-2 Data cache
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.
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Counter:134 Name:ITLB1_WRITES
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Description:
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A translation entry has been written to the Level-1 Instruction
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Translation Lookaside Buffer
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.
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Counter:135 Name:ITLB1_MISSES
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Description:
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Level-1 Instruction TLB miss in progress. Incremented by one for every
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cycle an ITLB1 miss is in progress
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.
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Counter:136 Name:L1I_L2I_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from the Level-2 Instruction cache
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.
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Counter:137 Name:TLB2_PTE_WRITES
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Description:
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A translation entry has been written to the Level-2 TLB Page Table
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Entry arrays
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.
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Counter:138 Name:TLB2_CRSTE_HPAGE_WRITES
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Description:
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A translation entry has been written to the Level-2 TLB Combined Region
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Segment Table Entry arrays for a one-megabyte large page translation
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.
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Counter:139 Name:TLB2_CRSTE_WRITES
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Description:
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A translation entry has been written to the Level-2 TLB Combined Region
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Segment Table Entry arrays
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.
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Counter:140 Name:TX_C_TEND
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Description:
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A TEND instruction has completed in a constrained transactional-execution
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mode
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.
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Counter:141 Name:TX_NC_TEND
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Description:
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A TEND instruction has completed in a non-constrained
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transactional-execution mode
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.
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Counter:143 Name:L1C_TLB1_MISSES
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Description:
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Increments by one for any cycle where a Level-1 cache or Level-1 TLB miss
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is in progress.
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.
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Counter:144 Name:L1D_ONCHIP_L3_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an On-Chip Level-3 cache without intervention
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.
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Counter:145 Name:L1D_ONCHIP_L3_SOURCED_WRITES_IV
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an On-Chip Level-3 cache with intervention
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.
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Counter:146 Name:L1D_ONNODE_L4_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an On-Node Level-4 cache
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.
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Counter:147 Name:L1D_ONNODE_L3_SOURCED_WRITES_IV
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an On-Node Level-3 cache with intervention
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.
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Counter:148 Name:L1D_ONNODE_L3_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an On-Node Level-3 cache without intervention
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.
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Counter:149 Name:L1D_ONDRAWER_L4_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an On-Drawer Level-4 cache
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.
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Counter:150 Name:L1D_ONDRAWER_L3_SOURCED_WRITES_IV
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an On-Drawer Level-3 cache with intervention
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.
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Counter:151 Name:L1D_ONDRAWER_L3_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an On-Drawer Level-3 cache without intervention
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.
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Counter:152 Name:L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an Off-Drawer Same-Column Level-4 cache
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.
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Counter:153 Name:L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an Off-Drawer Same-Column Level-3 cache with
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intervention
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.
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Counter:154 Name:L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an Off-Drawer Same-Column Level-3 cache
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without intervention
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.
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Counter:155 Name:L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an Off-Drawer Far-Column Level-4 cache
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.
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Counter:156 Name:L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an Off-Drawer Far-Column Level-3 cache with
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intervention
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.
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Counter:157 Name:L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an Off-Drawer Far-Column Level-3 cache
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without intervention
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.
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Counter:158 Name:L1D_ONNODE_MEM_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from On-Node memory
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.
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Counter:159 Name:L1D_ONDRAWER_MEM_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from On-Drawer memory
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.
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Counter:160 Name:L1D_OFFDRAWER_MEM_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from On-Drawer memory
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.
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Counter:161 Name:L1D_ONCHIP_MEM_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from On-Chip memory
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.
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Counter:162 Name:L1I_ONCHIP_L3_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from an On-Chip Level-3 cache without
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intervention
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.
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Counter:163 Name:L1I_ONCHIP_L3_SOURCED_WRITES_IV
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from an On Chip Level-3 cache with
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intervention
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.
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Counter:164 Name:L1I_ONNODE_L4_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from an On-Node Level-4 cache
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.
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Counter:165 Name:L1I_ONNODE_L3_SOURCED_WRITES_IV
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Description:
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A directory write to the Level-1 Instruction cache directory where
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the returned cache line was sourced from an On-Node Level-3 cache
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with intervention
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.
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Counter:166 Name:L1I_ONNODE_L3_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Instruction cache directory where
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the returned cache line was sourced from an On-Node Level-3 cache
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without intervention
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.
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Counter:167 Name:L1I_ONDRAWER_L4_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Instruction cache directory where
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the returned cache line was sourced from an On-Drawer Level-4 cache
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.
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Counter:168 Name:L1I_ONDRAWER_L3_SOURCED_WRITES_IV
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Description:
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A directory write to the Level-1 Instruction cache directory where
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the returned cache line was sourced from an On-Drawer Level-3 cache
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with intervention
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.
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Counter:169 Name:L1I_ONDRAWER_L3_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Instruction cache directory where
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the returned cache line was sourced from an On-Drawer Level-3 cache
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without intervention
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.
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Counter:170 Name:L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Instruction cache directory where
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the returned cache line was sourced from an Off-Drawer Same-Column
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Level-4 cache
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.
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Counter:171 Name:L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV
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Description:
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A directory write to the Level-1 Instruction cache directory where
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the returned cache line was sourced from an Off-Drawer Same-Column
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Level-3 cache with intervention
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.
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Counter:172 Name:L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Instruction cache directory where
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the returned cache line was sourced from an Off-Drawer Same-Column
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Level-3 cache without intervention
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.
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Counter:173 Name:L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Instruction cache directory where
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the returned cache line was sourced from an Off-Drawer Far-Column
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Level-4 cache
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.
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Counter:174 Name:L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV
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Description:
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A directory write to the Level-1 Instruction cache directory where
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the returned cache line was sourced from an Off-Drawer Far-Column
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Level-3 cache with intervention
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.
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Counter:175 Name:L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Instruction cache directory where
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the returned cache line was sourced from an Off-Drawer Far-Column
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Level-3 cache without intervention
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.
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Counter:176 Name:L1I_ONNODE_MEM_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Instruction cache directory where
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the returned cache line was sourced from On-Node memory
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.
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Counter:177 Name:L1I_ONDRAWER_MEM_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Instruction cache directory where
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the returned cache line was sourced from On-Drawer memory
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.
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Counter:178 Name:L1I_OFFDRAWER_MEM_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Instruction cache directory where
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the returned cache line was sourced from On-Drawer memory
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.
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Counter:179 Name:L1I_ONCHIP_MEM_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Instruction cache directory where
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the returned cache line was sourced from On-Chip memory
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.
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Counter:218 Name:TX_NC_TABORT
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Description:
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A transaction abort has occurred in a non-constrained
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transactional-execution mode
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.
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Counter:219 Name:TX_C_TABORT_NO_SPECIAL
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Description:
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A transaction abort has occurred in a constrained transactional-execution
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mode and the CPU is not using any special logic to allow the transaction
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to complete
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.
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Counter:220 Name:TX_C_TABORT_SPECIAL
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Description:
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A transaction abort has occurred in a constrained transactional-execution
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mode and the CPU is using special logic to allow the transaction to
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complete
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.
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#
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# MT-diagnostic counter set
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# ---------------------------------------------------------------------
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Counter:448 Name:MT_DIAG_CYCLES_ONE_THR_ACTIVE
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Description:
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Cycle count with one thread active
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.
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Counter:449 Name:MT_DIAG_CYCLES_TWO_THR_ACTIVE
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Description:
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Cycle count with two threads active
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.
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