mirror of
https://github.com/ibm-s390-linux/s390-tools.git
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b627b8d8e1
This commit is based on the s390-tools-1.39.0 version. Changes on top of s390-tools-1.39.0: - Add MIT license to all source files - Add LICENSE file - Transform REAMDE to README.md (markdown) - Add AUTHORS.md file - Add CONTRIBUTING.md file - Move changelog from README to CHANGELOG.md file Reviewed-by: Stefan Haberland <sth@linux.vnet.ibm.com> Signed-off-by: Michael Holzheu <holzheu@linux.vnet.ibm.com>
196 lines
6.6 KiB
Plaintext
196 lines
6.6 KiB
Plaintext
Counter: 128 Name:DTLB1_MISSES
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Description:
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Level-1 Data TLB miss in progress. Incremented by one for every cycle
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a DTLB1 miss is in progress.
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.
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Counter:129 Name:ITLB1_MISSES
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Description:
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Level-1 Instruction TLB miss in progress. Incremented by one for every
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cycle a ITLB1 miss is in progress.
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.
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Counter:130 Name:L1D_L2I_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from the Level-2 Instruction cache
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.
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Counter:131 Name:L1I_L2I_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from the Level-2 Instruction cache
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.
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Counter:132 Name:L1D_L2D_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from the Level-2 Data cache
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.
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Counter:133 Name:DTLB1_WRITES
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Description:
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A translation entry has been written to the Level-1 Data Translation
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Lookaside Buffer
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.
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Counter:135 Name:L1D_LMEM_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Data cache where the installed cache line
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was sourced from memory that is attached to the same book as the Data
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cache (Local Memory)
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.
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Counter:137 Name:L1I_LMEM_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Instruction cache where the installed cache
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line was sourced from memory that is attached to the same book as the
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Instruction cache (Local Memory)
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.
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Counter:138 Name:L1D_RO_EXCL_WRITES
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Description:
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A directory write to the Level-1 D-Cache where the line was originally
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in a Read-Only state in the cache but has been updated to be in the
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Exclusive state that allows stores to the cache line
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.
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Counter:139 Name:DTLB1_HPAGE_WRITES
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Description:
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A translation entry has been written to the Level-1 Data Translation
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Lookaside Buffer for a one-megabyte page
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.
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Counter:140 Name:ITLB1_WRITES
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Description:
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A translation entry has been written to the Level-1 Instruction
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Translation Lookaside Buffer
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.
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Counter:141 Name:TLB2_PTE_WRITES
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Description:
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A translation entry has been written to the Level-2 TLB Page Table
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Entry arrays
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.
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Counter:142 Name:TLB2_CRSTE_HPAGE_WRITES
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Description:
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A translation entry has been written to the Level-2 TLB Common Region
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Segment Table Entry arrays for a one-megabyte large page translation
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.
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Counter:143 Name:TLB2_CRSTE_WRITES
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Description:
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A translation entry has been written to the Level-2 TLB Common Region
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Segment Table Entry arrays
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.
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Counter:144 Name:L1D_ONCHIP_L3_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an On Chip Level-3 cache without intervention
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.
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Counter:145 Name:L1D_OFFCHIP_L3_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an Off Chip/On Book Level-3 cache without
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intervention
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.
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Counter:146 Name:L1D_OFFBOOK_L3_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an Off Book Level-3 cache without intervention
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.
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Counter:147 Name:L1D_ONBOOK_L4_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an On Book Level-4 cache
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.
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Counter:148 Name:L1D_OFFBOOK_L4_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an Off Book Level-4 cache
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.
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#
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# Notes for the transactional-execution mode notations:
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# TX .. transactional-execution mode
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# NC .. nonconstrained
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# C .. constrained
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#
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Counter:149 Name:TX_NC_TEND
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Description:
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A TEND instruction has completed in a nonconstrained
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transactional-execution mode
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.
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Counter:150 Name:L1D_ONCHIP_L3_SOURCED_WRITES_IV
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from a On Chip Level-3 cache with intervention
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.
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Counter:151 Name:L1D_OFFCHIP_L3_SOURCED_WRITES_IV
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an Off Chip/On Book Level-3 cache with
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intervention
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.
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# XXX Remove SOURCED from L1D_OFFBOOK_L3_SOURCED_WRITES...
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Counter:152 Name:L1D_OFFBOOK_L3_SOURCED_WRITES_IV
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an Off Book Level-3 cache with intervention
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.
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Counter:153 Name:L1I_ONCHIP_L3_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from an On Chip Level-3 cache without
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intervention
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.
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Counter:154 Name:L1I_OFFCHIP_L3_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from an Off Chip/On Book Level-3 cache
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without intervention
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.
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Counter:155 Name:L1I_OFFBOOK_L3_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from an Off Book Level-3 cache without
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intervention
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.
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Counter:156 Name:L1I_ONBOOK_L4_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from an On Book Level-4 cache
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.
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Counter:157 Name:L1I_OFFBOOK_L4_SOURCED_WRITES
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from an Off Book Level-4 cache
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.
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Counter:158 Name:TX_C_TEND
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Description:
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A TEND instruction has completed in a constrained transactional-execution
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mode
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.
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Counter:159 Name:L1I_ONCHIP_L3_SOURCED_WRITES_IV
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from an On Chip Level-3 cache with
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intervention
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.
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Counter:160 Name:L1I_OFFCHIP_L3_SOURCED_WRITES_IV
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from an Off Chip/On Book Level-3 cache
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with intervention
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.
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Counter:161 Name:L1I_OFFBOOK_L3_SOURCED_WRITES_IV
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from an Off Book Level-3 cache with
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intervention
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.
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Counter:177 Name:TX_NC_TABORT
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Description:
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A transaction abort has occurred in a nonconstrained
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transactional-execution mode
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.
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Counter:178 Name:TX_C_TABORT_NO_SPECIAL
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Description:
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A transaction abort has occurred in a constrained transactional-execution
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mode and the CPU is not using any special logic to allow the transaction
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to complete
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.
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Counter:179 Name:TX_C_TABORT_SPECIAL
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Description:
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A transaction abort has occurred in a constrained transactional-execution
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mode and the CPU is using special logic to allow the transaction to
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complete
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.
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