mirror of
https://github.com/ibm-s390-linux/s390-tools.git
synced 2026-08-05 02:14:52 +00:00
03b2bf028b
With GCC8 the following warning is displayed:
In file included from cio.h:15,
from stage2.h:15,
from menu.h:15,
from stage2.c:14:
s390.h:193:1: warning: alignment 1 of ‘struct _lowcore’ is less than 8
[-Wpacked-not-aligned]
} __packed;
^
Fix by aligning struct _lowcore to double page size.
Signed-off-by: Jan Höppner <hoeppner@linux.ibm.com>
480 lines
12 KiB
C
480 lines
12 KiB
C
/*
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* zipl - zSeries Initial Program Loader tool
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*
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* System z specific functions
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*
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* Copyright IBM Corp. 2013, 2017
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*
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* s390-tools is free software; you can redistribute it and/or modify
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* it under the terms of the MIT license. See LICENSE for details.
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*/
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#ifndef S390_H
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#define S390_H
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#include "../../include/lib/zt_common.h"
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#include "libc.h"
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#define __pa32(x) ((uint32_t)(unsigned long)(x))
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#define __pa(x) ((unsigned long)(x))
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#define MIN(x, y) ((x) < (y) ? (x) : (y))
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#define barrier() __asm__ __volatile__("": : :"memory")
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#define inline inline __attribute__((always_inline))
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/*
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* Helper macro for exception table entries
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*/
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#define EX_TABLE(_fault, _target) \
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".section .ex_table,\"a\"\n" \
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".align 4\n" \
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".long (" #_fault ")\n" \
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".long (" #_target ")\n" \
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".previous\n"
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struct psw_t {
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uint64_t mask;
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uint64_t addr;
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} __aligned(8);
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void load_wait_psw(uint64_t, struct psw_t *);
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struct _lowcore {
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uint8_t pad_0x0000[0x0014-0x0000]; /* 0x0000 */
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uint32_t ipl_parmblock_ptr; /* 0x0014 */
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uint8_t pad_0x0018[0x0080-0x0018]; /* 0x0018 */
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uint32_t ext_params; /* 0x0080 */
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uint16_t ext_cpu_addr; /* 0x0084 */
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uint16_t ext_int_code; /* 0x0086 */
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uint16_t svc_ilc; /* 0x0088 */
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uint16_t svc_code; /* 0x008a */
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uint16_t pgm_ilc; /* 0x008c */
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uint16_t pgm_code; /* 0x008e */
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uint32_t data_exc_code; /* 0x0090 */
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uint16_t mon_class_num; /* 0x0094 */
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uint16_t per_perc_atmid; /* 0x0096 */
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uint64_t per_address; /* 0x0098 */
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uint8_t exc_access_id; /* 0x00a0 */
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uint8_t per_access_id; /* 0x00a1 */
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uint8_t op_access_id; /* 0x00a2 */
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uint8_t ar_access_id; /* 0x00a3 */
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uint8_t pad_0x00a4[0x00a8-0x00a4]; /* 0x00a4 */
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uint64_t trans_exc_code; /* 0x00a8 */
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uint64_t monitor_code; /* 0x00b0 */
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uint16_t subchannel_id; /* 0x00b8 */
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uint16_t subchannel_nr; /* 0x00ba */
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uint32_t io_int_parm; /* 0x00bc */
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uint32_t io_int_word; /* 0x00c0 */
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uint8_t pad_0x00c4[0x00c8-0x00c4]; /* 0x00c4 */
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uint32_t stfl_fac_list; /* 0x00c8 */
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uint8_t pad_0x00cc[0x00e8-0x00cc]; /* 0x00cc */
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uint32_t mcck_interruption_code[2]; /* 0x00e8 */
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uint8_t pad_0x00f0[0x00f4-0x00f0]; /* 0x00f0 */
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uint32_t external_damage_code; /* 0x00f4 */
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uint64_t failing_storage_address; /* 0x00f8 */
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uint8_t pad_0x0100[0x0110-0x0100]; /* 0x0100 */
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uint64_t breaking_event_addr; /* 0x0110 */
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uint8_t pad_0x0118[0x0120-0x0118]; /* 0x0118 */
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struct psw_t restart_old_psw; /* 0x0120 */
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struct psw_t external_old_psw; /* 0x0130 */
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struct psw_t svc_old_psw; /* 0x0140 */
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struct psw_t program_old_psw; /* 0x0150 */
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struct psw_t mcck_old_psw; /* 0x0160 */
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struct psw_t io_old_psw; /* 0x0170 */
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uint8_t pad_0x0180[0x01a0-0x0180]; /* 0x0180 */
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struct psw_t restart_psw; /* 0x01a0 */
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struct psw_t external_new_psw; /* 0x01b0 */
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struct psw_t svc_new_psw; /* 0x01c0 */
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struct psw_t program_new_psw; /* 0x01d0 */
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struct psw_t mcck_new_psw; /* 0x01e0 */
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struct psw_t io_new_psw; /* 0x01f0 */
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/* Save areas. */
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uint64_t save_area_sync[8]; /* 0x0200 */
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uint64_t save_area_async[8]; /* 0x0240 */
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uint64_t save_area_restart[1]; /* 0x0280 */
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uint8_t pad_0x0288[0x0290-0x0288]; /* 0x0288 */
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/* Return psws. */
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struct psw_t return_psw; /* 0x0290 */
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struct psw_t return_mcck_psw; /* 0x02a0 */
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/* CPU accounting and timing values. */
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uint64_t sync_enter_timer; /* 0x02b0 */
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uint64_t async_enter_timer; /* 0x02b8 */
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uint64_t mcck_enter_timer; /* 0x02c0 */
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uint64_t exit_timer; /* 0x02c8 */
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uint64_t user_timer; /* 0x02d0 */
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uint64_t system_timer; /* 0x02d8 */
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uint64_t steal_timer; /* 0x02e0 */
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uint64_t last_update_timer; /* 0x02e8 */
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uint64_t last_update_clock; /* 0x02f0 */
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uint64_t int_clock; /* 0x02f8 */
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uint64_t mcck_clock; /* 0x0300 */
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uint64_t clock_comparator; /* 0x0308 */
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/* Current process. */
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uint64_t current_task; /* 0x0310 */
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uint64_t thread_info; /* 0x0318 */
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uint64_t kernel_stack; /* 0x0320 */
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/* Interrupt, panic and restart stack. */
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uint64_t async_stack; /* 0x0328 */
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uint64_t panic_stack; /* 0x0330 */
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uint64_t restart_stack; /* 0x0338 */
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/* Restart function and parameter. */
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uint64_t restart_fn; /* 0x0340 */
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uint64_t restart_data; /* 0x0348 */
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uint64_t restart_source; /* 0x0350 */
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/* Address space pointer. */
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uint64_t kernel_asce; /* 0x0358 */
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uint64_t user_asce; /* 0x0360 */
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uint64_t current_pid; /* 0x0368 */
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/* SMP info area */
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uint32_t cpu_nr; /* 0x0370 */
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uint32_t softirq_pending; /* 0x0374 */
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uint64_t percpu_offset; /* 0x0378 */
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uint64_t vdso_per_cpu_data; /* 0x0380 */
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uint64_t machine_flags; /* 0x0388 */
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uint64_t ftrace_func; /* 0x0390 */
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uint64_t gmap; /* 0x0398 */
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uint8_t pad_0x03a0[0x0400-0x03a0]; /* 0x03a0 */
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/* Interrupt response block. */
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uint8_t irb[64]; /* 0x0400 */
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/* Per cpu primary space access list */
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uint32_t paste[16]; /* 0x0440 */
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uint8_t pad_0x0480[0x0e00-0x0480]; /* 0x0480 */
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/*
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* 0xe00 contains the address of the IPL Parameter Information
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* block. Dump tools need IPIB for IPL after dump.
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* Note: do not change the position of any fields in 0x0e00-0x0f00
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*/
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uint64_t ipib; /* 0x0e00 */
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uint32_t ipib_checksum; /* 0x0e08 */
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uint64_t vmcore_info; /* 0x0e0c */
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uint8_t pad_0x0e14[0x0e18-0x0e14]; /* 0x0e14 */
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uint64_t os_info; /* 0x0e18 */
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uint8_t pad_0x0e20[0x0f00-0x0e20]; /* 0x0e20 */
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/* Extended facility list */
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uint64_t stfle_fac_list[32]; /* 0x0f00 */
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uint8_t pad_0x1000[0x11b0-0x1000]; /* 0x1000 */
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uint64_t vector_save_area_addr; /* 0x11b0 */
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/* 64 bit extparam used for pfault/diag 250: defined by architecture */
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uint64_t ext_params2; /* 0x11B8 */
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uint8_t pad_0x11c0[0x1200-0x11C0]; /* 0x11C0 */
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/* CPU register save area: defined by architecture */
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uint64_t floating_pt_save_area[16]; /* 0x1200 */
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uint64_t gpregs_save_area[16]; /* 0x1280 */
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struct psw_t psw_save_area; /* 0x1300 */
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uint8_t pad_0x1310[0x1318-0x1310]; /* 0x1310 */
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uint32_t prefixreg_save_area; /* 0x1318 */
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uint32_t fpt_creg_save_area; /* 0x131c */
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uint8_t pad_0x1320[0x1324-0x1320]; /* 0x1320 */
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uint32_t tod_progreg_save_area; /* 0x1324 */
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uint32_t cpu_timer_save_area[2]; /* 0x1328 */
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uint32_t clock_comp_save_area[2]; /* 0x1330 */
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uint8_t pad_0x1338[0x1340-0x1338]; /* 0x1338 */
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uint32_t access_regs_save_area[16]; /* 0x1340 */
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uint64_t cregs_save_area[16]; /* 0x1380 */
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uint8_t pad_0x1400[0x1800-0x1400]; /* 0x1400 */
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/* Transaction abort diagnostic block */
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uint8_t pgm_tdb[256]; /* 0x1800 */
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/* align to the top of the prefix area */
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uint8_t pad_0x1900[0x2000-0x1900]; /* 0x1900 */
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} __packed __aligned(8192);
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#define S390_lowcore (*((struct _lowcore *) 0))
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#define __LC_IPLDEV 0x0c6c
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#define __LC_OS_INFO 0x0e18
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#define PAGE_SIZE 4096
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void panic_notify(unsigned long reason);
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#define panic(reason, x...) \
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do { \
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printf(x); \
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panic_notify(reason); \
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libc_stop(reason); \
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} while (0)
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static inline int page_is_valid(unsigned long addr)
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{
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unsigned long tmp;
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int rc;
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asm volatile(
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"0: ic %1,%2\n"
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"1: lhi %0,1\n"
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"2:\n"
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".pushsection .fixup, \"ax\"\n"
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"3: xr %0,%0\n"
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" jg 2b\n"
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".popsection\n"
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EX_TABLE(0b, 3b) EX_TABLE(1b, 3b)
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: "=d" (rc), "=d" (tmp)
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: "Q" (*(unsigned long *) addr)
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: "cc");
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return rc;
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}
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static inline uint32_t csum_partial(const void *buf, int len, uint32_t sum)
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{
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register unsigned long reg2 asm("2") = (unsigned long) buf;
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register unsigned long reg3 asm("3") = (unsigned long) len;
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asm volatile(
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"0: cksm %0,%1\n" /* do checksum on longs */
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" jo 0b\n"
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: "+d" (sum), "+d" (reg2), "+d" (reg3) : : "cc", "memory");
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return sum;
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}
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#define __ctl_store(array, low, high) ({ \
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typedef struct { char _[sizeof(array)]; } __may_alias addrtype;\
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asm volatile( \
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" stctg %1,%2,%0\n" \
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: "=Q" (*(addrtype *)(&array)) \
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: "i" (low), "i" (high)); \
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})
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#define __ctl_load(array, low, high) ({ \
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typedef struct { char _[sizeof(array)]; } __may_alias addrtype; \
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asm volatile( \
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" lctlg %1,%2,%0\n" \
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: : "Q" (*(addrtype *)(&array)), \
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"i" (low), "i" (high)); \
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})
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static inline void __ctl_set_bit(unsigned int cr, unsigned int bit)
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{
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unsigned long reg;
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__ctl_store(reg, cr, cr);
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reg |= 1UL << bit;
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__ctl_load(reg, cr, cr);
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}
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/*
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* DIAG 308 support
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*/
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enum diag308_subcode {
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DIAG308_REL_HSA = 2,
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DIAG308_IPL = 3,
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DIAG308_DUMP = 4,
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DIAG308_SET = 5,
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DIAG308_STORE = 6,
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};
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static inline int diag308(unsigned long subcode, void *addr)
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{
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register unsigned long _addr asm("0") = (unsigned long) addr;
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register unsigned long _rc asm("1") = 0;
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asm volatile(
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" diag %0,%2,0x308\n"
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"0:\n"
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: "+d" (_addr), "+d" (_rc)
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: "d" (subcode) : "cc", "memory");
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return _rc;
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}
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/*
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* Signal Processor
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*/
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#define SIGP_STOP_AND_STORE_STATUS 9
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#define SIGP_SET_MULTI_THREADING 22
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#define SIGP_STORE_ASTATUS_AT_ADDRESS 23
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#define SIGP_CC_ORDER_CODE_ACCEPTED 0
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#define SIGP_CC_BUSY 2
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static inline int sigp(uint16_t addr, uint8_t order, uint32_t parm,
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uint32_t *status)
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{
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register unsigned int reg1 asm ("1") = parm;
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int cc;
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asm volatile(
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" sigp %1,%2,0(%3)\n"
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" ipm %0\n"
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" srl %0,28\n"
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: "=d" (cc), "+d" (reg1) : "d" (addr), "a" (order) : "cc");
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if (status && cc == 1)
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*status = reg1;
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return cc;
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}
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static inline int sigp_busy(uint16_t addr, uint8_t order, uint32_t parm,
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uint32_t *status)
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{
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int cc;
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do {
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cc = sigp(addr, order, parm, status);
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} while (cc == SIGP_CC_BUSY);
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return cc;
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}
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/*
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* Store CPU address
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*/
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static inline unsigned short stap(void)
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{
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unsigned short cpu_address;
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asm volatile("stap %0" : "=m" (cpu_address));
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return cpu_address;
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}
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/*
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* Program the clock comparator
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*/
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static inline void set_clock_comparator(uint64_t time)
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{
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asm volatile("sckc %0" : : "Q" (time));
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}
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/*
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* Program the CPU timer
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*/
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static inline void set_cpu_timer(uint64_t timer)
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{
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asm volatile("spt %0" : : "Q" (timer));
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}
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/*
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* Get current time (store clock)
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*/
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static inline unsigned long long get_tod_clock(void)
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{
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unsigned long long clk;
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asm volatile("stck %0" : "=Q" (clk) : : "cc");
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return clk;
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}
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/*
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* Get ID of current CPU
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*/
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struct cpuid {
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unsigned int version:8;
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unsigned int ident:24;
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unsigned int machine:16;
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unsigned int unused:16;
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} __packed __aligned(8);
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static inline void get_cpu_id(struct cpuid *ptr)
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{
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asm volatile("stidp %0" : "=Q" (*ptr));
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}
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/*
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* Check if we run under z/VM
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*/
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static inline int is_zvm(void)
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{
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struct cpuid cpuid;
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get_cpu_id(&cpuid);
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return cpuid.version == 0xff;
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}
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/*
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* Vector register definition
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*/
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typedef struct {
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uint32_t u[4];
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} __vector128;
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/*
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* Save vector registers
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*/
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static inline void save_vx_regs(__vector128 *vxrs)
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{
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typedef struct { __vector128 _[32]; } addrtype;
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asm volatile(
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" la 1,%0\n"
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" .word 0xe70f,0x1000,0x003e\n" /* vstm 0,15,0(1) */
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" .word 0xe70f,0x1100,0x0c3e\n" /* vstm 16,31,256(1) */
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: "=Q" (*(addrtype *) vxrs) : : "1");
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}
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/*
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* Save vector registers safe
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*/
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static inline void save_vx_regs_safe(__vector128 *vxrs)
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{
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unsigned long cr0;
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__ctl_store(cr0, 0, 0);
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__ctl_set_bit(0, 17);
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__ctl_set_bit(0, 18); /* AFP-register-control */
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save_vx_regs(vxrs);
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__ctl_load(cr0, 0, 0);
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}
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#define MAX_FACILITY_BIT (256*8) /* stfle_fac_list has 256 bytes */
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static inline int __test_facility(unsigned long nr, void *facilities)
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{
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unsigned char *ptr;
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if (nr >= MAX_FACILITY_BIT)
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return 0;
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ptr = (unsigned char *) facilities + (nr >> 3);
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return (*ptr & (0x80 >> (nr & 7))) != 0;
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}
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/*
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* The test_facility function uses the bit odering where the MSB is bit 0.
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* That makes it easier to query facility bits with the bit number as
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* documented in the Principles of Operation.
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*/
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static inline int test_facility(unsigned long nr)
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{
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return __test_facility(nr, &S390_lowcore.stfle_fac_list);
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}
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/**
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* stfle - Store facility list extended
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* @stfle_fac_list: array where facility list can be stored
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* @size: size of passed in array in double words
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*/
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static inline void stfle(u64 *stfle_fac_list, int size)
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{
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unsigned long nr;
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|
|
|
asm volatile(
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" .insn s,0xb2b10000,0(0)\n" /* stfl */
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|
"0:\n"
|
|
EX_TABLE(0b, 0b)
|
|
: "+m" (S390_lowcore.stfl_fac_list));
|
|
nr = 4; /* bytes stored by stfl */
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|
memcpy(stfle_fac_list, &S390_lowcore.stfl_fac_list, 4);
|
|
if (S390_lowcore.stfl_fac_list & 0x01000000) {
|
|
/* More facility bits available with stfle */
|
|
register unsigned long reg0 asm("0") = size - 1;
|
|
|
|
asm volatile(".insn s,0xb2b00000,0(%1)" /* stfle */
|
|
: "+d" (reg0)
|
|
: "a" (stfle_fac_list)
|
|
: "memory", "cc");
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|
nr = (reg0 + 1) * 8; /* # bytes stored by stfle */
|
|
}
|
|
memset((char *) stfle_fac_list + nr, 0, size * 8 - nr);
|
|
}
|
|
|
|
#endif /* S390_H */
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