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aarch64: Address Rust 1.51.0 clippy issue (redundant_slicing)

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error: redundant slicing of the whole range
Error:    --> devices/src/legacy/gpio_pl061.rs:298:37
    |
298 |             let value = read_le_u32(&data[..]);
    |                                     ^^^^^^^^^ help: use the original slice instead: `data`
    |
    = note: `-D clippy::redundant-slicing` implied by `-D warnings`
    = help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#redundant_slicing

Signed-off-by: Rob Bradford <robert.bradford@intel.com>
This commit is contained in:
Rob Bradford
2021-03-25 17:01:21 +00:00
parent 40da6210f4
commit 3671f5e94c
3 changed files with 21 additions and 21 deletions
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devices/src/legacy/uart_pl011.rs
+4 -4
View File
@@ -339,7 +339,7 @@ impl BusDevice for Pl011 {
fn write(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
if data.len() <= 4 {
let v = read_le_u32(&data[..]);
let v = read_le_u32(&data);
if let Err(e) = self.handle_write(offset, v) {
warn!("Failed to write to PL011 device: {}", e);
}
@@ -496,11 +496,11 @@ mod tests {
assert_eq!(intr_evt.read().unwrap(), 2);
let mut data = [0u8];
pl011.read(0, UARTDR as u64, &mut data[..]);
pl011.read(0, UARTDR as u64, &mut data);
assert_eq!(data[0], b'a');
pl011.read(0, UARTDR as u64, &mut data[..]);
pl011.read(0, UARTDR as u64, &mut data);
assert_eq!(data[0], b'b');
pl011.read(0, UARTDR as u64, &mut data[..]);
pl011.read(0, UARTDR as u64, &mut data);
assert_eq!(data[0], b'c');
}
}