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aarch64: Remove unnecessary casts (beta clippy check)

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Signed-off-by: Rob Bradford <robert.bradford@intel.com>
This commit is contained in:
Rob Bradford
2022-12-01 14:36:26 +00:00
parent 7fd2022e8e
commit 3888f57600
9 changed files with 28 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files
vmm/src/acpi.rs
+8 -8
View File
@@ -382,19 +382,19 @@ fn create_gtdt_table() -> Sdt {
// GTDT
let mut gtdt = Sdt::new(*b"GTDT", 104, 2, *b"CLOUDH", *b"CHGTDT ", 1);
// Secure EL1 Timer GSIV
gtdt.write(48, (ARCH_TIMER_S_EL1_IRQ + 16) as u32);
gtdt.write(48, ARCH_TIMER_S_EL1_IRQ + 16);
// Secure EL1 Timer Flags
gtdt.write(52, irqflags);
// Non-Secure EL1 Timer GSIV
gtdt.write(56, (ARCH_TIMER_NS_EL1_IRQ + 16) as u32);
gtdt.write(56, ARCH_TIMER_NS_EL1_IRQ + 16);
// Non-Secure EL1 Timer Flags
gtdt.write(60, (irqflags | ACPI_GTDT_CAP_ALWAYS_ON) as u32);
gtdt.write(60, irqflags | ACPI_GTDT_CAP_ALWAYS_ON);
// Virtual EL1 Timer GSIV
gtdt.write(64, (ARCH_TIMER_VIRT_IRQ + 16) as u32);
gtdt.write(64, ARCH_TIMER_VIRT_IRQ + 16);
// Virtual EL1 Timer Flags
gtdt.write(68, irqflags);
// EL2 Timer GSIV
gtdt.write(72, (ARCH_TIMER_NS_EL2_IRQ + 16) as u32);
gtdt.write(72, ARCH_TIMER_NS_EL2_IRQ + 16);
// EL2 Timer Flags
gtdt.write(76, irqflags);
@@ -414,7 +414,7 @@ fn create_spcr_table(base_address: u64, gsi: u32) -> Sdt {
// Interrupt Type: Bit[3] ARMH GIC interrupt
spcr.write(52, (1 << 3) as u8);
// Global System Interrupt used by the UART
spcr.write(54, (gsi as u32).to_le());
spcr.write(54, gsi.to_le());
// Baud Rate: 3 = 9600
spcr.write(58, 3u8);
// Stop Bits: 1 Stop bit
@@ -522,7 +522,7 @@ fn create_iort_table(pci_segments: &[PciSegment]) -> Sdt {
iort.write(40, (48u32).to_le());
// ITS group node
iort.write(48, ACPI_IORT_NODE_ITS_GROUP as u8);
iort.write(48, ACPI_IORT_NODE_ITS_GROUP);
// Length of the ITS group node in bytes
iort.write(49, (24u16).to_le());
// ITS counts
@@ -532,7 +532,7 @@ fn create_iort_table(pci_segments: &[PciSegment]) -> Sdt {
for (i, segment) in pci_segments.iter().enumerate() {
let node_offset: usize =
ACPI_IORT_NODE_ROOT_COMPLEX_OFFSET + i * ACPI_IORT_NODE_ROOT_COMPLEX_SIZE;
iort.write(node_offset, ACPI_IORT_NODE_PCI_ROOT_COMPLEX as u8);
iort.write(node_offset, ACPI_IORT_NODE_PCI_ROOT_COMPLEX);
// Length of the root complex node in bytes
iort.write(
node_offset + 1,
vmm/src/cpu.rs
+1 -1
View File
@@ -2671,7 +2671,7 @@ mod tests {
let offset = offset__of!(user_pt_regs, pc);
let regid = arm64_core_reg_id!(KVM_REG_SIZE_U64, offset);
assert!(!is_system_register(regid));
let regid = KVM_REG_ARM64 as u64 | KVM_REG_SIZE_U64 as u64 | KVM_REG_ARM64_SYSREG as u64;
let regid = KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM64_SYSREG as u64;
assert!(is_system_register(regid));
}
vmm/src/memory_manager.rs
+1 -1
View File
@@ -854,7 +854,7 @@ impl MemoryManager {
let uefi_mem_region = self.vm.make_user_memory_region(
uefi_mem_slot,
uefi_region.start_addr().raw_value(),
uefi_region.len() as u64,
uefi_region.len(),
uefi_region.as_ptr() as u64,
false,
false,