arch: Add a list of Hyper-V MSRs

When Cloud hypervisor has not been configured for (KVM) Hyper-V we want
to adapt the CPU profiles not to require existence of Hyper-V related
MSRs.

The first step introduced here is to create a list of such MSRs.

Signed-off-by: Oliver Anderson <oliver.anderson@cyberus-technology.de>
On-behalf-of: SAP oliver.anderson@sap.com

arch/src/x86_64/hyperv_msrs.rs

@@ -0,0 +1,127 @@
+// Copyright © 2026 Cyberus Technology GmbH
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+
+const HV_X64_MSR_GUEST_OS_ID: u32 = 0x40000000;
+const HV_X64_MSR_HYPERCALL: u32 = 0x40000001;
+const HV_X64_MSR_VP_INDEX: u32 = 0x40000002;
+const HV_X64_MSR_RESET: u32 = 0x40000003;
+const HV_X64_MSR_VP_RUNTIME: u32 = 0x40000010;
+const HV_X64_MSR_TIME_REF_COUNT: u32 = 0x40000020;
+const HV_X64_MSR_REFERENCE_TSC: u32 = 0x40000021;
+const HV_X64_MSR_TSC_FREQUENCY: u32 = 0x40000022;
+const HV_X64_MSR_APIC_FREQUENCY: u32 = 0x40000023;
+const HV_X64_MSR_EOI: u32 = 0x40000070;
+const HV_X64_MSR_ICR: u32 = 0x40000071;
+const HV_X64_MSR_TPR: u32 = 0x40000072;
+const HV_X64_MSR_VP_ASSIST_PAGE: u32 = 0x40000073;
+const HV_X64_MSR_SCONTROL: u32 = 0x40000080;
+const HV_X64_MSR_SVERSION: u32 = 0x40000081;
+const HV_X64_MSR_SIEFP: u32 = 0x40000082;
+const HV_X64_MSR_SIMP: u32 = 0x40000083;
+const HV_X64_MSR_EOM: u32 = 0x40000084;
+const HV_X64_MSR_SINT0: u32 = 0x40000090;
+const HV_X64_MSR_SINT1: u32 = 0x40000091;
+const HV_X64_MSR_SINT2: u32 = 0x40000092;
+const HV_X64_MSR_SINT3: u32 = 0x40000093;
+const HV_X64_MSR_SINT4: u32 = 0x40000094;
+const HV_X64_MSR_SINT5: u32 = 0x40000095;
+const HV_X64_MSR_SINT6: u32 = 0x40000096;
+const HV_X64_MSR_SINT7: u32 = 0x40000097;
+const HV_X64_MSR_SINT8: u32 = 0x40000098;
+const HV_X64_MSR_SINT9: u32 = 0x40000099;
+const HV_X64_MSR_SINT10: u32 = 0x4000009A;
+const HV_X64_MSR_SINT11: u32 = 0x4000009B;
+const HV_X64_MSR_SINT12: u32 = 0x4000009C;
+const HV_X64_MSR_SINT13: u32 = 0x4000009D;
+const HV_X64_MSR_SINT14: u32 = 0x4000009E;
+const HV_X64_MSR_SINT15: u32 = 0x4000009F;
+const HV_X64_MSR_STIMER0_CONFIG: u32 = 0x400000B0;
+const HV_X64_MSR_STIMER0_COUNT: u32 = 0x400000B1;
+const HV_X64_MSR_STIMER1_CONFIG: u32 = 0x400000B2;
+const HV_X64_MSR_STIMER1_COUNT: u32 = 0x400000B3;
+const HV_X64_MSR_STIMER2_CONFIG: u32 = 0x400000B4;
+const HV_X64_MSR_STIMER2_COUNT: u32 = 0x400000B5;
+const HV_X64_MSR_STIMER3_CONFIG: u32 = 0x400000B6;
+const HV_X64_MSR_STIMER3_COUNT: u32 = 0x400000B7;
+const HV_X64_MSR_GUEST_IDLE: u32 = 0x400000F0;
+const HV_X64_MSR_CRASH_P0: u32 = 0x40000100;
+const HV_X64_MSR_CRASH_P1: u32 = 0x40000101;
+const HV_X64_MSR_CRASH_P2: u32 = 0x40000102;
+const HV_X64_MSR_CRASH_P3: u32 = 0x40000103;
+const HV_X64_MSR_CRASH_P4: u32 = 0x40000104;
+const HV_X64_MSR_CRASH_CTL: u32 = 0x40000105;
+const HV_X64_MSR_REENLIGHTENMENT_CONTROL: u32 = 0x40000106;
+const HV_X64_MSR_TSC_EMULATION_CONTROL: u32 = 0x40000107;
+const HV_X64_MSR_TSC_EMULATION_STATUS: u32 = 0x40000108;
+const HV_X64_MSR_TSC_INVARIANT_CONTROL: u32 = 0x40000118;
+const HV_X64_MSR_SYNDBG_CONTROL: u32 = 0x400000F1;
+const HV_X64_MSR_SYNDBG_STATUS: u32 = 0x400000F2;
+const HV_X64_MSR_SYNDBG_SEND_BUFFER: u32 = 0x400000F3;
+const HV_X64_MSR_SYNDBG_RECV_BUFFER: u32 = 0x400000F4;
+const HV_X64_MSR_SYNDBG_PENDING_BUFFER: u32 = 0x400000F5;
+const HV_X64_MSR_SYNDBG_OPTIONS: u32 = 0x400000FF;
+
+// All Hyper-V MSRs extracted from https://elixir.bootlin.com/linux/v7.1.1/source/tools/testing/selftests/kvm/include/x86/hyperv.h#L23
+pub const HYPERV_MSRS: [u32; 59] = [
+    HV_X64_MSR_GUEST_OS_ID,
+    HV_X64_MSR_HYPERCALL,
+    HV_X64_MSR_VP_INDEX,
+    HV_X64_MSR_RESET,
+    HV_X64_MSR_VP_RUNTIME,
+    HV_X64_MSR_TIME_REF_COUNT,
+    HV_X64_MSR_REFERENCE_TSC,
+    HV_X64_MSR_TSC_FREQUENCY,
+    HV_X64_MSR_APIC_FREQUENCY,
+    HV_X64_MSR_EOI,
+    HV_X64_MSR_ICR,
+    HV_X64_MSR_TPR,
+    HV_X64_MSR_VP_ASSIST_PAGE,
+    HV_X64_MSR_SCONTROL,
+    HV_X64_MSR_SVERSION,
+    HV_X64_MSR_SIEFP,
+    HV_X64_MSR_SIMP,
+    HV_X64_MSR_EOM,
+    HV_X64_MSR_SINT0,
+    HV_X64_MSR_SINT1,
+    HV_X64_MSR_SINT2,
+    HV_X64_MSR_SINT3,
+    HV_X64_MSR_SINT4,
+    HV_X64_MSR_SINT5,
+    HV_X64_MSR_SINT6,
+    HV_X64_MSR_SINT7,
+    HV_X64_MSR_SINT8,
+    HV_X64_MSR_SINT9,
+    HV_X64_MSR_SINT10,
+    HV_X64_MSR_SINT11,
+    HV_X64_MSR_SINT12,
+    HV_X64_MSR_SINT13,
+    HV_X64_MSR_SINT14,
+    HV_X64_MSR_SINT15,
+    HV_X64_MSR_STIMER0_CONFIG,
+    HV_X64_MSR_STIMER0_COUNT,
+    HV_X64_MSR_STIMER1_CONFIG,
+    HV_X64_MSR_STIMER1_COUNT,
+    HV_X64_MSR_STIMER2_CONFIG,
+    HV_X64_MSR_STIMER2_COUNT,
+    HV_X64_MSR_STIMER3_CONFIG,
+    HV_X64_MSR_STIMER3_COUNT,
+    HV_X64_MSR_GUEST_IDLE,
+    HV_X64_MSR_CRASH_P0,
+    HV_X64_MSR_CRASH_P1,
+    HV_X64_MSR_CRASH_P2,
+    HV_X64_MSR_CRASH_P3,
+    HV_X64_MSR_CRASH_P4,
+    HV_X64_MSR_CRASH_CTL,
+    HV_X64_MSR_REENLIGHTENMENT_CONTROL,
+    HV_X64_MSR_TSC_EMULATION_CONTROL,
+    HV_X64_MSR_TSC_EMULATION_STATUS,
+    HV_X64_MSR_TSC_INVARIANT_CONTROL,
+    HV_X64_MSR_SYNDBG_CONTROL,
+    HV_X64_MSR_SYNDBG_STATUS,
+    HV_X64_MSR_SYNDBG_SEND_BUFFER,
+    HV_X64_MSR_SYNDBG_RECV_BUFFER,
+    HV_X64_MSR_SYNDBG_PENDING_BUFFER,
+    HV_X64_MSR_SYNDBG_OPTIONS,
+];

arch/src/x86_64/mod.rs

@@ -16,6 +16,7 @@ pub mod regs;
 pub mod tdx;
 
 mod helpers;
+mod hyperv_msrs;
 mod mpspec;
 mod mptable;
 mod smbios;