build: Release 17.0

Signed-off-by: Rob Bradford <robert.bradford@intel.com>

.github/ISSUE_TEMPLATE/bug_report.md

@@ -0,0 +1,34 @@
+---
+name: Bug report
+about: File a bug report
+title: ''
+labels: ''
+assignees: ''
+
+---
+
+**Describe the bug**
+A clear and concise description of what the bug is.
+
+**To Reproduce**
+Steps to reproduce the behaviour:
+
+**Version**
+
+Output of `cloud-hypervisor --version`:
+
+Did you build from source, if so build command line (e.g. features):
+
+**VM configuration**
+
+What command line did you run (or JSON config data):
+
+Guest OS version details:
+
+Host OS version details:
+
+**Logs**
+
+Output of `cloud-hypervisor -v` from either standard error or via `--log-file`:
+
+Linux kernel output:

.github/dependabot.yml

@@ -0,0 +1,18 @@
+version: 2
+updates:
+- package-ecosystem: cargo
+  directory: "/"
+  schedule:
+    interval: daily
+  open-pull-requests-limit: 3
+  allow:
+  - dependency-type: direct
+  - dependency-type: indirect
+- package-ecosystem: cargo
+  directory: "/fuzz"
+  schedule:
+    interval: daily
+  open-pull-requests-limit: 3
+  allow:
+  - dependency-type: direct
+  - dependency-type: indirect

.github/workflows/build.yaml

@@ -42,3 +42,6 @@ jobs:
         
       - name: Release Build (default features)
         run: cargo build --all --release --target=${{ matrix.target }}
+
+      - name: Check build did not modify any files
+        run: test -z "$(git status --porcelain)"

.github/workflows/cross-build.yaml

@@ -1,32 +0,0 @@
-name: Cloud Hypervisor Cross Build
-on: [pull_request, create]
-
-jobs:
-  build:
-    if: github.event_name == 'pull_request'
-    name: Build
-    runs-on: ubuntu-latest
-    strategy:
-      matrix:
-        rust:
-          - 1.46.0
-        target:
-          - aarch64-unknown-linux-gnu
-          - aarch64-unknown-linux-musl
-    steps:
-      - name: Code checkout
-        uses: actions/checkout@v2
-      - name: Install Rust toolchain (${{ matrix.rust }})
-        uses: actions-rs/toolchain@v1
-        with:
-            toolchain: ${{ matrix.rust }}
-            target: ${{ matrix.target }}
-            override: true
-      - name: Install arm64 libfdt
-        run: wget http://ftp.us.debian.org/debian/pool/main/d/device-tree-compiler/libfdt-dev_1.6.0-1_arm64.deb && dpkg-deb -xv libfdt-dev_1.6.0-1_arm64.deb ./tlibfdtdev && mkdir -p target/debug/deps &&  cp ./tlibfdtdev/usr/lib/aarch64-linux-gnu/libfdt.a target/debug/deps/ && echo "libfdt copied into build tree"
-      - name: Build
-        uses: actions-rs/cargo@v1
-        with:
-          use-cross: true
-          command: build
-          args: --target=${{ matrix.target }} --no-default-features --features "kvm"

.github/workflows/quality-aarch64.yaml

@@ -6,12 +6,19 @@ jobs:
     if: github.event_name == 'pull_request'
     name: Quality (clippy, rustfmt)
     runs-on: ubuntu-latest
+    continue-on-error: ${{ matrix.experimental }}
     strategy:
+      fail-fast: false
       matrix:
         rust:
           - stable
         target:
           - aarch64-unknown-linux-gnu
+        experimental: [false]
+        include:
+          - rust: beta
+            target: aarch64-unknown-linux-gnu
+            experimental: true
     steps:
       - name: Code checkout
         uses: actions/checkout@v2
@@ -22,13 +29,33 @@ jobs:
             target: ${{ matrix.target }}
             override: true
             components: rustfmt, clippy
-      - name: Install arm64 libfdt
-        run: wget http://ftp.us.debian.org/debian/pool/main/d/device-tree-compiler/libfdt-dev_1.6.0-1_arm64.deb && dpkg-deb -xv libfdt-dev_1.6.0-1_arm64.deb ./tlibfdtdev && sudo mkdir /tmmmp && mkdir target && mkdir target/debug && mkdir target/debug/deps && sudo cp ./tlibfdtdev/usr/lib/aarch64-linux-gnu/libfdt.a target/debug/deps/libfdt.a && echo "libfdt installed"
       - name: Formatting (rustfmt)
         run: cargo fmt -- --check
+
       - name: Clippy (kvm)
         uses: actions-rs/cargo@v1
         with:
           use-cross: true
           command: clippy
-          args: --target=${{ matrix.target }} --no-default-features --features "kvm" -- -D warnings
+          args: --target=${{ matrix.target }} --all --no-default-features --features "kvm" -- -D warnings
+
+      - name: Clippy (kvm,acpi)
+        uses: actions-rs/cargo@v1
+        with:
+          use-cross: true
+          command: clippy
+          args: --target=${{ matrix.target }} --all --no-default-features --features "kvm,acpi" -- -D warnings
+
+      - name: Clippy (all features,kvm)
+        uses: actions-rs/cargo@v1
+        with:
+          use-cross: true
+          command: clippy
+          args: --target=${{ matrix.target }} --all --no-default-features --features "common,kvm" -- -D warnings
+
+      - name: Clippy (default)
+        uses: actions-rs/cargo@v1
+        with:
+          use-cross: true
+          command: clippy
+          args: --target=${{ matrix.target }} --all -- -D warnings

.github/workflows/quality.yaml

@@ -6,12 +6,19 @@ jobs:
     if: github.event_name == 'pull_request'
     name: Quality (clippy, rustfmt)
     runs-on: ubuntu-latest
+    continue-on-error: ${{ matrix.experimental }}
     strategy:
+      fail-fast: false
       matrix:
         rust:
           - stable
         target:
           - x86_64-unknown-linux-gnu
+        experimental: [false]
+        include:
+          - rust: beta
+            target: x86_64-unknown-linux-gnu
+            experimental: true
     steps:
       - name: Code checkout
         uses: actions/checkout@v2
@@ -35,6 +42,9 @@ jobs:
       - name: Clippy (acpi,kvm)
         run: cargo clippy --all --all-targets --no-default-features --tests --features "acpi,kvm" -- -D warnings
 
+      - name: Clippy (acpi,kvm,tdx)
+        run: cargo clippy --all --all-targets --no-default-features --tests --features "acpi,kvm,tdx" -- -D warnings
+
       - name: Clippy (kvm)
         run: cargo clippy --all --all-targets --no-default-features --tests --features "kvm" -- -D warnings
 
@@ -46,3 +56,6 @@ jobs:
 
       - name: Clippy (integration tests)
         run: cargo clippy --all --all-targets --tests --features "integration_tests" -- -D warnings
+
+      - name: Check build did not modify any files
+        run: test -z "$(git status --porcelain)"

Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "cloud-hypervisor"
-version = "0.13.0"
+version = "17.0.0"
 authors = ["The Cloud Hypervisor Authors"]
 edition = "2018"
 default-run = "cloud-hypervisor"
@@ -13,39 +13,40 @@ homepage = "https://github.com/cloud-hypervisor/cloud-hypervisor"
 lto = true
 
 [dependencies]
-anyhow = "1.0"
+anyhow = "1.0.42"
 api_client = { path = "api_client" }
 clap = { version = "2.33.3", features = ["wrap_help"] }
-epoll = ">=4.0.1"
+epoll = "4.3.1"
+event_monitor = { path = "event_monitor" }
 hypervisor = { path = "hypervisor" }
-libc = "0.2.86"
+libc = "0.2.98"
 log = { version = "0.4.14", features = ["std"] }
 option_parser = { path = "option_parser" }
-seccomp = { git = "https://github.com/firecracker-microvm/firecracker", tag = "v0.22.0" }
-serde_json = "1.0.62"
-signal-hook = "0.3.4"
-thiserror = "1.0"
+seccomp = { git = "https://github.com/firecracker-microvm/firecracker", tag = "v0.24.4" }
+serde_json = "1.0.64"
+signal-hook = "0.3.9"
+thiserror = "1.0.26"
 vmm = { path = "vmm" }
-vmm-sys-util = "0.7.0"
+vmm-sys-util = "0.8.0"
 vm-memory = "0.5.0"
-wait-timeout = "0.2.0"
 
 [build-dependencies]
 clap = { version = "2.33.3", features = ["wrap_help"] }
 
 # List of patched crates
-[patch.'https://github.com/rust-vmm/vhost']
-vhost_rs = { git = "https://github.com/cloud-hypervisor/vhost", branch = "ch", package = "vhost", features = ["vhost-user-master", "vhost-user-slave"] }
+[patch.crates-io]
+kvm-bindings = { git = "https://github.com/cloud-hypervisor/kvm-bindings", branch = "ch-v0.4.0", features = ["with-serde", "fam-wrappers"] }
+versionize_derive = { git = "https://github.com/cloud-hypervisor/versionize_derive", branch = "ch" }
+vm-memory = { git = "https://github.com/rust-vmm/vm-memory", rev = "5bd7138758183a73ac0da27ce40c004d95f1a7e9"}
 
 [dev-dependencies]
-ssh2 = "0.9.1"
-dirs = "3.0.1"
 credibility = "0.1.3"
-tempdir = "0.3.7"
+dirs = "3.0.2"
 lazy_static= "1.4.0"
-tempfile = "3.2.0"
-serde_json = "1.0.62"
 net_util = { path = "net_util" }
+serde_json = "1.0.64"
+test_infra = { path = "test_infra" }
+wait-timeout = "0.2.0"
 
 [features]
 default = ["acpi", "cmos", "io_uring", "kvm"]
@@ -57,6 +58,7 @@ fwdebug = ["vmm/fwdebug"]
 kvm = ["vmm/kvm"]
 mshv = ["vmm/mshv"]
 io_uring = ["vmm/io_uring"]
+tdx = ["vmm/tdx"]
 
 # Integration tests require a special environment to run in
 integration_tests = []
@@ -66,15 +68,16 @@ members = [
     "acpi_tables",
     "api_client",
     "arch",
-    "arch_gen",
     "block_util",
     "devices",
+    "event_monitor",
     "hypervisor",
     "net_gen",
     "net_util",
     "option_parser",
     "pci",
     "qcow",
+    "rate_limiter",
     "vhost_user_backend",
     "vhost_user_block",
     "vhost_user_net",
@@ -85,3 +88,4 @@ members = [
     "vm-migration",
     "vm-virtio"
 ]
+exclude = ["test_infra"]

Jenkinsfile

@@ -24,7 +24,7 @@ pipeline{
 		stage ('Build') {
             		parallel {
 				stage ('Worker build') {
-					agent { node { label 'groovy' } }
+					agent { node { label 'hirsute' } }
 					stages {
 						stage ('Checkout') {
 							steps {
@@ -46,6 +46,7 @@ pipeline{
 								timeout(time: 1, unit: 'HOURS')
 							}
 							steps {
+								sh "sudo modprobe openvswitch"
 								sh "scripts/dev_cli.sh tests --integration"
 							}
 						}
@@ -69,6 +70,7 @@ pipeline{
 								timeout(time: 1, unit: 'HOURS')
 							}
 							steps {
+								sh "sudo modprobe openvswitch"
 								sh "scripts/dev_cli.sh tests --integration"
 							}
 						}
@@ -81,7 +83,7 @@ pipeline{
 					}
 				}
 				stage ('Worker build (musl)') {
-					agent { node { label 'groovy' } }
+					agent { node { label 'hirsute' } }
 					stages {
 						stage ('Checkout') {
 							steps {
@@ -98,6 +100,7 @@ pipeline{
 								timeout(time: 1, unit: 'HOURS')
 							}
 							steps {
+								sh "sudo modprobe openvswitch"
 								sh "scripts/dev_cli.sh tests --integration --libc musl"
 							}
 						}
@@ -105,7 +108,10 @@ pipeline{
 				}
 				stage ('Worker build SGX') {
 					agent { node { label 'bionic-sgx' } }
-					when { branch 'master' }
+					when {
+						beforeAgent true
+						branch 'master'
+					}
 					stages {
 						stage ('Checkout') {
 							steps {
@@ -136,8 +142,47 @@ pipeline{
 						}
 					}
 				}
+				stage ('Worker build VFIO') {
+					agent { node { label 'bionic-vfio' } }
+					when {
+						beforeAgent true
+						branch 'master'
+					}
+					stages {
+						stage ('Checkout') {
+							steps {
+								checkout scm
+							}
+						}
+						stage ('Run VFIO integration tests') {
+							options {
+								timeout(time: 1, unit: 'HOURS')
+							}
+							steps {
+								sh "scripts/dev_cli.sh tests --integration-vfio"
+							}
+						}
+						stage ('Run VFIO integration tests for musl') {
+							options {
+								timeout(time: 1, unit: 'HOURS')
+							}
+							steps {
+								sh "scripts/dev_cli.sh tests --integration-vfio --libc musl"
+							}
+						}
+					}
+					post {
+						always {
+							sh "sudo chown -R jenkins.jenkins ${WORKSPACE}"
+							deleteDir()
+						}
+					}
+				}
 				stage ('Worker build - Windows guest') {
-					agent { node { label 'groovy-win' } }
+					agent { node { label 'hirsute' } }
+					environment {
+        					AZURE_CONNECTION_STRING = credentials('46b4e7d6-315f-4cc1-8333-b58780863b9b')
+					}
 					stages {
 						stage ('Checkout') {
 							steps {
@@ -146,17 +191,10 @@ pipeline{
 						}
 						stage ('Download assets') {
 							steps {
+								sh "sudo apt install -y azure-cli"
 								sh "mkdir ${env.HOME}/workloads"
-								azureDownload(storageCredentialId: 'ch-image-store',
-											  containerName: 'private-images',
-											  includeFilesPattern: 'OVMF.fd',
-											  downloadType: 'container',
-											  downloadDirLoc: "${env.HOME}/workloads")
-								azureDownload(storageCredentialId: 'ch-image-store',
-											  containerName: 'private-images',
-											  includeFilesPattern: 'windows-server-2019.raw',
-											  downloadType: 'container',
-											  downloadDirLoc: "${env.HOME}/workloads")
+								sh 'az storage blob download --container-name private-images --file "$HOME/workloads/OVMF-4b47d0c6c8.fd" --name OVMF-4b47d0c6c8.fd --connection-string "$AZURE_CONNECTION_STRING"'
+								sh 'az storage blob download --container-name private-images --file "$HOME/workloads/windows-server-2019.raw" --name windows-server-2019.raw --connection-string "$AZURE_CONNECTION_STRING"'
 							}
 						}
 						stage ('Run Windows guest integration tests') {

README.md

@@ -26,7 +26,8 @@
 
 # 1. What is Cloud Hypervisor?
 
-Cloud Hypervisor is an open source Virtual Machine Monitor (VMM) that runs on top of [KVM](https://www.kernel.org/doc/Documentation/virtual/kvm/api.txt).
+Cloud Hypervisor is an open source Virtual Machine Monitor (VMM) that runs on top of [KVM](https://www.kernel.org/doc/Documentation/virtual/kvm/api.txt) and the MSHV hypervisors .
+
 The project focuses on exclusively running modern, cloud workloads, on top of a limited set of hardware architectures and platforms.
 Cloud workloads refers to those that are usually run by customers inside a cloud provider. For our purposes this means modern operating systems with most I/O handled by paravirtualised devices (i.e. virtio), no requirement for legacy devices, and 64-bit CPUs.
 
@@ -36,7 +37,7 @@ Cloud Hypervisor is implemented in [Rust](https://www.rust-lang.org/) and is bas
 
 ### High Level
 
-- KVM based
+- Runs on KVM or MSHV
 - Minimal emulation
 - Low latency
 - Low memory footprint
@@ -53,7 +54,7 @@ Cloud Hypervisor supports the `x86-64` and `AArch64` architectures. There are so
 
 ### Guest OS
 
-Cloud Hypervisor supports `64-bit Linux` with support for _modern_ 64-bit Windows guests currently under development.
+Cloud Hypervisor supports `64-bit Linux` and Windows 10/Windows Server 2019.
 
 # 2. Getting Started
 
@@ -148,7 +149,7 @@ We need to get the latest `rust-hypervisor-firmware` release and also a working
 $ pushd $CLOUDH
 $ wget https://cloud-images.ubuntu.com/focal/current/focal-server-cloudimg-amd64.img
 $ qemu-img convert -p -f qcow2 -O raw focal-server-cloudimg-amd64.img focal-server-cloudimg-amd64.raw
-$ wget https://github.com/cloud-hypervisor/rust-hypervisor-firmware/releases/download/0.2.8/hypervisor-fw
+$ wget https://github.com/cloud-hypervisor/rust-hypervisor-firmware/releases/download/0.3.1/hypervisor-fw
 $ popd
 ```
 
@@ -171,7 +172,7 @@ Multiple arguments can be given to the `--disk` parameter.
 
 #### Building your kernel
 
-Cloud Hypervisor also supports direct kernel boot into a `vmlinux` ELF kernel or `bzImage`. In order to support virtio-fs and virtio-iommu we have our own development branch. You are of course able to use your own kernel but these instructions will continue with the version that we develop and test against.
+Cloud Hypervisor also supports direct kernel boot into a `vmlinux` ELF kernel. In order to support virtio-iommu we have our own development branch. You are of course able to use your own kernel but these instructions will continue with the version that we develop and test against.
 
 To build the kernel:
 
@@ -179,7 +180,7 @@ To build the kernel:
 
 # Clone the Cloud Hypervisor Linux branch
 $ pushd $CLOUDH
-$ git clone --depth 1 https://github.com/cloud-hypervisor/linux.git -b virtio-fs-virtio-iommu-virtio-mem-5.6-rc4 linux-cloud-hypervisor
+$ git clone --depth 1 https://github.com/cloud-hypervisor/linux.git -b ch-5.13-rc5 linux-cloud-hypervisor
 $ pushd linux-cloud-hypervisor
 
 # Use the cloud-hypervisor kernel config to build your kernel
@@ -204,7 +205,7 @@ $ popd
 #### Booting the guest VM
 
 Now we can directly boot into our custom kernel and make it use the Ubuntu root partition.
-If we want to have 4 vCPUs and 512 MBytes of memory:
+If we want to have 4 vCPUs and 1024 MBytes of memory:
 
 ```shell
 $ pushd $CLOUDH
@@ -241,23 +242,40 @@ $ ./cloud-hypervisor/target/release/cloud-hypervisor \
 
 # 3. Status
 
-Cloud Hypervisor is under active development. No API or feature stability is guaranteed.
+Cloud Hypervisor is under active development. The following stability guarantees are currently made:
 
-As of 2020-07-02, the following cloud images are supported:
+* The API (including command line options) will not be removed or changed in a
+  breaking way without a minimum of 2 releases notice. Where possible warnings
+  will be given about the use of deprecated functionality and the deprecations
+  will be documented in the release notes.
+* Point releases will be made between individual releases where there are
+  substantial bug fixes or security issues that need to be fixed.
+
+Currently the following items are **not** guaranteed across updates:
+
+* Snapshot/restore is not supported across different versions
+* Live migration is not supported across different versions
+* The following features are considered experimental and may change
+  substantially between releases: TDX, SGX.
+
+
+As of 2021-04-29, the following cloud images are supported:
 
 - [Ubuntu Bionic](https://cloud-images.ubuntu.com/bionic/current/) (cloudimg)
 - [Ubuntu Focal](https://cloud-images.ubuntu.com/focal/current/) (cloudimg)
+- [Ubuntu Groovy](https://cloud-images.ubuntu.com/groovy/current/) (cloudimg)
+- [Ubuntu Hirsute](https://cloud-images.ubuntu.com/hirsute/current/) (cloudimg)
 
 Direct kernel boot to userspace should work with a rootfs from most distributions.
 
 ## Hot Plug
 
-Cloud Hypervisor supports hotplug of CPUs, passthrough devices (VFIO), `virtio-{net,block,pmem,fs,vsock}` and memory resizing. This [document](https://github.com/cloud-hypervisor/cloud-hypervisor/blob/master/docs/hotplug.md) details how to add devices to
+Cloud Hypervisor supports hotplug of CPUs, passthrough devices (VFIO), `virtio-{net,block,pmem,fs,vsock}` and memory resizing. This [document](docs/hotplug.md) details how to add devices to
 a running VM.
 
 ## Device Model
 
-Details of the device model can be found in this [documentation](https://github.com/cloud-hypervisor/cloud-hypervisor/blob/master/docs/device_model.md).
+Details of the device model can be found in this [documentation](docs/device_model.md).
 
 ## TODO
 
@@ -317,3 +335,7 @@ etc, are all equal and welcome means of contribution. See the [CONTRIBUTING](CON
 
 Get an [invite to our Slack channel](https://join.slack.com/t/cloud-hypervisor/shared_invite/enQtNjY3MTE3MDkwNDQ4LWQ1MTA1ZDVmODkwMWQ1MTRhYzk4ZGNlN2UwNTI3ZmFlODU0OTcwOWZjMTkwZDExYWE3YjFmNzgzY2FmNDAyMjI)
 and [join us on Slack](https://cloud-hypervisor.slack.com/).
+
+## Security issues
+
+Please use the GitHub security advisories feature for reporting issues: https://github.com/cloud-hypervisor/cloud-hypervisor/security/advisories/new

acpi_tables/Cargo.toml

@@ -6,4 +6,3 @@ edition = "2018"
 
 [dependencies]
 vm-memory = "0.5.0"
-

acpi_tables/src/aml.rs

@@ -95,8 +95,7 @@ pub type Byte = u8;
 
 impl Aml for Byte {
     fn to_aml_bytes(&self) -> Vec<u8> {
-        let mut bytes = Vec::new();
-        bytes.push(0x0a); /* BytePrefix */
+        let mut bytes = vec![0x0a]; /* BytePrefix */
         bytes.push(*self);
         bytes
     }
@@ -106,8 +105,7 @@ pub type Word = u16;
 
 impl Aml for Word {
     fn to_aml_bytes(&self) -> Vec<u8> {
-        let mut bytes = Vec::new();
-        bytes.push(0x0bu8); /* WordPrefix */
+        let mut bytes = vec![0x0bu8]; /* WordPrefix */
         bytes.append(&mut self.to_le_bytes().to_vec());
         bytes
     }
@@ -117,8 +115,7 @@ pub type DWord = u32;
 
 impl Aml for DWord {
     fn to_aml_bytes(&self) -> Vec<u8> {
-        let mut bytes = Vec::new();
-        bytes.push(0x0c); /* DWordPrefix */
+        let mut bytes = vec![0x0c]; /* DWordPrefix */
         bytes.append(&mut self.to_le_bytes().to_vec());
         bytes
     }
@@ -128,8 +125,7 @@ pub type QWord = u64;
 
 impl Aml for QWord {
     fn to_aml_bytes(&self) -> Vec<u8> {
-        let mut bytes = Vec::new();
-        bytes.push(0x0e); /* QWordPrefix */
+        let mut bytes = vec![0x0e]; /* QWordPrefix */
         bytes.append(&mut self.to_le_bytes().to_vec());
         bytes
     }
@@ -147,8 +143,7 @@ impl Aml for Name {
 
 impl Name {
     pub fn new(path: Path, inner: &dyn Aml) -> Self {
-        let mut bytes = Vec::new();
-        bytes.push(0x08); /* NameOp */
+        let mut bytes = vec![0x08]; /* NameOp */
         bytes.append(&mut path.to_aml_bytes());
         bytes.append(&mut inner.to_aml_bytes());
         Name { bytes }
@@ -161,8 +156,7 @@ pub struct Package<'a> {
 
 impl<'a> Aml for Package<'a> {
     fn to_aml_bytes(&self) -> Vec<u8> {
-        let mut bytes = Vec::new();
-        bytes.push(self.children.len() as u8);
+        let mut bytes = vec![self.children.len() as u8];
         for child in &self.children {
             bytes.append(&mut child.to_aml_bytes());
         }
@@ -239,11 +233,11 @@ fn create_pkg_length(data: &[u8], include_self: bool) -> Vec<u8> {
     result
 }
 
-pub struct EISAName {
+pub struct EisaName {
     value: DWord,
 }
 
-impl EISAName {
+impl EisaName {
     pub fn new(name: &str) -> Self {
         assert_eq!(name.len(), 7);
 
@@ -258,11 +252,11 @@ impl EISAName {
             | name.chars().nth(6).unwrap().to_digit(16).unwrap())
         .swap_bytes();
 
-        EISAName { value }
+        EisaName { value }
     }
 }
 
-impl Aml for EISAName {
+impl Aml for EisaName {
     fn to_aml_bytes(&self) -> Vec<u8> {
         self.value.to_aml_bytes()
     }
@@ -289,8 +283,7 @@ impl Aml for Usize {
 }
 
 fn create_aml_string(v: &str) -> Vec<u8> {
-    let mut data = Vec::new();
-    data.push(0x0D); /* String Op */
+    let mut data = vec![0x0D]; /* String Op */
     data.extend_from_slice(v.as_bytes());
     data.push(0x0); /* NullChar */
     data
@@ -374,9 +367,7 @@ impl Memory32Fixed {
 
 impl Aml for Memory32Fixed {
     fn to_aml_bytes(&self) -> Vec<u8> {
-        let mut bytes = Vec::new();
-
-        bytes.push(0x86); /* Memory32Fixed */
+        let mut bytes = vec![0x86]; /* Memory32Fixed */
         bytes.append(&mut 9u16.to_le_bytes().to_vec());
 
         // 9 bytes of payload
@@ -390,7 +381,7 @@ impl Aml for Memory32Fixed {
 #[derive(Copy, Clone)]
 enum AddressSpaceType {
     Memory,
-    IO,
+    Io,
     BusNumber,
 }
 
@@ -421,7 +412,7 @@ impl<T> AddressSpace<T> {
 
     pub fn new_io(min: T, max: T) -> Self {
         AddressSpace {
-            r#type: AddressSpaceType::IO,
+            r#type: AddressSpaceType::Io,
             min,
             max,
             type_flags: 3, /* EntireRange */
@@ -510,16 +501,16 @@ impl Aml for AddressSpace<u64> {
     }
 }
 
-pub struct IO {
+pub struct Io {
     min: u16,
     max: u16,
     alignment: u8,
     length: u8,
 }
 
-impl IO {
+impl Io {
     pub fn new(min: u16, max: u16, alignment: u8, length: u8) -> Self {
-        IO {
+        Io {
             min,
             max,
             alignment,
@@ -528,11 +519,10 @@ impl IO {
     }
 }
 
-impl Aml for IO {
+impl Aml for Io {
     fn to_aml_bytes(&self) -> Vec<u8> {
-        let mut bytes = Vec::new();
+        let mut bytes = vec![0x47]; /* Io Port Descriptor */
 
-        bytes.push(0x47); /* IO Port Descriptor */
         bytes.push(1); /* IODecode16 */
         bytes.append(&mut self.min.to_le_bytes().to_vec());
         bytes.append(&mut self.max.to_le_bytes().to_vec());
@@ -571,9 +561,7 @@ impl Interrupt {
 
 impl Aml for Interrupt {
     fn to_aml_bytes(&self) -> Vec<u8> {
-        let mut bytes = Vec::new();
-
-        bytes.push(0x89); /* Extended IRQ Descriptor */
+        let mut bytes = vec![0x89]; /* Extended IRQ Descriptor */
         bytes.append(&mut 6u16.to_le_bytes().to_vec());
         let flags = (self.shared as u8) << 3
             | (self.active_low as u8) << 2
@@ -699,8 +687,7 @@ impl<'a> Return<'a> {
 
 impl<'a> Aml for Return<'a> {
     fn to_aml_bytes(&self) -> Vec<u8> {
-        let mut bytes = Vec::new();
-        bytes.push(0xa4); /* ReturnOp */
+        let mut bytes = vec![0xa4]; /* ReturnOp */
         bytes.append(&mut self.value.to_aml_bytes());
         bytes
     }
@@ -745,9 +732,9 @@ impl Field {
     ) -> Self {
         Field {
             path,
+            fields,
             access_type,
             update_rule,
-            fields,
         }
     }
 }
@@ -788,14 +775,14 @@ impl Aml for Field {
 #[derive(Clone, Copy)]
 pub enum OpRegionSpace {
     SystemMemory,
-    SystemIO,
-    PCIConfig,
+    SystemIo,
+    PConfig,
     EmbeddedControl,
-    SMBus,
-    SystemCMOS,
+    Smbus,
+    SystemCmos,
     PciBarTarget,
-    IPMI,
-    GeneralPurposeIO,
+    Ipmi,
+    GeneralPurposeIo,
     GenericSerialBus,
 }
 
@@ -864,8 +851,8 @@ impl<'a> Aml for If<'a> {
 }
 
 pub struct Equal<'a> {
-    right: &'a dyn Aml,
     left: &'a dyn Aml,
+    right: &'a dyn Aml,
 }
 
 impl<'a> Equal<'a> {
@@ -876,8 +863,7 @@ impl<'a> Equal<'a> {
 
 impl<'a> Aml for Equal<'a> {
     fn to_aml_bytes(&self) -> Vec<u8> {
-        let mut bytes = Vec::new();
-        bytes.push(0x93); /* LEqualOp */
+        let mut bytes = vec![0x93]; /* LEqualOp */
         bytes.extend_from_slice(&self.left.to_aml_bytes());
         bytes.extend_from_slice(&self.right.to_aml_bytes());
         bytes
@@ -885,8 +871,8 @@ impl<'a> Aml for Equal<'a> {
 }
 
 pub struct LessThan<'a> {
-    right: &'a dyn Aml,
     left: &'a dyn Aml,
+    right: &'a dyn Aml,
 }
 
 impl<'a> LessThan<'a> {
@@ -897,8 +883,7 @@ impl<'a> LessThan<'a> {
 
 impl<'a> Aml for LessThan<'a> {
     fn to_aml_bytes(&self) -> Vec<u8> {
-        let mut bytes = Vec::new();
-        bytes.push(0x95); /* LLessOp */
+        let mut bytes = vec![0x95]; /* LLessOp */
         bytes.extend_from_slice(&self.left.to_aml_bytes());
         bytes.extend_from_slice(&self.right.to_aml_bytes());
         bytes
@@ -940,8 +925,7 @@ impl<'a> Store<'a> {
 
 impl<'a> Aml for Store<'a> {
     fn to_aml_bytes(&self) -> Vec<u8> {
-        let mut bytes = Vec::new();
-        bytes.push(0x70); /* StoreOp */
+        let mut bytes = vec![0x70]; /* StoreOp */
         bytes.extend_from_slice(&self.value.to_aml_bytes());
         bytes.extend_from_slice(&self.name.to_aml_bytes());
         bytes
@@ -961,8 +945,7 @@ impl Mutex {
 
 impl Aml for Mutex {
     fn to_aml_bytes(&self) -> Vec<u8> {
-        let mut bytes = Vec::new();
-        bytes.push(0x5b); /* ExtOpPrefix */
+        let mut bytes = vec![0x5b]; /* ExtOpPrefix */
         bytes.push(0x01); /* MutexOp */
         bytes.extend_from_slice(&self.path.to_aml_bytes());
         bytes.push(self.sync_level);
@@ -983,8 +966,7 @@ impl Acquire {
 
 impl Aml for Acquire {
     fn to_aml_bytes(&self) -> Vec<u8> {
-        let mut bytes = Vec::new();
-        bytes.push(0x5b); /* ExtOpPrefix */
+        let mut bytes = vec![0x5b]; /* ExtOpPrefix */
         bytes.push(0x23); /* AcquireOp */
         bytes.extend_from_slice(&self.mutex.to_aml_bytes());
         bytes.extend_from_slice(&self.timeout.to_le_bytes());
@@ -1004,8 +986,7 @@ impl Release {
 
 impl Aml for Release {
     fn to_aml_bytes(&self) -> Vec<u8> {
-        let mut bytes = Vec::new();
-        bytes.push(0x5b); /* ExtOpPrefix */
+        let mut bytes = vec![0x5b]; /* ExtOpPrefix */
         bytes.push(0x27); /* ReleaseOp */
         bytes.extend_from_slice(&self.mutex.to_aml_bytes());
         bytes
@@ -1025,8 +1006,7 @@ impl<'a> Notify<'a> {
 
 impl<'a> Aml for Notify<'a> {
     fn to_aml_bytes(&self) -> Vec<u8> {
-        let mut bytes = Vec::new();
-        bytes.push(0x86); /* NotifyOp */
+        let mut bytes = vec![0x86]; /* NotifyOp */
         bytes.extend_from_slice(&self.object.to_aml_bytes());
         bytes.extend_from_slice(&self.value.to_aml_bytes());
         bytes
@@ -1076,14 +1056,13 @@ macro_rules! binary_op {
 
         impl<'a> $name<'a> {
             pub fn new(target: &'a dyn Aml, a: &'a dyn Aml, b: &'a dyn Aml) -> Self {
-                $name { target, a, b }
+                $name { a, b, target }
             }
         }
 
         impl<'a> Aml for $name<'a> {
             fn to_aml_bytes(&self) -> Vec<u8> {
-                let mut bytes = Vec::new();
-                bytes.push($opcode); /* Op for the binary operator */
+                let mut bytes = vec![$opcode]; /* Op for the binary operator */
                 bytes.extend_from_slice(&self.a.to_aml_bytes());
                 bytes.extend_from_slice(&self.b.to_aml_bytes());
                 bytes.extend_from_slice(&self.target.to_aml_bytes());
@@ -1180,8 +1159,7 @@ impl<'a, T> CreateField<'a, T> {
 
 impl<'a> Aml for CreateField<'a, u64> {
     fn to_aml_bytes(&self) -> Vec<u8> {
-        let mut bytes = Vec::new();
-        bytes.push(0x8f); /* CreateQWordFieldOp */
+        let mut bytes = vec![0x8f]; /* CreateQWordFieldOp */
         bytes.extend_from_slice(&self.buffer.to_aml_bytes());
         bytes.extend_from_slice(&self.offset.to_aml_bytes());
         bytes.extend_from_slice(&self.field.to_aml_bytes());
@@ -1191,8 +1169,7 @@ impl<'a> Aml for CreateField<'a, u64> {
 
 impl<'a> Aml for CreateField<'a, u32> {
     fn to_aml_bytes(&self) -> Vec<u8> {
-        let mut bytes = Vec::new();
-        bytes.push(0x8a); /* CreateDWordFieldOp */
+        let mut bytes = vec![0x8a]; /* CreateDWordFieldOp */
         bytes.extend_from_slice(&self.buffer.to_aml_bytes());
         bytes.extend_from_slice(&self.offset.to_aml_bytes());
         bytes.extend_from_slice(&self.field.to_aml_bytes());
@@ -1235,12 +1212,12 @@ mod tests {
             Device::new(
                 "_SB_.COM1".into(),
                 vec![
-                    &Name::new("_HID".into(), &EISAName::new("PNP0501")),
+                    &Name::new("_HID".into(), &EisaName::new("PNP0501")),
                     &Name::new(
                         "_CRS".into(),
                         &ResourceTemplate::new(vec![
                             &Interrupt::new(true, true, false, false, 4),
-                            &IO::new(0x3f8, 0x3f8, 0, 0x8)
+                            &Io::new(0x3f8, 0x3f8, 0, 0x8)
                         ])
                     )
                 ]
@@ -1476,7 +1453,7 @@ mod tests {
                 "_CRS".into(),
                 &ResourceTemplate::new(vec![
                     &Interrupt::new(true, true, false, false, 4),
-                    &IO::new(0x3f8, 0x3f8, 0, 0x8)
+                    &Io::new(0x3f8, 0x3f8, 0, 0x8)
                 ])
             )
             .to_aml_bytes(),
@@ -1519,7 +1496,7 @@ mod tests {
     #[test]
     fn test_eisa_name() {
         assert_eq!(
-            Name::new("_HID".into(), &EISAName::new("PNP0501")).to_aml_bytes(),
+            Name::new("_HID".into(), &EisaName::new("PNP0501")).to_aml_bytes(),
             [0x08, 0x5F, 0x48, 0x49, 0x44, 0x0C, 0x41, 0xD0, 0x05, 0x01],
         )
     }
@@ -1665,14 +1642,14 @@ mod tests {
     #[test]
     fn test_op_region() {
         /*
-            OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C)
+            OperationRegion (PRST, SystemIo, 0x0CD8, 0x0C)
         */
         let op_region_data = [
             0x5Bu8, 0x80, 0x50, 0x52, 0x53, 0x54, 0x01, 0x0B, 0xD8, 0x0C, 0x0A, 0x0C,
         ];
 
         assert_eq!(
-            OpRegion::new("PRST".into(), OpRegionSpace::SystemIO, 0xcd8, 0xc).to_aml_bytes(),
+            OpRegion::new("PRST".into(), OpRegionSpace::SystemIo, 0xcd8, 0xc).to_aml_bytes(),
             &op_region_data[..]
         );
     }
@@ -1766,7 +1743,7 @@ mod tests {
             Device::new(
                 "_SB_.MHPC".into(),
                 vec![
-                    &Name::new("_HID".into(), &EISAName::new("PNP0A06")),
+                    &Name::new("_HID".into(), &EisaName::new("PNP0A06")),
                     &mutex,
                     &Method::new(
                         "TEST".into(),
@@ -1807,7 +1784,7 @@ mod tests {
             Device::new(
                 "_SB_.MHPC".into(),
                 vec![
-                    &Name::new("_HID".into(), &EISAName::new("PNP0A06")),
+                    &Name::new("_HID".into(), &EisaName::new("PNP0A06")),
                     &Method::new(
                         "TEST".into(),
                         0,
@@ -1848,7 +1825,7 @@ mod tests {
             Device::new(
                 "_SB_.MHPC".into(),
                 vec![
-                    &Name::new("_HID".into(), &EISAName::new("PNP0A06")),
+                    &Name::new("_HID".into(), &EisaName::new("PNP0A06")),
                     &Method::new(
                         "TEST".into(),
                         0,

acpi_tables/src/rsdp.rs

@@ -7,7 +7,7 @@ use vm_memory::ByteValued;
 
 #[repr(packed)]
 #[derive(Clone, Copy, Default)]
-pub struct RSDP {
+pub struct Rsdp {
     pub signature: [u8; 8],
     pub checksum: u8,
     pub oem_id: [u8; 6],
@@ -19,40 +19,40 @@ pub struct RSDP {
     _reserved: [u8; 3],
 }
 
-unsafe impl ByteValued for RSDP {}
+unsafe impl ByteValued for Rsdp {}
 
-impl RSDP {
+impl Rsdp {
     pub fn new(oem_id: [u8; 6], xsdt_addr: u64) -> Self {
-        let mut rsdp = RSDP {
+        let mut rsdp = Rsdp {
             signature: *b"RSD PTR ",
             checksum: 0,
             oem_id,
             revision: 2,
             _rsdt_addr: 0,
-            length: std::mem::size_of::<RSDP>() as u32,
+            length: std::mem::size_of::<Rsdp>() as u32,
             xsdt_addr,
             extended_checksum: 0,
             _reserved: [0; 3],
         };
 
         rsdp.checksum = super::generate_checksum(&rsdp.as_slice()[0..19]);
-        rsdp.extended_checksum = super::generate_checksum(&rsdp.as_slice());
+        rsdp.extended_checksum = super::generate_checksum(rsdp.as_slice());
         rsdp
     }
 
     pub fn len() -> usize {
-        std::mem::size_of::<RSDP>()
+        std::mem::size_of::<Rsdp>()
     }
 }
 
 #[cfg(test)]
 mod tests {
-    use super::RSDP;
+    use super::Rsdp;
     use vm_memory::bytes::ByteValued;
 
     #[test]
     fn test_rsdp() {
-        let rsdp = RSDP::new(*b"CHYPER", 0xdead_beef);
+        let rsdp = Rsdp::new(*b"CHYPER", 0xdead_beef);
         let sum = rsdp
             .as_slice()
             .iter()

acpi_tables/src/sdt.rs

@@ -22,14 +22,23 @@ impl GenericAddress {
             address: u64::from(address),
         }
     }
+    pub fn mmio_address<T>(address: u64) -> Self {
+        GenericAddress {
+            address_space_id: 0,
+            register_bit_width: 8 * std::mem::size_of::<T>() as u8,
+            register_bit_offset: 0,
+            access_size: std::mem::size_of::<T>() as u8,
+            address,
+        }
+    }
 }
 
-pub struct SDT {
+pub struct Sdt {
     data: Vec<u8>,
 }
 
 #[allow(clippy::len_without_is_empty)]
-impl SDT {
+impl Sdt {
     pub fn new(
         signature: [u8; 4],
         length: u32,
@@ -53,7 +62,7 @@ impl SDT {
         assert_eq!(data.len(), 36);
 
         data.resize(length as usize, 0);
-        let mut sdt = SDT { data };
+        let mut sdt = Sdt { data };
 
         sdt.update_checksum();
         sdt
@@ -66,7 +75,7 @@ impl SDT {
     }
 
     pub fn as_slice(&self) -> &[u8] {
-        &self.data.as_slice()
+        self.data.as_slice()
     }
 
     pub fn append<T>(&mut self, value: T) {
@@ -117,11 +126,11 @@ impl SDT {
 
 #[cfg(test)]
 mod tests {
-    use super::SDT;
+    use super::Sdt;
 
     #[test]
     fn test_sdt() {
-        let mut sdt = SDT::new(*b"TEST", 40, 1, *b"CLOUDH", *b"TESTTEST", 1);
+        let mut sdt = Sdt::new(*b"TEST", 40, 1, *b"CLOUDH", *b"TESTTEST", 1);
         let sum: u8 = sdt
             .as_slice()
             .iter()

api_client/Cargo.toml

@@ -3,3 +3,6 @@ name = "api_client"
 version = "0.1.0"
 authors = ["The Cloud Hypervisor Authors"]
 edition = "2018"
+
+[dependencies]
+vmm-sys-util = "0.8.0"

api_client/src/lib.rs

@@ -5,10 +5,13 @@
 
 use std::fmt;
 use std::io::{Read, Write};
+use std::os::unix::io::RawFd;
+use vmm_sys_util::sock_ctrl_msg::ScmSocket;
 
 #[derive(Debug)]
 pub enum Error {
     Socket(std::io::Error),
+    SocketSendFds(vmm_sys_util::errno::Error),
     StatusCodeParsing(std::num::ParseIntError),
     MissingProtocol,
     ContentLengthParsing(std::num::ParseIntError),
@@ -20,6 +23,7 @@ impl fmt::Display for Error {
         use Error::*;
         match self {
             Socket(e) => write!(f, "Error writing to or reading from HTTP socket: {}", e),
+            SocketSendFds(e) => write!(f, "Error writing to or reading from HTTP socket: {}", e),
             StatusCodeParsing(e) => write!(f, "Error parsing HTTP status code: {}", e),
             MissingProtocol => write!(f, "HTTP output is missing protocol statement"),
             ContentLengthParsing(e) => write!(f, "Error parsing HTTP Content-Length field: {}", e),
@@ -37,7 +41,7 @@ impl fmt::Display for Error {
 #[derive(Clone, Copy, Debug)]
 pub enum StatusCode {
     Continue,
-    OK,
+    Ok,
     NoContent,
     BadRequest,
     NotFound,
@@ -50,7 +54,7 @@ impl StatusCode {
     fn from_raw(code: usize) -> StatusCode {
         match code {
             100 => StatusCode::Continue,
-            200 => StatusCode::OK,
+            200 => StatusCode::Ok,
             204 => StatusCode::NoContent,
             400 => StatusCode::BadRequest,
             404 => StatusCode::NotFound,
@@ -69,18 +73,15 @@ impl StatusCode {
     fn is_server_error(self) -> bool {
         !matches!(
             self,
-            StatusCode::OK | StatusCode::Continue | StatusCode::NoContent
+            StatusCode::Ok | StatusCode::Continue | StatusCode::NoContent
         )
     }
 }
 
 fn get_header<'a>(res: &'a str, header: &'a str) -> Option<&'a str> {
     let header_str = format!("{}: ", header);
-    if let Some(o) = res.find(&header_str) {
-        Some(&res[o + header_str.len()..o + res[o..].find('\r').unwrap()])
-    } else {
-        None
-    }
+    res.find(&header_str)
+        .map(|o| &res[o + header_str.len()..o + res[o..].find('\r').unwrap()])
 }
 
 fn get_status_code(res: &str) -> Result<StatusCode, Error> {
@@ -136,21 +137,23 @@ fn parse_http_response(socket: &mut dyn Read) -> Result<Option<String>, Error> {
     }
 }
 
-pub fn simple_api_command<T: Read + Write>(
+pub fn simple_api_command_with_fds<T: Read + Write + ScmSocket>(
     socket: &mut T,
     method: &str,
     c: &str,
     request_body: Option<&str>,
+    request_fds: Vec<RawFd>,
 ) -> Result<(), Error> {
     socket
-        .write_all(
-            format!(
+        .send_with_fds(
+            &[format!(
                 "{} /api/v1/vm.{} HTTP/1.1\r\nHost: localhost\r\nAccept: */*\r\n",
                 method, c
             )
-            .as_bytes(),
+            .as_bytes()],
+            &request_fds,
         )
-        .map_err(Error::Socket)?;
+        .map_err(Error::SocketSendFds)?;
 
     if let Some(request_body) = request_body {
         socket
@@ -173,3 +176,12 @@ pub fn simple_api_command<T: Read + Write>(
     }
     Ok(())
 }
+
+pub fn simple_api_command<T: Read + Write + ScmSocket>(
+    socket: &mut T,
+    method: &str,
+    c: &str,
+    request_body: Option<&str>,
+) -> Result<(), Error> {
+    simple_api_command_with_fds(socket, method, c, request_body, Vec::new())
+}

arch/Cargo.toml

@@ -2,28 +2,29 @@
 name = "arch"
 version = "0.1.0"
 authors = ["The Chromium OS Authors"]
+edition = "2018"
 
 [features]
 default = []
 acpi = ["acpi_tables"]
+tdx = []
 
 [dependencies]
+acpi_tables = { path = "../acpi_tables", optional = true }
 anyhow = "1.0"
-byteorder = "1.3.4"
+byteorder = "1.4.3"
 hypervisor = { path = "../hypervisor" }
-libc = "0.2.86"
+libc = "0.2.98"
+linux-loader = { version = "0.3.0", features = ["elf", "bzimage", "pe"] }
 log = "0.4.14"
 serde = {version = ">=1.0.27", features = ["rc"] }
-serde_derive = ">=1.0.27"
-serde_json = ">=1.0.9"
-vm-memory = { version = "0.5.0", features = ["backend-mmap"] }
+thiserror = "1.0"
+versionize = "0.1.6"
+versionize_derive = "0.1.4"
+vm-memory = { version = "0.5.0", features = ["backend-mmap", "backend-bitmap"] }
 vm-migration = { path = "../vm-migration" }
-acpi_tables = { path = "../acpi_tables", optional = true }
-arch_gen = { path = "../arch_gen" }
+vmm-sys-util = { version = ">=0.5.0", features = ["with-serde"] }
 
-[dependencies.linux-loader]
-git = "https://github.com/rust-vmm/linux-loader"
-features = ["elf", "bzimage"]
-
-[dev-dependencies]
-rand = "0.8.3"
+[target.'cfg(target_arch = "aarch64")'.dependencies]
+fdt_parser = { version = "0.1.3", package = 'fdt'}
+vm-fdt = { git = "https://github.com/rust-vmm/vm-fdt", branch = "master" }

arch/src/aarch64/fdt.rs

@@ -6,23 +6,25 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the THIRD-PARTY file.
 
-use libc::{c_char, c_int, c_void};
+use byteorder::{BigEndian, ByteOrder};
+use std::cmp;
 use std::collections::HashMap;
-use std::ffi::{CStr, CString, NulError};
+use std::ffi::CStr;
 use std::fmt::Debug;
-use std::ptr::null;
-use std::{io, result};
+use std::result;
+use std::str;
 
 use super::super::DeviceType;
+use super::super::GuestMemoryMmap;
 use super::super::InitramfsConfig;
 use super::get_fdt_addr;
-use super::gic::GICDevice;
+use super::gic::GicDevice;
 use super::layout::{
-    FDT_MAX_SIZE, MEM_32BIT_DEVICES_SIZE, MEM_32BIT_DEVICES_START, PCI_MMCONFIG_SIZE,
-    PCI_MMCONFIG_START,
+    IRQ_BASE, MEM_32BIT_DEVICES_SIZE, MEM_32BIT_DEVICES_START, MEM_PCI_IO_SIZE, MEM_PCI_IO_START,
+    PCI_HIGH_BASE, PCI_MMCONFIG_SIZE, PCI_MMCONFIG_START,
 };
-use crate::aarch64::fdt::Error::CstringFDTTransform;
-use vm_memory::{Address, Bytes, GuestAddress, GuestMemory, GuestMemoryError, GuestMemoryMmap};
+use vm_fdt::{FdtWriter, FdtWriterResult};
+use vm_memory::{Address, Bytes, GuestAddress, GuestMemory, GuestMemoryError};
 
 // This is a value for uniquely identifying the FDT node declaring the interrupt controller.
 const GIC_PHANDLE: u32 = 1;
@@ -30,6 +32,8 @@ const GIC_PHANDLE: u32 = 1;
 const MSI_PHANDLE: u32 = 2;
 // This is a value for uniquely identifying the FDT node containing the clock definition.
 const CLOCK_PHANDLE: u32 = 3;
+// This is a value for uniquely identifying the FDT node containing the gpio controller.
+const GPIO_PHANDLE: u32 = 4;
 
 // Read the documentation specified when appending the root node to the FDT.
 const ADDRESS_CELLS: u32 = 0x2;
@@ -45,24 +49,12 @@ const GIC_FDT_IRQ_TYPE_PPI: u32 = 1;
 const IRQ_TYPE_EDGE_RISING: u32 = 1;
 const IRQ_TYPE_LEVEL_HI: u32 = 4;
 
-// This links to libfdt which handles the creation of the binary blob
-// flattened device tree (fdt) that is passed to the kernel and indicates
-// the hardware configuration of the machine.
-#[link(name = "fdt")]
-extern "C" {
-    fn fdt_create(buf: *mut c_void, bufsize: c_int) -> c_int;
-    fn fdt_finish_reservemap(fdt: *mut c_void) -> c_int;
-    fn fdt_begin_node(fdt: *mut c_void, name: *const c_char) -> c_int;
-    fn fdt_property(fdt: *mut c_void, name: *const c_char, val: *const c_void, len: c_int)
-        -> c_int;
-    fn fdt_end_node(fdt: *mut c_void) -> c_int;
-    fn fdt_open_into(fdt: *const c_void, buf: *mut c_void, bufsize: c_int) -> c_int;
-    fn fdt_finish(fdt: *const c_void) -> c_int;
-    fn fdt_pack(fdt: *mut c_void) -> c_int;
-}
+// Keys and Buttons
+// System Power Down
+const KEY_POWER: u32 = 116;
 
 /// Trait for devices to be added to the Flattened Device Tree.
-pub trait DeviceInfoForFDT {
+pub trait DeviceInfoForFdt {
     /// Returns the address where this device will be loaded.
     fn addr(&self) -> u64;
     /// Returns the associated interrupt for this device.
@@ -74,53 +66,41 @@ pub trait DeviceInfoForFDT {
 /// Errors thrown while configuring the Flattened Device Tree for aarch64.
 #[derive(Debug)]
 pub enum Error {
-    /// Failed to append node to the FDT.
-    AppendFDTNode(io::Error),
-    /// Failed to append a property to the FDT.
-    AppendFDTProperty(io::Error),
-    /// Syscall for creating FDT failed.
-    CreateFDT(io::Error),
-    /// Failed to obtain a C style string.
-    CstringFDTTransform(NulError),
-    /// Failure in calling syscall for terminating this FDT.
-    FinishFDTReserveMap(io::Error),
     /// Failure in writing FDT in memory.
-    WriteFDTToMemory(GuestMemoryError),
+    WriteFdtToMemory(GuestMemoryError),
 }
 type Result<T> = result::Result<T, Error>;
 
 /// Creates the flattened device tree for this aarch64 VM.
-pub fn create_fdt<T: DeviceInfoForFDT + Clone + Debug, S: ::std::hash::BuildHasher>(
+pub fn create_fdt<T: DeviceInfoForFdt + Clone + Debug, S: ::std::hash::BuildHasher>(
     guest_mem: &GuestMemoryMmap,
     cmdline: &CStr,
     vcpu_mpidr: Vec<u64>,
     device_info: &HashMap<(DeviceType, String), T, S>,
-    gic_device: &dyn GICDevice,
+    gic_device: &dyn GicDevice,
     initrd: &Option<InitramfsConfig>,
     pci_space_address: &(u64, u64),
-) -> Result<Vec<u8>> {
+) -> FdtWriterResult<Vec<u8>> {
     // Allocate stuff necessary for the holding the blob.
-    let mut fdt = vec![0; FDT_MAX_SIZE];
-
-    allocate_fdt(&mut fdt)?;
+    let mut fdt = FdtWriter::new().unwrap();
 
     // For an explanation why these nodes were introduced in the blob take a look at
     // https://github.com/torvalds/linux/blob/master/Documentation/devicetree/booting-without-of.txt#L845
     // Look for "Required nodes and properties".
 
     // Header or the root node as per above mentioned documentation.
-    append_begin_node(&mut fdt, "")?;
-    append_property_string(&mut fdt, "compatible", "linux,dummy-virt")?;
+    let root_node = fdt.begin_node("")?;
+    fdt.property_string("compatible", "linux,dummy-virt")?;
     // For info on #address-cells and size-cells read "Note about cells and address representation"
     // from the above mentioned txt file.
-    append_property_u32(&mut fdt, "#address-cells", ADDRESS_CELLS)?;
-    append_property_u32(&mut fdt, "#size-cells", SIZE_CELLS)?;
+    fdt.property_u32("#address-cells", ADDRESS_CELLS)?;
+    fdt.property_u32("#size-cells", SIZE_CELLS)?;
     // This is not mandatory but we use it to point the root node to the node
     // containing description of the interrupt controller for this VM.
-    append_property_u32(&mut fdt, "interrupt-parent", GIC_PHANDLE)?;
+    fdt.property_u32("interrupt-parent", GIC_PHANDLE)?;
     create_cpu_nodes(&mut fdt, &vcpu_mpidr)?;
     create_memory_node(&mut fdt, guest_mem)?;
-    create_chosen_node(&mut fdt, cmdline, initrd)?;
+    create_chosen_node(&mut fdt, cmdline.to_str().unwrap(), initrd)?;
     create_gic_node(&mut fdt, gic_device)?;
     create_timer_node(&mut fdt)?;
     create_clock_node(&mut fdt)?;
@@ -129,307 +109,138 @@ pub fn create_fdt<T: DeviceInfoForFDT + Clone + Debug, S: ::std::hash::BuildHash
     create_pci_nodes(&mut fdt, pci_space_address.0, pci_space_address.1)?;
 
     // End Header node.
-    append_end_node(&mut fdt)?;
+    fdt.end_node(root_node)?;
 
-    // Allocate another buffer so we can format and then write fdt to guest.
-    let mut fdt_final = vec![0; FDT_MAX_SIZE];
-    finish_fdt(&mut fdt, &mut fdt_final)?;
+    let fdt_final = fdt.finish()?;
 
-    // Write FDT to memory.
-    let fdt_address = GuestAddress(get_fdt_addr(&guest_mem));
-    guest_mem
-        .write_slice(fdt_final.as_slice(), fdt_address)
-        .map_err(Error::WriteFDTToMemory)?;
     Ok(fdt_final)
 }
 
-// Following are auxiliary functions for allocating and finishing the FDT.
-fn allocate_fdt(fdt: &mut Vec<u8>) -> Result<()> {
-    // Safe since we allocated this array with FDT_MAX_SIZE.
-    let mut fdt_ret = unsafe { fdt_create(fdt.as_mut_ptr() as *mut c_void, FDT_MAX_SIZE as c_int) };
-
-    if fdt_ret != 0 {
-        return Err(Error::CreateFDT(io::Error::last_os_error()));
-    }
-
-    // The flattened device trees created with fdt_create() contains a list of
-    // reserved memory areas. We need to call `fdt_finish_reservemap` so as to make sure that there is a
-    // terminator in the reservemap list and whatever happened to be at the
-    // start of the FDT data section would end up being interpreted as
-    // reservemap entries.
-    // Safe since we previously allocated this array.
-    fdt_ret = unsafe { fdt_finish_reservemap(fdt.as_mut_ptr() as *mut c_void) };
-    if fdt_ret != 0 {
-        return Err(Error::FinishFDTReserveMap(io::Error::last_os_error()));
-    }
+pub fn write_fdt_to_memory(fdt_final: Vec<u8>, guest_mem: &GuestMemoryMmap) -> Result<()> {
+    // Write FDT to memory.
+    let fdt_address = GuestAddress(get_fdt_addr());
+    guest_mem
+        .write_slice(fdt_final.as_slice(), fdt_address)
+        .map_err(Error::WriteFdtToMemory)?;
     Ok(())
 }
 
-fn finish_fdt(from_fdt: &mut Vec<u8>, to_fdt: &mut Vec<u8>) -> Result<()> {
-    // Safe since we allocated `fdt_final` and previously passed in its size.
-    let mut fdt_ret = unsafe { fdt_finish(from_fdt.as_mut_ptr() as *mut c_void) };
-    if fdt_ret != 0 {
-        return Err(Error::FinishFDTReserveMap(io::Error::last_os_error()));
-    }
-
-    // Safe because we allocated both arrays with the correct size.
-    fdt_ret = unsafe {
-        fdt_open_into(
-            from_fdt.as_mut_ptr() as *mut c_void,
-            to_fdt.as_mut_ptr() as *mut c_void,
-            FDT_MAX_SIZE as i32,
-        )
-    };
-    if fdt_ret != 0 {
-        return Err(Error::FinishFDTReserveMap(io::Error::last_os_error()));
-    }
-
-    // Safe since we allocated `to_fdt`.
-    fdt_ret = unsafe { fdt_pack(to_fdt.as_mut_ptr() as *mut c_void) };
-    if fdt_ret != 0 {
-        return Err(Error::FinishFDTReserveMap(io::Error::last_os_error()));
-    }
-    Ok(())
-}
-
-// Following are auxiliary functions for appending nodes to FDT.
-fn append_begin_node(fdt: &mut Vec<u8>, name: &str) -> Result<()> {
-    let cstr_name = CString::new(name).map_err(CstringFDTTransform)?;
-
-    // Safe because we allocated fdt and converted name to a CString
-    let fdt_ret = unsafe { fdt_begin_node(fdt.as_mut_ptr() as *mut c_void, cstr_name.as_ptr()) };
-    if fdt_ret != 0 {
-        return Err(Error::AppendFDTNode(io::Error::last_os_error()));
-    }
-    Ok(())
-}
-
-fn append_end_node(fdt: &mut Vec<u8>) -> Result<()> {
-    // Safe because we allocated fdt.
-    let fdt_ret = unsafe { fdt_end_node(fdt.as_mut_ptr() as *mut c_void) };
-    if fdt_ret != 0 {
-        return Err(Error::AppendFDTNode(io::Error::last_os_error()));
-    }
-    Ok(())
-}
-
-// Following are auxiliary functions for appending property nodes to the nodes of the FDT.
-fn append_property_u32(fdt: &mut Vec<u8>, name: &str, val: u32) -> Result<()> {
-    append_property(fdt, name, &to_be32(val))
-}
-
-fn append_property_u64(fdt: &mut Vec<u8>, name: &str, val: u64) -> Result<()> {
-    append_property(fdt, name, &to_be64(val))
-}
-
-fn append_property_string(fdt: &mut Vec<u8>, name: &str, value: &str) -> Result<()> {
-    let cstr_value = CString::new(value).map_err(CstringFDTTransform)?;
-    append_property_cstring(fdt, name, &cstr_value)
-}
-
-fn append_property_cstring(fdt: &mut Vec<u8>, name: &str, cstr_value: &CStr) -> Result<()> {
-    let value_bytes = cstr_value.to_bytes_with_nul();
-    let cstr_name = CString::new(name).map_err(CstringFDTTransform)?;
-    // Safe because we allocated fdt, converted name and value to CStrings
-    let fdt_ret = unsafe {
-        fdt_property(
-            fdt.as_mut_ptr() as *mut c_void,
-            cstr_name.as_ptr(),
-            value_bytes.as_ptr() as *mut c_void,
-            value_bytes.len() as i32,
-        )
-    };
-    if fdt_ret != 0 {
-        return Err(Error::AppendFDTProperty(io::Error::last_os_error()));
-    }
-    Ok(())
-}
-
-fn append_property_null(fdt: &mut Vec<u8>, name: &str) -> Result<()> {
-    let cstr_name = CString::new(name).map_err(CstringFDTTransform)?;
-
-    // Safe because we allocated fdt, converted name to a CString
-    let fdt_ret = unsafe {
-        fdt_property(
-            fdt.as_mut_ptr() as *mut c_void,
-            cstr_name.as_ptr(),
-            null(),
-            0,
-        )
-    };
-    if fdt_ret != 0 {
-        return Err(Error::AppendFDTProperty(io::Error::last_os_error()));
-    }
-    Ok(())
-}
-
-fn append_property(fdt: &mut Vec<u8>, name: &str, val: &[u8]) -> Result<()> {
-    let cstr_name = CString::new(name).map_err(CstringFDTTransform)?;
-    let val_ptr = val.as_ptr() as *const c_void;
-
-    // Safe because we allocated fdt and converted name to a CString
-    let fdt_ret = unsafe {
-        fdt_property(
-            fdt.as_mut_ptr() as *mut c_void,
-            cstr_name.as_ptr(),
-            val_ptr,
-            val.len() as i32,
-        )
-    };
-    if fdt_ret != 0 {
-        return Err(Error::AppendFDTProperty(io::Error::last_os_error()));
-    }
-    Ok(())
-}
-
-// Auxiliary functions for writing u32/u64 numbers in big endian order.
-fn to_be32(input: u32) -> [u8; 4] {
-    u32::to_be_bytes(input)
-}
-
-fn to_be64(input: u64) -> [u8; 8] {
-    u64::to_be_bytes(input)
-}
-
-// Helper functions for generating a properly formatted byte vector using 32-bit/64-bit cells.
-fn generate_prop32(cells: &[u32]) -> Vec<u8> {
-    let mut ret: Vec<u8> = Vec::new();
-    for &e in cells {
-        ret.extend(to_be32(e).iter());
-    }
-    ret
-}
-
-fn generate_prop64(cells: &[u64]) -> Vec<u8> {
-    let mut ret: Vec<u8> = Vec::new();
-    for &e in cells {
-        ret.extend(to_be64(e).iter());
-    }
-    ret
-}
-
 // Following are the auxiliary function for creating the different nodes that we append to our FDT.
-fn create_cpu_nodes(fdt: &mut Vec<u8>, vcpu_mpidr: &[u64]) -> Result<()> {
+fn create_cpu_nodes(fdt: &mut FdtWriter, vcpu_mpidr: &[u64]) -> FdtWriterResult<()> {
     // See https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/arm/cpus.yaml.
-    append_begin_node(fdt, "cpus")?;
-    // As per documentation, on ARM v8 64-bit systems value should be set to 2.
-    append_property_u32(fdt, "#address-cells", 0x02)?;
-    append_property_u32(fdt, "#size-cells", 0x0)?;
+    let cpus_node = fdt.begin_node("cpus")?;
+    fdt.property_u32("#address-cells", 0x1)?;
+    fdt.property_u32("#size-cells", 0x0)?;
     let num_cpus = vcpu_mpidr.len();
 
-    for (cpu_index, mpidr) in vcpu_mpidr.iter().enumerate().take(num_cpus) {
-        let cpu_name = format!("cpu@{:x}", cpu_index);
-        append_begin_node(fdt, &cpu_name)?;
-        append_property_string(fdt, "device_type", "cpu")?;
-        append_property_string(fdt, "compatible", "arm,arm-v8")?;
+    for (cpu_id, mpidr) in vcpu_mpidr.iter().enumerate().take(num_cpus) {
+        let cpu_name = format!("cpu@{:x}", cpu_id);
+        let cpu_node = fdt.begin_node(&cpu_name)?;
+        fdt.property_string("device_type", "cpu")?;
+        fdt.property_string("compatible", "arm,arm-v8")?;
         if num_cpus > 1 {
             // This is required on armv8 64-bit. See aforementioned documentation.
-            append_property_string(fdt, "enable-method", "psci")?;
+            fdt.property_string("enable-method", "psci")?;
         }
         // Set the field to first 24 bits of the MPIDR - Multiprocessor Affinity Register.
         // See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0488c/BABHBJCI.html.
-        append_property_u64(fdt, "reg", mpidr & 0x7FFFFF)?;
-        append_end_node(fdt)?;
+        fdt.property_u32("reg", (mpidr & 0x7FFFFF) as u32)?;
+        fdt.end_node(cpu_node)?;
     }
-    append_end_node(fdt)?;
+    fdt.end_node(cpus_node)?;
     Ok(())
 }
 
-fn create_memory_node(fdt: &mut Vec<u8>, guest_mem: &GuestMemoryMmap) -> Result<()> {
+fn create_memory_node(fdt: &mut FdtWriter, guest_mem: &GuestMemoryMmap) -> FdtWriterResult<()> {
     let mem_size = guest_mem.last_addr().raw_value() - super::layout::RAM_64BIT_START + 1;
     // See https://github.com/torvalds/linux/blob/master/Documentation/devicetree/booting-without-of.txt#L960
     // for an explanation of this.
-    let mem_reg_prop = generate_prop64(&[super::layout::RAM_64BIT_START as u64, mem_size as u64]);
+    let mem_reg_prop = [super::layout::RAM_64BIT_START as u64, mem_size as u64];
+
+    let memory_node = fdt.begin_node("memory")?;
+    fdt.property_string("device_type", "memory")?;
+    fdt.property_array_u64("reg", &mem_reg_prop)?;
+    fdt.end_node(memory_node)?;
 
-    append_begin_node(fdt, "memory")?;
-    append_property_string(fdt, "device_type", "memory")?;
-    append_property(fdt, "reg", &mem_reg_prop)?;
-    append_end_node(fdt)?;
     Ok(())
 }
 
 fn create_chosen_node(
-    fdt: &mut Vec<u8>,
-    cmdline: &CStr,
+    fdt: &mut FdtWriter,
+    cmdline: &str,
     initrd: &Option<InitramfsConfig>,
-) -> Result<()> {
-    append_begin_node(fdt, "chosen")?;
-    append_property_cstring(fdt, "bootargs", cmdline)?;
+) -> FdtWriterResult<()> {
+    let chosen_node = fdt.begin_node("chosen")?;
+    fdt.property_string("bootargs", cmdline)?;
 
     if let Some(initrd_config) = initrd {
-        append_property_u64(
-            fdt,
-            "linux,initrd-start",
-            initrd_config.address.raw_value() as u64,
-        )?;
-        append_property_u64(
-            fdt,
-            "linux,initrd-end",
-            initrd_config.address.raw_value() + initrd_config.size as u64,
-        )?;
+        let initrd_start = initrd_config.address.raw_value() as u64;
+        let initrd_end = initrd_config.address.raw_value() + initrd_config.size as u64;
+        fdt.property_u64("linux,initrd-start", initrd_start)?;
+        fdt.property_u64("linux,initrd-end", initrd_end)?;
     }
 
-    append_end_node(fdt)?;
+    fdt.end_node(chosen_node)?;
 
     Ok(())
 }
 
-fn create_gic_node(fdt: &mut Vec<u8>, gic_device: &dyn GICDevice) -> Result<()> {
-    let gic_reg_prop = generate_prop64(gic_device.device_properties());
+fn create_gic_node(fdt: &mut FdtWriter, gic_device: &dyn GicDevice) -> FdtWriterResult<()> {
+    let gic_reg_prop = gic_device.device_properties();
 
-    append_begin_node(fdt, "intc")?;
-    append_property_string(fdt, "compatible", gic_device.fdt_compatibility())?;
-    append_property_null(fdt, "interrupt-controller")?;
+    let intc_node = fdt.begin_node("intc")?;
+
+    fdt.property_string("compatible", gic_device.fdt_compatibility())?;
+    fdt.property_null("interrupt-controller")?;
     // "interrupt-cells" field specifies the number of cells needed to encode an
     // interrupt source. The type shall be a <u32> and the value shall be 3 if no PPI affinity description
     // is required.
-    append_property_u32(fdt, "#interrupt-cells", 3)?;
-    append_property(fdt, "reg", &gic_reg_prop)?;
-    append_property_u32(fdt, "phandle", GIC_PHANDLE)?;
-    append_property_u32(fdt, "#address-cells", 2)?;
-    append_property_u32(fdt, "#size-cells", 2)?;
-    append_property_null(fdt, "ranges")?;
-    let gic_intr = [
+    fdt.property_u32("#interrupt-cells", 3)?;
+    fdt.property_array_u64("reg", gic_reg_prop)?;
+    fdt.property_u32("phandle", GIC_PHANDLE)?;
+    fdt.property_u32("#address-cells", 2)?;
+    fdt.property_u32("#size-cells", 2)?;
+    fdt.property_null("ranges")?;
+
+    let gic_intr_prop = [
         GIC_FDT_IRQ_TYPE_PPI,
         gic_device.fdt_maint_irq(),
         IRQ_TYPE_LEVEL_HI,
     ];
-    let gic_intr_prop = generate_prop32(&gic_intr);
-
-    append_property(fdt, "interrupts", &gic_intr_prop)?;
+    fdt.property_array_u32("interrupts", &gic_intr_prop)?;
 
     if gic_device.msi_compatible() {
-        append_begin_node(fdt, "msic")?;
-        append_property_string(fdt, "compatible", gic_device.msi_compatibility())?;
-        append_property_null(fdt, "msi-controller")?;
-        append_property_u32(fdt, "phandle", MSI_PHANDLE)?;
-        let msi_reg_prop = generate_prop64(gic_device.msi_properties());
-        append_property(fdt, "reg", &msi_reg_prop)?;
-        append_end_node(fdt)?;
+        let msic_node = fdt.begin_node("msic")?;
+        fdt.property_string("compatible", gic_device.msi_compatibility())?;
+        fdt.property_null("msi-controller")?;
+        fdt.property_u32("phandle", MSI_PHANDLE)?;
+        let msi_reg_prop = gic_device.msi_properties();
+        fdt.property_array_u64("reg", msi_reg_prop)?;
+        fdt.end_node(msic_node)?;
     }
 
-    append_end_node(fdt)?;
+    fdt.end_node(intc_node)?;
 
     Ok(())
 }
 
-fn create_clock_node(fdt: &mut Vec<u8>) -> Result<()> {
+fn create_clock_node(fdt: &mut FdtWriter) -> FdtWriterResult<()> {
     // The Advanced Peripheral Bus (APB) is part of the Advanced Microcontroller Bus Architecture
     // (AMBA) protocol family. It defines a low-cost interface that is optimized for minimal power
     // consumption and reduced interface complexity.
     // PCLK is the clock source and this node defines exactly the clock for the APB.
-    append_begin_node(fdt, "apb-pclk")?;
-    append_property_string(fdt, "compatible", "fixed-clock")?;
-    append_property_u32(fdt, "#clock-cells", 0x0)?;
-    append_property_u32(fdt, "clock-frequency", 24000000)?;
-    append_property_string(fdt, "clock-output-names", "clk24mhz")?;
-    append_property_u32(fdt, "phandle", CLOCK_PHANDLE)?;
-    append_end_node(fdt)?;
+    let clock_node = fdt.begin_node("apb-pclk")?;
+    fdt.property_string("compatible", "fixed-clock")?;
+    fdt.property_u32("#clock-cells", 0x0)?;
+    fdt.property_u32("clock-frequency", 24000000)?;
+    fdt.property_string("clock-output-names", "clk24mhz")?;
+    fdt.property_u32("phandle", CLOCK_PHANDLE)?;
+    fdt.end_node(clock_node)?;
 
     Ok(())
 }
 
-fn create_timer_node(fdt: &mut Vec<u8>) -> Result<()> {
+fn create_timer_node(fdt: &mut FdtWriter) -> FdtWriterResult<()> {
     // See
     // https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/interrupt-controller/arch_timer.txt
     // These are fixed interrupt numbers for the timer device.
@@ -442,93 +253,143 @@ fn create_timer_node(fdt: &mut Vec<u8>) -> Result<()> {
         timer_reg_cells.push(irq);
         timer_reg_cells.push(IRQ_TYPE_LEVEL_HI);
     }
-    let timer_reg_prop = generate_prop32(timer_reg_cells.as_slice());
 
-    append_begin_node(fdt, "timer")?;
-    append_property_string(fdt, "compatible", compatible)?;
-    append_property_null(fdt, "always-on")?;
-    append_property(fdt, "interrupts", &timer_reg_prop)?;
-    append_end_node(fdt)?;
+    let timer_node = fdt.begin_node("timer")?;
+    fdt.property_string("compatible", compatible)?;
+    fdt.property_null("always-on")?;
+    fdt.property_array_u32("interrupts", &timer_reg_cells)?;
+    fdt.end_node(timer_node)?;
 
     Ok(())
 }
 
-fn create_psci_node(fdt: &mut Vec<u8>) -> Result<()> {
+fn create_psci_node(fdt: &mut FdtWriter) -> FdtWriterResult<()> {
     let compatible = "arm,psci-0.2";
-    append_begin_node(fdt, "psci")?;
-    append_property_string(fdt, "compatible", compatible)?;
+    let psci_node = fdt.begin_node("psci")?;
+    fdt.property_string("compatible", compatible)?;
     // Two methods available: hvc and smc.
     // As per documentation, PSCI calls between a guest and hypervisor may use the HVC conduit instead of SMC.
     // So, since we are using kvm, we need to use hvc.
-    append_property_string(fdt, "method", "hvc")?;
-    append_end_node(fdt)?;
+    fdt.property_string("method", "hvc")?;
+    fdt.end_node(psci_node)?;
 
     Ok(())
 }
 
-fn create_virtio_node<T: DeviceInfoForFDT + Clone + Debug>(
-    fdt: &mut Vec<u8>,
+fn create_virtio_node<T: DeviceInfoForFdt + Clone + Debug>(
+    fdt: &mut FdtWriter,
     dev_info: &T,
-) -> Result<()> {
-    let device_reg_prop = generate_prop64(&[dev_info.addr(), dev_info.length()]);
-    let irq = generate_prop32(&[GIC_FDT_IRQ_TYPE_SPI, dev_info.irq(), IRQ_TYPE_EDGE_RISING]);
+) -> FdtWriterResult<()> {
+    let device_reg_prop = [dev_info.addr(), dev_info.length()];
+    let irq = [GIC_FDT_IRQ_TYPE_SPI, dev_info.irq(), IRQ_TYPE_EDGE_RISING];
 
-    append_begin_node(fdt, &format!("virtio_mmio@{:x}", dev_info.addr()))?;
-    append_property_string(fdt, "compatible", "virtio,mmio")?;
-    append_property(fdt, "reg", &device_reg_prop)?;
-    append_property(fdt, "interrupts", &irq)?;
-    append_property_u32(fdt, "interrupt-parent", GIC_PHANDLE)?;
-    append_end_node(fdt)?;
+    let virtio_node = fdt.begin_node(&format!("virtio_mmio@{:x}", dev_info.addr()))?;
+    fdt.property_string("compatible", "virtio,mmio")?;
+    fdt.property_array_u64("reg", &device_reg_prop)?;
+    fdt.property_array_u32("interrupts", &irq)?;
+    fdt.property_u32("interrupt-parent", GIC_PHANDLE)?;
+    fdt.end_node(virtio_node)?;
 
     Ok(())
 }
 
-fn create_serial_node<T: DeviceInfoForFDT + Clone + Debug>(
-    fdt: &mut Vec<u8>,
+fn create_serial_node<T: DeviceInfoForFdt + Clone + Debug>(
+    fdt: &mut FdtWriter,
     dev_info: &T,
-) -> Result<()> {
-    let serial_reg_prop = generate_prop64(&[dev_info.addr(), dev_info.length()]);
-    let irq = generate_prop32(&[GIC_FDT_IRQ_TYPE_SPI, dev_info.irq(), IRQ_TYPE_EDGE_RISING]);
+) -> FdtWriterResult<()> {
+    let compatible = b"arm,pl011\0arm,primecell\0";
+    let serial_reg_prop = [dev_info.addr(), dev_info.length()];
+    let irq = [
+        GIC_FDT_IRQ_TYPE_SPI,
+        dev_info.irq() - IRQ_BASE,
+        IRQ_TYPE_EDGE_RISING,
+    ];
 
-    append_begin_node(fdt, &format!("uart@{:x}", dev_info.addr()))?;
-    append_property_string(fdt, "compatible", "ns16550a")?;
-    append_property(fdt, "reg", &serial_reg_prop)?;
-    append_property_u32(fdt, "clocks", CLOCK_PHANDLE)?;
-    append_property_string(fdt, "clock-names", "apb_pclk")?;
-    append_property(fdt, "interrupts", &irq)?;
-    append_end_node(fdt)?;
+    let serial_node = fdt.begin_node(&format!("pl011@{:x}", dev_info.addr()))?;
+    fdt.property("compatible", compatible)?;
+    fdt.property_array_u64("reg", &serial_reg_prop)?;
+    fdt.property_u32("clocks", CLOCK_PHANDLE)?;
+    fdt.property_string("clock-names", "apb_pclk")?;
+    fdt.property_array_u32("interrupts", &irq)?;
+    fdt.end_node(serial_node)?;
 
     Ok(())
 }
 
-fn create_rtc_node<T: DeviceInfoForFDT + Clone + Debug>(
-    fdt: &mut Vec<u8>,
+fn create_rtc_node<T: DeviceInfoForFdt + Clone + Debug>(
+    fdt: &mut FdtWriter,
     dev_info: &T,
-) -> Result<()> {
+) -> FdtWriterResult<()> {
     let compatible = b"arm,pl031\0arm,primecell\0";
-    let rtc_reg_prop = generate_prop64(&[dev_info.addr(), dev_info.length()]);
-    let irq = generate_prop32(&[GIC_FDT_IRQ_TYPE_SPI, dev_info.irq(), IRQ_TYPE_LEVEL_HI]);
-    append_begin_node(fdt, &format!("rtc@{:x}", dev_info.addr()))?;
-    append_property(fdt, "compatible", compatible)?;
-    append_property(fdt, "reg", &rtc_reg_prop)?;
-    append_property(fdt, "interrupts", &irq)?;
-    append_property_u32(fdt, "clocks", CLOCK_PHANDLE)?;
-    append_property_string(fdt, "clock-names", "apb_pclk")?;
-    append_end_node(fdt)?;
+    let rtc_reg_prop = [dev_info.addr(), dev_info.length()];
+    let irq = [
+        GIC_FDT_IRQ_TYPE_SPI,
+        dev_info.irq() - IRQ_BASE,
+        IRQ_TYPE_LEVEL_HI,
+    ];
+
+    let rtc_node = fdt.begin_node(&format!("rtc@{:x}", dev_info.addr()))?;
+    fdt.property("compatible", compatible)?;
+    fdt.property_array_u64("reg", &rtc_reg_prop)?;
+    fdt.property_array_u32("interrupts", &irq)?;
+    fdt.property_u32("clocks", CLOCK_PHANDLE)?;
+    fdt.property_string("clock-names", "apb_pclk")?;
+    fdt.end_node(rtc_node)?;
 
     Ok(())
 }
 
-fn create_devices_node<T: DeviceInfoForFDT + Clone + Debug, S: ::std::hash::BuildHasher>(
-    fdt: &mut Vec<u8>,
+fn create_gpio_node<T: DeviceInfoForFdt + Clone + Debug>(
+    fdt: &mut FdtWriter,
+    dev_info: &T,
+) -> FdtWriterResult<()> {
+    // PL061 GPIO controller node
+    let compatible = b"arm,pl061\0arm,primecell\0";
+    let gpio_reg_prop = [dev_info.addr(), dev_info.length()];
+    let irq = [
+        GIC_FDT_IRQ_TYPE_SPI,
+        dev_info.irq() - IRQ_BASE,
+        IRQ_TYPE_EDGE_RISING,
+    ];
+
+    let gpio_node = fdt.begin_node(&format!("pl061@{:x}", dev_info.addr()))?;
+    fdt.property("compatible", compatible)?;
+    fdt.property_array_u64("reg", &gpio_reg_prop)?;
+    fdt.property_array_u32("interrupts", &irq)?;
+    fdt.property_null("gpio-controller")?;
+    fdt.property_u32("#gpio-cells", 2)?;
+    fdt.property_u32("clocks", CLOCK_PHANDLE)?;
+    fdt.property_string("clock-names", "apb_pclk")?;
+    fdt.property_u32("phandle", GPIO_PHANDLE)?;
+    fdt.end_node(gpio_node)?;
+
+    // gpio-keys node
+    let gpio_keys_node = fdt.begin_node("gpio-keys")?;
+    fdt.property_string("compatible", "gpio-keys")?;
+    fdt.property_u32("#size-cells", 0)?;
+    fdt.property_u32("#address-cells", 1)?;
+    let gpio_keys_poweroff_node = fdt.begin_node("button@1")?;
+    fdt.property_string("label", "GPIO Key Poweroff")?;
+    fdt.property_u32("linux,code", KEY_POWER)?;
+    let gpios = [GPIO_PHANDLE, 3, 0];
+    fdt.property_array_u32("gpios", &gpios)?;
+    fdt.end_node(gpio_keys_poweroff_node)?;
+    fdt.end_node(gpio_keys_node)?;
+
+    Ok(())
+}
+
+fn create_devices_node<T: DeviceInfoForFdt + Clone + Debug, S: ::std::hash::BuildHasher>(
+    fdt: &mut FdtWriter,
     dev_info: &HashMap<(DeviceType, String), T, S>,
-) -> Result<()> {
+) -> FdtWriterResult<()> {
     // Create one temp Vec to store all virtio devices
     let mut ordered_virtio_device: Vec<&T> = Vec::new();
 
     for ((device_type, _device_id), info) in dev_info {
         match device_type {
-            DeviceType::RTC => create_rtc_node(fdt, info)?,
+            DeviceType::Gpio => create_gpio_node(fdt, info)?,
+            DeviceType::Rtc => create_rtc_node(fdt, info)?,
             DeviceType::Serial => create_serial_node(fdt, info)?,
             DeviceType::Virtio(_) => {
                 ordered_virtio_device.push(info);
@@ -549,11 +410,40 @@ fn create_devices_node<T: DeviceInfoForFDT + Clone + Debug, S: ::std::hash::Buil
     Ok(())
 }
 
-fn create_pci_nodes(fdt: &mut Vec<u8>, pci_device_base: u64, pci_device_size: u64) -> Result<()> {
+fn create_pci_nodes(
+    fdt: &mut FdtWriter,
+    pci_device_base: u64,
+    pci_device_size: u64,
+) -> FdtWriterResult<()> {
     // Add node for PCIe controller.
     // See Documentation/devicetree/bindings/pci/host-generic-pci.txt in the kernel
     // and https://elinux.org/Device_Tree_Usage.
-    let ranges = generate_prop32(&[
+
+    // EDK2 requires the PCIe high space above 4G address.
+    // The actual space in CLH follows the RAM. If the RAM space is small, the PCIe high space
+    // could fall bellow 4G.
+    // Here we put it above 512G in FDT to workaround the EDK2 check.
+    // But the address written in ACPI is not impacted.
+    let pci_device_base_64bit: u64 = if cfg!(feature = "acpi") {
+        pci_device_base + PCI_HIGH_BASE
+    } else {
+        pci_device_base
+    };
+    let pci_device_size_64bit: u64 = if cfg!(feature = "acpi") {
+        pci_device_size - PCI_HIGH_BASE
+    } else {
+        pci_device_size
+    };
+
+    let ranges = [
+        // io addresses
+        0x1000000,
+        0_u32,
+        0_u32,
+        (MEM_PCI_IO_START.0 >> 32) as u32,
+        MEM_PCI_IO_START.0 as u32,
+        (MEM_PCI_IO_SIZE >> 32) as u32,
+        MEM_PCI_IO_SIZE as u32,
         // mmio addresses
         0x2000000,                                // (ss = 10: 32-bit memory space)
         (MEM_32BIT_DEVICES_START.0 >> 32) as u32, // PCI address
@@ -563,31 +453,111 @@ fn create_pci_nodes(fdt: &mut Vec<u8>, pci_device_base: u64, pci_device_size: u6
         (MEM_32BIT_DEVICES_SIZE >> 32) as u32, // size
         MEM_32BIT_DEVICES_SIZE as u32,
         // device addresses
-        0x3000000,                      // (ss = 11: 64-bit memory space)
-        (pci_device_base >> 32) as u32, // PCI address
-        pci_device_base as u32,
-        (pci_device_base >> 32) as u32, // CPU address
-        pci_device_base as u32,
-        (pci_device_size >> 32) as u32, // size
-        pci_device_size as u32,
-    ]);
-    let bus_range = generate_prop32(&[0, 0]); // Only bus 0
-    let reg = generate_prop64(&[PCI_MMCONFIG_START.0, PCI_MMCONFIG_SIZE]);
+        0x3000000,                            // (ss = 11: 64-bit memory space)
+        (pci_device_base_64bit >> 32) as u32, // PCI address
+        pci_device_base_64bit as u32,
+        (pci_device_base_64bit >> 32) as u32, // CPU address
+        pci_device_base_64bit as u32,
+        (pci_device_size_64bit >> 32) as u32, // size
+        pci_device_size_64bit as u32,
+    ];
+    let bus_range = [0, 0]; // Only bus 0
+    let reg = [PCI_MMCONFIG_START.0, PCI_MMCONFIG_SIZE];
 
-    append_begin_node(fdt, "pci")?;
-    append_property_string(fdt, "compatible", "pci-host-ecam-generic")?;
-    append_property_string(fdt, "device_type", "pci")?;
-    append_property(fdt, "ranges", &ranges)?;
-    append_property(fdt, "bus-range", &bus_range)?;
-    append_property_u32(fdt, "#address-cells", 3)?;
-    append_property_u32(fdt, "#size-cells", 2)?;
-    append_property(fdt, "reg", &reg)?;
-    append_property_u32(fdt, "#interrupt-cells", 1)?;
-    append_property_null(fdt, "interrupt-map")?;
-    append_property_null(fdt, "interrupt-map-mask")?;
-    append_property_null(fdt, "dma-coherent")?;
-    append_property_u32(fdt, "msi-parent", MSI_PHANDLE)?;
-    append_end_node(fdt)?;
+    let pci_node = fdt.begin_node("pci")?;
+    fdt.property_string("compatible", "pci-host-ecam-generic")?;
+    fdt.property_string("device_type", "pci")?;
+    fdt.property_array_u32("ranges", &ranges)?;
+    fdt.property_array_u32("bus-range", &bus_range)?;
+    fdt.property_u32("#address-cells", 3)?;
+    fdt.property_u32("#size-cells", 2)?;
+    fdt.property_array_u64("reg", &reg)?;
+    fdt.property_u32("#interrupt-cells", 1)?;
+    fdt.property_null("interrupt-map")?;
+    fdt.property_null("interrupt-map-mask")?;
+    fdt.property_null("dma-coherent")?;
+    fdt.property_u32("msi-parent", MSI_PHANDLE)?;
+    fdt.end_node(pci_node)?;
 
     Ok(())
 }
+
+// Parse the DTB binary and print for debugging
+pub fn print_fdt(dtb: &[u8]) {
+    match fdt_parser::Fdt::new(dtb) {
+        Ok(fdt) => {
+            if let Some(root) = fdt.find_node("/") {
+                debug!("Printing the FDT:");
+                print_node(root, 0);
+            } else {
+                debug!("Failed to find root node in FDT for debugging.");
+            }
+        }
+        Err(_) => debug!("Failed to parse FDT for debugging."),
+    }
+}
+
+fn print_node(node: fdt_parser::node::FdtNode<'_, '_>, n_spaces: usize) {
+    debug!("{:indent$}{}/", "", node.name, indent = n_spaces);
+    for property in node.properties() {
+        let name = property.name;
+
+        // If the property is 'compatible', its value requires special handling.
+        // The u8 array could contain multiple null-terminated strings.
+        // We copy the original array and simply replace all 'null' characters with spaces.
+        let value = if name == "compatible" {
+            let mut compatible = vec![0u8; 256];
+            let handled_value = property
+                .value
+                .iter()
+                .map(|&c| if c == 0 { b' ' } else { c })
+                .collect::<Vec<_>>();
+            let len = cmp::min(255, handled_value.len());
+            compatible[..len].copy_from_slice(&handled_value[..len]);
+            compatible[..(len + 1)].to_vec()
+        } else {
+            property.value.to_vec()
+        };
+        let value = &value;
+
+        // Now the value can be either:
+        //   - A null-terminated C string, or
+        //   - Binary data
+        // We follow a very simple logic to present the value:
+        //   - At first, try to convert it to CStr and print,
+        //   - If failed, print it as u32 array.
+        let value_result = match CStr::from_bytes_with_nul(value) {
+            Ok(value_cstr) => match value_cstr.to_str() {
+                Ok(value_str) => Some(value_str),
+                Err(_e) => None,
+            },
+            Err(_e) => None,
+        };
+
+        if let Some(value_str) = value_result {
+            debug!(
+                "{:indent$}{} : {:#?}",
+                "",
+                name,
+                value_str,
+                indent = (n_spaces + 2)
+            );
+        } else {
+            let mut array = Vec::with_capacity(256);
+            array.resize(value.len() / 4, 0u32);
+            BigEndian::read_u32_into(value, &mut array);
+            debug!(
+                "{:indent$}{} : {:X?}",
+                "",
+                name,
+                array,
+                indent = (n_spaces + 2)
+            );
+        };
+    }
+
+    // Print children nodes if there is any
+    for child in node.children() {
+        print_node(child, n_spaces + 2);
+    }
+}

arch/src/aarch64/gic/dist_regs.rs

@@ -152,7 +152,7 @@ pub fn set_dist_regs(gic: &Arc<dyn hypervisor::Device>, state: &[u32]) -> Result
 
     for dreg in VGIC_DIST_REGS {
         let mut base = dreg.base + REG_SIZE as u32 * dreg.bpi as u32;
-        let end = compute_reg_len(gic, &dreg, base)?;
+        let end = compute_reg_len(gic, dreg, base)?;
 
         while base < end {
             let val = state[idx];
@@ -169,7 +169,7 @@ pub fn get_dist_regs(gic: &Arc<dyn hypervisor::Device>) -> Result<Vec<u32>> {
 
     for dreg in VGIC_DIST_REGS {
         let mut base = dreg.base + REG_SIZE as u32 * dreg.bpi as u32;
-        let end = compute_reg_len(gic, &dreg, base)?;
+        let end = compute_reg_len(gic, dreg, base)?;
 
         while base < end {
             let val: u32 = 0;

arch/src/aarch64/gic/gicv3.rs

@@ -1,22 +1,30 @@
+// Copyright 2021 Arm Limited (or its affiliates). All rights reserved.
 // Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 // SPDX-License-Identifier: Apache-2.0
+//
+// This file implements the GicV3 device.
 
 pub mod kvm {
     use crate::aarch64::gic::dist_regs::{get_dist_regs, read_ctlr, set_dist_regs, write_ctlr};
     use crate::aarch64::gic::icc_regs::{get_icc_regs, set_icc_regs};
-    use crate::aarch64::gic::kvm::{save_pending_tables, KvmGICDevice};
-    use crate::aarch64::gic::redist_regs::{get_redist_regs, set_redist_regs};
-    use crate::aarch64::gic::GICDevice;
+    use crate::aarch64::gic::kvm::{save_pending_tables, KvmGicDevice};
+    use crate::aarch64::gic::redist_regs::{
+        construct_gicr_typers, get_redist_regs, set_redist_regs,
+    };
+    use crate::aarch64::gic::GicDevice;
     use crate::layout;
     use anyhow::anyhow;
     use hypervisor::kvm::kvm_bindings;
+    use hypervisor::CpuState;
     use std::any::Any;
     use std::convert::TryInto;
     use std::sync::Arc;
     use std::{boxed::Box, result};
+    use versionize::{VersionMap, Versionize, VersionizeResult};
+    use versionize_derive::Versionize;
     use vm_migration::{
-        Migratable, MigratableError, Pausable, Snapshot, SnapshotDataSection, Snapshottable,
-        Transportable,
+        Migratable, MigratableError, Pausable, Snapshot, Snapshottable, Transportable,
+        VersionMapped,
     };
 
     /// Errors thrown while saving/restoring the GICv3.
@@ -37,15 +45,15 @@ pub mod kvm {
         /// Error in restoring GIC redistributor registers.
         RestoreRedistributorRegisters(crate::aarch64::gic::Error),
         /// Error in saving GIC CPU interface registers.
-        SaveICCRegisters(crate::aarch64::gic::Error),
+        SaveIccRegisters(crate::aarch64::gic::Error),
         /// Error in restoring GIC CPU interface registers.
-        RestoreICCRegisters(crate::aarch64::gic::Error),
+        RestoreIccRegisters(crate::aarch64::gic::Error),
     }
 
     type Result<T> = result::Result<T, Error>;
 
-    pub struct KvmGICv3 {
-        /// The hypervisor agnostic device
+    pub struct KvmGicV3 {
+        /// The hypervisor agnostic device for the GicV3
         device: Arc<dyn hypervisor::Device>,
 
         /// Vector holding values of GICR_TYPER for each vCPU
@@ -58,7 +66,7 @@ pub mod kvm {
         vcpu_count: u64,
     }
 
-    #[derive(Serialize, Deserialize)]
+    #[derive(Versionize)]
     pub struct Gicv3State {
         dist: Vec<u32>,
         rdist: Vec<u32>,
@@ -67,52 +75,54 @@ pub mod kvm {
         gicd_ctlr: u32,
     }
 
-    impl KvmGICv3 {
+    impl VersionMapped for Gicv3State {}
+
+    impl KvmGicV3 {
         // Unfortunately bindgen omits defines that are based on other defines.
         // See arch/arm64/include/uapi/asm/kvm.h file from the linux kernel.
         pub const SZ_64K: u64 = 0x0001_0000;
-        const KVM_VGIC_V3_DIST_SIZE: u64 = KvmGICv3::SZ_64K;
-        const KVM_VGIC_V3_REDIST_SIZE: u64 = (2 * KvmGICv3::SZ_64K);
+        const KVM_VGIC_V3_DIST_SIZE: u64 = KvmGicV3::SZ_64K;
+        const KVM_VGIC_V3_REDIST_SIZE: u64 = (2 * KvmGicV3::SZ_64K);
 
         // Device trees specific constants
         pub const ARCH_GIC_V3_MAINT_IRQ: u32 = 9;
 
         /// Get the address of the GIC distributor.
         pub fn get_dist_addr() -> u64 {
-            layout::MAPPED_IO_START - KvmGICv3::KVM_VGIC_V3_DIST_SIZE
+            layout::MAPPED_IO_START - KvmGicV3::KVM_VGIC_V3_DIST_SIZE
         }
 
         /// Get the size of the GIC distributor.
         pub fn get_dist_size() -> u64 {
-            KvmGICv3::KVM_VGIC_V3_DIST_SIZE
+            KvmGicV3::KVM_VGIC_V3_DIST_SIZE
         }
 
         /// Get the address of the GIC redistributors.
         pub fn get_redists_addr(vcpu_count: u64) -> u64 {
-            KvmGICv3::get_dist_addr() - KvmGICv3::get_redists_size(vcpu_count)
+            KvmGicV3::get_dist_addr() - KvmGicV3::get_redists_size(vcpu_count)
         }
 
         /// Get the size of the GIC redistributors.
         pub fn get_redists_size(vcpu_count: u64) -> u64 {
-            vcpu_count * KvmGICv3::KVM_VGIC_V3_REDIST_SIZE
+            vcpu_count * KvmGicV3::KVM_VGIC_V3_REDIST_SIZE
         }
 
         /// Save the state of GIC.
         fn state(&self, gicr_typers: &[u64]) -> Result<Gicv3State> {
             // Flush redistributors pending tables to guest RAM.
-            save_pending_tables(&self.device()).map_err(Error::SavePendingTables)?;
+            save_pending_tables(self.device()).map_err(Error::SavePendingTables)?;
 
             let gicd_ctlr =
-                read_ctlr(&self.device()).map_err(Error::SaveDistributorCtrlRegisters)?;
+                read_ctlr(self.device()).map_err(Error::SaveDistributorCtrlRegisters)?;
 
             let dist_state =
-                get_dist_regs(&self.device()).map_err(Error::SaveDistributorRegisters)?;
+                get_dist_regs(self.device()).map_err(Error::SaveDistributorRegisters)?;
 
-            let rdist_state = get_redist_regs(&self.device(), &gicr_typers)
+            let rdist_state = get_redist_regs(self.device(), gicr_typers)
                 .map_err(Error::SaveRedistributorRegisters)?;
 
             let icc_state =
-                get_icc_regs(&self.device(), &gicr_typers).map_err(Error::SaveICCRegisters)?;
+                get_icc_regs(self.device(), gicr_typers).map_err(Error::SaveIccRegisters)?;
 
             Ok(Gicv3State {
                 dist: dist_state,
@@ -124,23 +134,23 @@ pub mod kvm {
 
         /// Restore the state of GIC.
         fn set_state(&mut self, gicr_typers: &[u64], state: &Gicv3State) -> Result<()> {
-            write_ctlr(&self.device(), state.gicd_ctlr)
+            write_ctlr(self.device(), state.gicd_ctlr)
                 .map_err(Error::RestoreDistributorCtrlRegisters)?;
 
-            set_dist_regs(&self.device(), &state.dist)
+            set_dist_regs(self.device(), &state.dist)
                 .map_err(Error::RestoreDistributorRegisters)?;
 
-            set_redist_regs(&self.device(), gicr_typers, &state.rdist)
+            set_redist_regs(self.device(), gicr_typers, &state.rdist)
                 .map_err(Error::RestoreRedistributorRegisters)?;
 
-            set_icc_regs(&self.device(), &gicr_typers, &state.icc)
-                .map_err(Error::RestoreICCRegisters)?;
+            set_icc_regs(self.device(), gicr_typers, &state.icc)
+                .map_err(Error::RestoreIccRegisters)?;
 
             Ok(())
         }
     }
 
-    impl GICDevice for KvmGICv3 {
+    impl GicDevice for KvmGicV3 {
         fn device(&self) -> &Arc<dyn hypervisor::Device> {
             &self.device
         }
@@ -150,7 +160,7 @@ pub mod kvm {
         }
 
         fn fdt_maint_irq(&self) -> u32 {
-            KvmGICv3::ARCH_GIC_V3_MAINT_IRQ
+            KvmGicV3::ARCH_GIC_V3_MAINT_IRQ
         }
 
         fn device_properties(&self) -> &[u64] {
@@ -161,7 +171,10 @@ pub mod kvm {
             self.vcpu_count
         }
 
-        fn set_gicr_typers(&mut self, gicr_typers: Vec<u64>) {
+        fn set_its_device(&mut self, _its_device: Option<Arc<dyn hypervisor::Device>>) {}
+
+        fn set_gicr_typers(&mut self, vcpu_states: &[CpuState]) {
+            let gicr_typers = construct_gicr_typers(vcpu_states);
             self.gicr_typers = gicr_typers;
         }
 
@@ -170,7 +183,7 @@ pub mod kvm {
         }
     }
 
-    impl KvmGICDevice for KvmGICv3 {
+    impl KvmGicDevice for KvmGicV3 {
         fn version() -> u32 {
             kvm_bindings::kvm_device_type_KVM_DEV_TYPE_ARM_VGIC_V3
         }
@@ -178,15 +191,15 @@ pub mod kvm {
         fn create_device(
             device: Arc<dyn hypervisor::Device>,
             vcpu_count: u64,
-        ) -> Box<dyn GICDevice> {
-            Box::new(KvmGICv3 {
+        ) -> Box<dyn GicDevice> {
+            Box::new(KvmGicV3 {
                 device,
                 gicr_typers: vec![0; vcpu_count.try_into().unwrap()],
                 properties: [
-                    KvmGICv3::get_dist_addr(),
-                    KvmGICv3::get_dist_size(),
-                    KvmGICv3::get_redists_addr(vcpu_count),
-                    KvmGICv3::get_redists_size(vcpu_count),
+                    KvmGicV3::get_dist_addr(),
+                    KvmGicV3::get_dist_size(),
+                    KvmGicV3::get_redists_addr(vcpu_count),
+                    KvmGicV3::get_redists_size(vcpu_count),
                 ],
                 vcpu_count,
             })
@@ -194,7 +207,7 @@ pub mod kvm {
 
         fn init_device_attributes(
             _vm: &Arc<dyn hypervisor::Vm>,
-            gic_device: &dyn GICDevice,
+            gic_device: &mut dyn GicDevice,
         ) -> crate::aarch64::gic::Result<()> {
             /* Setting up the distributor attribute.
              We are placing the GIC below 1GB so we need to substract the size of the distributor.
@@ -203,7 +216,7 @@ pub mod kvm {
                 gic_device.device(),
                 kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ADDR,
                 u64::from(kvm_bindings::KVM_VGIC_V3_ADDR_TYPE_DIST),
-                &KvmGICv3::get_dist_addr() as *const u64 as u64,
+                &KvmGicV3::get_dist_addr() as *const u64 as u64,
                 0,
             )?;
 
@@ -214,7 +227,7 @@ pub mod kvm {
                 gic_device.device(),
                 kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ADDR,
                 u64::from(kvm_bindings::KVM_VGIC_V3_ADDR_TYPE_REDIST),
-                &KvmGICv3::get_redists_addr(gic_device.vcpu_count()) as *const u64 as u64,
+                &KvmGicV3::get_redists_addr(gic_device.vcpu_count()) as *const u64 as u64,
                 0,
             )?;
 
@@ -223,53 +236,26 @@ pub mod kvm {
     }
 
     pub const GIC_V3_SNAPSHOT_ID: &str = "gic-v3";
-    impl Snapshottable for KvmGICv3 {
+    impl Snapshottable for KvmGicV3 {
         fn id(&self) -> String {
             GIC_V3_SNAPSHOT_ID.to_string()
         }
 
         fn snapshot(&mut self) -> std::result::Result<Snapshot, MigratableError> {
             let gicr_typers = self.gicr_typers.clone();
-            let snapshot = serde_json::to_vec(&self.state(&gicr_typers).unwrap())
-                .map_err(|e| MigratableError::Snapshot(e.into()))?;
-
-            let mut gic_v3_snapshot = Snapshot::new(self.id().as_str());
-            gic_v3_snapshot.add_data_section(SnapshotDataSection {
-                id: format!("{}-section", self.id()),
-                snapshot,
-            });
-
-            Ok(gic_v3_snapshot)
+            Snapshot::new_from_versioned_state(&self.id(), &self.state(&gicr_typers).unwrap())
         }
 
         fn restore(&mut self, snapshot: Snapshot) -> std::result::Result<(), MigratableError> {
-            if let Some(gic_v3_section) = snapshot
-                .snapshot_data
-                .get(&format!("{}-section", self.id()))
-            {
-                let gic_v3_state = match serde_json::from_slice(&gic_v3_section.snapshot) {
-                    Ok(state) => state,
-                    Err(error) => {
-                        return Err(MigratableError::Restore(anyhow!(
-                            "Could not deserialize GICv3 {}",
-                            error
-                        )))
-                    }
-                };
-
-                let gicr_typers = self.gicr_typers.clone();
-                return self.set_state(&gicr_typers, &gic_v3_state).map_err(|e| {
+            let gicr_typers = self.gicr_typers.clone();
+            self.set_state(&gicr_typers, &snapshot.to_versioned_state(&self.id())?)
+                .map_err(|e| {
                     MigratableError::Restore(anyhow!("Could not restore GICv3 state {:?}", e))
-                });
-            }
-
-            Err(MigratableError::Restore(anyhow!(
-                "Could not find GICv3 snapshot section"
-            )))
+                })
         }
     }
 
-    impl Pausable for KvmGICv3 {}
-    impl Transportable for KvmGICv3 {}
-    impl Migratable for KvmGICv3 {}
+    impl Pausable for KvmGicV3 {}
+    impl Transportable for KvmGicV3 {}
+    impl Migratable for KvmGicV3 {}
 }

arch/src/aarch64/gic/gicv3_its.rs

@@ -1,21 +1,153 @@
-// Copyright 2020 ARM Limited
+// Copyright 2021 Arm Limited (or its affiliates). All rights reserved.
 // SPDX-License-Identifier: Apache-2.0
+//
+// This file implements the GicV3 device with ITS (Virtual Interrupt Translation Service).
 
 pub mod kvm {
+    use crate::aarch64::gic::dist_regs::{get_dist_regs, read_ctlr, set_dist_regs, write_ctlr};
+    use crate::aarch64::gic::icc_regs::{get_icc_regs, set_icc_regs};
+    use crate::aarch64::gic::redist_regs::{
+        construct_gicr_typers, get_redist_regs, set_redist_regs,
+    };
+
+    use crate::aarch64::gic::gicv3::kvm::KvmGicV3;
+    use crate::aarch64::gic::kvm::{save_pending_tables, KvmGicDevice};
+    use crate::aarch64::gic::GicDevice;
+    use anyhow::anyhow;
+    use hypervisor::kvm::kvm_bindings;
+    use hypervisor::CpuState;
     use std::any::Any;
     use std::convert::TryInto;
     use std::sync::Arc;
     use std::{boxed::Box, result};
-    type Result<T> = result::Result<T, Error>;
-    use crate::aarch64::gic::gicv3::kvm::KvmGICv3;
-    use crate::aarch64::gic::kvm::KvmGICDevice;
-    use crate::aarch64::gic::{Error, GICDevice};
-    use hypervisor::kvm::kvm_bindings;
+    use versionize::{VersionMap, Versionize, VersionizeResult};
+    use versionize_derive::Versionize;
+    use vm_migration::{
+        Migratable, MigratableError, Pausable, Snapshot, Snapshottable, Transportable,
+        VersionMapped,
+    };
 
-    pub struct KvmGICv3ITS {
-        /// The hypervisor agnostic device
+    const GITS_CTLR: u32 = 0x0000;
+    const GITS_IIDR: u32 = 0x0004;
+    const GITS_CBASER: u32 = 0x0080;
+    const GITS_CWRITER: u32 = 0x0088;
+    const GITS_CREADR: u32 = 0x0090;
+    const GITS_BASER: u32 = 0x0100;
+
+    /// Errors thrown while saving/restoring the GICv3ITS.
+    #[derive(Debug)]
+    pub enum Error {
+        /// Error in saving RDIST pending tables into guest RAM.
+        SavePendingTables(crate::aarch64::gic::Error),
+        /// Error in saving GIC distributor registers.
+        SaveDistributorRegisters(crate::aarch64::gic::Error),
+        /// Error in restoring GIC distributor registers.
+        RestoreDistributorRegisters(crate::aarch64::gic::Error),
+        /// Error in saving GIC distributor control registers.
+        SaveDistributorCtrlRegisters(crate::aarch64::gic::Error),
+        /// Error in restoring GIC distributor control registers.
+        RestoreDistributorCtrlRegisters(crate::aarch64::gic::Error),
+        /// Error in saving GIC redistributor registers.
+        SaveRedistributorRegisters(crate::aarch64::gic::Error),
+        /// Error in restoring GIC redistributor registers.
+        RestoreRedistributorRegisters(crate::aarch64::gic::Error),
+        /// Error in saving GIC CPU interface registers.
+        SaveIccRegisters(crate::aarch64::gic::Error),
+        /// Error in restoring GIC CPU interface registers.
+        RestoreIccRegisters(crate::aarch64::gic::Error),
+        /// Error in saving GICv3ITS IIDR register.
+        SaveITSIIDR(crate::aarch64::gic::Error),
+        /// Error in restoring GICv3ITS IIDR register.
+        RestoreITSIIDR(crate::aarch64::gic::Error),
+        /// Error in saving GICv3ITS CBASER register.
+        SaveITSCBASER(crate::aarch64::gic::Error),
+        /// Error in restoring GICv3ITS CBASER register.
+        RestoreITSCBASER(crate::aarch64::gic::Error),
+        /// Error in saving GICv3ITS CREADR register.
+        SaveITSCREADR(crate::aarch64::gic::Error),
+        /// Error in restoring GICv3ITS CREADR register.
+        RestoreITSCREADR(crate::aarch64::gic::Error),
+        /// Error in saving GICv3ITS CWRITER register.
+        SaveITSCWRITER(crate::aarch64::gic::Error),
+        /// Error in restoring GICv3ITS CWRITER register.
+        RestoreITSCWRITER(crate::aarch64::gic::Error),
+        /// Error in saving GICv3ITS BASER register.
+        SaveITSBASER(crate::aarch64::gic::Error),
+        /// Error in restoring GICv3ITS BASER register.
+        RestoreITSBASER(crate::aarch64::gic::Error),
+        /// Error in saving GICv3ITS CTLR register.
+        SaveITSCTLR(crate::aarch64::gic::Error),
+        /// Error in restoring GICv3ITS CTLR register.
+        RestoreITSCTLR(crate::aarch64::gic::Error),
+        /// Error in saving GICv3ITS restore tables.
+        SaveITSTables(crate::aarch64::gic::Error),
+        /// Error in restoring GICv3ITS restore tables.
+        RestoreITSTables(crate::aarch64::gic::Error),
+    }
+
+    type Result<T> = result::Result<T, Error>;
+
+    /// Access an ITS device attribute.
+    ///
+    /// This is a helper function to get/set the ITS device attribute depending
+    /// the bool parameter `set` provided.
+    pub fn gicv3_its_attr_access(
+        its_device: &Arc<dyn hypervisor::Device>,
+        group: u32,
+        attr: u32,
+        val: &u64,
+        set: bool,
+    ) -> crate::aarch64::gic::Result<()> {
+        let mut gicv3_its_attr = kvm_bindings::kvm_device_attr {
+            group,
+            attr: attr as u64,
+            addr: val as *const u64 as u64,
+            flags: 0,
+        };
+        if set {
+            its_device
+                .set_device_attr(&gicv3_its_attr)
+                .map_err(crate::aarch64::gic::Error::SetDeviceAttribute)?;
+        } else {
+            its_device
+                .get_device_attr(&mut gicv3_its_attr)
+                .map_err(crate::aarch64::gic::Error::GetDeviceAttribute)?;
+        }
+        Ok(())
+    }
+
+    /// Function that saves/restores ITS tables into guest RAM.
+    ///
+    /// The tables get flushed to guest RAM whenever the VM gets stopped.
+    pub fn gicv3_its_tables_access(
+        its_device: &Arc<dyn hypervisor::Device>,
+        save: bool,
+    ) -> crate::aarch64::gic::Result<()> {
+        let attr: u64;
+        if save {
+            attr = u64::from(kvm_bindings::KVM_DEV_ARM_ITS_SAVE_TABLES);
+        } else {
+            attr = u64::from(kvm_bindings::KVM_DEV_ARM_ITS_RESTORE_TABLES);
+        }
+
+        let init_gic_attr = kvm_bindings::kvm_device_attr {
+            group: kvm_bindings::KVM_DEV_ARM_VGIC_GRP_CTRL,
+            attr,
+            addr: 0,
+            flags: 0,
+        };
+        its_device
+            .set_device_attr(&init_gic_attr)
+            .map_err(crate::aarch64::gic::Error::SetDeviceAttribute)
+    }
+
+    pub struct KvmGicV3Its {
+        /// The hypervisor agnostic device for the GicV3
         device: Arc<dyn hypervisor::Device>,
 
+        /// The hypervisor agnostic device for the Its device
+        its_device: Option<Arc<dyn hypervisor::Device>>,
+
         /// Vector holding values of GICR_TYPER for each vCPU
         gicr_typers: Vec<u64>,
 
@@ -29,23 +161,219 @@ pub mod kvm {
         vcpu_count: u64,
     }
 
-    impl KvmGICv3ITS {
-        const KVM_VGIC_V3_ITS_SIZE: u64 = (2 * KvmGICv3::SZ_64K);
+    #[derive(Versionize)]
+    pub struct Gicv3ItsState {
+        dist: Vec<u32>,
+        rdist: Vec<u32>,
+        icc: Vec<u32>,
+        // special register that enables interrupts and affinity routing
+        gicd_ctlr: u32,
+        its_ctlr: u64,
+        its_iidr: u64,
+        its_cbaser: u64,
+        its_cwriter: u64,
+        its_creadr: u64,
+        its_baser: [u64; 8],
+    }
+
+    impl VersionMapped for Gicv3ItsState {}
+
+    impl KvmGicV3Its {
+        const KVM_VGIC_V3_ITS_SIZE: u64 = (2 * KvmGicV3::SZ_64K);
 
         fn get_msi_size() -> u64 {
-            KvmGICv3ITS::KVM_VGIC_V3_ITS_SIZE
+            KvmGicV3Its::KVM_VGIC_V3_ITS_SIZE
         }
 
         fn get_msi_addr(vcpu_count: u64) -> u64 {
-            KvmGICv3::get_redists_addr(vcpu_count) - KvmGICv3ITS::get_msi_size()
+            KvmGicV3::get_redists_addr(vcpu_count) - KvmGicV3Its::get_msi_size()
+        }
+
+        /// Save the state of GICv3ITS.
+        fn state(&self, gicr_typers: &[u64]) -> Result<Gicv3ItsState> {
+            // Flush redistributors pending tables to guest RAM.
+            save_pending_tables(self.device()).map_err(Error::SavePendingTables)?;
+
+            let gicd_ctlr =
+                read_ctlr(self.device()).map_err(Error::SaveDistributorCtrlRegisters)?;
+
+            let dist_state =
+                get_dist_regs(self.device()).map_err(Error::SaveDistributorRegisters)?;
+
+            let rdist_state = get_redist_regs(self.device(), gicr_typers)
+                .map_err(Error::SaveRedistributorRegisters)?;
+
+            let icc_state =
+                get_icc_regs(self.device(), gicr_typers).map_err(Error::SaveIccRegisters)?;
+
+            // Save GICv3ITS registers
+            gicv3_its_tables_access(self.its_device().unwrap(), true)
+                .map_err(Error::SaveITSTables)?;
+
+            let its_baser_state: [u64; 8] = [0; 8];
+            for i in 0..8 {
+                gicv3_its_attr_access(
+                    self.its_device().unwrap(),
+                    kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                    GITS_BASER + i * 8,
+                    &its_baser_state[i as usize],
+                    false,
+                )
+                .map_err(Error::SaveITSBASER)?;
+            }
+
+            let its_ctlr_state: u64 = 0;
+            gicv3_its_attr_access(
+                self.its_device().unwrap(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                GITS_CTLR,
+                &its_ctlr_state,
+                false,
+            )
+            .map_err(Error::SaveITSCTLR)?;
+
+            let its_cbaser_state: u64 = 0;
+            gicv3_its_attr_access(
+                self.its_device().unwrap(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                GITS_CBASER,
+                &its_cbaser_state,
+                false,
+            )
+            .map_err(Error::SaveITSCBASER)?;
+
+            let its_creadr_state: u64 = 0;
+            gicv3_its_attr_access(
+                self.its_device().unwrap(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                GITS_CREADR,
+                &its_creadr_state,
+                false,
+            )
+            .map_err(Error::SaveITSCREADR)?;
+
+            let its_cwriter_state: u64 = 0;
+            gicv3_its_attr_access(
+                self.its_device().unwrap(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                GITS_CWRITER,
+                &its_cwriter_state,
+                false,
+            )
+            .map_err(Error::SaveITSCWRITER)?;
+
+            let its_iidr_state: u64 = 0;
+            gicv3_its_attr_access(
+                self.its_device().unwrap(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                GITS_IIDR,
+                &its_iidr_state,
+                false,
+            )
+            .map_err(Error::SaveITSIIDR)?;
+
+            Ok(Gicv3ItsState {
+                dist: dist_state,
+                rdist: rdist_state,
+                icc: icc_state,
+                gicd_ctlr,
+                its_ctlr: its_ctlr_state,
+                its_iidr: its_iidr_state,
+                its_cbaser: its_cbaser_state,
+                its_cwriter: its_cwriter_state,
+                its_creadr: its_creadr_state,
+                its_baser: its_baser_state,
+            })
+        }
+
+        /// Restore the state of GICv3ITS.
+        fn set_state(&mut self, gicr_typers: &[u64], state: &Gicv3ItsState) -> Result<()> {
+            write_ctlr(self.device(), state.gicd_ctlr)
+                .map_err(Error::RestoreDistributorCtrlRegisters)?;
+
+            set_dist_regs(self.device(), &state.dist)
+                .map_err(Error::RestoreDistributorRegisters)?;
+
+            set_redist_regs(self.device(), gicr_typers, &state.rdist)
+                .map_err(Error::RestoreRedistributorRegisters)?;
+
+            set_icc_regs(self.device(), gicr_typers, &state.icc)
+                .map_err(Error::RestoreIccRegisters)?;
+
+            //Restore GICv3ITS registers
+            gicv3_its_attr_access(
+                self.its_device().unwrap(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                GITS_IIDR,
+                &state.its_iidr,
+                true,
+            )
+            .map_err(Error::RestoreITSIIDR)?;
+
+            gicv3_its_attr_access(
+                self.its_device().unwrap(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                GITS_CBASER,
+                &state.its_cbaser,
+                true,
+            )
+            .map_err(Error::RestoreITSCBASER)?;
+
+            gicv3_its_attr_access(
+                self.its_device().unwrap(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                GITS_CREADR,
+                &state.its_creadr,
+                true,
+            )
+            .map_err(Error::RestoreITSCREADR)?;
+
+            gicv3_its_attr_access(
+                self.its_device().unwrap(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                GITS_CWRITER,
+                &state.its_cwriter,
+                true,
+            )
+            .map_err(Error::RestoreITSCWRITER)?;
+
+            for i in 0..8 {
+                gicv3_its_attr_access(
+                    self.its_device().unwrap(),
+                    kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                    GITS_BASER + i * 8,
+                    &state.its_baser[i as usize],
+                    true,
+                )
+                .map_err(Error::RestoreITSBASER)?;
+            }
+
+            // Restore ITS tables
+            gicv3_its_tables_access(self.its_device().unwrap(), false)
+                .map_err(Error::RestoreITSTables)?;
+
+            gicv3_its_attr_access(
+                self.its_device().unwrap(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                GITS_CTLR,
+                &state.its_ctlr,
+                true,
+            )
+            .map_err(Error::RestoreITSCTLR)?;
+
+            Ok(())
         }
     }
 
-    impl GICDevice for KvmGICv3ITS {
+    impl GicDevice for KvmGicV3Its {
         fn device(&self) -> &Arc<dyn hypervisor::Device> {
             &self.device
         }
 
+        fn its_device(&self) -> Option<&Arc<dyn hypervisor::Device>> {
+            self.its_device.as_ref()
+        }
+
         fn fdt_compatibility(&self) -> &str {
             "arm,gic-v3"
         }
@@ -59,7 +387,7 @@ pub mod kvm {
         }
 
         fn fdt_maint_irq(&self) -> u32 {
-            KvmGICv3::ARCH_GIC_V3_MAINT_IRQ
+            KvmGicV3::ARCH_GIC_V3_MAINT_IRQ
         }
 
         fn msi_properties(&self) -> &[u64] {
@@ -74,7 +402,12 @@ pub mod kvm {
             self.vcpu_count
         }
 
-        fn set_gicr_typers(&mut self, gicr_typers: Vec<u64>) {
+        fn set_its_device(&mut self, its_device: Option<Arc<dyn hypervisor::Device>>) {
+            self.its_device = its_device;
+        }
+
+        fn set_gicr_typers(&mut self, vcpu_states: &[CpuState]) {
+            let gicr_typers = construct_gicr_typers(vcpu_states);
             self.gicr_typers = gicr_typers;
         }
 
@@ -83,27 +416,28 @@ pub mod kvm {
         }
     }
 
-    impl KvmGICDevice for KvmGICv3ITS {
+    impl KvmGicDevice for KvmGicV3Its {
         fn version() -> u32 {
-            KvmGICv3::version()
+            KvmGicV3::version()
         }
 
         fn create_device(
             device: Arc<dyn hypervisor::Device>,
             vcpu_count: u64,
-        ) -> Box<dyn GICDevice> {
-            Box::new(KvmGICv3ITS {
+        ) -> Box<dyn GicDevice> {
+            Box::new(KvmGicV3Its {
                 device,
+                its_device: None,
                 gicr_typers: vec![0; vcpu_count.try_into().unwrap()],
                 gic_properties: [
-                    KvmGICv3::get_dist_addr(),
-                    KvmGICv3::get_dist_size(),
-                    KvmGICv3::get_redists_addr(vcpu_count),
-                    KvmGICv3::get_redists_size(vcpu_count),
+                    KvmGicV3::get_dist_addr(),
+                    KvmGicV3::get_dist_size(),
+                    KvmGicV3::get_redists_addr(vcpu_count),
+                    KvmGicV3::get_redists_size(vcpu_count),
                 ],
                 msi_properties: [
-                    KvmGICv3ITS::get_msi_addr(vcpu_count),
-                    KvmGICv3ITS::get_msi_size(),
+                    KvmGicV3Its::get_msi_addr(vcpu_count),
+                    KvmGicV3Its::get_msi_size(),
                 ],
                 vcpu_count,
             })
@@ -111,9 +445,9 @@ pub mod kvm {
 
         fn init_device_attributes(
             vm: &Arc<dyn hypervisor::Vm>,
-            gic_device: &dyn GICDevice,
-        ) -> Result<()> {
-            KvmGICv3::init_device_attributes(vm, gic_device)?;
+            gic_device: &mut dyn GicDevice,
+        ) -> crate::aarch64::gic::Result<()> {
+            KvmGicV3::init_device_attributes(vm, gic_device)?;
 
             let mut its_device = kvm_bindings::kvm_create_device {
                 type_: kvm_bindings::kvm_device_type_KVM_DEV_TYPE_ARM_VGIC_ITS,
@@ -123,13 +457,13 @@ pub mod kvm {
 
             let its_fd = vm
                 .create_device(&mut its_device)
-                .map_err(Error::CreateGIC)?;
+                .map_err(crate::aarch64::gic::Error::CreateGic)?;
 
             Self::set_device_attribute(
                 &its_fd,
                 kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ADDR,
                 u64::from(kvm_bindings::KVM_VGIC_ITS_ADDR_TYPE),
-                &KvmGICv3ITS::get_msi_addr(gic_device.vcpu_count()) as *const u64 as u64,
+                &KvmGicV3Its::get_msi_addr(gic_device.vcpu_count()) as *const u64 as u64,
                 0,
             )?;
 
@@ -141,7 +475,33 @@ pub mod kvm {
                 0,
             )?;
 
+            gic_device.set_its_device(Some(its_fd));
+
             Ok(())
         }
     }
+
+    pub const GIC_V3_ITS_SNAPSHOT_ID: &str = "gic-v3-its";
+    impl Snapshottable for KvmGicV3Its {
+        fn id(&self) -> String {
+            GIC_V3_ITS_SNAPSHOT_ID.to_string()
+        }
+
+        fn snapshot(&mut self) -> std::result::Result<Snapshot, MigratableError> {
+            let gicr_typers = self.gicr_typers.clone();
+            Snapshot::new_from_versioned_state(&self.id(), &self.state(&gicr_typers).unwrap())
+        }
+
+        fn restore(&mut self, snapshot: Snapshot) -> std::result::Result<(), MigratableError> {
+            let gicr_typers = self.gicr_typers.clone();
+            self.set_state(&gicr_typers, &snapshot.to_versioned_state(&self.id())?)
+                .map_err(|e| {
+                    MigratableError::Restore(anyhow!("Could not restore GICv3ITS state {:?}", e))
+                })
+        }
+    }
+
+    impl Pausable for KvmGicV3Its {}
+    impl Transportable for KvmGicV3Its {}
+    impl Migratable for KvmGicV3Its {}
 }

arch/src/aarch64/gic/mod.rs

@@ -1,3 +1,4 @@
+// Copyright 2021 Arm Limited (or its affiliates). All rights reserved.
 // Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -10,6 +11,7 @@ pub mod redist_regs;
 pub use self::dist_regs::{get_dist_regs, read_ctlr, set_dist_regs, write_ctlr};
 pub use self::icc_regs::{get_icc_regs, set_icc_regs};
 pub use self::redist_regs::{get_redist_regs, set_redist_regs};
+use hypervisor::CpuState;
 use std::any::Any;
 use std::result;
 use std::sync::Arc;
@@ -18,7 +20,7 @@ use std::sync::Arc;
 #[derive(Debug)]
 pub enum Error {
     /// Error while calling KVM ioctl for setting up the global interrupt controller.
-    CreateGIC(hypervisor::HypervisorVmError),
+    CreateGic(hypervisor::HypervisorVmError),
     /// Error while setting device attributes for the GIC.
     SetDeviceAttribute(hypervisor::HypervisorDeviceError),
     /// Error while getting device attributes for the GIC.
@@ -26,10 +28,15 @@ pub enum Error {
 }
 type Result<T> = result::Result<T, Error>;
 
-pub trait GICDevice: Send {
+pub trait GicDevice: Send {
     /// Returns the hypervisor agnostic Device of the GIC device
     fn device(&self) -> &Arc<dyn hypervisor::Device>;
 
+    /// Returns the hypervisor agnostic Device of the ITS device
+    fn its_device(&self) -> Option<&Arc<dyn hypervisor::Device>> {
+        None
+    }
+
     /// Returns the fdt compatibility property of the device
     fn fdt_compatibility(&self) -> &str;
 
@@ -57,24 +64,26 @@ pub trait GICDevice: Send {
         &[]
     }
 
+    fn set_its_device(&mut self, its_device: Option<Arc<dyn hypervisor::Device>>);
+
     /// Get the values of GICR_TYPER for each vCPU.
-    fn set_gicr_typers(&mut self, gicr_typers: Vec<u64>);
+    fn set_gicr_typers(&mut self, vcpu_states: &[CpuState]);
 
     /// Downcast the trait object to its concrete type.
     fn as_any_concrete_mut(&mut self) -> &mut dyn Any;
 }
 
 pub mod kvm {
-    use super::GICDevice;
+    use super::GicDevice;
     use super::Result;
-    use crate::aarch64::gic::gicv3_its::kvm::KvmGICv3ITS;
+    use crate::aarch64::gic::gicv3_its::kvm::KvmGicV3Its;
     use crate::layout;
     use hypervisor::kvm::kvm_bindings;
     use std::boxed::Box;
     use std::sync::Arc;
 
     /// Trait for GIC devices.
-    pub trait KvmGICDevice: Send + Sync + GICDevice {
+    pub trait KvmGicDevice: Send + Sync + GicDevice {
         /// Returns the GIC version of the device
         fn version() -> u32;
 
@@ -82,12 +91,12 @@ pub mod kvm {
         fn create_device(
             device: Arc<dyn hypervisor::Device>,
             vcpu_count: u64,
-        ) -> Box<dyn GICDevice>;
+        ) -> Box<dyn GicDevice>;
 
         /// Setup the device-specific attributes
         fn init_device_attributes(
             vm: &Arc<dyn hypervisor::Vm>,
-            gic_device: &dyn GICDevice,
+            gic_device: &mut dyn GicDevice,
         ) -> Result<()>;
 
         /// Initialize a GIC device
@@ -99,7 +108,7 @@ pub mod kvm {
             };
 
             vm.create_device(&mut gic_device)
-                .map_err(super::Error::CreateGIC)
+                .map_err(super::Error::CreateGic)
         }
 
         /// Set a GIC device attribute
@@ -111,10 +120,10 @@ pub mod kvm {
             flags: u32,
         ) -> Result<()> {
             let attr = kvm_bindings::kvm_device_attr {
+                flags,
                 group,
                 attr,
                 addr,
-                flags,
             };
             device
                 .set_device_attr(&attr)
@@ -132,10 +141,10 @@ pub mod kvm {
             flags: u32,
         ) -> Result<()> {
             let mut attr = kvm_bindings::kvm_device_attr {
+                flags,
                 group,
                 attr,
                 addr,
-                flags,
             };
             device
                 .get_device_attr(&mut attr)
@@ -145,11 +154,11 @@ pub mod kvm {
         }
 
         /// Finalize the setup of a GIC device
-        fn finalize_device(gic_device: &dyn GICDevice) -> Result<()> {
+        fn finalize_device(gic_device: &dyn GicDevice) -> Result<()> {
             /* We need to tell the kernel how many irqs to support with this vgic.
              * See the `layout` module for details.
              */
-            let nr_irqs: u32 = layout::IRQ_MAX - layout::IRQ_BASE + 1;
+            let nr_irqs: u32 = layout::IRQ_NUM;
             let nr_irqs_ptr = &nr_irqs as *const u32;
             Self::set_device_attribute(
                 gic_device.device(),
@@ -175,12 +184,12 @@ pub mod kvm {
 
         /// Method to initialize the GIC device
         #[allow(clippy::new_ret_no_self)]
-        fn new(vm: &Arc<dyn hypervisor::Vm>, vcpu_count: u64) -> Result<Box<dyn GICDevice>> {
+        fn new(vm: &Arc<dyn hypervisor::Vm>, vcpu_count: u64) -> Result<Box<dyn GicDevice>> {
             let vgic_fd = Self::init_device(vm)?;
 
-            let device = Self::create_device(vgic_fd, vcpu_count);
+            let mut device = Self::create_device(vgic_fd, vcpu_count);
 
-            Self::init_device_attributes(vm, &*device)?;
+            Self::init_device_attributes(vm, &mut *device)?;
 
             Self::finalize_device(&*device)?;
 
@@ -190,9 +199,9 @@ pub mod kvm {
 
     /// Create a GICv3-ITS device.
     ///
-    pub fn create_gic(vm: &Arc<dyn hypervisor::Vm>, vcpu_count: u64) -> Result<Box<dyn GICDevice>> {
+    pub fn create_gic(vm: &Arc<dyn hypervisor::Vm>, vcpu_count: u64) -> Result<Box<dyn GicDevice>> {
         debug!("creating a GICv3-ITS");
-        KvmGICv3ITS::new(vm, vcpu_count)
+        KvmGicV3Its::new(vm, vcpu_count)
     }
 
     /// Function that saves RDIST pending tables into guest RAM.

arch/src/aarch64/gic/redist_regs.rs

@@ -3,6 +3,7 @@
 
 use super::{Error, Result};
 use hypervisor::kvm::kvm_bindings::{kvm_device_attr, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS};
+use hypervisor::CpuState;
 use std::sync::Arc;
 
 // Relevant redistributor registers that we want to save/restore.
@@ -61,11 +62,11 @@ macro_rules! VGIC_RDIST_REG {
 
 // List with relevant distributor registers that we will be restoring.
 static VGIC_RDIST_REGS: &'static [RdistReg] = &[
-    VGIC_RDIST_REG!(GICR_CTLR, 4),
     VGIC_RDIST_REG!(GICR_STATUSR, 4),
     VGIC_RDIST_REG!(GICR_WAKER, 4),
     VGIC_RDIST_REG!(GICR_PROPBASER, 8),
     VGIC_RDIST_REG!(GICR_PENDBASER, 8),
+    VGIC_RDIST_REG!(GICR_CTLR, 4),
 ];
 
 // List with relevant distributor registers that we will be restoring.
@@ -141,14 +142,14 @@ pub fn get_redist_regs(gic: &Arc<dyn hypervisor::Device>, gicr_typer: &[u64]) ->
     let mut idx: usize = 0;
     access_redists_aux(
         gic,
-        &gicr_typer,
+        gicr_typer,
         &mut state,
         VGIC_RDIST_REGS,
         &mut idx,
         false,
     )?;
 
-    access_redists_aux(gic, &gicr_typer, &mut state, VGIC_SGI_REGS, &mut idx, false)?;
+    access_redists_aux(gic, gicr_typer, &mut state, VGIC_SGI_REGS, &mut idx, false)?;
     Ok(state)
 }
 
@@ -177,3 +178,34 @@ pub fn set_redist_regs(
         true,
     )
 }
+
+pub fn construct_gicr_typers(vcpu_states: &[CpuState]) -> Vec<u64> {
+    /* Pre-construct the GICR_TYPER:
+     * For our implementation:
+     *  Top 32 bits are the affinity value of the associated CPU
+     *  CommonLPIAff == 01 (redistributors with same Aff3 share LPI table)
+     *  Processor_Number == CPU index starting from 0
+     *  DPGS == 0 (GICR_CTLR.DPG* not supported)
+     *  Last == 1 if this is the last redistributor in a series of
+     *            contiguous redistributor pages
+     *  DirectLPI == 0 (direct injection of LPIs not supported)
+     *  VLPIS == 0 (virtual LPIs not supported)
+     *  PLPIS == 0 (physical LPIs not supported)
+     */
+    let mut gicr_typers: Vec<u64> = Vec::new();
+    for (index, state) in vcpu_states.iter().enumerate() {
+        let last = {
+            if index == vcpu_states.len() - 1 {
+                1
+            } else {
+                0
+            }
+        };
+        //calculate affinity
+        let mut cpu_affid = state.mpidr & 1095233437695;
+        cpu_affid = ((cpu_affid & 0xFF00000000) >> 8) | (cpu_affid & 0xFFFFFF);
+        gicr_typers.push((cpu_affid << 32) | (1 << 24) | (index as u64) << 8 | (last << 4));
+    }
+
+    gicr_typers
+}

arch/src/aarch64/layout.rs

@@ -19,15 +19,14 @@
 // memory)   |                                                               |
 //           |                            DRAM                               |
 //           |                                                               |
-// 2GB       +---------------------------------------------------------------+
 //           |                                                               |
-//           |                           Reserved                            |
 //           |                                                               |
-// 1G+256M   +---------------------------------------------------------------+
+// 1GB       +---------------------------------------------------------------+
 //           |                                                               |
 //           |                        PCI MMCONFIG space                     |
 //           |                                                               |
-// 1GB       +---------------------------------------------------------------+
+// 768 M     +---------------------------------------------------------------+
+//           |                                                               |
 //           |                                                               |
 //           |                           PCI MMIO space                      |
 //           |                                                               |
@@ -36,8 +35,10 @@
 //           |                        Legacy devices space                   |
 //           |                                                               |
 // 144 M     +---------------------------------------------------------------|
-//           |                                                               |
 //           |                    Reserved (now GIC is here)                 |
+// 64  M     +---------------------------------------------------------------+
+//           |                                                               |
+//           |                          UEFI space                           |
 //           |                                                               |
 // 0GB       +---------------------------------------------------------------+
 //
@@ -45,42 +46,63 @@
 
 use vm_memory::GuestAddress;
 
+/// 0x0 ~ 0x40_0000 (4 MiB) is reserved to UEFI
+/// UEFI binary size is required less than 3 MiB, reserving 4 MiB is enough.
+pub const UEFI_START: u64 = 0x0;
+pub const MEM_UEFI_START: GuestAddress = GuestAddress(0);
+pub const UEFI_SIZE: u64 = 0x040_0000;
+
 /// Below this address will reside the GIC, above this address will reside the MMIO devices.
 pub const MAPPED_IO_START: u64 = 0x0900_0000;
 
-/// Space 0x0900_0000 ~ 0x1000_0000 is reserved for legacy devices.
+/// Space 0x0900_0000 ~ 0x0905_0000 is reserved for legacy devices.
 pub const LEGACY_SERIAL_MAPPED_IO_START: u64 = 0x0900_0000;
 pub const LEGACY_RTC_MAPPED_IO_START: u64 = 0x0901_0000;
+pub const LEGACY_GPIO_MAPPED_IO_START: u64 = 0x0902_0000;
 
-/// Legacy space will be allocated at once whiling setting up legacy devices.
-pub const LEGACY_DEVICES_MAPPED_IO_SIZE: u64 = 0x0700_0000;
+/// Space 0x0905_0000 ~ 0x0906_0000 is reserved for pcie io address
+pub const MEM_PCI_IO_START: GuestAddress = GuestAddress(0x0905_0000);
+pub const MEM_PCI_IO_SIZE: u64 = 0x10000;
 
-/// Starting from 0x1000_0000 (256MiB), the 768MiB (ends at 1 GiB) is used for PCIE MMIO
+/// Starting from 0x1000_0000 (256MiB) to 0x3000_0000 (768MiB) is used for PCIE MMIO
 pub const MEM_32BIT_DEVICES_START: GuestAddress = GuestAddress(0x1000_0000);
-pub const MEM_32BIT_DEVICES_SIZE: u64 = 0x3000_0000;
+pub const MEM_32BIT_DEVICES_SIZE: u64 = 0x2000_0000;
 
 /// PCI MMCONFIG space (start: after the device space at 1 GiB, length: 256MiB)
-pub const PCI_MMCONFIG_START: GuestAddress = GuestAddress(0x4000_0000);
+pub const PCI_MMCONFIG_START: GuestAddress = GuestAddress(0x3000_0000);
 pub const PCI_MMCONFIG_SIZE: u64 = 256 << 20;
 
 /// Start of RAM on 64 bit ARM.
-pub const RAM_64BIT_START: u64 = 0x8000_0000;
+pub const RAM_64BIT_START: u64 = 0x4000_0000;
 
 /// Kernel command line maximum size.
 /// As per `arch/arm64/include/uapi/asm/setup.h`.
 pub const CMDLINE_MAX_SIZE: usize = 2048;
 
+/// FDT is at the beginning of RAM.
 /// Maximum size of the device tree blob as specified in https://www.kernel.org/doc/Documentation/arm64/booting.txt.
+pub const FDT_START: u64 = RAM_64BIT_START;
 pub const FDT_MAX_SIZE: usize = 0x20_0000;
 
+/// Put ACPI table above dtb
+pub const ACPI_START: u64 = RAM_64BIT_START + FDT_MAX_SIZE as u64;
+pub const ACPI_MAX_SIZE: usize = 0x20_0000;
+pub const RSDP_POINTER: GuestAddress = GuestAddress(ACPI_START);
+
+/// Kernel start after FDT and ACPI
+pub const KERNEL_START: u64 = ACPI_START + ACPI_MAX_SIZE as u64;
+
+/// Pci high memory base
+pub const PCI_HIGH_BASE: u64 = 0x80_0000_0000_u64;
+
 // As per virt/kvm/arm/vgic/vgic-kvm-device.c we need
 // the number of interrupts our GIC will support to be:
 // * bigger than 32
 // * less than 1023 and
 // * a multiple of 32.
-// We are setting up our interrupt controller to support a maximum of 128 interrupts.
-/// First usable interrupt on aarch64.
+// We are setting up our interrupt controller to support a maximum of 256 interrupts.
+/// First usable interrupt on aarch64
 pub const IRQ_BASE: u32 = 32;
 
-/// Last usable interrupt on aarch64.
-pub const IRQ_MAX: u32 = 159;
+/// Number of supported interrupts
+pub const IRQ_NUM: u32 = 256;

arch/src/aarch64/mod.rs

@@ -10,37 +10,44 @@ pub mod gic;
 pub mod layout;
 /// Logic for configuring aarch64 registers.
 pub mod regs;
+/// Module for loading UEFI binary.
+pub mod uefi;
 
-pub use self::fdt::DeviceInfoForFDT;
+pub use self::fdt::DeviceInfoForFdt;
 use crate::DeviceType;
+use crate::GuestMemoryMmap;
 use crate::RegionType;
-use aarch64::gic::GICDevice;
+use gic::GicDevice;
+use log::{log_enabled, Level};
 use std::collections::HashMap;
+use std::convert::TryInto;
 use std::ffi::CStr;
 use std::fmt::Debug;
 use std::sync::Arc;
 use vm_memory::{
-    Address, GuestAddress, GuestAddressSpace, GuestMemory, GuestMemoryAtomic, GuestMemoryMmap,
-    GuestUsize,
+    Address, GuestAddress, GuestAddressSpace, GuestMemory, GuestMemoryAtomic, GuestUsize,
 };
 
 /// Errors thrown while configuring aarch64 system.
 #[derive(Debug)]
 pub enum Error {
     /// Failed to create a FDT.
-    SetupFDT(fdt::Error),
+    SetupFdt,
+
+    /// Failed to write FDT to memory.
+    WriteFdtToMemory(fdt::Error),
 
     /// Failed to create a GIC.
-    SetupGIC(gic::Error),
+    SetupGic(gic::Error),
 
     /// Failed to compute the initramfs address.
     InitramfsAddress,
 
     /// Error configuring the general purpose registers
-    REGSConfiguration(regs::Error),
+    RegsConfiguration(regs::Error),
 
     /// Error configuring the MPIDR register
-    VcpuRegMPIDR(hypervisor::HypervisorCpuError),
+    VcpuRegMpidr(hypervisor::HypervisorCpuError),
 }
 
 impl From<Error> for super::Error {
@@ -71,76 +78,90 @@ pub fn configure_vcpu(
             kernel_entry_point.entry_addr.raw_value(),
             &vm_memory.memory(),
         )
-        .map_err(Error::REGSConfiguration)?;
+        .map_err(Error::RegsConfiguration)?;
     }
 
-    let mpidr = fd.read_mpidr().map_err(Error::VcpuRegMPIDR)?;
+    let mpidr = fd.read_mpidr().map_err(Error::VcpuRegMpidr)?;
     Ok(mpidr)
 }
 
 pub fn arch_memory_regions(size: GuestUsize) -> Vec<(GuestAddress, usize, RegionType)> {
-    let mut regions = Vec::new();
-    // 0 ~ 256 MiB: Reserved
-    regions.push((
-        GuestAddress(0),
-        layout::MEM_32BIT_DEVICES_START.0 as usize,
-        RegionType::Reserved,
-    ));
+    // Normally UEFI should be loaded to a flash area at the beginning of memory.
+    // But now flash memory type is not supported.
+    // As a workaround, we take 4 MiB memory from the main RAM for UEFI.
+    // As a result, the RAM that the guest can see is less than what has been
+    // assigned in command line, when ACPI and UEFI is enabled.
+    let ram_deduction = if cfg!(feature = "acpi") {
+        layout::UEFI_SIZE
+    } else {
+        0
+    };
 
-    // 256 MiB ~ 1 G: MMIO space
-    regions.push((
-        layout::MEM_32BIT_DEVICES_START,
-        layout::MEM_32BIT_DEVICES_SIZE as usize,
-        RegionType::SubRegion,
-    ));
-
-    // 1G  ~ 2G: reserved. The leading 256M for PCIe MMCONFIG space
-    regions.push((
-        layout::PCI_MMCONFIG_START,
-        (layout::RAM_64BIT_START - layout::PCI_MMCONFIG_START.0) as usize,
-        RegionType::Reserved,
-    ));
-
-    regions.push((
-        GuestAddress(layout::RAM_64BIT_START),
-        size as usize,
-        RegionType::Ram,
-    ));
-
-    regions
+    vec![
+        // 0 ~ 4 MiB: Reserved for UEFI space
+        #[cfg(feature = "acpi")]
+        (GuestAddress(0), layout::UEFI_SIZE as usize, RegionType::Ram),
+        #[cfg(not(feature = "acpi"))]
+        (
+            GuestAddress(0),
+            layout::UEFI_SIZE as usize,
+            RegionType::Reserved,
+        ),
+        // 4 MiB ~ 256 MiB: Gic and legacy devices
+        (
+            GuestAddress(layout::UEFI_SIZE),
+            (layout::MEM_32BIT_DEVICES_START.0 - layout::UEFI_SIZE) as usize,
+            RegionType::Reserved,
+        ),
+        // 256 MiB ~ 768 MiB: MMIO space
+        (
+            layout::MEM_32BIT_DEVICES_START,
+            layout::MEM_32BIT_DEVICES_SIZE as usize,
+            RegionType::SubRegion,
+        ),
+        // 768 MiB ~ 1 GiB: reserved. The leading 256M for PCIe MMCONFIG space
+        (
+            layout::PCI_MMCONFIG_START,
+            layout::PCI_MMCONFIG_SIZE as usize,
+            RegionType::Reserved,
+        ),
+        // 1 GiB ~ : Ram
+        (
+            GuestAddress(layout::RAM_64BIT_START),
+            (size - ram_deduction) as usize,
+            RegionType::Ram,
+        ),
+    ]
 }
 
 /// Configures the system and should be called once per vm before starting vcpu threads.
-///
-/// # Arguments
-///
-/// * `guest_mem` - The memory to be used by the guest.
-/// * `num_cpus` - Number of virtual CPUs the guest will have.
-#[allow(clippy::too_many_arguments)]
-pub fn configure_system<T: DeviceInfoForFDT + Clone + Debug, S: ::std::hash::BuildHasher>(
-    vm: &Arc<dyn hypervisor::Vm>,
+pub fn configure_system<T: DeviceInfoForFdt + Clone + Debug, S: ::std::hash::BuildHasher>(
     guest_mem: &GuestMemoryMmap,
     cmdline_cstring: &CStr,
-    vcpu_count: u64,
     vcpu_mpidr: Vec<u64>,
     device_info: &HashMap<(DeviceType, String), T, S>,
     initrd: &Option<super::InitramfsConfig>,
     pci_space_address: &(u64, u64),
-) -> super::Result<Box<dyn GICDevice>> {
-    let gic_device = gic::kvm::create_gic(vm, vcpu_count).map_err(Error::SetupGIC)?;
-
-    fdt::create_fdt(
+    gic_device: &dyn GicDevice,
+) -> super::Result<()> {
+    let fdt_final = fdt::create_fdt(
         guest_mem,
         cmdline_cstring,
         vcpu_mpidr,
         device_info,
-        &*gic_device,
+        gic_device,
         initrd,
         pci_space_address,
     )
-    .map_err(Error::SetupFDT)?;
+    .map_err(|_| Error::SetupFdt)?;
 
-    Ok(gic_device)
+    if log_enabled!(Level::Debug) {
+        fdt::print_fdt(&fdt_final);
+    }
+
+    fdt::write_fdt_to_memory(fdt_final, guest_mem).map_err(Error::WriteFdtToMemory)?;
+
+    Ok(())
 }
 
 /// Returns the memory address where the initramfs could be loaded.
@@ -149,8 +170,9 @@ pub fn initramfs_load_addr(
     initramfs_size: usize,
 ) -> super::Result<u64> {
     let round_to_pagesize = |size| (size + (super::PAGE_SIZE - 1)) & !(super::PAGE_SIZE - 1);
-    match GuestAddress(get_fdt_addr(&guest_mem))
-        .checked_sub(round_to_pagesize(initramfs_size) as u64)
+    match guest_mem
+        .last_addr()
+        .checked_sub(round_to_pagesize(initramfs_size) as u64 - 1)
     {
         Some(offset) => {
             if guest_mem.address_in_range(offset) {
@@ -165,41 +187,31 @@ pub fn initramfs_load_addr(
 
 /// Returns the memory address where the kernel could be loaded.
 pub fn get_kernel_start() -> u64 {
-    layout::RAM_64BIT_START
+    layout::KERNEL_START
+}
+
+///Return guest memory address where the uefi should be loaded.
+pub fn get_uefi_start() -> u64 {
+    layout::UEFI_START
 }
 
 // Auxiliary function to get the address where the device tree blob is loaded.
-fn get_fdt_addr(mem: &GuestMemoryMmap) -> u64 {
-    // If the memory allocated is smaller than the size allocated for the FDT,
-    // we return the start of the DRAM so that
-    // we allow the code to try and load the FDT.
-
-    if let Some(addr) = mem.last_addr().checked_sub(layout::FDT_MAX_SIZE as u64 - 1) {
-        if mem.address_in_range(addr) {
-            return addr.raw_value();
-        }
-    }
-
-    layout::RAM_64BIT_START
+fn get_fdt_addr() -> u64 {
+    layout::FDT_START
 }
 
 pub fn get_host_cpu_phys_bits() -> u8 {
-    // The value returned here is used to determine the physical address space size
-    // for a VM (IPA size).
-    // In recent kernel versions, the maximum IPA size supported by the host can be
-    // known by querying cap KVM_CAP_ARM_VM_IPA_SIZE. And the IPA size for a
-    // guest can be configured smaller.
-    // But in Cloud-Hypervisor we simply use the maximum value for the VM.
-    // Reference https://lwn.net/Articles/766767/.
-    //
-    // The correct way to query KVM_CAP_ARM_VM_IPA_SIZE is via rust-vmm/kvm-ioctls,
-    // which wraps all IOCTL's and provides easy interface to user hypervisors.
-    // For now the cap hasn't been supported. A separate patch will be submitted to
-    // rust-vmm to add it.
-    // So a hardcoded value is used here as a temporary solution.
-    // It will be replace once rust-vmm/kvm-ioctls is ready.
-    //
-    40
+    // A dummy hypervisor created only for querying the host IPA size and will
+    // be freed after the query.
+    let hv = hypervisor::new().unwrap();
+    let host_cpu_phys_bits = hv.get_host_ipa_limit().try_into().unwrap();
+    if host_cpu_phys_bits == 0 {
+        // Host kernel does not support `get_host_ipa_limit`,
+        // we return the default value 40 here.
+        40
+    } else {
+        host_cpu_phys_bits
+    }
 }
 
 #[cfg(test)]
@@ -209,38 +221,9 @@ mod tests {
     #[test]
     fn test_arch_memory_regions_dram() {
         let regions = arch_memory_regions((1usize << 32) as u64); //4GB
-        assert_eq!(4, regions.len());
-        assert_eq!(GuestAddress(layout::RAM_64BIT_START), regions[3].0);
-        assert_eq!(1usize << 32, regions[3].1);
-        assert_eq!(RegionType::Ram, regions[3].2);
-    }
-
-    #[test]
-    fn test_get_fdt_addr() {
-        let mut regions = Vec::new();
-
-        regions.push((
-            GuestAddress(layout::RAM_64BIT_START),
-            (layout::FDT_MAX_SIZE - 0x1000) as usize,
-        ));
-        let mem = GuestMemoryMmap::from_ranges(&regions).expect("Cannot initialize memory");
-        assert_eq!(get_fdt_addr(&mem), layout::RAM_64BIT_START);
-        regions.clear();
-
-        regions.push((
-            GuestAddress(layout::RAM_64BIT_START),
-            (layout::FDT_MAX_SIZE) as usize,
-        ));
-        let mem = GuestMemoryMmap::from_ranges(&regions).expect("Cannot initialize memory");
-        assert_eq!(get_fdt_addr(&mem), layout::RAM_64BIT_START);
-        regions.clear();
-
-        regions.push((
-            GuestAddress(layout::RAM_64BIT_START),
-            (layout::FDT_MAX_SIZE + 0x1000) as usize,
-        ));
-        let mem = GuestMemoryMmap::from_ranges(&regions).expect("Cannot initialize memory");
-        assert_eq!(get_fdt_addr(&mem), 0x1000 + layout::RAM_64BIT_START);
-        regions.clear();
+        assert_eq!(5, regions.len());
+        assert_eq!(GuestAddress(layout::RAM_64BIT_START), regions[4].0);
+        assert_eq!(1usize << 32, regions[4].1);
+        assert_eq!(RegionType::Ram, regions[4].2);
     }
 }

arch/src/aarch64/regs.rs

@@ -6,13 +6,13 @@
 // found in the THIRD-PARTY file.
 
 use super::get_fdt_addr;
+use crate::GuestMemoryMmap;
 use hypervisor::kvm::kvm_bindings::{
     kvm_regs, user_pt_regs, KVM_REG_ARM64, KVM_REG_ARM_CORE, KVM_REG_SIZE_U64,
 };
 use hypervisor::{arm64_core_reg_id, offset__of};
 use std::sync::Arc;
 use std::{mem, result};
-use vm_memory::GuestMemoryMmap;
 
 /// Errors thrown while setting aarch64 registers.
 #[derive(Debug)]
@@ -47,7 +47,7 @@ pub fn setup_regs(
     vcpu: &Arc<dyn hypervisor::Vcpu>,
     cpu_id: u8,
     boot_ip: u64,
-    mem: &GuestMemoryMmap,
+    _mem: &GuestMemoryMmap,
 ) -> Result<()> {
     let kreg_off = offset__of!(kvm_regs, regs);
 
@@ -73,7 +73,7 @@ pub fn setup_regs(
         let regs0 = offset__of!(user_pt_regs, regs) + kreg_off;
         vcpu.set_reg(
             arm64_core_reg_id!(KVM_REG_SIZE_U64, regs0),
-            get_fdt_addr(mem) as u64,
+            get_fdt_addr() as u64,
         )
         .map_err(Error::SetCoreRegister)?;
     }

arch/src/aarch64/uefi.rs

@@ -0,0 +1,43 @@
+// Copyright 2020 Arm Limited (or its affiliates). All rights reserved.
+
+use std::io::{Read, Seek, SeekFrom};
+use std::result;
+use vm_memory::{Bytes, GuestAddress, GuestMemory};
+
+/// Errors thrown while loading UEFI binary
+#[derive(Debug)]
+pub enum Error {
+    /// Unable to seek to UEFI image start.
+    SeekUefiStart,
+    /// Unable to seek to UEFI image end.
+    SeekUefiEnd,
+    /// UEFI image too big.
+    UefiTooBig,
+    /// Unable to read UEFI image
+    ReadUefiImage,
+}
+type Result<T> = result::Result<T, Error>;
+
+pub fn load_uefi<F, M: GuestMemory>(
+    guest_mem: &M,
+    guest_addr: GuestAddress,
+    uefi_image: &mut F,
+) -> Result<()>
+where
+    F: Read + Seek,
+{
+    let uefi_size = uefi_image
+        .seek(SeekFrom::End(0))
+        .map_err(|_| Error::SeekUefiEnd)? as usize;
+
+    // edk2 image on virtual platform is smaller than 3M
+    if uefi_size > 0x300000 {
+        return Err(Error::UefiTooBig);
+    }
+    uefi_image
+        .seek(SeekFrom::Start(0))
+        .map_err(|_| Error::SeekUefiStart)?;
+    guest_mem
+        .read_exact_from(guest_addr, uefi_image, uefi_size)
+        .map_err(|_| Error::ReadUefiImage)
+}

arch/src/lib.rs

@@ -6,35 +6,16 @@
 
 //! Implements platform specific functionality.
 //! Supported platforms: x86_64, aarch64.
-#![allow(
-    clippy::unreadable_literal,
-    clippy::redundant_static_lifetimes,
-    clippy::cast_lossless,
-    clippy::transmute_ptr_to_ptr,
-    clippy::cast_ptr_alignment
-)]
+#![allow(clippy::transmute_ptr_to_ptr, clippy::redundant_static_lifetimes)]
 
-extern crate anyhow;
-extern crate byteorder;
-extern crate hypervisor;
-extern crate libc;
 #[macro_use]
 extern crate log;
-#[cfg(feature = "acpi")]
-extern crate acpi_tables;
-extern crate arch_gen;
-extern crate linux_loader;
-extern crate serde;
-extern crate vm_memory;
-extern crate vm_migration;
-#[cfg(target_arch = "aarch64")]
-#[macro_use]
-extern crate serde_derive;
-extern crate serde_json;
 
 use std::fmt;
 use std::result;
 
+type GuestMemoryMmap = vm_memory::GuestMemoryMmap<vm_memory::bitmap::AtomicBitmap>;
+
 /// Type for returning error code.
 #[derive(Debug)]
 pub enum Error {
@@ -61,7 +42,7 @@ pub enum Error {
     /// Error writing module entry to guest memory.
     ModlistSetup(vm_memory::GuestMemoryError),
     /// RSDP Beyond Guest Memory
-    RSDPPastRamEnd,
+    RsdpPastRamEnd,
 }
 
 /// Type for returning public functions outcome.
@@ -92,9 +73,9 @@ pub mod aarch64;
 
 #[cfg(target_arch = "aarch64")]
 pub use aarch64::{
-    arch_memory_regions, configure_system, configure_vcpu, fdt::DeviceInfoForFDT,
-    get_host_cpu_phys_bits, get_kernel_start, initramfs_load_addr, layout,
-    layout::CMDLINE_MAX_SIZE, layout::IRQ_BASE, layout::IRQ_MAX, EntryPoint,
+    arch_memory_regions, configure_system, configure_vcpu, fdt::DeviceInfoForFdt,
+    get_host_cpu_phys_bits, get_kernel_start, get_uefi_start, initramfs_load_addr, layout,
+    layout::CMDLINE_MAX_SIZE, layout::IRQ_BASE, uefi, EntryPoint,
 };
 
 #[cfg(target_arch = "x86_64")]
@@ -102,9 +83,9 @@ pub mod x86_64;
 
 #[cfg(target_arch = "x86_64")]
 pub use x86_64::{
-    arch_memory_regions, configure_system, configure_vcpu, get_host_cpu_phys_bits,
-    initramfs_load_addr, layout, layout::CMDLINE_MAX_SIZE, layout::CMDLINE_START, regs,
-    BootProtocol, CpuidPatch, CpuidReg, EntryPoint,
+    arch_memory_regions, configure_system, configure_vcpu, generate_common_cpuid,
+    get_host_cpu_phys_bits, initramfs_load_addr, layout, layout::CMDLINE_MAX_SIZE,
+    layout::CMDLINE_START, regs, EntryPoint,
 };
 
 /// Safe wrapper for `sysconf(_SC_PAGESIZE)`.
@@ -133,7 +114,10 @@ pub enum DeviceType {
     Serial,
     /// Device Type: RTC.
     #[cfg(target_arch = "aarch64")]
-    RTC,
+    Rtc,
+    /// Device Type: GPIO.
+    #[cfg(target_arch = "aarch64")]
+    Gpio,
 }
 
 /// Default (smallest) memory page size for the supported architectures.
@@ -148,13 +132,13 @@ impl fmt::Display for DeviceType {
 /// Structure to describe MMIO device information
 #[derive(Clone, Debug)]
 #[cfg(target_arch = "aarch64")]
-pub struct MMIODeviceInfo {
+pub struct MmioDeviceInfo {
     pub addr: u64,
     pub irq: u32,
 }
 
 #[cfg(target_arch = "aarch64")]
-impl DeviceInfoForFDT for MMIODeviceInfo {
+impl DeviceInfoForFdt for MmioDeviceInfo {
     fn addr(&self) -> u64 {
         self.addr
     }

arch/src/x86_64/interrupts.rs

@@ -5,21 +5,13 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE-BSD-3-Clause file.
 
+use byteorder::{LittleEndian, ReadBytesExt, WriteBytesExt};
+use hypervisor::x86_64::LapicState;
 use std::io::Cursor;
 use std::mem;
 use std::result;
 use std::sync::Arc;
 
-use byteorder::{LittleEndian, ReadBytesExt, WriteBytesExt};
-
-use hypervisor::x86_64::LapicState;
-
-#[derive(Debug)]
-pub enum Error {
-    GetLapic(anyhow::Error),
-    SetLapic(anyhow::Error),
-}
-
 pub type Result<T> = result::Result<T, hypervisor::HypervisorCpuError>;
 
 // Defines poached from apicdef.h kernel header.
@@ -82,12 +74,7 @@ pub fn set_lint(vcpu: &Arc<dyn hypervisor::Vcpu>) -> Result<()> {
 }
 
 #[cfg(test)]
-#[cfg(feature = "kvm")]
 mod tests {
-
-    extern crate rand;
-    use self::rand::Rng;
-
     use super::*;
 
     const KVM_APIC_REG_SIZE: usize = 0x400;
@@ -111,8 +98,15 @@ mod tests {
 
     #[test]
     fn test_apic_delivery_mode() {
-        let mut rng = rand::thread_rng();
-        let mut v: Vec<u32> = (0..20).map(|_| rng.gen::<u32>()).collect();
+        let mut v: Vec<u32> = Vec::new();
+        v.resize(20, 0);
+
+        unsafe {
+            assert_eq!(
+                libc::getrandom(v.as_mut_ptr() as *mut _ as *mut libc::c_void, 80, 0),
+                80
+            );
+        }
 
         v.iter_mut()
             .for_each(|x| *x = set_apic_delivery_mode(*x, 2));

arch/src/x86_64/mod.rs

@@ -9,37 +9,47 @@
 use std::sync::Arc;
 pub mod interrupts;
 pub mod layout;
+mod mpspec;
 mod mptable;
 pub mod regs;
+use crate::GuestMemoryMmap;
 use crate::InitramfsConfig;
 use crate::RegionType;
-use hypervisor::{CpuId, CpuIdEntry, CPUID_FLAG_VALID_INDEX};
-use linux_loader::loader::bootparam::{boot_params, setup_header};
+use hypervisor::{CpuId, CpuIdEntry, HypervisorError, CPUID_FLAG_VALID_INDEX};
+use linux_loader::loader::bootparam::boot_params;
 use linux_loader::loader::elf::start_info::{
     hvm_memmap_table_entry, hvm_modlist_entry, hvm_start_info,
 };
+use std::collections::BTreeMap;
 use std::mem;
 use vm_memory::{
     Address, ByteValued, Bytes, GuestAddress, GuestAddressSpace, GuestMemory, GuestMemoryAtomic,
-    GuestMemoryMmap, GuestMemoryRegion, GuestUsize,
+    GuestMemoryRegion, GuestUsize,
 };
 mod smbios;
 use std::arch::x86_64;
+#[cfg(feature = "tdx")]
+pub mod tdx;
 
-#[derive(Debug, Copy, Clone)]
-pub enum BootProtocol {
-    LinuxBoot,
-    PvhBoot,
-}
+// CPUID feature bits
+const TSC_DEADLINE_TIMER_ECX_BIT: u8 = 24; // tsc deadline timer ecx bit.
+const HYPERVISOR_ECX_BIT: u8 = 31; // Hypervisor ecx bit.
+const MTRR_EDX_BIT: u8 = 12; // Hypervisor ecx bit.
 
-impl ::std::fmt::Display for BootProtocol {
-    fn fmt(&self, f: &mut ::std::fmt::Formatter) -> ::std::fmt::Result {
-        match self {
-            BootProtocol::LinuxBoot => write!(f, "Linux 64-bit boot protocol"),
-            BootProtocol::PvhBoot => write!(f, "PVH boot protocol"),
-        }
-    }
-}
+// KVM feature bits
+const KVM_FEATURE_ASYNC_PF_INT_BIT: u8 = 14;
+#[cfg(feature = "tdx")]
+const KVM_FEATURE_CLOCKSOURCE_BIT: u8 = 0;
+#[cfg(feature = "tdx")]
+const KVM_FEATURE_CLOCKSOURCE2_BIT: u8 = 3;
+#[cfg(feature = "tdx")]
+const KVM_FEATURE_CLOCKSOURCE_STABLE_BIT: u8 = 24;
+#[cfg(feature = "tdx")]
+const KVM_FEATURE_ASYNC_PF_BIT: u8 = 4;
+#[cfg(feature = "tdx")]
+const KVM_FEATURE_ASYNC_PF_VMEXIT_BIT: u8 = 10;
+#[cfg(feature = "tdx")]
+const KVM_FEATURE_STEAL_TIME_BIT: u8 = 5;
 
 #[derive(Debug, Copy, Clone)]
 /// Specifies the entry point address where the guest must start
@@ -48,10 +58,6 @@ impl ::std::fmt::Display for BootProtocol {
 pub struct EntryPoint {
     /// Address in guest memory where the guest must start execution
     pub entry_addr: GuestAddress,
-    /// Specifies which boot protocol to use
-    pub protocol: BootProtocol,
-    /// This field is used for bzImage to fill zero page
-    pub setup_header: Option<setup_header>,
 }
 
 const E820_RAM: u32 = 1;
@@ -79,7 +85,7 @@ impl SgxEpcSection {
 pub struct SgxEpcRegion {
     start: GuestAddress,
     size: GuestUsize,
-    epc_sections: Vec<SgxEpcSection>,
+    epc_sections: BTreeMap<String, SgxEpcSection>,
 }
 
 impl SgxEpcRegion {
@@ -87,7 +93,7 @@ impl SgxEpcRegion {
         SgxEpcRegion {
             start,
             size,
-            epc_sections: Vec::new(),
+            epc_sections: BTreeMap::new(),
         }
     }
     pub fn start(&self) -> GuestAddress {
@@ -96,11 +102,11 @@ impl SgxEpcRegion {
     pub fn size(&self) -> GuestUsize {
         self.size
     }
-    pub fn epc_sections(&self) -> &Vec<SgxEpcSection> {
+    pub fn epc_sections(&self) -> &BTreeMap<String, SgxEpcSection> {
         &self.epc_sections
     }
-    pub fn push(&mut self, epc_section: SgxEpcSection) {
-        self.epc_sections.push(epc_section);
+    pub fn insert(&mut self, id: String, epc_section: SgxEpcSection) {
+        self.epc_sections.insert(id, epc_section);
     }
 }
 
@@ -138,23 +144,20 @@ unsafe impl ByteValued for BootParamsWrapper {}
 
 #[derive(Debug)]
 pub enum Error {
-    /// Invalid e820 setup params.
-    E820Configuration,
-
     /// Error writing MP table to memory.
     MpTableSetup(mptable::Error),
 
     /// Error configuring the general purpose registers
-    REGSConfiguration(regs::Error),
+    RegsConfiguration(regs::Error),
 
     /// Error configuring the special registers
-    SREGSConfiguration(regs::Error),
+    SregsConfiguration(regs::Error),
 
     /// Error configuring the floating point related registers
-    FPUConfiguration(regs::Error),
+    FpuConfiguration(regs::Error),
 
     /// Error configuring the MSR registers
-    MSRSConfiguration(regs::Error),
+    MsrsConfiguration(regs::Error),
 
     /// Failed to set supported CPUs.
     SetSupportedCpusFailed(anyhow::Error),
@@ -173,6 +176,15 @@ pub enum Error {
 
     /// Missing SGX_LC CPU feature
     MissingSgxLaunchControlFeature,
+
+    /// Error getting supported CPUID through the hypervisor (kvm/mshv) API
+    CpuidGetSupported(HypervisorError),
+
+    /// Error populating CPUID with KVM HyperV emulation details
+    CpuidKvmHyperV(vmm_sys_util::fam::Error),
+
+    /// Error populating CPUID with CPU identification
+    CpuidIdentification(vmm_sys_util::fam::Error),
 }
 
 impl From<Error> for super::Error {
@@ -181,7 +193,7 @@ impl From<Error> for super::Error {
     }
 }
 
-#[allow(dead_code)]
+#[allow(dead_code, clippy::upper_case_acronyms)]
 #[derive(Copy, Clone)]
 pub enum CpuidReg {
     EAX,
@@ -326,6 +338,168 @@ impl CpuidPatch {
     }
 }
 
+pub fn generate_common_cpuid(
+    hypervisor: Arc<dyn hypervisor::Hypervisor>,
+    topology: Option<(u8, u8, u8)>,
+    sgx_epc_sections: Option<Vec<SgxEpcSection>>,
+    phys_bits: u8,
+    kvm_hyperv: bool,
+    #[cfg(feature = "tdx")] tdx_enabled: bool,
+) -> super::Result<CpuId> {
+    let cpuid_patches = vec![
+        // Patch tsc deadline timer bit
+        CpuidPatch {
+            function: 1,
+            index: 0,
+            flags_bit: None,
+            eax_bit: None,
+            ebx_bit: None,
+            ecx_bit: Some(TSC_DEADLINE_TIMER_ECX_BIT),
+            edx_bit: None,
+        },
+        // Patch hypervisor bit
+        CpuidPatch {
+            function: 1,
+            index: 0,
+            flags_bit: None,
+            eax_bit: None,
+            ebx_bit: None,
+            ecx_bit: Some(HYPERVISOR_ECX_BIT),
+            edx_bit: None,
+        },
+        // Enable MTRR feature
+        CpuidPatch {
+            function: 1,
+            index: 0,
+            flags_bit: None,
+            eax_bit: None,
+            ebx_bit: None,
+            ecx_bit: None,
+            edx_bit: Some(MTRR_EDX_BIT),
+        },
+    ];
+
+    // Supported CPUID
+    let mut cpuid = hypervisor.get_cpuid().map_err(Error::CpuidGetSupported)?;
+
+    CpuidPatch::patch_cpuid(&mut cpuid, cpuid_patches);
+
+    if let Some(t) = topology {
+        update_cpuid_topology(&mut cpuid, t.0, t.1, t.2);
+    }
+
+    if let Some(sgx_epc_sections) = sgx_epc_sections {
+        update_cpuid_sgx(&mut cpuid, sgx_epc_sections)?;
+    }
+
+    // Update some existing CPUID
+    for entry in cpuid.as_mut_slice().iter_mut() {
+        match entry.function {
+            // Set CPU physical bits
+            0x8000_0008 => {
+                entry.eax = (entry.eax & 0xffff_ff00) | (phys_bits as u32 & 0xff);
+            }
+            // Disable KVM_FEATURE_ASYNC_PF_INT
+            // This is required until we find out why the asynchronous page
+            // fault is generating unexpected behavior when using interrupt
+            // mechanism.
+            // TODO: Re-enable KVM_FEATURE_ASYNC_PF_INT (#2277)
+            0x4000_0001 => {
+                entry.eax &= !(1 << KVM_FEATURE_ASYNC_PF_INT_BIT);
+
+                // These features are not supported by TDX
+                #[cfg(feature = "tdx")]
+                if tdx_enabled {
+                    entry.eax &= !(1 << KVM_FEATURE_CLOCKSOURCE_BIT
+                        | 1 << KVM_FEATURE_CLOCKSOURCE2_BIT
+                        | 1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT
+                        | 1 << KVM_FEATURE_ASYNC_PF_BIT
+                        | 1 << KVM_FEATURE_ASYNC_PF_VMEXIT_BIT
+                        | 1 << KVM_FEATURE_STEAL_TIME_BIT)
+                }
+            }
+            _ => {}
+        }
+    }
+
+    // Copy CPU identification string
+    for i in 0x8000_0002..=0x8000_0004 {
+        cpuid.retain(|c| c.function != i);
+        let leaf = unsafe { std::arch::x86_64::__cpuid(i) };
+        cpuid
+            .push(CpuIdEntry {
+                function: i,
+                eax: leaf.eax,
+                ebx: leaf.ebx,
+                ecx: leaf.ecx,
+                edx: leaf.edx,
+                ..Default::default()
+            })
+            .map_err(Error::CpuidIdentification)?;
+    }
+
+    if kvm_hyperv {
+        // Remove conflicting entries
+        cpuid.retain(|c| c.function != 0x4000_0000);
+        cpuid.retain(|c| c.function != 0x4000_0001);
+        // See "Hypervisor Top Level Functional Specification" for details
+        // Compliance with "Hv#1" requires leaves up to 0x4000_000a
+        cpuid
+            .push(CpuIdEntry {
+                function: 0x40000000,
+                eax: 0x4000000a, // Maximum cpuid leaf
+                ebx: 0x756e694c, // "Linu"
+                ecx: 0x564b2078, // "x KV"
+                edx: 0x7648204d, // "M Hv"
+                ..Default::default()
+            })
+            .map_err(Error::CpuidKvmHyperV)?;
+        cpuid
+            .push(CpuIdEntry {
+                function: 0x40000001,
+                eax: 0x31237648, // "Hv#1"
+                ..Default::default()
+            })
+            .map_err(Error::CpuidKvmHyperV)?;
+        cpuid
+            .push(CpuIdEntry {
+                function: 0x40000002,
+                eax: 0x3839,  // "Build number"
+                ebx: 0xa0000, // "Version"
+                ..Default::default()
+            })
+            .map_err(Error::CpuidKvmHyperV)?;
+        cpuid
+            .push(CpuIdEntry {
+                function: 0x4000_0003,
+                eax: 1 << 1 // AccessPartitionReferenceCounter
+                   | 1 << 2 // AccessSynicRegs
+                   | 1 << 3 // AccessSyntheticTimerRegs
+                   | 1 << 9, // AccessPartitionReferenceTsc
+                edx: 1 << 3, // CPU dynamic partitioning
+                ..Default::default()
+            })
+            .map_err(Error::CpuidKvmHyperV)?;
+        cpuid
+            .push(CpuIdEntry {
+                function: 0x4000_0004,
+                eax: 1 << 5, // Recommend relaxed timing
+                ..Default::default()
+            })
+            .map_err(Error::CpuidKvmHyperV)?;
+        for i in 0x4000_0005..=0x4000_000a {
+            cpuid
+                .push(CpuIdEntry {
+                    function: i,
+                    ..Default::default()
+                })
+                .map_err(Error::CpuidKvmHyperV)?;
+        }
+    }
+
+    Ok(cpuid)
+}
+
 pub fn configure_vcpu(
     fd: &Arc<dyn hypervisor::Vcpu>,
     id: u8,
@@ -334,7 +508,7 @@ pub fn configure_vcpu(
     cpuid: CpuId,
     kvm_hyperv: bool,
 ) -> super::Result<()> {
-    // Per vCPU CPUID changes; common are handled via CpuManager::generate_common_cpuid()
+    // Per vCPU CPUID changes; common are handled via generate_common_cpuid()
     let mut cpuid = cpuid;
     CpuidPatch::set_cpuid_reg(&mut cpuid, 0xb, None, CpuidReg::EDX, u32::from(id));
     CpuidPatch::set_cpuid_reg(&mut cpuid, 0x1f, None, CpuidReg::EDX, u32::from(id));
@@ -346,20 +520,13 @@ pub fn configure_vcpu(
         fd.enable_hyperv_synic().unwrap();
     }
 
-    regs::setup_msrs(fd).map_err(Error::MSRSConfiguration)?;
+    regs::setup_msrs(fd).map_err(Error::MsrsConfiguration)?;
     if let Some(kernel_entry_point) = kernel_entry_point {
         // Safe to unwrap because this method is called after the VM is configured
-        regs::setup_regs(
-            fd,
-            kernel_entry_point.entry_addr.raw_value(),
-            layout::BOOT_STACK_POINTER.raw_value(),
-            layout::ZERO_PAGE_START.raw_value(),
-            kernel_entry_point.protocol,
-        )
-        .map_err(Error::REGSConfiguration)?;
-        regs::setup_fpu(fd).map_err(Error::FPUConfiguration)?;
-        regs::setup_sregs(&vm_memory.memory(), fd, kernel_entry_point.protocol)
-            .map_err(Error::SREGSConfiguration)?;
+        regs::setup_regs(fd, kernel_entry_point.entry_addr.raw_value())
+            .map_err(Error::RegsConfiguration)?;
+        regs::setup_fpu(fd).map_err(Error::FpuConfiguration)?;
+        regs::setup_sregs(&vm_memory.memory(), fd).map_err(Error::SregsConfiguration)?;
     }
     interrupts::set_lint(fd).map_err(|e| Error::LocalIntConfiguration(e.into()))?;
     Ok(())
@@ -424,12 +591,9 @@ pub fn arch_memory_regions(size: GuestUsize) -> Vec<(GuestAddress, usize, Region
 pub fn configure_system(
     guest_mem: &GuestMemoryMmap,
     cmdline_addr: GuestAddress,
-    cmdline_size: usize,
     initramfs: &Option<InitramfsConfig>,
     _num_cpus: u8,
-    setup_hdr: Option<setup_header>,
     rsdp_addr: Option<GuestAddress>,
-    boot_prot: BootProtocol,
     sgx_epc_region: Option<SgxEpcRegion>,
 ) -> super::Result<()> {
     let size = smbios::setup_smbios(guest_mem).map_err(Error::SmbiosSetup)?;
@@ -442,34 +606,17 @@ pub fn configure_system(
     // Check that the RAM is not smaller than the RSDP start address
     if let Some(rsdp_addr) = rsdp_addr {
         if rsdp_addr.0 > guest_mem.last_addr().0 {
-            return Err(super::Error::RSDPPastRamEnd);
+            return Err(super::Error::RsdpPastRamEnd);
         }
     }
 
-    match boot_prot {
-        BootProtocol::PvhBoot => {
-            configure_pvh(
-                guest_mem,
-                cmdline_addr,
-                initramfs,
-                rsdp_addr,
-                sgx_epc_region,
-            )?;
-        }
-        BootProtocol::LinuxBoot => {
-            configure_64bit_boot(
-                guest_mem,
-                cmdline_addr,
-                cmdline_size,
-                initramfs,
-                setup_hdr,
-                rsdp_addr,
-                sgx_epc_region,
-            )?;
-        }
-    }
-
-    Ok(())
+    configure_pvh(
+        guest_mem,
+        cmdline_addr,
+        initramfs,
+        rsdp_addr,
+        sgx_epc_region,
+    )
 }
 
 fn configure_pvh(
@@ -612,121 +759,6 @@ fn add_memmap_entry(memmap: &mut Vec<hvm_memmap_table_entry>, addr: u64, size: u
     });
 }
 
-fn configure_64bit_boot(
-    guest_mem: &GuestMemoryMmap,
-    cmdline_addr: GuestAddress,
-    cmdline_size: usize,
-    initramfs: &Option<InitramfsConfig>,
-    setup_hdr: Option<setup_header>,
-    rsdp_addr: Option<GuestAddress>,
-    sgx_epc_region: Option<SgxEpcRegion>,
-) -> super::Result<()> {
-    const KERNEL_BOOT_FLAG_MAGIC: u16 = 0xaa55;
-    const KERNEL_HDR_MAGIC: u32 = 0x53726448;
-    const KERNEL_LOADER_OTHER: u8 = 0xff;
-    const KERNEL_MIN_ALIGNMENT_BYTES: u32 = 0x1000000; // Must be non-zero.
-
-    let mut params: BootParamsWrapper = BootParamsWrapper(boot_params::default());
-
-    if let Some(hdr) = setup_hdr {
-        // We should use the header if the loader provides one (e.g. from a bzImage).
-        params.0.hdr = hdr;
-    } else {
-        params.0.hdr.boot_flag = KERNEL_BOOT_FLAG_MAGIC;
-        params.0.hdr.header = KERNEL_HDR_MAGIC;
-        params.0.hdr.kernel_alignment = KERNEL_MIN_ALIGNMENT_BYTES;
-    };
-
-    // Common bootparams settings
-    if params.0.hdr.type_of_loader == 0 {
-        params.0.hdr.type_of_loader = KERNEL_LOADER_OTHER;
-    }
-    params.0.hdr.cmd_line_ptr = cmdline_addr.raw_value() as u32;
-    params.0.hdr.cmdline_size = cmdline_size as u32;
-
-    if let Some(initramfs_config) = initramfs {
-        params.0.hdr.ramdisk_image = initramfs_config.address.raw_value() as u32;
-        params.0.hdr.ramdisk_size = initramfs_config.size as u32;
-    }
-
-    add_e820_entry(&mut params.0, 0, layout::EBDA_START.raw_value(), E820_RAM)?;
-
-    let mem_end = guest_mem.last_addr();
-    if mem_end < layout::MEM_32BIT_RESERVED_START {
-        add_e820_entry(
-            &mut params.0,
-            layout::HIGH_RAM_START.raw_value(),
-            mem_end.unchecked_offset_from(layout::HIGH_RAM_START) + 1,
-            E820_RAM,
-        )?;
-    } else {
-        add_e820_entry(
-            &mut params.0,
-            layout::HIGH_RAM_START.raw_value(),
-            layout::MEM_32BIT_RESERVED_START.unchecked_offset_from(layout::HIGH_RAM_START),
-            E820_RAM,
-        )?;
-        if mem_end > layout::RAM_64BIT_START {
-            add_e820_entry(
-                &mut params.0,
-                layout::RAM_64BIT_START.raw_value(),
-                mem_end.unchecked_offset_from(layout::RAM_64BIT_START) + 1,
-                E820_RAM,
-            )?;
-        }
-    }
-
-    add_e820_entry(
-        &mut params.0,
-        layout::PCI_MMCONFIG_START.0,
-        layout::PCI_MMCONFIG_SIZE,
-        E820_RESERVED,
-    )?;
-
-    if let Some(sgx_epc_region) = sgx_epc_region {
-        add_e820_entry(
-            &mut params.0,
-            sgx_epc_region.start().raw_value(),
-            sgx_epc_region.size() as u64,
-            E820_RESERVED,
-        )?;
-    }
-
-    if let Some(rsdp_addr) = rsdp_addr {
-        params.0.acpi_rsdp_addr = rsdp_addr.0;
-    }
-
-    let zero_page_addr = layout::ZERO_PAGE_START;
-    guest_mem
-        .checked_offset(zero_page_addr, mem::size_of::<boot_params>())
-        .ok_or(super::Error::ZeroPagePastRamEnd)?;
-    guest_mem
-        .write_obj(params, zero_page_addr)
-        .map_err(super::Error::ZeroPageSetup)?;
-
-    Ok(())
-}
-
-/// Add an e820 region to the e820 map.
-/// Returns Ok(()) if successful, or an error if there is no space left in the map.
-fn add_e820_entry(
-    params: &mut boot_params,
-    addr: u64,
-    size: u64,
-    mem_type: u32,
-) -> Result<(), Error> {
-    if params.e820_entries >= params.e820_table.len() as u8 {
-        return Err(Error::E820Configuration);
-    }
-
-    params.e820_table[params.e820_entries as usize].addr = addr;
-    params.e820_table[params.e820_entries as usize].size = size;
-    params.e820_table[params.e820_entries as usize].type_ = mem_type;
-    params.e820_entries += 1;
-
-    Ok(())
-}
-
 /// Returns the memory address where the initramfs could be loaded.
 pub fn initramfs_load_addr(
     guest_mem: &GuestMemoryMmap,
@@ -773,7 +805,7 @@ pub fn get_host_cpu_phys_bits() -> u8 {
     }
 }
 
-pub fn update_cpuid_topology(
+fn update_cpuid_topology(
     cpuid: &mut CpuId,
     threads_per_core: u8,
     cores_per_die: u8,
@@ -838,7 +870,7 @@ pub fn update_cpuid_topology(
 
 // The goal is to update the CPUID sub-leaves to reflect the number of EPC
 // sections exposed to the guest.
-pub fn update_cpuid_sgx(cpuid: &mut CpuId, epc_sections: Vec<SgxEpcSection>) -> Result<(), Error> {
+fn update_cpuid_sgx(cpuid: &mut CpuId, epc_sections: Vec<SgxEpcSection>) -> Result<(), Error> {
     // Something's wrong if there's no EPC section.
     if epc_sections.is_empty() {
         return Err(Error::NoSgxEpcSection);
@@ -885,7 +917,6 @@ pub fn update_cpuid_sgx(cpuid: &mut CpuId, epc_sections: Vec<SgxEpcSection>) ->
 #[cfg(test)]
 mod tests {
     use super::*;
-    use linux_loader::loader::bootparam::boot_e820_entry;
 
     #[test]
     fn regions_lt_4gb() {
@@ -910,12 +941,9 @@ mod tests {
         let config_err = configure_system(
             &gm,
             GuestAddress(0),
-            0,
             &None,
             1,
-            None,
             Some(layout::RSDP_POINTER),
-            BootProtocol::LinuxBoot,
             None,
         );
         assert!(config_err.is_err());
@@ -929,31 +957,8 @@ mod tests {
             .map(|r| (r.0, r.1))
             .collect();
         let gm = GuestMemoryMmap::from_ranges(&ram_regions).unwrap();
-        configure_system(
-            &gm,
-            GuestAddress(0),
-            0,
-            &None,
-            no_vcpus,
-            None,
-            None,
-            BootProtocol::LinuxBoot,
-            None,
-        )
-        .unwrap();
 
-        configure_system(
-            &gm,
-            GuestAddress(0),
-            0,
-            &None,
-            no_vcpus,
-            None,
-            None,
-            BootProtocol::PvhBoot,
-            None,
-        )
-        .unwrap();
+        configure_system(&gm, GuestAddress(0), &None, no_vcpus, None, None).unwrap();
 
         // Now assigning some memory that is equal to the start of the 32bit memory hole.
         let mem_size = 3328 << 20;
@@ -964,31 +969,9 @@ mod tests {
             .map(|r| (r.0, r.1))
             .collect();
         let gm = GuestMemoryMmap::from_ranges(&ram_regions).unwrap();
-        configure_system(
-            &gm,
-            GuestAddress(0),
-            0,
-            &None,
-            no_vcpus,
-            None,
-            None,
-            BootProtocol::LinuxBoot,
-            None,
-        )
-        .unwrap();
+        configure_system(&gm, GuestAddress(0), &None, no_vcpus, None, None).unwrap();
 
-        configure_system(
-            &gm,
-            GuestAddress(0),
-            0,
-            &None,
-            no_vcpus,
-            None,
-            None,
-            BootProtocol::PvhBoot,
-            None,
-        )
-        .unwrap();
+        configure_system(&gm, GuestAddress(0), &None, no_vcpus, None, None).unwrap();
 
         // Now assigning some memory that falls after the 32bit memory hole.
         let mem_size = 3330 << 20;
@@ -999,71 +982,9 @@ mod tests {
             .map(|r| (r.0, r.1))
             .collect();
         let gm = GuestMemoryMmap::from_ranges(&ram_regions).unwrap();
-        configure_system(
-            &gm,
-            GuestAddress(0),
-            0,
-            &None,
-            no_vcpus,
-            None,
-            None,
-            BootProtocol::LinuxBoot,
-            None,
-        )
-        .unwrap();
+        configure_system(&gm, GuestAddress(0), &None, no_vcpus, None, None).unwrap();
 
-        configure_system(
-            &gm,
-            GuestAddress(0),
-            0,
-            &None,
-            no_vcpus,
-            None,
-            None,
-            BootProtocol::PvhBoot,
-            None,
-        )
-        .unwrap();
-    }
-
-    #[test]
-    fn test_add_e820_entry() {
-        let e820_table = [(boot_e820_entry {
-            addr: 0x1,
-            size: 4,
-            type_: 1,
-        }); 128];
-
-        let expected_params = boot_params {
-            e820_table,
-            e820_entries: 1,
-            ..Default::default()
-        };
-
-        let mut params: boot_params = Default::default();
-        add_e820_entry(
-            &mut params,
-            e820_table[0].addr,
-            e820_table[0].size,
-            e820_table[0].type_,
-        )
-        .unwrap();
-        assert_eq!(
-            format!("{:?}", params.e820_table[0]),
-            format!("{:?}", expected_params.e820_table[0])
-        );
-        assert_eq!(params.e820_entries, expected_params.e820_entries);
-
-        // Exercise the scenario where the field storing the length of the e820 entry table is
-        // is bigger than the allocated memory.
-        params.e820_entries = params.e820_table.len() as u8 + 1;
-        assert!(add_e820_entry(
-            &mut params,
-            e820_table[0].addr,
-            e820_table[0].size,
-            e820_table[0].type_
-        )
-        .is_err());
+        configure_system(&gm, GuestAddress(0), &None, no_vcpus, None, None).unwrap();
     }
 
     #[test]

arch/src/x86_64/mpspec.rs

@@ -0,0 +1,112 @@
+// Copyright 2017 The Chromium OS Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style license that can be
+// found in the LICENSE-BSD-3-Clause file.
+
+pub const MP_PROCESSOR: ::std::os::raw::c_uint = 0;
+pub const MP_BUS: ::std::os::raw::c_uint = 1;
+pub const MP_IOAPIC: ::std::os::raw::c_uint = 2;
+pub const MP_INTSRC: ::std::os::raw::c_uint = 3;
+pub const MP_LINTSRC: ::std::os::raw::c_uint = 4;
+pub const CPU_ENABLED: ::std::os::raw::c_uint = 1;
+pub const CPU_BOOTPROCESSOR: ::std::os::raw::c_uint = 2;
+pub const MPC_APIC_USABLE: ::std::os::raw::c_uint = 1;
+pub const MP_IRQDIR_DEFAULT: ::std::os::raw::c_uint = 0;
+
+#[repr(C)]
+#[derive(Debug, Default, Copy, Clone)]
+pub struct mpf_intel {
+    pub signature: [::std::os::raw::c_char; 4usize],
+    pub physptr: ::std::os::raw::c_uint,
+    pub length: ::std::os::raw::c_uchar,
+    pub specification: ::std::os::raw::c_uchar,
+    pub checksum: ::std::os::raw::c_uchar,
+    pub feature1: ::std::os::raw::c_uchar,
+    pub feature2: ::std::os::raw::c_uchar,
+    pub feature3: ::std::os::raw::c_uchar,
+    pub feature4: ::std::os::raw::c_uchar,
+    pub feature5: ::std::os::raw::c_uchar,
+}
+
+#[repr(C)]
+#[derive(Debug, Default, Copy, Clone)]
+pub struct mpc_table {
+    pub signature: [::std::os::raw::c_char; 4usize],
+    pub length: ::std::os::raw::c_ushort,
+    pub spec: ::std::os::raw::c_char,
+    pub checksum: ::std::os::raw::c_char,
+    pub oem: [::std::os::raw::c_char; 8usize],
+    pub productid: [::std::os::raw::c_char; 12usize],
+    pub oemptr: ::std::os::raw::c_uint,
+    pub oemsize: ::std::os::raw::c_ushort,
+    pub oemcount: ::std::os::raw::c_ushort,
+    pub lapic: ::std::os::raw::c_uint,
+    pub reserved: ::std::os::raw::c_uint,
+}
+
+#[repr(C)]
+#[derive(Debug, Default, Copy, Clone)]
+pub struct mpc_cpu {
+    pub type_: ::std::os::raw::c_uchar,
+    pub apicid: ::std::os::raw::c_uchar,
+    pub apicver: ::std::os::raw::c_uchar,
+    pub cpuflag: ::std::os::raw::c_uchar,
+    pub cpufeature: ::std::os::raw::c_uint,
+    pub featureflag: ::std::os::raw::c_uint,
+    pub reserved: [::std::os::raw::c_uint; 2usize],
+}
+
+#[repr(C)]
+#[derive(Debug, Default, Copy, Clone)]
+pub struct mpc_bus {
+    pub type_: ::std::os::raw::c_uchar,
+    pub busid: ::std::os::raw::c_uchar,
+    pub bustype: [::std::os::raw::c_uchar; 6usize],
+}
+
+#[repr(C)]
+#[derive(Debug, Default, Copy, Clone)]
+pub struct mpc_ioapic {
+    pub type_: ::std::os::raw::c_uchar,
+    pub apicid: ::std::os::raw::c_uchar,
+    pub apicver: ::std::os::raw::c_uchar,
+    pub flags: ::std::os::raw::c_uchar,
+    pub apicaddr: ::std::os::raw::c_uint,
+}
+
+#[repr(C)]
+#[derive(Debug, Default, Copy, Clone)]
+pub struct mpc_intsrc {
+    pub type_: ::std::os::raw::c_uchar,
+    pub irqtype: ::std::os::raw::c_uchar,
+    pub irqflag: ::std::os::raw::c_ushort,
+    pub srcbus: ::std::os::raw::c_uchar,
+    pub srcbusirq: ::std::os::raw::c_uchar,
+    pub dstapic: ::std::os::raw::c_uchar,
+    pub dstirq: ::std::os::raw::c_uchar,
+}
+
+pub const MP_IRQ_SOURCE_TYPES_MP_INT: ::std::os::raw::c_uint = 0;
+pub const MP_IRQ_SOURCE_TYPES_MP_NMI: ::std::os::raw::c_uint = 1;
+pub const MP_IRQ_SOURCE_TYPES_MP_EXT_INT: ::std::os::raw::c_uint = 3;
+
+#[repr(C)]
+#[derive(Debug, Default, Copy, Clone)]
+pub struct mpc_lintsrc {
+    pub type_: ::std::os::raw::c_uchar,
+    pub irqtype: ::std::os::raw::c_uchar,
+    pub irqflag: ::std::os::raw::c_ushort,
+    pub srcbusid: ::std::os::raw::c_uchar,
+    pub srcbusirq: ::std::os::raw::c_uchar,
+    pub destapic: ::std::os::raw::c_uchar,
+    pub destapiclint: ::std::os::raw::c_uchar,
+}
+
+#[repr(C)]
+#[derive(Debug, Default, Copy, Clone)]
+pub struct mpc_oemtable {
+    pub signature: [::std::os::raw::c_char; 4usize],
+    pub length: ::std::os::raw::c_ushort,
+    pub rev: ::std::os::raw::c_char,
+    pub checksum: ::std::os::raw::c_char,
+    pub mpc: [::std::os::raw::c_char; 8usize],
+}

arch/src/x86_64/mptable.rs

@@ -5,18 +5,15 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE-BSD-3-Clause file.
 
+use crate::layout::{APIC_START, HIGH_RAM_START, IOAPIC_START};
+use crate::x86_64::mpspec;
+use crate::GuestMemoryMmap;
+use libc::c_char;
 use std::io;
 use std::mem;
 use std::result;
 use std::slice;
-
-use libc::c_char;
-
-use arch_gen::x86::mpspec;
-use layout::{APIC_START, HIGH_RAM_START, IOAPIC_START};
-use vm_memory::{
-    Address, ByteValued, Bytes, GuestAddress, GuestMemory, GuestMemoryError, GuestMemoryMmap,
-};
+use vm_memory::{Address, ByteValued, Bytes, GuestAddress, GuestMemory, GuestMemoryError};
 
 // This is a workaround to the Rust enforcement specifying that any implementation of a foreign
 // trait (in this case `ByteValued`) where:
@@ -222,7 +219,7 @@ pub fn setup_mptable(offset: GuestAddress, mem: &GuestMemoryMmap, num_cpus: u8)
         let size = mem::size_of::<MpcIntsrcWrapper>();
         let mut mpc_intsrc = MpcIntsrcWrapper(mpspec::mpc_intsrc::default());
         mpc_intsrc.0.type_ = mpspec::MP_INTSRC as u8;
-        mpc_intsrc.0.irqtype = mpspec::mp_irq_source_types_mp_INT as u8;
+        mpc_intsrc.0.irqtype = mpspec::MP_IRQ_SOURCE_TYPES_MP_INT as u8;
         mpc_intsrc.0.irqflag = mpspec::MP_IRQDIR_DEFAULT as u16;
         mpc_intsrc.0.srcbus = 0;
         mpc_intsrc.0.srcbusirq = i;
@@ -237,7 +234,7 @@ pub fn setup_mptable(offset: GuestAddress, mem: &GuestMemoryMmap, num_cpus: u8)
         let size = mem::size_of::<MpcLintsrcWrapper>();
         let mut mpc_lintsrc = MpcLintsrcWrapper(mpspec::mpc_lintsrc::default());
         mpc_lintsrc.0.type_ = mpspec::MP_LINTSRC as u8;
-        mpc_lintsrc.0.irqtype = mpspec::mp_irq_source_types_mp_ExtINT as u8;
+        mpc_lintsrc.0.irqtype = mpspec::MP_IRQ_SOURCE_TYPES_MP_EXT_INT as u8;
         mpc_lintsrc.0.irqflag = mpspec::MP_IRQDIR_DEFAULT as u16;
         mpc_lintsrc.0.srcbusid = 0;
         mpc_lintsrc.0.srcbusirq = 0;
@@ -252,7 +249,7 @@ pub fn setup_mptable(offset: GuestAddress, mem: &GuestMemoryMmap, num_cpus: u8)
         let size = mem::size_of::<MpcLintsrcWrapper>();
         let mut mpc_lintsrc = MpcLintsrcWrapper(mpspec::mpc_lintsrc::default());
         mpc_lintsrc.0.type_ = mpspec::MP_LINTSRC as u8;
-        mpc_lintsrc.0.irqtype = mpspec::mp_irq_source_types_mp_NMI as u8;
+        mpc_lintsrc.0.irqtype = mpspec::MP_IRQ_SOURCE_TYPES_MP_NMI as u8;
         mpc_lintsrc.0.irqflag = mpspec::MP_IRQDIR_DEFAULT as u16;
         mpc_lintsrc.0.srcbusid = 0;
         mpc_lintsrc.0.srcbusirq = 0;
@@ -287,7 +284,7 @@ pub fn setup_mptable(offset: GuestAddress, mem: &GuestMemoryMmap, num_cpus: u8)
 #[cfg(test)]
 mod tests {
     use super::*;
-    use layout::MPTABLE_START;
+    use crate::layout::MPTABLE_START;
     use vm_memory::{GuestAddress, GuestUsize};
 
     fn table_entry_size(type_: u8) -> usize {

arch/src/x86_64/regs.rs

@@ -6,17 +6,14 @@
 // Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE-BSD-3-Clause file.
-use std::sync::Arc;
-use std::{mem, result};
-
-use super::BootProtocol;
+use crate::layout::{BOOT_GDT_START, BOOT_IDT_START, PVH_INFO_START};
+use crate::GuestMemoryMmap;
 use hypervisor::arch::x86::gdt::{gdt_entry, segment_from_gdt};
 use hypervisor::arch::x86::regs::*;
 use hypervisor::x86_64::{FpuState, SpecialRegisters, StandardRegisters};
-use layout::{
-    BOOT_GDT_START, BOOT_IDT_START, PDE_START, PDPTE_START, PML4_START, PML5_START, PVH_INFO_START,
-};
-use vm_memory::{Address, Bytes, GuestMemory, GuestMemoryError, GuestMemoryMmap};
+use std::sync::Arc;
+use std::{mem, result};
+use vm_memory::{Address, Bytes, GuestMemory, GuestMemoryError};
 
 #[derive(Debug)]
 pub enum Error {
@@ -25,25 +22,25 @@ pub enum Error {
     /// Failed to set base registers for this CPU.
     SetBaseRegisters(hypervisor::HypervisorCpuError),
     /// Failed to configure the FPU.
-    SetFPURegisters(hypervisor::HypervisorCpuError),
+    SetFpuRegisters(hypervisor::HypervisorCpuError),
     /// Setting up MSRs failed.
     SetModelSpecificRegisters(hypervisor::HypervisorCpuError),
     /// Failed to set SREGs for this CPU.
     SetStatusRegisters(hypervisor::HypervisorCpuError),
     /// Checking the GDT address failed.
-    CheckGDTAddr,
+    CheckGdtAddr,
     /// Writing the GDT to RAM failed.
-    WriteGDT(GuestMemoryError),
+    WriteGdt(GuestMemoryError),
     /// Writing the IDT to RAM failed.
-    WriteIDT(GuestMemoryError),
+    WriteIdt(GuestMemoryError),
     /// Writing PDPTE to RAM failed.
-    WritePDPTEAddress(GuestMemoryError),
+    WritePdpteAddress(GuestMemoryError),
     /// Writing PDE to RAM failed.
-    WritePDEAddress(GuestMemoryError),
+    WritePdeAddress(GuestMemoryError),
     /// Writing PML4 to RAM failed.
-    WritePML4Address(GuestMemoryError),
+    WritePml4Address(GuestMemoryError),
     /// Writing PML5 to RAM failed.
-    WritePML5Address(GuestMemoryError),
+    WritePml5Address(GuestMemoryError),
 }
 
 pub type Result<T> = result::Result<T, Error>;
@@ -60,7 +57,7 @@ pub fn setup_fpu(vcpu: &Arc<dyn hypervisor::Vcpu>) -> Result<()> {
         ..Default::default()
     };
 
-    vcpu.set_fpu(&fpu).map_err(Error::SetFPURegisters)
+    vcpu.set_fpu(&fpu).map_err(Error::SetFpuRegisters)
 }
 
 /// Configure Model Specific Registers (MSRs) for a given CPU.
@@ -81,32 +78,12 @@ pub fn setup_msrs(vcpu: &Arc<dyn hypervisor::Vcpu>) -> Result<()> {
 ///
 /// * `vcpu` - Structure for the VCPU that holds the VCPU's fd.
 /// * `boot_ip` - Starting instruction pointer.
-/// * `boot_sp` - Starting stack pointer.
-/// * `boot_si` - Must point to zero page address per Linux ABI.
-pub fn setup_regs(
-    vcpu: &Arc<dyn hypervisor::Vcpu>,
-    boot_ip: u64,
-    boot_sp: u64,
-    boot_si: u64,
-    boot_prot: BootProtocol,
-) -> Result<()> {
-    let regs: StandardRegisters = match boot_prot {
-        // Configure regs as required by PVH boot protocol.
-        BootProtocol::PvhBoot => StandardRegisters {
-            rflags: 0x0000000000000002u64,
-            rbx: PVH_INFO_START.raw_value(),
-            rip: boot_ip,
-            ..Default::default()
-        },
-        // Configure regs as required by Linux 64-bit boot protocol.
-        BootProtocol::LinuxBoot => StandardRegisters {
-            rflags: 0x0000000000000002u64,
-            rip: boot_ip,
-            rsp: boot_sp,
-            rbp: boot_sp,
-            rsi: boot_si,
-            ..Default::default()
-        },
+pub fn setup_regs(vcpu: &Arc<dyn hypervisor::Vcpu>, boot_ip: u64) -> Result<()> {
+    let regs = StandardRegisters {
+        rflags: 0x0000000000000002u64,
+        rbx: PVH_INFO_START.raw_value(),
+        rip: boot_ip,
+        ..Default::default()
     };
     vcpu.set_regs(&regs).map_err(Error::SetBaseRegisters)
 }
@@ -117,19 +94,9 @@ pub fn setup_regs(
 ///
 /// * `mem` - The memory that will be passed to the guest.
 /// * `vcpu` - Structure for the VCPU that holds the VCPU's fd.
-pub fn setup_sregs(
-    mem: &GuestMemoryMmap,
-    vcpu: &Arc<dyn hypervisor::Vcpu>,
-    boot_prot: BootProtocol,
-) -> Result<()> {
+pub fn setup_sregs(mem: &GuestMemoryMmap, vcpu: &Arc<dyn hypervisor::Vcpu>) -> Result<()> {
     let mut sregs: SpecialRegisters = vcpu.get_sregs().map_err(Error::GetStatusRegisters)?;
-
-    configure_segments_and_sregs(mem, &mut sregs, boot_prot)?;
-
-    if let BootProtocol::LinuxBoot = boot_prot {
-        setup_page_tables(mem, &mut sregs)?; // TODO(dgreid) - Can this be done once per system instead?
-    }
-
+    configure_segments_and_sregs(mem, &mut sregs)?;
     vcpu.set_sregs(&sregs).map_err(Error::SetStatusRegisters)
 }
 
@@ -140,8 +107,8 @@ fn write_gdt_table(table: &[u64], guest_mem: &GuestMemoryMmap) -> Result<()> {
     for (index, entry) in table.iter().enumerate() {
         let addr = guest_mem
             .checked_offset(boot_gdt_addr, index * mem::size_of::<u64>())
-            .ok_or(Error::CheckGDTAddr)?;
-        guest_mem.write_obj(*entry, addr).map_err(Error::WriteGDT)?;
+            .ok_or(Error::CheckGdtAddr)?;
+        guest_mem.write_obj(*entry, addr).map_err(Error::WriteGdt)?;
     }
     Ok(())
 }
@@ -150,33 +117,21 @@ fn write_idt_value(val: u64, guest_mem: &GuestMemoryMmap) -> Result<()> {
     let boot_idt_addr = BOOT_IDT_START;
     guest_mem
         .write_obj(val, boot_idt_addr)
-        .map_err(Error::WriteIDT)
+        .map_err(Error::WriteIdt)
 }
 
 pub fn configure_segments_and_sregs(
     mem: &GuestMemoryMmap,
     sregs: &mut SpecialRegisters,
-    boot_prot: BootProtocol,
 ) -> Result<()> {
-    let gdt_table: [u64; BOOT_GDT_MAX as usize] = match boot_prot {
-        BootProtocol::PvhBoot => {
-            // Configure GDT entries as specified by PVH boot protocol
-            [
-                gdt_entry(0, 0, 0),               // NULL
-                gdt_entry(0xc09b, 0, 0xffffffff), // CODE
-                gdt_entry(0xc093, 0, 0xffffffff), // DATA
-                gdt_entry(0x008b, 0, 0x67),       // TSS
-            ]
-        }
-        BootProtocol::LinuxBoot => {
-            // Configure GDT entries as specified by Linux 64bit boot protocol
-            [
-                gdt_entry(0, 0, 0),            // NULL
-                gdt_entry(0xa09b, 0, 0xfffff), // CODE
-                gdt_entry(0xc093, 0, 0xfffff), // DATA
-                gdt_entry(0x808b, 0, 0xfffff), // TSS
-            ]
-        }
+    let gdt_table: [u64; BOOT_GDT_MAX as usize] = {
+        // Configure GDT entries as specified by PVH boot protocol
+        [
+            gdt_entry(0, 0, 0),               // NULL
+            gdt_entry(0xc09b, 0, 0xffffffff), // CODE
+            gdt_entry(0xc093, 0, 0xffffffff), // DATA
+            gdt_entry(0x008b, 0, 0x67),       // TSS
+        ]
     };
 
     let code_seg = segment_from_gdt(gdt_table[1], 1);
@@ -200,61 +155,17 @@ pub fn configure_segments_and_sregs(
     sregs.ss = data_seg;
     sregs.tr = tss_seg;
 
-    match boot_prot {
-        BootProtocol::PvhBoot => {
-            sregs.cr0 = CR0_PE;
-            sregs.cr4 = 0;
-        }
-        BootProtocol::LinuxBoot => {
-            /* 64-bit protected mode */
-            sregs.cr0 |= CR0_PE;
-            sregs.efer |= EFER_LME | EFER_LMA;
-        }
-    }
-
-    Ok(())
-}
-
-pub fn setup_page_tables(mem: &GuestMemoryMmap, sregs: &mut SpecialRegisters) -> Result<()> {
-    // Puts PML5 or PML4 right after zero page but aligned to 4k.
-    if unsafe { std::arch::x86_64::__cpuid(7).ecx } & (1 << 16) != 0 {
-        // Entry covering VA [0..256TB)
-        mem.write_obj(PML4_START.raw_value() | 0x03, PML5_START)
-            .map_err(Error::WritePML5Address)?;
-
-        sregs.cr3 = PML5_START.raw_value();
-        sregs.cr4 |= CR4_LA57;
-    } else {
-        sregs.cr3 = PML4_START.raw_value();
-    }
-
-    // Entry covering VA [0..512GB)
-    mem.write_obj(PDPTE_START.raw_value() | 0x03, PML4_START)
-        .map_err(Error::WritePML4Address)?;
-
-    // Entry covering VA [0..1GB)
-    mem.write_obj(PDE_START.raw_value() | 0x03, PDPTE_START)
-        .map_err(Error::WritePDPTEAddress)?;
-
-    // 512 2MB entries together covering VA [0..1GB). Note we are assuming
-    // CPU supports 2MB pages (/proc/cpuinfo has 'pse'). All modern CPUs do.
-    for i in 0..512 {
-        mem.write_obj((i << 21) + 0x83u64, PDE_START.unchecked_add(i * 8))
-            .map_err(Error::WritePDEAddress)?;
-    }
-
-    sregs.cr4 |= CR4_PAE;
-    sregs.cr0 |= CR0_PG;
+    sregs.cr0 = CR0_PE;
+    sregs.cr4 = 0;
 
     Ok(())
 }
 
 #[cfg(test)]
 mod tests {
-    extern crate vm_memory;
-
     use super::*;
-    use vm_memory::{GuestAddress, GuestMemoryMmap};
+    use crate::GuestMemoryMmap;
+    use vm_memory::GuestAddress;
 
     fn create_guest_mem() -> GuestMemoryMmap {
         GuestMemoryMmap::from_ranges(&[(GuestAddress(0), 0x10000)]).unwrap()
@@ -268,36 +179,7 @@ mod tests {
     fn segments_and_sregs() {
         let mut sregs: SpecialRegisters = Default::default();
         let gm = create_guest_mem();
-        configure_segments_and_sregs(&gm, &mut sregs, BootProtocol::LinuxBoot).unwrap();
-
-        assert_eq!(0x0, read_u64(&gm, BOOT_GDT_START));
-        assert_eq!(
-            0xaf9b000000ffff,
-            read_u64(&gm, BOOT_GDT_START.unchecked_add(8))
-        );
-        assert_eq!(
-            0xcf93000000ffff,
-            read_u64(&gm, BOOT_GDT_START.unchecked_add(16))
-        );
-        assert_eq!(
-            0x8f8b000000ffff,
-            read_u64(&gm, BOOT_GDT_START.unchecked_add(24))
-        );
-        assert_eq!(0x0, read_u64(&gm, BOOT_IDT_START));
-
-        assert_eq!(0, sregs.cs.base);
-        assert_eq!(0xffffffff, sregs.ds.limit);
-        assert_eq!(0x10, sregs.es.selector);
-        assert_eq!(1, sregs.fs.present);
-        assert_eq!(1, sregs.gs.g);
-        assert_eq!(0, sregs.ss.avl);
-        assert_eq!(0, sregs.tr.base);
-        assert_eq!(0xffffffff, sregs.tr.limit);
-        assert_eq!(0, sregs.tr.avl);
-        assert_eq!(CR0_PE, sregs.cr0);
-        assert_eq!(EFER_LME | EFER_LMA, sregs.efer);
-
-        configure_segments_and_sregs(&gm, &mut sregs, BootProtocol::PvhBoot).unwrap();
+        configure_segments_and_sregs(&gm, &mut sregs).unwrap();
         assert_eq!(0x0, read_u64(&gm, BOOT_GDT_START));
         assert_eq!(
             0xcf9b000000ffff,
@@ -327,31 +209,4 @@ mod tests {
         assert_eq!(CR0_PE, sregs.cr0);
         assert_eq!(0, sregs.cr4);
     }
-
-    #[test]
-    fn page_tables() {
-        let mut sregs: SpecialRegisters = Default::default();
-        let gm = create_guest_mem();
-        setup_page_tables(&gm, &mut sregs).unwrap();
-
-        if unsafe { std::arch::x86_64::__cpuid(7).ecx } & (1 << 16) != 0 {
-            assert_eq!(0xa003, read_u64(&gm, PML5_START));
-        }
-        assert_eq!(0xb003, read_u64(&gm, PML4_START));
-        assert_eq!(0xc003, read_u64(&gm, PDPTE_START));
-        for i in 0..512 {
-            assert_eq!(
-                (i << 21) + 0x83u64,
-                read_u64(&gm, PDE_START.unchecked_add(i * 8))
-            );
-        }
-
-        if unsafe { std::arch::x86_64::__cpuid(7).ecx } & (1 << 16) != 0 {
-            assert_eq!(PML5_START.raw_value(), sregs.cr3);
-        } else {
-            assert_eq!(PML4_START.raw_value(), sregs.cr3);
-        }
-        assert_eq!(CR4_PAE, sregs.cr4);
-        assert_eq!(CR0_PG, sregs.cr0);
-    }
 }

arch/src/x86_64/smbios.rs

@@ -6,13 +6,14 @@
 //
 // SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
 
-use layout::SMBIOS_START;
+use crate::layout::SMBIOS_START;
+use crate::GuestMemoryMmap;
 use std::fmt::{self, Display};
 use std::mem;
 use std::result;
 use std::slice;
 use vm_memory::ByteValued;
-use vm_memory::{Address, Bytes, GuestAddress, GuestMemoryMmap};
+use vm_memory::{Address, Bytes, GuestAddress};
 
 #[allow(unused_variables)]
 #[derive(Debug)]

arch/src/x86_64/tdx/mod.rs

@@ -0,0 +1,321 @@
+// Copyright © 2021 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0
+use crate::GuestMemoryMmap;
+use std::fs::File;
+use std::io::{Read, Seek, SeekFrom};
+use thiserror::Error;
+use vm_memory::{ByteValued, Bytes, GuestAddress, GuestMemoryError};
+
+#[derive(Error, Debug)]
+pub enum TdvfError {
+    #[error("Failed read TDVF descriptor: {0}")]
+    ReadDescriptor(#[source] std::io::Error),
+    #[error("Failed read TDVF descriptor offset: {0}")]
+    ReadDescriptorOffset(#[source] std::io::Error),
+    #[error("Invalid descriptor signature")]
+    InvalidDescriptorSignature,
+    #[error("Invalid descriptor size")]
+    InvalidDescriptorSize,
+    #[error("Invalid descriptor version")]
+    InvalidDescriptorVersion,
+    #[error("Failed to write HOB details to guest memory: {0}")]
+    GuestMemoryWriteHob(#[source] GuestMemoryError),
+}
+
+// TDVF_DESCRIPTOR
+#[repr(packed)]
+pub struct TdvfDescriptor {
+    signature: [u8; 4],
+    length: u32,
+    version: u32,
+    num_sections: u32, // NumberOfSectionEntry
+}
+
+// TDVF_SECTION
+#[repr(packed)]
+#[derive(Clone, Copy, Default, Debug)]
+pub struct TdvfSection {
+    pub data_offset: u32,
+    pub data_size: u32, // RawDataSize
+    pub address: u64,   // MemoryAddress
+    pub size: u64,      // MemoryDataSize
+    pub r#type: TdvfSectionType,
+    pub attributes: u32,
+}
+
+#[repr(u32)]
+#[derive(Clone, Copy, Debug)]
+pub enum TdvfSectionType {
+    Bfv,
+    Cfv,
+    TdHob,
+    TempMem,
+    Reserved = 0xffffffff,
+}
+
+impl Default for TdvfSectionType {
+    fn default() -> Self {
+        TdvfSectionType::Reserved
+    }
+}
+
+pub fn parse_tdvf_sections(file: &mut File) -> Result<Vec<TdvfSection>, TdvfError> {
+    // The 32-bit offset to the TDVF metadata is located 32 bytes from
+    // the end of the file.
+    // See "TDVF Metadata Pointer" in "TDX Virtual Firmware Design Guide
+    file.seek(SeekFrom::End(-0x20))
+        .map_err(TdvfError::ReadDescriptorOffset)?;
+
+    let mut descriptor_offset: [u8; 4] = [0; 4];
+    file.read_exact(&mut descriptor_offset)
+        .map_err(TdvfError::ReadDescriptorOffset)?;
+    let descriptor_offset = u32::from_le_bytes(descriptor_offset) as u64;
+
+    file.seek(SeekFrom::Start(descriptor_offset))
+        .map_err(TdvfError::ReadDescriptor)?;
+
+    let mut descriptor: TdvfDescriptor = unsafe { std::mem::zeroed() };
+    // Safe as we read exactly the size of the descriptor header
+    file.read_exact(unsafe {
+        std::slice::from_raw_parts_mut(
+            &mut descriptor as *mut _ as *mut u8,
+            std::mem::size_of::<TdvfDescriptor>(),
+        )
+    })
+    .map_err(TdvfError::ReadDescriptor)?;
+
+    if &descriptor.signature != b"TDVF" {
+        return Err(TdvfError::InvalidDescriptorSignature);
+    }
+
+    if descriptor.length as usize
+        != std::mem::size_of::<TdvfDescriptor>()
+            + std::mem::size_of::<TdvfSection>() * descriptor.num_sections as usize
+    {
+        return Err(TdvfError::InvalidDescriptorSize);
+    }
+
+    if descriptor.version != 1 {
+        return Err(TdvfError::InvalidDescriptorVersion);
+    }
+
+    let mut sections = Vec::new();
+    sections.resize_with(descriptor.num_sections as usize, TdvfSection::default);
+
+    // Safe as we read exactly the advertised sections
+    file.read_exact(unsafe {
+        std::slice::from_raw_parts_mut(
+            sections.as_mut_ptr() as *mut u8,
+            descriptor.num_sections as usize * std::mem::size_of::<TdvfSection>(),
+        )
+    })
+    .map_err(TdvfError::ReadDescriptor)?;
+
+    Ok(sections)
+}
+
+#[repr(u16)]
+#[derive(Copy, Clone, Debug)]
+enum HobType {
+    Handoff = 0x1,
+    ResourceDescriptor = 0x3,
+    Unused = 0xfffe,
+    EndOfHobList = 0xffff,
+}
+
+impl Default for HobType {
+    fn default() -> Self {
+        HobType::Unused
+    }
+}
+
+#[repr(C)]
+#[derive(Copy, Clone, Default, Debug)]
+struct HobHeader {
+    r#type: HobType,
+    length: u16,
+    reserved: u32,
+}
+unsafe impl ByteValued for HobHeader {}
+
+#[repr(C)]
+#[derive(Copy, Clone, Default, Debug)]
+struct HobHandoffInfoTable {
+    header: HobHeader,
+    version: u32,
+    boot_mode: u32,
+    efi_memory_top: u64,
+    efi_memory_bottom: u64,
+    efi_free_memory_top: u64,
+    efi_free_memory_bottom: u64,
+    efi_end_of_hob_list: u64,
+}
+unsafe impl ByteValued for HobHandoffInfoTable {}
+
+#[repr(C)]
+#[derive(Copy, Clone, Default, Debug)]
+struct EfiGuid {
+    data1: u32,
+    data2: u16,
+    data3: u16,
+    data4: [u8; 8],
+}
+
+#[repr(C)]
+#[derive(Copy, Clone, Default, Debug)]
+struct HobResourceDescriptor {
+    header: HobHeader,
+    owner: EfiGuid,
+    resource_type: u32,
+    resource_attribute: u32,
+    physical_start: u64,
+    resource_length: u64,
+}
+unsafe impl ByteValued for HobResourceDescriptor {}
+
+pub struct TdHob {
+    start_offset: u64,
+    current_offset: u64,
+}
+
+fn align_hob(v: u64) -> u64 {
+    (v + 7) / 8 * 8
+}
+
+impl TdHob {
+    fn update_offset<T>(&mut self) {
+        self.current_offset = align_hob(self.current_offset + std::mem::size_of::<T>() as u64)
+    }
+
+    pub fn start(offset: u64) -> TdHob {
+        // Leave a gap to place the HandoffTable at the start as it can only be filled in later
+        let mut hob = TdHob {
+            start_offset: offset,
+            current_offset: offset,
+        };
+        hob.update_offset::<HobHandoffInfoTable>();
+        hob
+    }
+
+    pub fn finish(&mut self, mem: &GuestMemoryMmap) -> Result<(), TdvfError> {
+        // Write end
+        let end = HobHeader {
+            r#type: HobType::EndOfHobList,
+            length: std::mem::size_of::<HobHeader>() as u16,
+            reserved: 0,
+        };
+        info!("Writing HOB end {:x} {:x?}", self.current_offset, end);
+        mem.write_obj(end, GuestAddress(self.current_offset))
+            .map_err(TdvfError::GuestMemoryWriteHob)?;
+        self.update_offset::<HobHeader>();
+
+        // Write handoff, delayed as it needs end of HOB list
+        let efi_end_of_hob_list = self.current_offset;
+        let handoff = HobHandoffInfoTable {
+            header: HobHeader {
+                r#type: HobType::Handoff,
+                length: std::mem::size_of::<HobHandoffInfoTable>() as u16,
+                reserved: 0,
+            },
+            version: 0x9,
+            boot_mode: 0,
+            efi_memory_top: 0,
+            efi_memory_bottom: 0,
+            efi_free_memory_top: 0,
+            efi_free_memory_bottom: 0,
+            efi_end_of_hob_list,
+        };
+        info!("Writing HOB start {:x} {:x?}", self.start_offset, handoff);
+        mem.write_obj(handoff, GuestAddress(self.start_offset))
+            .map_err(TdvfError::GuestMemoryWriteHob)
+    }
+
+    pub fn add_resource(
+        &mut self,
+        mem: &GuestMemoryMmap,
+        physical_start: u64,
+        resource_length: u64,
+        resource_type: u32,
+        resource_attribute: u32,
+    ) -> Result<(), TdvfError> {
+        let resource_descriptor = HobResourceDescriptor {
+            header: HobHeader {
+                r#type: HobType::ResourceDescriptor,
+                length: std::mem::size_of::<HobResourceDescriptor>() as u16,
+                reserved: 0,
+            },
+            owner: EfiGuid::default(),
+            resource_type,
+            resource_attribute,
+            physical_start,
+            resource_length,
+        };
+        info!(
+            "Writing HOB resource {:x} {:x?}",
+            self.current_offset, resource_descriptor
+        );
+        mem.write_obj(resource_descriptor, GuestAddress(self.current_offset))
+            .map_err(TdvfError::GuestMemoryWriteHob)?;
+        self.update_offset::<HobResourceDescriptor>();
+        Ok(())
+    }
+
+    pub fn add_memory_resource(
+        &mut self,
+        mem: &GuestMemoryMmap,
+        physical_start: u64,
+        resource_length: u64,
+        ram: bool,
+    ) -> Result<(), TdvfError> {
+        self.add_resource(
+            mem,
+            physical_start,
+            resource_length,
+            if ram {
+                0 /* EFI_RESOURCE_SYSTEM_MEMORY */
+            } else {
+                0x5 /*EFI_RESOURCE_MEMORY_RESERVED */
+            },
+            /* TODO:
+             * QEMU currently fills it in like this:
+             * EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_ENCRYPTED | EFI_RESOURCE_ATTRIBUTE_TESTED
+             * which differs from the spec (due to TDVF implementation issue?)
+             */
+            0x04000007,
+        )
+    }
+
+    pub fn add_mmio_resource(
+        &mut self,
+        mem: &GuestMemoryMmap,
+        physical_start: u64,
+        resource_length: u64,
+    ) -> Result<(), TdvfError> {
+        self.add_resource(
+            mem,
+            physical_start,
+            resource_length,
+            0x1, /* EFI_RESOURCE_MEMORY_MAPPED_IO */
+            /*
+             * EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
+             */
+            0x403,
+        )
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    #[ignore]
+    fn test_parse_tdvf_sections() {
+        let mut f = std::fs::File::open("tdvf.fd").unwrap();
+        let sections = parse_tdvf_sections(&mut f).unwrap();
+        for section in sections {
+            eprintln!("{:x?}", section)
+        }
+    }
+}

arch_gen/Cargo.lock

@@ -1,6 +0,0 @@
-# This file is automatically @generated by Cargo.
-# It is not intended for manual editing.
-[[package]]
-name = "arch_gen"
-version = "0.1.0"
-

arch_gen/Cargo.toml

@@ -1,7 +0,0 @@
-[package]
-name = "arch_gen"
-version = "0.1.0"
-authors = ["Amazon firecracker team <firecracker-devel@amazon.com>"]
-
-[dependencies]
-

arch_gen/src/lib.rs

@@ -1,5 +0,0 @@
-// Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
-// SPDX-License-Identifier: Apache-2.0
-
-#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
-pub mod x86;

arch_gen/src/x86/mod.rs

@@ -1,22 +0,0 @@
-// Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
-// Use of this source code is governed by a BSD-style license that can be
-// found in the LICENSE-BSD-3-Clause file.
-
-#[allow(non_upper_case_globals)]
-#[allow(non_camel_case_types)]
-#[allow(non_snake_case)]
-#[allow(
-    clippy::unreadable_literal,
-    clippy::redundant_static_lifetimes,
-    clippy::trivially_copy_pass_by_ref,
-    clippy::useless_transmute,
-    clippy::should_implement_trait,
-    clippy::transmute_ptr_to_ptr
-)]
-#[allow(non_camel_case_types)]
-#[allow(non_upper_case_globals)]
-#[allow(clippy::unreadable_literal, clippy::redundant_static_lifetimes)]
-pub mod mpspec;

arch_gen/src/x86/mpspec.rs

@@ -1,832 +0,0 @@
-// Copyright 2017 The Chromium OS Authors. All rights reserved.
-// Use of this source code is governed by a BSD-style license that can be
-// found in the LICENSE-BSD-3-Clause file.
-
-/* automatically generated by rust-bindgen */
-
-pub const MPC_SIGNATURE: &'static [u8; 5usize] = b"PCMP\x00";
-pub const MP_PROCESSOR: ::std::os::raw::c_uint = 0;
-pub const MP_BUS: ::std::os::raw::c_uint = 1;
-pub const MP_IOAPIC: ::std::os::raw::c_uint = 2;
-pub const MP_INTSRC: ::std::os::raw::c_uint = 3;
-pub const MP_LINTSRC: ::std::os::raw::c_uint = 4;
-pub const MP_TRANSLATION: ::std::os::raw::c_uint = 192;
-pub const CPU_ENABLED: ::std::os::raw::c_uint = 1;
-pub const CPU_BOOTPROCESSOR: ::std::os::raw::c_uint = 2;
-pub const CPU_STEPPING_MASK: ::std::os::raw::c_uint = 15;
-pub const CPU_MODEL_MASK: ::std::os::raw::c_uint = 240;
-pub const CPU_FAMILY_MASK: ::std::os::raw::c_uint = 3840;
-pub const BUSTYPE_EISA: &'static [u8; 5usize] = b"EISA\x00";
-pub const BUSTYPE_ISA: &'static [u8; 4usize] = b"ISA\x00";
-pub const BUSTYPE_INTERN: &'static [u8; 7usize] = b"INTERN\x00";
-pub const BUSTYPE_MCA: &'static [u8; 4usize] = b"MCA\x00";
-pub const BUSTYPE_VL: &'static [u8; 3usize] = b"VL\x00";
-pub const BUSTYPE_PCI: &'static [u8; 4usize] = b"PCI\x00";
-pub const BUSTYPE_PCMCIA: &'static [u8; 7usize] = b"PCMCIA\x00";
-pub const BUSTYPE_CBUS: &'static [u8; 5usize] = b"CBUS\x00";
-pub const BUSTYPE_CBUSII: &'static [u8; 7usize] = b"CBUSII\x00";
-pub const BUSTYPE_FUTURE: &'static [u8; 7usize] = b"FUTURE\x00";
-pub const BUSTYPE_MBI: &'static [u8; 4usize] = b"MBI\x00";
-pub const BUSTYPE_MBII: &'static [u8; 5usize] = b"MBII\x00";
-pub const BUSTYPE_MPI: &'static [u8; 4usize] = b"MPI\x00";
-pub const BUSTYPE_MPSA: &'static [u8; 5usize] = b"MPSA\x00";
-pub const BUSTYPE_NUBUS: &'static [u8; 6usize] = b"NUBUS\x00";
-pub const BUSTYPE_TC: &'static [u8; 3usize] = b"TC\x00";
-pub const BUSTYPE_VME: &'static [u8; 4usize] = b"VME\x00";
-pub const BUSTYPE_XPRESS: &'static [u8; 7usize] = b"XPRESS\x00";
-pub const MPC_APIC_USABLE: ::std::os::raw::c_uint = 1;
-pub const MP_IRQDIR_DEFAULT: ::std::os::raw::c_uint = 0;
-pub const MP_IRQDIR_HIGH: ::std::os::raw::c_uint = 1;
-pub const MP_IRQDIR_LOW: ::std::os::raw::c_uint = 3;
-pub const MP_APIC_ALL: ::std::os::raw::c_uint = 255;
-pub const MPC_OEM_SIGNATURE: &'static [u8; 5usize] = b"_OEM\x00";
-#[repr(C)]
-#[derive(Debug, Default, Copy)]
-pub struct mpf_intel {
-    pub signature: [::std::os::raw::c_char; 4usize],
-    pub physptr: ::std::os::raw::c_uint,
-    pub length: ::std::os::raw::c_uchar,
-    pub specification: ::std::os::raw::c_uchar,
-    pub checksum: ::std::os::raw::c_uchar,
-    pub feature1: ::std::os::raw::c_uchar,
-    pub feature2: ::std::os::raw::c_uchar,
-    pub feature3: ::std::os::raw::c_uchar,
-    pub feature4: ::std::os::raw::c_uchar,
-    pub feature5: ::std::os::raw::c_uchar,
-}
-#[test]
-fn bindgen_test_layout_mpf_intel() {
-    assert_eq!(
-        ::std::mem::size_of::<mpf_intel>(),
-        16usize,
-        concat!("Size of: ", stringify!(mpf_intel))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<mpf_intel>(),
-        4usize,
-        concat!("Alignment of ", stringify!(mpf_intel))
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpf_intel>()).signature as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpf_intel),
-            "::",
-            stringify!(signature)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpf_intel>()).physptr as *const _ as usize },
-        4usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpf_intel),
-            "::",
-            stringify!(physptr)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpf_intel>()).length as *const _ as usize },
-        8usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpf_intel),
-            "::",
-            stringify!(length)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpf_intel>()).specification as *const _ as usize },
-        9usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpf_intel),
-            "::",
-            stringify!(specification)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpf_intel>()).checksum as *const _ as usize },
-        10usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpf_intel),
-            "::",
-            stringify!(checksum)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpf_intel>()).feature1 as *const _ as usize },
-        11usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpf_intel),
-            "::",
-            stringify!(feature1)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpf_intel>()).feature2 as *const _ as usize },
-        12usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpf_intel),
-            "::",
-            stringify!(feature2)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpf_intel>()).feature3 as *const _ as usize },
-        13usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpf_intel),
-            "::",
-            stringify!(feature3)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpf_intel>()).feature4 as *const _ as usize },
-        14usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpf_intel),
-            "::",
-            stringify!(feature4)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpf_intel>()).feature5 as *const _ as usize },
-        15usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpf_intel),
-            "::",
-            stringify!(feature5)
-        )
-    );
-}
-impl Clone for mpf_intel {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
-#[repr(C)]
-#[derive(Debug, Default, Copy)]
-pub struct mpc_table {
-    pub signature: [::std::os::raw::c_char; 4usize],
-    pub length: ::std::os::raw::c_ushort,
-    pub spec: ::std::os::raw::c_char,
-    pub checksum: ::std::os::raw::c_char,
-    pub oem: [::std::os::raw::c_char; 8usize],
-    pub productid: [::std::os::raw::c_char; 12usize],
-    pub oemptr: ::std::os::raw::c_uint,
-    pub oemsize: ::std::os::raw::c_ushort,
-    pub oemcount: ::std::os::raw::c_ushort,
-    pub lapic: ::std::os::raw::c_uint,
-    pub reserved: ::std::os::raw::c_uint,
-}
-#[test]
-fn bindgen_test_layout_mpc_table() {
-    assert_eq!(
-        ::std::mem::size_of::<mpc_table>(),
-        44usize,
-        concat!("Size of: ", stringify!(mpc_table))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<mpc_table>(),
-        4usize,
-        concat!("Alignment of ", stringify!(mpc_table))
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_table>()).signature as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_table),
-            "::",
-            stringify!(signature)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_table>()).length as *const _ as usize },
-        4usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_table),
-            "::",
-            stringify!(length)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_table>()).spec as *const _ as usize },
-        6usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_table),
-            "::",
-            stringify!(spec)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_table>()).checksum as *const _ as usize },
-        7usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_table),
-            "::",
-            stringify!(checksum)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_table>()).oem as *const _ as usize },
-        8usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_table),
-            "::",
-            stringify!(oem)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_table>()).productid as *const _ as usize },
-        16usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_table),
-            "::",
-            stringify!(productid)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_table>()).oemptr as *const _ as usize },
-        28usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_table),
-            "::",
-            stringify!(oemptr)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_table>()).oemsize as *const _ as usize },
-        32usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_table),
-            "::",
-            stringify!(oemsize)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_table>()).oemcount as *const _ as usize },
-        34usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_table),
-            "::",
-            stringify!(oemcount)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_table>()).lapic as *const _ as usize },
-        36usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_table),
-            "::",
-            stringify!(lapic)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_table>()).reserved as *const _ as usize },
-        40usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_table),
-            "::",
-            stringify!(reserved)
-        )
-    );
-}
-impl Clone for mpc_table {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
-#[repr(C)]
-#[derive(Debug, Default, Copy)]
-pub struct mpc_cpu {
-    pub type_: ::std::os::raw::c_uchar,
-    pub apicid: ::std::os::raw::c_uchar,
-    pub apicver: ::std::os::raw::c_uchar,
-    pub cpuflag: ::std::os::raw::c_uchar,
-    pub cpufeature: ::std::os::raw::c_uint,
-    pub featureflag: ::std::os::raw::c_uint,
-    pub reserved: [::std::os::raw::c_uint; 2usize],
-}
-#[test]
-fn bindgen_test_layout_mpc_cpu() {
-    assert_eq!(
-        ::std::mem::size_of::<mpc_cpu>(),
-        20usize,
-        concat!("Size of: ", stringify!(mpc_cpu))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<mpc_cpu>(),
-        4usize,
-        concat!("Alignment of ", stringify!(mpc_cpu))
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_cpu>()).type_ as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_cpu),
-            "::",
-            stringify!(type_)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_cpu>()).apicid as *const _ as usize },
-        1usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_cpu),
-            "::",
-            stringify!(apicid)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_cpu>()).apicver as *const _ as usize },
-        2usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_cpu),
-            "::",
-            stringify!(apicver)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_cpu>()).cpuflag as *const _ as usize },
-        3usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_cpu),
-            "::",
-            stringify!(cpuflag)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_cpu>()).cpufeature as *const _ as usize },
-        4usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_cpu),
-            "::",
-            stringify!(cpufeature)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_cpu>()).featureflag as *const _ as usize },
-        8usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_cpu),
-            "::",
-            stringify!(featureflag)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_cpu>()).reserved as *const _ as usize },
-        12usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_cpu),
-            "::",
-            stringify!(reserved)
-        )
-    );
-}
-impl Clone for mpc_cpu {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
-#[repr(C)]
-#[derive(Debug, Default, Copy)]
-pub struct mpc_bus {
-    pub type_: ::std::os::raw::c_uchar,
-    pub busid: ::std::os::raw::c_uchar,
-    pub bustype: [::std::os::raw::c_uchar; 6usize],
-}
-#[test]
-fn bindgen_test_layout_mpc_bus() {
-    assert_eq!(
-        ::std::mem::size_of::<mpc_bus>(),
-        8usize,
-        concat!("Size of: ", stringify!(mpc_bus))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<mpc_bus>(),
-        1usize,
-        concat!("Alignment of ", stringify!(mpc_bus))
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_bus>()).type_ as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_bus),
-            "::",
-            stringify!(type_)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_bus>()).busid as *const _ as usize },
-        1usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_bus),
-            "::",
-            stringify!(busid)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_bus>()).bustype as *const _ as usize },
-        2usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_bus),
-            "::",
-            stringify!(bustype)
-        )
-    );
-}
-impl Clone for mpc_bus {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
-#[repr(C)]
-#[derive(Debug, Default, Copy)]
-pub struct mpc_ioapic {
-    pub type_: ::std::os::raw::c_uchar,
-    pub apicid: ::std::os::raw::c_uchar,
-    pub apicver: ::std::os::raw::c_uchar,
-    pub flags: ::std::os::raw::c_uchar,
-    pub apicaddr: ::std::os::raw::c_uint,
-}
-#[test]
-fn bindgen_test_layout_mpc_ioapic() {
-    assert_eq!(
-        ::std::mem::size_of::<mpc_ioapic>(),
-        8usize,
-        concat!("Size of: ", stringify!(mpc_ioapic))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<mpc_ioapic>(),
-        4usize,
-        concat!("Alignment of ", stringify!(mpc_ioapic))
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_ioapic>()).type_ as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_ioapic),
-            "::",
-            stringify!(type_)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_ioapic>()).apicid as *const _ as usize },
-        1usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_ioapic),
-            "::",
-            stringify!(apicid)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_ioapic>()).apicver as *const _ as usize },
-        2usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_ioapic),
-            "::",
-            stringify!(apicver)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_ioapic>()).flags as *const _ as usize },
-        3usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_ioapic),
-            "::",
-            stringify!(flags)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_ioapic>()).apicaddr as *const _ as usize },
-        4usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_ioapic),
-            "::",
-            stringify!(apicaddr)
-        )
-    );
-}
-impl Clone for mpc_ioapic {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
-#[repr(C)]
-#[derive(Debug, Default, Copy)]
-pub struct mpc_intsrc {
-    pub type_: ::std::os::raw::c_uchar,
-    pub irqtype: ::std::os::raw::c_uchar,
-    pub irqflag: ::std::os::raw::c_ushort,
-    pub srcbus: ::std::os::raw::c_uchar,
-    pub srcbusirq: ::std::os::raw::c_uchar,
-    pub dstapic: ::std::os::raw::c_uchar,
-    pub dstirq: ::std::os::raw::c_uchar,
-}
-#[test]
-fn bindgen_test_layout_mpc_intsrc() {
-    assert_eq!(
-        ::std::mem::size_of::<mpc_intsrc>(),
-        8usize,
-        concat!("Size of: ", stringify!(mpc_intsrc))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<mpc_intsrc>(),
-        2usize,
-        concat!("Alignment of ", stringify!(mpc_intsrc))
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_intsrc>()).type_ as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_intsrc),
-            "::",
-            stringify!(type_)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_intsrc>()).irqtype as *const _ as usize },
-        1usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_intsrc),
-            "::",
-            stringify!(irqtype)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_intsrc>()).irqflag as *const _ as usize },
-        2usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_intsrc),
-            "::",
-            stringify!(irqflag)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_intsrc>()).srcbus as *const _ as usize },
-        4usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_intsrc),
-            "::",
-            stringify!(srcbus)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_intsrc>()).srcbusirq as *const _ as usize },
-        5usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_intsrc),
-            "::",
-            stringify!(srcbusirq)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_intsrc>()).dstapic as *const _ as usize },
-        6usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_intsrc),
-            "::",
-            stringify!(dstapic)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_intsrc>()).dstirq as *const _ as usize },
-        7usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_intsrc),
-            "::",
-            stringify!(dstirq)
-        )
-    );
-}
-impl Clone for mpc_intsrc {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
-pub const mp_irq_source_types_mp_INT: mp_irq_source_types = 0;
-pub const mp_irq_source_types_mp_NMI: mp_irq_source_types = 1;
-pub const mp_irq_source_types_mp_SMI: mp_irq_source_types = 2;
-pub const mp_irq_source_types_mp_ExtINT: mp_irq_source_types = 3;
-pub type mp_irq_source_types = ::std::os::raw::c_uint;
-#[repr(C)]
-#[derive(Debug, Default, Copy)]
-pub struct mpc_lintsrc {
-    pub type_: ::std::os::raw::c_uchar,
-    pub irqtype: ::std::os::raw::c_uchar,
-    pub irqflag: ::std::os::raw::c_ushort,
-    pub srcbusid: ::std::os::raw::c_uchar,
-    pub srcbusirq: ::std::os::raw::c_uchar,
-    pub destapic: ::std::os::raw::c_uchar,
-    pub destapiclint: ::std::os::raw::c_uchar,
-}
-#[test]
-fn bindgen_test_layout_mpc_lintsrc() {
-    assert_eq!(
-        ::std::mem::size_of::<mpc_lintsrc>(),
-        8usize,
-        concat!("Size of: ", stringify!(mpc_lintsrc))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<mpc_lintsrc>(),
-        2usize,
-        concat!("Alignment of ", stringify!(mpc_lintsrc))
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_lintsrc>()).type_ as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_lintsrc),
-            "::",
-            stringify!(type_)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_lintsrc>()).irqtype as *const _ as usize },
-        1usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_lintsrc),
-            "::",
-            stringify!(irqtype)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_lintsrc>()).irqflag as *const _ as usize },
-        2usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_lintsrc),
-            "::",
-            stringify!(irqflag)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_lintsrc>()).srcbusid as *const _ as usize },
-        4usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_lintsrc),
-            "::",
-            stringify!(srcbusid)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_lintsrc>()).srcbusirq as *const _ as usize },
-        5usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_lintsrc),
-            "::",
-            stringify!(srcbusirq)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_lintsrc>()).destapic as *const _ as usize },
-        6usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_lintsrc),
-            "::",
-            stringify!(destapic)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_lintsrc>()).destapiclint as *const _ as usize },
-        7usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_lintsrc),
-            "::",
-            stringify!(destapiclint)
-        )
-    );
-}
-impl Clone for mpc_lintsrc {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
-#[repr(C)]
-#[derive(Debug, Default, Copy)]
-pub struct mpc_oemtable {
-    pub signature: [::std::os::raw::c_char; 4usize],
-    pub length: ::std::os::raw::c_ushort,
-    pub rev: ::std::os::raw::c_char,
-    pub checksum: ::std::os::raw::c_char,
-    pub mpc: [::std::os::raw::c_char; 8usize],
-}
-#[test]
-fn bindgen_test_layout_mpc_oemtable() {
-    assert_eq!(
-        ::std::mem::size_of::<mpc_oemtable>(),
-        16usize,
-        concat!("Size of: ", stringify!(mpc_oemtable))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<mpc_oemtable>(),
-        2usize,
-        concat!("Alignment of ", stringify!(mpc_oemtable))
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_oemtable>()).signature as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_oemtable),
-            "::",
-            stringify!(signature)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_oemtable>()).length as *const _ as usize },
-        4usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_oemtable),
-            "::",
-            stringify!(length)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_oemtable>()).rev as *const _ as usize },
-        6usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_oemtable),
-            "::",
-            stringify!(rev)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_oemtable>()).checksum as *const _ as usize },
-        7usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_oemtable),
-            "::",
-            stringify!(checksum)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*std::ptr::null::<mpc_oemtable>()).mpc as *const _ as usize },
-        8usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_oemtable),
-            "::",
-            stringify!(mpc)
-        )
-    );
-}
-impl Clone for mpc_oemtable {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
-pub const mp_bustype_MP_BUS_ISA: mp_bustype = 1;
-pub const mp_bustype_MP_BUS_EISA: mp_bustype = 2;
-pub const mp_bustype_MP_BUS_PCI: mp_bustype = 3;
-pub type mp_bustype = ::std::os::raw::c_uint;

block_util/Cargo.toml

@@ -10,17 +10,14 @@ io_uring = []
 
 [dependencies]
 io-uring = ">=0.4.0"
-libc = "0.2.86"
+libc = "0.2.98"
 log = "0.4.14"
 qcow = { path = "../qcow" }
-serde = ">=1.0.27"
-serde_derive = ">=1.0.27"
-serde_json = ">=1.0.9"
 thiserror = "1.0"
+versionize = "0.1.6"
+versionize_derive = "0.1.4"
 virtio-bindings = { version = "0.1", features = ["virtio-v5_0_0"]}
-vm-memory = { version = "0.5.0", features = ["backend-mmap", "backend-atomic"] }
+vm-memory = { version = "0.5.0", features = ["backend-mmap", "backend-atomic", "backend-bitmap"] }
 vm-virtio = { path = "../vm-virtio" }
 vmm-sys-util = ">=0.3.1"
 
-[dev-dependencies]
-tempfile = "3.2.0"

block_util/src/lib.rs

@@ -10,8 +10,6 @@
 
 #[macro_use]
 extern crate log;
-#[macro_use]
-extern crate serde_derive;
 
 pub mod async_io;
 pub mod fixed_vhd_async;
@@ -24,7 +22,6 @@ pub mod vhd;
 use crate::async_io::{AsyncIo, AsyncIoError, AsyncIoResult, DiskFileError, DiskFileResult};
 #[cfg(feature = "io_uring")]
 use io_uring::{opcode, IoUring, Probe};
-use serde::ser::{Serialize, SerializeStruct, Serializer};
 use std::cmp;
 use std::convert::TryInto;
 use std::fs::File;
@@ -32,14 +29,21 @@ use std::io::{self, IoSlice, IoSliceMut, Read, Seek, SeekFrom, Write};
 use std::os::linux::fs::MetadataExt;
 #[cfg(feature = "io_uring")]
 use std::os::unix::io::AsRawFd;
-use std::path::PathBuf;
+use std::path::Path;
 use std::result;
 use std::sync::{Arc, Mutex};
+use versionize::{VersionMap, Versionize, VersionizeResult};
+use versionize_derive::Versionize;
 use virtio_bindings::bindings::virtio_blk::*;
-use vm_memory::{ByteValued, Bytes, GuestAddress, GuestMemory, GuestMemoryError, GuestMemoryMmap};
+use vm_memory::{
+    bitmap::AtomicBitmap, bitmap::Bitmap, ByteValued, Bytes, GuestAddress, GuestMemory,
+    GuestMemoryError,
+};
 use vm_virtio::DescriptorChain;
 use vmm_sys_util::eventfd::EventFd;
 
+type GuestMemoryMmap = vm_memory::GuestMemoryMmap<AtomicBitmap>;
+
 const SECTOR_SHIFT: u8 = 9;
 pub const SECTOR_SIZE: u64 = 0x01 << SECTOR_SHIFT;
 
@@ -65,7 +69,7 @@ pub enum Error {
     TooManyDescriptors,
 }
 
-fn build_device_id(disk_path: &PathBuf) -> result::Result<String, Error> {
+fn build_device_id(disk_path: &Path) -> result::Result<String, Error> {
     let blk_metadata = match disk_path.metadata() {
         Err(_) => return Err(Error::GetFileMetadata),
         Ok(m) => m,
@@ -80,7 +84,7 @@ fn build_device_id(disk_path: &PathBuf) -> result::Result<String, Error> {
     Ok(device_id)
 }
 
-pub fn build_disk_image_id(disk_path: &PathBuf) -> Vec<u8> {
+pub fn build_disk_image_id(disk_path: &Path) -> Vec<u8> {
     let mut default_disk_image_id = vec![0; VIRTIO_BLK_ID_BYTES as usize];
     match build_device_id(disk_path) {
         Err(_) => {
@@ -135,7 +139,7 @@ pub enum RequestType {
     In,
     Out,
     Flush,
-    GetDeviceID,
+    GetDeviceId,
     Unsupported(u32),
 }
 
@@ -148,7 +152,7 @@ pub fn request_type(
         VIRTIO_BLK_T_IN => Ok(RequestType::In),
         VIRTIO_BLK_T_OUT => Ok(RequestType::Out),
         VIRTIO_BLK_T_FLUSH => Ok(RequestType::Flush),
-        VIRTIO_BLK_T_GET_ID => Ok(RequestType::GetDeviceID),
+        VIRTIO_BLK_T_GET_ID => Ok(RequestType::GetDeviceId),
         t => Ok(RequestType::Unsupported(t)),
     }
 }
@@ -163,6 +167,7 @@ fn sector(mem: &GuestMemoryMmap, desc_addr: GuestAddress) -> result::Result<u64,
     mem.read_obj(addr).map_err(Error::GuestMemory)
 }
 
+#[derive(Debug)]
 pub struct Request {
     pub request_type: RequestType,
     pub sector: u64,
@@ -182,8 +187,8 @@ impl Request {
         }
 
         let mut req = Request {
-            request_type: request_type(&mem, avail_desc.addr)?,
-            sector: sector(&mem, avail_desc.addr)?,
+            request_type: request_type(mem, avail_desc.addr)?,
+            sector: sector(mem, avail_desc.addr)?,
             data_descriptors: Vec::new(),
             status_addr: GuestAddress(0),
             writeback: true,
@@ -192,12 +197,17 @@ impl Request {
         let status_desc;
         let mut desc = avail_desc
             .next_descriptor()
-            .ok_or(Error::DescriptorChainTooShort)?;
+            .ok_or(Error::DescriptorChainTooShort)
+            .map_err(|e| {
+                error!("Only head descriptor present: request = {:?}", req);
+                e
+            })?;
 
         if !desc.has_next() {
             status_desc = desc;
             // Only flush requests are allowed to skip the data descriptor.
             if req.request_type != RequestType::Flush {
+                error!("Need a data descriptor: request = {:?}", req);
                 return Err(Error::DescriptorChainTooShort);
             }
         } else {
@@ -208,13 +218,17 @@ impl Request {
                 if !desc.is_write_only() && req.request_type == RequestType::In {
                     return Err(Error::UnexpectedReadOnlyDescriptor);
                 }
-                if !desc.is_write_only() && req.request_type == RequestType::GetDeviceID {
+                if !desc.is_write_only() && req.request_type == RequestType::GetDeviceId {
                     return Err(Error::UnexpectedReadOnlyDescriptor);
                 }
                 req.data_descriptors.push((desc.addr, desc.len));
                 desc = desc
                     .next_descriptor()
-                    .ok_or(Error::DescriptorChainTooShort)?;
+                    .ok_or(Error::DescriptorChainTooShort)
+                    .map_err(|e| {
+                        error!("DescriptorChain corrupted: request = {:?}", req);
+                        e
+                    })?;
             }
             status_desc = desc;
         }
@@ -270,11 +284,11 @@ impl Request {
                     }
                 }
                 RequestType::Flush => disk.flush().map_err(ExecuteError::Flush)?,
-                RequestType::GetDeviceID => {
+                RequestType::GetDeviceId => {
                     if (*data_len as usize) < disk_id.len() {
                         return Err(ExecuteError::BadRequest(Error::InvalidOffset));
                     }
-                    mem.write_slice(&disk_id.as_slice(), *data_addr)
+                    mem.write_slice(disk_id.as_slice(), *data_addr)
                         .map_err(ExecuteError::Write)?;
                 }
                 RequestType::Unsupported(t) => return Err(ExecuteError::Unsupported(t)),
@@ -322,6 +336,12 @@ impl Request {
         // Queue operations expected to be submitted.
         match request_type {
             RequestType::In => {
+                for (data_addr, data_len) in &self.data_descriptors {
+                    mem.get_slice(*data_addr, *data_len as usize)
+                        .map_err(ExecuteError::GetHostAddress)?
+                        .bitmap()
+                        .mark_dirty(0, *data_len as usize);
+                }
                 disk_image
                     .read_vectored(offset, iovecs, user_data)
                     .map_err(ExecuteError::AsyncRead)?;
@@ -336,7 +356,7 @@ impl Request {
                     .fsync(Some(user_data))
                     .map_err(ExecuteError::AsyncFlush)?;
             }
-            RequestType::GetDeviceID => {
+            RequestType::GetDeviceId => {
                 let (data_addr, data_len) = if self.data_descriptors.len() == 1 {
                     (self.data_descriptors[0].0, self.data_descriptors[0].1)
                 } else {
@@ -360,7 +380,7 @@ impl Request {
     }
 }
 
-#[derive(Copy, Clone, Debug, Default, Deserialize)]
+#[derive(Copy, Clone, Debug, Default, Versionize)]
 #[repr(C, packed)]
 pub struct VirtioBlockConfig {
     pub capacity: u64,
@@ -383,95 +403,15 @@ pub struct VirtioBlockConfig {
     pub write_zeroes_may_unmap: u8,
     pub unused1: [u8; 3],
 }
-
-// We must explicitly implement Serialize since the structure is packed and
-// it's unsafe to borrow from a packed structure. And by default, if we derive
-// Serialize from serde, it will borrow the values from the structure.
-// That's why this implementation copies each field separately before it
-// serializes the entire structure field by field.
-impl Serialize for VirtioBlockConfig {
-    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
-    where
-        S: Serializer,
-    {
-        let capacity = self.capacity;
-        let size_max = self.size_max;
-        let seg_max = self.seg_max;
-        let geometry = self.geometry;
-        let blk_size = self.blk_size;
-        let physical_block_exp = self.physical_block_exp;
-        let alignment_offset = self.alignment_offset;
-        let min_io_size = self.min_io_size;
-        let opt_io_size = self.opt_io_size;
-        let writeback = self.writeback;
-        let unused = self.unused;
-        let num_queues = self.num_queues;
-        let max_discard_sectors = self.max_discard_sectors;
-        let max_discard_seg = self.max_discard_seg;
-        let discard_sector_alignment = self.discard_sector_alignment;
-        let max_write_zeroes_sectors = self.max_write_zeroes_sectors;
-        let max_write_zeroes_seg = self.max_write_zeroes_seg;
-        let write_zeroes_may_unmap = self.write_zeroes_may_unmap;
-        let unused1 = self.unused1;
-
-        let mut virtio_block_config = serializer.serialize_struct("VirtioBlockConfig", 60)?;
-        virtio_block_config.serialize_field("capacity", &capacity)?;
-        virtio_block_config.serialize_field("size_max", &size_max)?;
-        virtio_block_config.serialize_field("seg_max", &seg_max)?;
-        virtio_block_config.serialize_field("geometry", &geometry)?;
-        virtio_block_config.serialize_field("blk_size", &blk_size)?;
-        virtio_block_config.serialize_field("physical_block_exp", &physical_block_exp)?;
-        virtio_block_config.serialize_field("alignment_offset", &alignment_offset)?;
-        virtio_block_config.serialize_field("min_io_size", &min_io_size)?;
-        virtio_block_config.serialize_field("opt_io_size", &opt_io_size)?;
-        virtio_block_config.serialize_field("writeback", &writeback)?;
-        virtio_block_config.serialize_field("unused", &unused)?;
-        virtio_block_config.serialize_field("num_queues", &num_queues)?;
-        virtio_block_config.serialize_field("max_discard_sectors", &max_discard_sectors)?;
-        virtio_block_config.serialize_field("max_discard_seg", &max_discard_seg)?;
-        virtio_block_config
-            .serialize_field("discard_sector_alignment", &discard_sector_alignment)?;
-        virtio_block_config
-            .serialize_field("max_write_zeroes_sectors", &max_write_zeroes_sectors)?;
-        virtio_block_config.serialize_field("max_write_zeroes_seg", &max_write_zeroes_seg)?;
-        virtio_block_config.serialize_field("write_zeroes_may_unmap", &write_zeroes_may_unmap)?;
-        virtio_block_config.serialize_field("unused1", &unused1)?;
-        virtio_block_config.end()
-    }
-}
-
 unsafe impl ByteValued for VirtioBlockConfig {}
 
-#[derive(Copy, Clone, Debug, Default, Deserialize)]
+#[derive(Copy, Clone, Debug, Default, Versionize)]
 #[repr(C, packed)]
 pub struct VirtioBlockGeometry {
     pub cylinders: u16,
     pub heads: u8,
     pub sectors: u8,
 }
-
-// We must explicitly implement Serialize since the structure is packed and
-// it's unsafe to borrow from a packed structure. And by default, if we derive
-// Serialize from serde, it will borrow the values from the structure.
-// That's why this implementation copies each field separately before it
-// serializes the entire structure field by field.
-impl Serialize for VirtioBlockGeometry {
-    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
-    where
-        S: Serializer,
-    {
-        let cylinders = self.cylinders;
-        let heads = self.heads;
-        let sectors = self.sectors;
-
-        let mut virtio_block_geometry = serializer.serialize_struct("VirtioBlockGeometry", 4)?;
-        virtio_block_geometry.serialize_field("cylinders", &cylinders)?;
-        virtio_block_geometry.serialize_field("heads", &heads)?;
-        virtio_block_geometry.serialize_field("sectors", &sectors)?;
-        virtio_block_geometry.end()
-    }
-}
-
 unsafe impl ByteValued for VirtioBlockGeometry {}
 
 /// Check if io_uring for block device can be used on the current system, as

block_util/src/raw_async.rs

@@ -5,7 +5,7 @@
 use crate::async_io::{
     AsyncIo, AsyncIoError, AsyncIoResult, DiskFile, DiskFileError, DiskFileResult,
 };
-use io_uring::{opcode, squeue, IoUring};
+use io_uring::{opcode, squeue, types, IoUring};
 use std::fs::File;
 use std::io::{Seek, SeekFrom};
 use std::os::unix::io::{AsRawFd, RawFd};
@@ -71,28 +71,23 @@ impl AsyncIo for RawFileAsync {
         iovecs: Vec<libc::iovec>,
         user_data: u64,
     ) -> AsyncIoResult<()> {
-        let (submitter, sq, _) = self.io_uring.split();
-        let mut avail_sq = sq.available();
+        let (submitter, mut sq, _) = self.io_uring.split();
 
         // Safe because we know the file descriptor is valid and we
         // relied on vm-memory to provide the buffer address.
         let _ = unsafe {
-            avail_sq.push(
-                opcode::Readv::new(
-                    opcode::types::Fd(self.fd),
-                    iovecs.as_ptr(),
-                    iovecs.len() as u32,
-                )
-                .offset(offset)
-                .build()
-                .flags(squeue::Flags::ASYNC)
-                .user_data(user_data),
+            sq.push(
+                &opcode::Readv::new(types::Fd(self.fd), iovecs.as_ptr(), iovecs.len() as u32)
+                    .offset(offset)
+                    .build()
+                    .flags(squeue::Flags::ASYNC)
+                    .user_data(user_data),
             )
         };
 
         // Update the submission queue and submit new operations to the
         // io_uring instance.
-        avail_sq.sync();
+        sq.sync();
         submitter.submit().map_err(AsyncIoError::ReadVectored)?;
 
         Ok(())
@@ -104,28 +99,23 @@ impl AsyncIo for RawFileAsync {
         iovecs: Vec<libc::iovec>,
         user_data: u64,
     ) -> AsyncIoResult<()> {
-        let (submitter, sq, _) = self.io_uring.split();
-        let mut avail_sq = sq.available();
+        let (submitter, mut sq, _) = self.io_uring.split();
 
         // Safe because we know the file descriptor is valid and we
         // relied on vm-memory to provide the buffer address.
         let _ = unsafe {
-            avail_sq.push(
-                opcode::Writev::new(
-                    opcode::types::Fd(self.fd),
-                    iovecs.as_ptr(),
-                    iovecs.len() as u32,
-                )
-                .offset(offset)
-                .build()
-                .flags(squeue::Flags::ASYNC)
-                .user_data(user_data),
+            sq.push(
+                &opcode::Writev::new(types::Fd(self.fd), iovecs.as_ptr(), iovecs.len() as u32)
+                    .offset(offset)
+                    .build()
+                    .flags(squeue::Flags::ASYNC)
+                    .user_data(user_data),
             )
         };
 
         // Update the submission queue and submit new operations to the
         // io_uring instance.
-        avail_sq.sync();
+        sq.sync();
         submitter.submit().map_err(AsyncIoError::WriteVectored)?;
 
         Ok(())
@@ -133,13 +123,12 @@ impl AsyncIo for RawFileAsync {
 
     fn fsync(&mut self, user_data: Option<u64>) -> AsyncIoResult<()> {
         if let Some(user_data) = user_data {
-            let (submitter, sq, _) = self.io_uring.split();
-            let mut avail_sq = sq.available();
+            let (submitter, mut sq, _) = self.io_uring.split();
 
             // Safe because we know the file descriptor is valid.
             let _ = unsafe {
-                avail_sq.push(
-                    opcode::Fsync::new(opcode::types::Fd(self.fd))
+                sq.push(
+                    &opcode::Fsync::new(types::Fd(self.fd))
                         .build()
                         .flags(squeue::Flags::ASYNC)
                         .user_data(user_data),
@@ -148,7 +137,7 @@ impl AsyncIo for RawFileAsync {
 
             // Update the submission queue and submit new operations to the
             // io_uring instance.
-            avail_sq.sync();
+            sq.sync();
             submitter.submit().map_err(AsyncIoError::Fsync)?;
         } else {
             unsafe { libc::fsync(self.fd) };
@@ -161,7 +150,7 @@ impl AsyncIo for RawFileAsync {
         let mut completion_list = Vec::new();
 
         let cq = self.io_uring.completion();
-        for cq_entry in cq.available() {
+        for cq_entry in cq {
             completion_list.push((cq_entry.user_data(), cq_entry.result()));
         }
 

block_util/src/vhd.rs

@@ -124,7 +124,7 @@ mod tests {
     use super::{is_fixed_vhd, VhdFooter};
     use std::fs::File;
     use std::io::{Seek, SeekFrom, Write};
-    use tempfile::tempfile;
+    use vmm_sys_util::tempfile::TempFile;
 
     fn valid_fixed_vhd_footer() -> Vec<u8> {
         vec![
@@ -172,10 +172,10 @@ mod tests {
     where
         F: FnMut(File),
     {
-        let mut disk_file: File = tempfile().unwrap();
+        let mut disk_file: File = TempFile::new().unwrap().into_file();
         disk_file.set_len(0x1000_0200).unwrap();
         disk_file.seek(SeekFrom::Start(0x1000_0000)).unwrap();
-        disk_file.write_all(&footer).unwrap();
+        disk_file.write_all(footer).unwrap();
 
         testfn(disk_file); // File closed when the function exits.
     }

devices/Cargo.toml

@@ -2,26 +2,24 @@
 name = "devices"
 version = "0.1.0"
 authors = ["The Chromium OS Authors"]
+edition = "2018"
 
 [dependencies]
-anyhow = "1.0"
-bitflags = ">=1.2.1"
-byteorder = "1.3.4"
-epoll = ">=4.0.1"
-libc = "0.2.86"
-log = "0.4.14"
-serde = {version = ">=1.0.27", features = ["rc"] }
-serde_derive = ">=1.0.27"
-serde_json = ">=1.0.9"
-vm-device = { path = "../vm-device" }
 acpi_tables = { path = "../acpi_tables", optional = true }
+anyhow = "1.0"
+arch = { path = "../arch" }
+bitflags = ">=1.2.1"
+byteorder = "1.4.3"
+epoll = ">=4.0.1"
+libc = "0.2.98"
+log = "0.4.14"
+versionize = "0.1.6"
+versionize_derive = "0.1.4"
+vm-device = { path = "../vm-device" }
 vm-memory = "0.5.0"
 vm-migration = { path = "../vm-migration" }
 vmm-sys-util = ">=0.3.1"
 
-[dev-dependencies]
-tempfile = "3.2.0"
-
 [features]
 default = []
 acpi = ["acpi_tables"]

devices/src/acpi.rs

@@ -3,6 +3,7 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 
+use super::AcpiNotificationFlags;
 use acpi_tables::{aml, aml::Aml};
 use std::sync::{Arc, Barrier};
 use std::time::Instant;
@@ -10,7 +11,6 @@ use vm_device::interrupt::InterruptSourceGroup;
 use vm_device::BusDevice;
 use vm_memory::GuestAddress;
 use vmm_sys_util::eventfd::EventFd;
-use AcpiNotificationFlags;
 
 pub const GED_DEVICE_ACPI_SIZE: usize = 0x1;
 
@@ -52,7 +52,6 @@ impl BusDevice for AcpiShutdownDevice {
         const SLEEP_VALUE_BIT: u8 = 2;
         if data[0] == (S5_SLEEP_VALUE << SLEEP_VALUE_BIT) | (1 << SLEEP_STATUS_EN_BIT) {
             debug!("ACPI Shutdown signalled");
-            extern crate bitflags;
             if let Err(e) = self.exit_evt.write(1) {
                 error!("Error triggering ACPI shutdown event: {}", e);
             }
@@ -62,20 +61,20 @@ impl BusDevice for AcpiShutdownDevice {
 }
 
 /// A device for handling ACPI GED event generation
-pub struct AcpiGEDDevice {
+pub struct AcpiGedDevice {
     interrupt: Arc<Box<dyn InterruptSourceGroup>>,
     notification_type: AcpiNotificationFlags,
     ged_irq: u32,
     address: GuestAddress,
 }
 
-impl AcpiGEDDevice {
+impl AcpiGedDevice {
     pub fn new(
         interrupt: Arc<Box<dyn InterruptSourceGroup>>,
         ged_irq: u32,
         address: GuestAddress,
-    ) -> AcpiGEDDevice {
-        AcpiGEDDevice {
+    ) -> AcpiGedDevice {
+        AcpiGedDevice {
             interrupt,
             notification_type: AcpiNotificationFlags::NO_DEVICES_CHANGED,
             ged_irq,
@@ -97,7 +96,7 @@ impl AcpiGEDDevice {
 }
 
 // I/O port reports what type of notification was made
-impl BusDevice for AcpiGEDDevice {
+impl BusDevice for AcpiGedDevice {
     // Spec has all fields as zero
     fn read(&mut self, _base: u64, _offset: u64, data: &mut [u8]) {
         data[0] = self.notification_type.bits();
@@ -106,7 +105,7 @@ impl BusDevice for AcpiGEDDevice {
 }
 
 #[cfg(feature = "acpi")]
-impl Aml for AcpiGEDDevice {
+impl Aml for AcpiGedDevice {
     fn to_aml_bytes(&self) -> Vec<u8> {
         aml::Device::new(
             "_SB_.GED_".into(),
@@ -172,11 +171,11 @@ impl Aml for AcpiGEDDevice {
     }
 }
 
-pub struct AcpiPMTimerDevice {
+pub struct AcpiPmTimerDevice {
     start: Instant,
 }
 
-impl AcpiPMTimerDevice {
+impl AcpiPmTimerDevice {
     pub fn new() -> Self {
         Self {
             start: Instant::now(),
@@ -184,13 +183,13 @@ impl AcpiPMTimerDevice {
     }
 }
 
-impl Default for AcpiPMTimerDevice {
+impl Default for AcpiPmTimerDevice {
     fn default() -> Self {
         Self::new()
     }
 }
 
-impl BusDevice for AcpiPMTimerDevice {
+impl BusDevice for AcpiPmTimerDevice {
     fn read(&mut self, _base: u64, _offset: u64, data: &mut [u8]) {
         let now = Instant::now();
         let since = now.duration_since(self.start);

devices/src/gic.rs

@@ -3,19 +3,21 @@
 // SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
 
 use super::interrupt_controller::{Error, InterruptController};
+extern crate arch;
+use arch::aarch64::gic::GicDevice;
 use std::result;
-use std::sync::Arc;
+use std::sync::{Arc, Mutex};
 use vm_device::interrupt::{
-    InterruptIndex, InterruptManager, InterruptSourceGroup, MsiIrqGroupConfig,
+    InterruptIndex, InterruptManager, InterruptSourceConfig, InterruptSourceGroup,
+    LegacyIrqSourceConfig, MsiIrqGroupConfig,
 };
 use vmm_sys_util::eventfd::EventFd;
 
 type Result<T> = result::Result<T, Error>;
 
-// Reserve 32 IRQs (GSI 32 ~ 64) for legacy device.
-// GsiAllocator should allocate beyond this: from 64 on
+// Reserve 32 IRQs for legacy device.
+pub const IRQ_LEGACY_BASE: usize = arch::layout::IRQ_BASE as usize;
 pub const IRQ_LEGACY_COUNT: usize = 32;
-pub const IRQ_SPI_OFFSET: usize = 32;
 
 // This Gic struct implements InterruptController to provide interrupt delivery service.
 // The Gic source files in arch/ folder maintain the Aarch64 specific Gic device.
@@ -25,6 +27,7 @@ pub const IRQ_SPI_OFFSET: usize = 32;
 //   2. Move this file and ioapic.rs to arch/, as they are architecture specific.
 pub struct Gic {
     interrupt_source_group: Arc<Box<dyn InterruptSourceGroup>>,
+    gic_device: Option<Arc<Mutex<Box<dyn GicDevice>>>>,
 }
 
 impl Gic {
@@ -34,22 +37,48 @@ impl Gic {
     ) -> Result<Gic> {
         let interrupt_source_group = interrupt_manager
             .create_group(MsiIrqGroupConfig {
-                base: IRQ_SPI_OFFSET as InterruptIndex,
+                base: IRQ_LEGACY_BASE as InterruptIndex,
                 count: IRQ_LEGACY_COUNT as InterruptIndex,
             })
             .map_err(Error::CreateInterruptSourceGroup)?;
 
         Ok(Gic {
             interrupt_source_group,
+            gic_device: None,
         })
     }
+
+    pub fn set_gic_device(&mut self, gic_device: Arc<Mutex<Box<dyn GicDevice>>>) {
+        self.gic_device = Some(gic_device);
+    }
+
+    pub fn get_gic_device(&self) -> Option<&Arc<Mutex<Box<dyn GicDevice>>>> {
+        self.gic_device.as_ref()
+    }
 }
 
 impl InterruptController for Gic {
     fn enable(&self) -> Result<()> {
+        // Set irqfd for legacy interrupts
         self.interrupt_source_group
             .enable()
             .map_err(Error::EnableInterrupt)?;
+
+        // Set irq_routing for legacy interrupts.
+        //   irqchip: Hardcode to 0 as we support only 1 GIC
+        //   pin: Use irq number as pin
+        for i in IRQ_LEGACY_BASE..(IRQ_LEGACY_BASE + IRQ_LEGACY_COUNT) {
+            let config = LegacyIrqSourceConfig {
+                irqchip: 0,
+                pin: (i - IRQ_LEGACY_BASE) as u32,
+            };
+            self.interrupt_source_group
+                .update(
+                    i as InterruptIndex,
+                    InterruptSourceConfig::LegacyIrq(config),
+                )
+                .map_err(Error::EnableInterrupt)?;
+        }
         Ok(())
     }
 

devices/src/ioapic.rs

@@ -14,6 +14,8 @@ use anyhow::anyhow;
 use byteorder::{ByteOrder, LittleEndian};
 use std::result;
 use std::sync::{Arc, Barrier};
+use versionize::{VersionMap, Versionize, VersionizeResult};
+use versionize_derive::Versionize;
 use vm_device::interrupt::{
     InterruptIndex, InterruptManager, InterruptSourceConfig, InterruptSourceGroup,
     MsiIrqGroupConfig, MsiIrqSourceConfig,
@@ -21,15 +23,10 @@ use vm_device::interrupt::{
 use vm_device::BusDevice;
 use vm_memory::GuestAddress;
 use vm_migration::{
-    Migratable, MigratableError, Pausable, Snapshot, SnapshotDataSection, Snapshottable,
-    Transportable,
+    Migratable, MigratableError, Pausable, Snapshot, Snapshottable, Transportable, VersionMapped,
 };
 use vmm_sys_util::eventfd::EventFd;
 
-#[derive(Serialize, Deserialize)]
-#[serde(remote = "GuestAddress")]
-pub struct GuestAddressDef(pub u64);
-
 type Result<T> = result::Result<T, Error>;
 
 // I/O REDIRECTION TABLE REGISTER
@@ -113,9 +110,9 @@ enum TriggerMode {
 enum DeliveryMode {
     Fixed = 0b000,
     Lowest = 0b001,
-    SMI = 0b010,        // System management interrupt
+    Smi = 0b010,        // System management interrupt
     RemoteRead = 0b011, // This is no longer supported by intel.
-    NMI = 0b100,        // Non maskable interrupt
+    Nmi = 0b100,        // Non maskable interrupt
     Init = 0b101,
     Startup = 0b110,
     External = 0b111,
@@ -140,15 +137,15 @@ pub struct Ioapic {
     interrupt_source_group: Arc<Box<dyn InterruptSourceGroup>>,
 }
 
-#[derive(Serialize, Deserialize)]
+#[derive(Versionize)]
 pub struct IoapicState {
     id_reg: u32,
     reg_sel: u32,
     reg_entries: [RedirectionTableEntry; NUM_IOAPIC_PINS],
     used_entries: [bool; NUM_IOAPIC_PINS],
-    #[serde(with = "GuestAddressDef")]
-    apic_address: GuestAddress,
+    apic_address: u64,
 }
+impl VersionMapped for IoapicState {}
 
 impl BusDevice for Ioapic {
     fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
@@ -284,7 +281,7 @@ impl Ioapic {
             reg_sel: self.reg_sel,
             reg_entries: self.reg_entries,
             used_entries: self.used_entries,
-            apic_address: self.apic_address,
+            apic_address: self.apic_address.0,
         }
     }
 
@@ -293,7 +290,7 @@ impl Ioapic {
         self.reg_sel = state.reg_sel;
         self.reg_entries = state.reg_entries;
         self.used_entries = state.used_entries;
-        self.apic_address = state.apic_address;
+        self.apic_address = GuestAddress(state.apic_address);
         for (irq, entry) in self.used_entries.iter().enumerate() {
             if *entry {
                 self.update_entry(irq)?;
@@ -333,9 +330,9 @@ impl Ioapic {
         match delivery_mode {
             x if (x == DeliveryMode::Fixed as u8)
                 || (x == DeliveryMode::Lowest as u8)
-                || (x == DeliveryMode::SMI as u8)
+                || (x == DeliveryMode::Smi as u8)
                 || (x == DeliveryMode::RemoteRead as u8)
-                || (x == DeliveryMode::NMI as u8)
+                || (x == DeliveryMode::Nmi as u8)
                 || (x == DeliveryMode::Init as u8)
                 || (x == DeliveryMode::Startup as u8)
                 || (x == DeliveryMode::External as u8) => {}
@@ -418,38 +415,18 @@ impl Snapshottable for Ioapic {
     }
 
     fn snapshot(&mut self) -> std::result::Result<Snapshot, MigratableError> {
-        let snapshot =
-            serde_json::to_vec(&self.state()).map_err(|e| MigratableError::Snapshot(e.into()))?;
-
-        let mut ioapic_snapshot = Snapshot::new(self.id.as_str());
-        ioapic_snapshot.add_data_section(SnapshotDataSection {
-            id: format!("{}-section", self.id),
-            snapshot,
-        });
-
-        Ok(ioapic_snapshot)
+        Snapshot::new_from_versioned_state(&self.id, &self.state())
     }
 
     fn restore(&mut self, snapshot: Snapshot) -> std::result::Result<(), MigratableError> {
-        if let Some(ioapic_section) = snapshot.snapshot_data.get(&format!("{}-section", self.id)) {
-            let ioapic_state = match serde_json::from_slice(&ioapic_section.snapshot) {
-                Ok(state) => state,
-                Err(error) => {
-                    return Err(MigratableError::Restore(anyhow!(
-                        "Could not deserialize IOAPIC {}",
-                        error
-                    )))
-                }
-            };
-
-            return self.set_state(&ioapic_state).map_err(|e| {
-                MigratableError::Restore(anyhow!("Could not restore IOAPIC state {:?}", e))
-            });
-        }
-
-        Err(MigratableError::Restore(anyhow!(
-            "Could not find IOAPIC snapshot section"
-        )))
+        self.set_state(&snapshot.to_versioned_state(&self.id)?)
+            .map_err(|e| {
+                MigratableError::Restore(anyhow!(
+                    "Could not restore state for {}: {:?}",
+                    self.id,
+                    e
+                ))
+            })
     }
 }
 

devices/src/legacy/gpio_pl061.rs

@@ -0,0 +1,460 @@
+// Copyright 2021 Arm Limited (or its affiliates). All rights reserved.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+//! ARM PrimeCell General Purpose Input/Output(PL061)
+//!
+//! This module implements an ARM PrimeCell General Purpose Input/Output(PL061) to support gracefully poweroff microvm from external.
+//!
+
+use crate::{read_le_u32, write_le_u32};
+use std::result;
+use std::sync::{Arc, Barrier};
+use std::{fmt, io};
+use versionize::{VersionMap, Versionize, VersionizeResult};
+use versionize_derive::Versionize;
+use vm_device::interrupt::InterruptSourceGroup;
+use vm_device::BusDevice;
+use vm_migration::{
+    Migratable, MigratableError, Pausable, Snapshot, Snapshottable, Transportable, VersionMapped,
+};
+
+const OFS_DATA: u64 = 0x400; // Data Register
+const GPIODIR: u64 = 0x400; // Direction Register
+const GPIOIS: u64 = 0x404; // Interrupt Sense Register
+const GPIOIBE: u64 = 0x408; // Interrupt Both Edges Register
+const GPIOIEV: u64 = 0x40c; // Interrupt Event Register
+const GPIOIE: u64 = 0x410; // Interrupt Mask Register
+const GPIORIE: u64 = 0x414; // Raw Interrupt Status Register
+const GPIOMIS: u64 = 0x418; // Masked Interrupt Status Register
+const GPIOIC: u64 = 0x41c; // Interrupt Clear Register
+const GPIOAFSEL: u64 = 0x420; // Mode Control Select Register
+                              // From 0x424 to 0xFDC => reserved space.
+                              // From 0xFE0 to 0xFFC => Peripheral and PrimeCell Identification Registers which are Read Only registers.
+                              // Thses registers can conceptually be treated as a 32-bit register, and PartNumber[11:0] is used to identify the peripheral.
+                              // We are putting the expected values (look at 'Reset value' column from above mentioned document) in an array.
+const GPIO_ID: [u8; 8] = [0x61, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1];
+// ID Margins
+const GPIO_ID_LOW: u64 = 0xfe0;
+const GPIO_ID_HIGH: u64 = 0x1000;
+
+const N_GPIOS: u32 = 8;
+
+#[derive(Debug)]
+pub enum Error {
+    BadWriteOffset(u64),
+    GpioInterruptDisabled,
+    GpioInterruptFailure(io::Error),
+    GpioTriggerKeyFailure(u32),
+}
+
+impl fmt::Display for Error {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        match self {
+            Error::BadWriteOffset(offset) => write!(f, "Bad Write Offset: {}", offset),
+            Error::GpioInterruptDisabled => write!(f, "GPIO interrupt disabled by guest driver.",),
+            Error::GpioInterruptFailure(ref e) => {
+                write!(f, "Could not trigger GPIO interrupt: {}.", e)
+            }
+            Error::GpioTriggerKeyFailure(key) => {
+                write!(f, "Invalid GPIO Input key triggerd: {}.", key)
+            }
+        }
+    }
+}
+
+type Result<T> = result::Result<T, Error>;
+
+/// A GPIO device following the PL061 specification.
+pub struct Gpio {
+    id: String,
+    // Data Register
+    data: u32,
+    old_in_data: u32,
+    // Direction Register
+    dir: u32,
+    // Interrupt Sense Register
+    isense: u32,
+    // Interrupt Both Edges Register
+    ibe: u32,
+    // Interrupt Event Register
+    iev: u32,
+    // Interrupt Mask Register
+    im: u32,
+    // Raw Interrupt Status Register
+    istate: u32,
+    // Mode Control Select Register
+    afsel: u32,
+    // GPIO irq_field
+    interrupt: Arc<Box<dyn InterruptSourceGroup>>,
+}
+
+#[derive(Versionize)]
+pub struct GpioState {
+    data: u32,
+    old_in_data: u32,
+    dir: u32,
+    isense: u32,
+    ibe: u32,
+    iev: u32,
+    im: u32,
+    istate: u32,
+    afsel: u32,
+}
+
+impl VersionMapped for GpioState {}
+
+impl Gpio {
+    /// Constructs an PL061 GPIO device.
+    pub fn new(id: String, interrupt: Arc<Box<dyn InterruptSourceGroup>>) -> Self {
+        Self {
+            id,
+            data: 0,
+            old_in_data: 0,
+            dir: 0,
+            isense: 0,
+            ibe: 0,
+            iev: 0,
+            im: 0,
+            istate: 0,
+            afsel: 0,
+            interrupt,
+        }
+    }
+
+    fn state(&self) -> GpioState {
+        GpioState {
+            data: self.data,
+            old_in_data: self.old_in_data,
+            dir: self.dir,
+            isense: self.isense,
+            ibe: self.ibe,
+            iev: self.iev,
+            im: self.im,
+            istate: self.istate,
+            afsel: self.afsel,
+        }
+    }
+
+    fn set_state(&mut self, state: &GpioState) {
+        self.data = state.data;
+        self.old_in_data = state.old_in_data;
+        self.dir = state.dir;
+        self.isense = state.isense;
+        self.ibe = state.ibe;
+        self.iev = state.iev;
+        self.im = state.im;
+        self.istate = state.istate;
+        self.afsel = state.afsel;
+    }
+
+    fn pl061_internal_update(&mut self) {
+        // FIXME:
+        //  Missing Output Interrupt Emulation.
+
+        // Input Edging Interrupt Emulation.
+        let changed = ((self.old_in_data ^ self.data) & !self.dir) as u32;
+        if changed > 0 {
+            self.old_in_data = self.data;
+            for i in 0..N_GPIOS {
+                let mask = (1 << i) as u32;
+                if (changed & mask) > 0 {
+                    // Bits set high in GPIOIS(Interrupt sense register) configure the corresponding
+                    // pins to detect levels, otherwise, detect edges.
+                    if (self.isense & mask) == 0 {
+                        if (self.ibe & mask) > 0 {
+                            // Bits set high in GPIOIBE(Interrupt both-edges register) configure the corresponding
+                            // pins to detect both falling and rising edges.
+                            // Clearing a bit configures the pin to be controlled by GPIOIEV.
+                            self.istate |= mask;
+                        } else {
+                            // Bits set to high in GPIOIEV(Interrupt event register) configure the
+                            // corresponding pin to detect rising edges, otherwise, detect falling edges.
+                            self.istate |= !(self.data ^ self.iev) & mask;
+                        }
+                    }
+                }
+            }
+        }
+
+        // Input Level Interrupt Emulation.
+        self.istate |= !(self.data ^ self.iev) & self.isense;
+    }
+
+    fn handle_write(&mut self, offset: u64, val: u32) -> Result<()> {
+        if offset < OFS_DATA {
+            // In order to write to data register, the corresponding bits in the mask, resulting
+            // from the offsite[9:2], must be HIGH. otherwise the bit values remain unchanged.
+            let mask = (offset >> 2) as u32 & self.dir;
+            self.data = (self.data & !mask) | (val & mask);
+        } else {
+            match offset {
+                GPIODIR => {
+                    /* Direction Register */
+                    self.dir = val & 0xff;
+                }
+                GPIOIS => {
+                    /* Interrupt Sense Register */
+                    self.isense = val & 0xff;
+                }
+                GPIOIBE => {
+                    /* Interrupt Both Edges Register */
+                    self.ibe = val & 0xff;
+                }
+                GPIOIEV => {
+                    /* Interrupt Event Register */
+                    self.iev = val & 0xff;
+                }
+                GPIOIE => {
+                    /* Interrupt Mask Register */
+                    self.im = val & 0xff;
+                }
+                GPIOIC => {
+                    /* Interrupt Clear Register */
+                    self.istate &= !val;
+                }
+                GPIOAFSEL => {
+                    /* Mode Control Select Register */
+                    self.afsel = val & 0xff;
+                }
+                o => {
+                    return Err(Error::BadWriteOffset(o));
+                }
+            }
+        }
+        Ok(())
+    }
+
+    pub fn trigger_key(&mut self, key: u32) -> Result<()> {
+        let mask = (1 << key) as u32;
+        if (!self.dir & mask) > 0 {
+            // emulate key event
+            // By default, Input Pin is configured to detect both rising and falling edges.
+            // So reverse the input pin data to generate a pulse.
+            self.data |= !(self.data & mask) & mask;
+            self.pl061_internal_update();
+
+            match self.trigger_gpio_interrupt() {
+                Ok(_) | Err(Error::GpioInterruptDisabled) => return Ok(()),
+                Err(e) => return Err(e),
+            }
+        }
+
+        Err(Error::GpioTriggerKeyFailure(key))
+    }
+
+    fn trigger_gpio_interrupt(&self) -> Result<()> {
+        // Bits set to high in GPIOIE(Interrupt mask register) allow the corresponding pins to
+        // trigger their individual interrupts and then the combined GPIOINTR line.
+        if (self.istate & self.im) == 0 {
+            warn!("Failed to trigger GPIO input interrupt (disabled by guest OS)");
+            return Err(Error::GpioInterruptDisabled);
+        }
+        self.interrupt
+            .trigger(0)
+            .map_err(Error::GpioInterruptFailure)?;
+        Ok(())
+    }
+}
+
+impl BusDevice for Gpio {
+    fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
+        let value;
+        let mut read_ok = true;
+
+        if (GPIO_ID_LOW..GPIO_ID_HIGH).contains(&offset) {
+            let index = ((offset - GPIO_ID_LOW) >> 2) as usize;
+            value = u32::from(GPIO_ID[index]);
+        } else if offset < OFS_DATA {
+            value = self.data & ((offset >> 2) as u32)
+        } else {
+            value = match offset {
+                GPIODIR => self.dir,
+                GPIOIS => self.isense,
+                GPIOIBE => self.ibe,
+                GPIOIEV => self.iev,
+                GPIOIE => self.im,
+                GPIORIE => self.istate,
+                GPIOMIS => self.istate & self.im,
+                GPIOAFSEL => self.afsel,
+                _ => {
+                    read_ok = false;
+                    0
+                }
+            };
+        }
+
+        if read_ok && data.len() <= 4 {
+            write_le_u32(data, value);
+        } else {
+            warn!(
+                "Invalid GPIO PL061 read: offset {}, data length {}",
+                offset,
+                data.len()
+            );
+        }
+    }
+
+    fn write(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
+        if data.len() <= 4 {
+            let value = read_le_u32(data);
+            if let Err(e) = self.handle_write(offset, value) {
+                warn!("Failed to write to GPIO PL061 device: {}", e);
+            }
+        } else {
+            warn!(
+                "Invalid GPIO PL061 write: offset {}, data length {}",
+                offset,
+                data.len()
+            );
+        }
+
+        None
+    }
+}
+
+impl Snapshottable for Gpio {
+    fn id(&self) -> String {
+        self.id.clone()
+    }
+
+    fn snapshot(&mut self) -> std::result::Result<Snapshot, MigratableError> {
+        Snapshot::new_from_versioned_state(&self.id, &self.state())
+    }
+
+    fn restore(&mut self, snapshot: Snapshot) -> std::result::Result<(), MigratableError> {
+        self.set_state(&snapshot.to_versioned_state(&self.id)?);
+        Ok(())
+    }
+}
+
+impl Pausable for Gpio {}
+impl Transportable for Gpio {}
+impl Migratable for Gpio {}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+    use crate::{read_le_u32, write_le_u32};
+    use std::sync::Arc;
+    use vm_device::interrupt::{InterruptIndex, InterruptSourceConfig};
+    use vmm_sys_util::eventfd::EventFd;
+
+    const GPIO_NAME: &str = "gpio";
+    const LEGACY_GPIO_MAPPED_IO_START: u64 = 0x0902_0000;
+
+    struct TestInterrupt {
+        event_fd: EventFd,
+    }
+
+    impl InterruptSourceGroup for TestInterrupt {
+        fn trigger(&self, _index: InterruptIndex) -> result::Result<(), std::io::Error> {
+            self.event_fd.write(1)
+        }
+
+        fn update(
+            &self,
+            _index: InterruptIndex,
+            _config: InterruptSourceConfig,
+        ) -> result::Result<(), std::io::Error> {
+            Ok(())
+        }
+
+        fn notifier(&self, _index: InterruptIndex) -> Option<EventFd> {
+            Some(self.event_fd.try_clone().unwrap())
+        }
+    }
+
+    impl TestInterrupt {
+        fn new(event_fd: EventFd) -> Self {
+            TestInterrupt { event_fd }
+        }
+    }
+
+    #[test]
+    fn test_gpio_read_write_and_event() {
+        let intr_evt = EventFd::new(libc::EFD_NONBLOCK).unwrap();
+        let mut gpio = Gpio::new(
+            String::from(GPIO_NAME),
+            Arc::new(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap()))),
+        );
+        let mut data = [0; 4];
+
+        // Read and write to the GPIODIR register.
+        // Set pin 0 output pin.
+        write_le_u32(&mut data, 1);
+        gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIODIR, &data);
+        gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIODIR, &mut data);
+        let v = read_le_u32(&data);
+        assert_eq!(v, 1);
+
+        // Read and write to the GPIODATA register.
+        write_le_u32(&mut data, 1);
+        // Set pin 0 high.
+        let offset = 0x00000004_u64;
+        gpio.write(LEGACY_GPIO_MAPPED_IO_START, offset, &data);
+        gpio.read(LEGACY_GPIO_MAPPED_IO_START, offset, &mut data);
+        let v = read_le_u32(&data);
+        assert_eq!(v, 1);
+
+        // Read and write to the GPIOIS register.
+        // Configure pin 0 detecting level interrupt.
+        write_le_u32(&mut data, 1);
+        gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIS, &data);
+        gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOIS, &mut data);
+        let v = read_le_u32(&data);
+        assert_eq!(v, 1);
+
+        // Read and write to the GPIOIBE register.
+        // Configure pin 1 detecting both falling and rising edges.
+        write_le_u32(&mut data, 2);
+        gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIBE, &data);
+        gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOIBE, &mut data);
+        let v = read_le_u32(&data);
+        assert_eq!(v, 2);
+
+        // Read and write to the GPIOIEV register.
+        // Configure pin 2 detecting both falling and rising edges.
+        write_le_u32(&mut data, 4);
+        gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIEV, &data);
+        gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOIEV, &mut data);
+        let v = read_le_u32(&data);
+        assert_eq!(v, 4);
+
+        // Read and write to the GPIOIE register.
+        // Configure pin 0...2 capable of triggering their individual interrupts
+        // and then the combined GPIOINTR line.
+        write_le_u32(&mut data, 7);
+        gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIE, &data);
+        gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOIE, &mut data);
+        let v = read_le_u32(&data);
+        assert_eq!(v, 7);
+
+        let mask = 0x00000002_u32;
+        // emulate an rising pulse in pin 1.
+        gpio.data |= !(gpio.data & mask) & mask;
+        gpio.pl061_internal_update();
+        // The interrupt line on pin 1 should be on.
+        // Read the GPIOMIS register.
+        gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOMIS, &mut data);
+        let v = read_le_u32(&data);
+        assert_eq!(v, 2);
+
+        // Read and Write to the GPIOIC register.
+        // clear interrupt in pin 1.
+        write_le_u32(&mut data, 2);
+        gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIC, &data);
+        gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOIC, &mut data);
+        let v = read_le_u32(&data);
+        assert_eq!(v, 2);
+
+        // Attempts to write beyond the writable space.
+        write_le_u32(&mut data, 0);
+        gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIO_ID_LOW, &data);
+
+        let mut data = [0; 4];
+        gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIO_ID_LOW, &mut data);
+        let index = GPIO_ID_LOW + 3;
+        assert_eq!(data[0], GPIO_ID[((index - GPIO_ID_LOW) >> 2) as usize]);
+    }
+}

devices/src/legacy/mod.rs

@@ -9,10 +9,14 @@
 mod cmos;
 #[cfg(feature = "fwdebug")]
 mod fwdebug;
+#[cfg(target_arch = "aarch64")]
+mod gpio_pl061;
 mod i8042;
 #[cfg(target_arch = "aarch64")]
 mod rtc_pl031;
 mod serial;
+#[cfg(target_arch = "aarch64")]
+mod uart_pl011;
 
 #[cfg(feature = "cmos")]
 pub use self::cmos::Cmos;
@@ -22,4 +26,10 @@ pub use self::i8042::I8042Device;
 pub use self::serial::Serial;
 
 #[cfg(target_arch = "aarch64")]
-pub use self::rtc_pl031::RTC;
+pub use self::gpio_pl061::Error as GpioDeviceError;
+#[cfg(target_arch = "aarch64")]
+pub use self::gpio_pl061::Gpio;
+#[cfg(target_arch = "aarch64")]
+pub use self::rtc_pl031::Rtc;
+#[cfg(target_arch = "aarch64")]
+pub use self::uart_pl011::Pl011;

devices/src/legacy/rtc_pl031.rs

@@ -8,6 +8,7 @@
 //! This is achieved by generating an interrupt signal after counting for a programmed number of cycles of
 //! a real-time clock input.
 //!
+use crate::{read_le_u32, write_le_u32};
 use std::fmt;
 use std::sync::{Arc, Barrier};
 use std::time::Instant;
@@ -38,52 +39,6 @@ const AMBA_ID_HIGH: u64 = 0x1000;
 /// Constant to convert seconds to nanoseconds.
 pub const NANOS_PER_SECOND: u64 = 1_000_000_000;
 
-#[allow(unused_macros)]
-macro_rules! generate_read_fn {
-    ($fn_name: ident, $data_type: ty, $byte_type: ty, $type_size: expr, $endian_type: ident) => {
-        #[allow(dead_code)]
-        pub fn $fn_name(input: &[$byte_type]) -> $data_type {
-            assert!($type_size == std::mem::size_of::<$data_type>());
-            let mut array = [0u8; $type_size];
-            for (byte, read) in array.iter_mut().zip(input.iter().cloned()) {
-                *byte = read as u8;
-            }
-            <$data_type>::$endian_type(array)
-        }
-    };
-}
-
-#[allow(unused_macros)]
-macro_rules! generate_write_fn {
-    ($fn_name: ident, $data_type: ty, $byte_type: ty, $endian_type: ident) => {
-        #[allow(dead_code)]
-        pub fn $fn_name(buf: &mut [$byte_type], n: $data_type) {
-            for (byte, read) in buf
-                .iter_mut()
-                .zip(<$data_type>::$endian_type(n).iter().cloned())
-            {
-                *byte = read as $byte_type;
-            }
-        }
-    };
-}
-
-generate_read_fn!(read_le_u16, u16, u8, 2, from_le_bytes);
-generate_read_fn!(read_le_u32, u32, u8, 4, from_le_bytes);
-generate_read_fn!(read_le_u64, u64, u8, 8, from_le_bytes);
-generate_read_fn!(read_le_i32, i32, i8, 4, from_le_bytes);
-
-generate_read_fn!(read_be_u16, u16, u8, 2, from_be_bytes);
-generate_read_fn!(read_be_u32, u32, u8, 4, from_be_bytes);
-
-generate_write_fn!(write_le_u16, u16, u8, to_le_bytes);
-generate_write_fn!(write_le_u32, u32, u8, to_le_bytes);
-generate_write_fn!(write_le_u64, u64, u8, to_le_bytes);
-generate_write_fn!(write_le_i32, i32, i8, to_le_bytes);
-
-generate_write_fn!(write_be_u16, u16, u8, to_be_bytes);
-generate_write_fn!(write_be_u32, u32, u8, to_be_bytes);
-
 #[derive(Debug)]
 pub enum Error {
     BadWriteOffset(u64),
@@ -115,9 +70,9 @@ pub enum ClockType {
     ThreadCpu,
 }
 
-impl Into<libc::clockid_t> for ClockType {
-    fn into(self) -> libc::clockid_t {
-        match self {
+impl From<ClockType> for libc::clockid_t {
+    fn from(ct: ClockType) -> libc::clockid_t {
+        match ct {
             ClockType::Monotonic => libc::CLOCK_MONOTONIC,
             ClockType::Real => libc::CLOCK_REALTIME,
             ClockType::ProcessCpu => libc::CLOCK_PROCESS_CPUTIME_ID,
@@ -260,7 +215,7 @@ pub fn seconds_to_nanoseconds(value: i64) -> Option<i64> {
 }
 
 /// A RTC device following the PL031 specification..
-pub struct RTC {
+pub struct Rtc {
     previous_now: Instant,
     tick_offset: i64,
     // This is used for implementing the RTC alarm. However, in Firecracker we do not need it.
@@ -272,10 +227,10 @@ pub struct RTC {
     interrupt: Arc<Box<dyn InterruptSourceGroup>>,
 }
 
-impl RTC {
+impl Rtc {
     /// Constructs an AMBA PL031 RTC device.
-    pub fn new(interrupt: Arc<Box<dyn InterruptSourceGroup>>) -> RTC {
-        RTC {
+    pub fn new(interrupt: Arc<Box<dyn InterruptSourceGroup>>) -> Self {
+        Self {
             // This is used only for duration measuring purposes.
             previous_now: Instant::now(),
             tick_offset: get_time(ClockType::Real) as i64,
@@ -334,7 +289,7 @@ impl RTC {
     }
 }
 
-impl BusDevice for RTC {
+impl BusDevice for Rtc {
     fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
         let v;
         let mut read_ok = true;
@@ -373,7 +328,7 @@ impl BusDevice for RTC {
 
     fn write(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
         if data.len() <= 4 {
-            let v = read_le_u32(&data[..]);
+            let v = read_le_u32(data);
             if let Err(e) = self.handle_write(offset, v) {
                 warn!("Failed to write to RTC PL031 device: {}", e);
             }
@@ -392,6 +347,10 @@ impl BusDevice for RTC {
 #[cfg(test)]
 mod tests {
     use super::*;
+    use crate::{
+        read_be_u16, read_be_u32, read_le_i32, read_le_u16, read_le_u32, read_le_u64, write_be_u16,
+        write_be_u32, write_le_i32, write_le_u16, write_le_u32, write_le_u64,
+    };
     use std::sync::Arc;
     use vm_device::interrupt::{InterruptIndex, InterruptSourceConfig};
     use vmm_sys_util::eventfd::EventFd;
@@ -491,71 +450,71 @@ mod tests {
     fn test_rtc_read_write_and_event() {
         let intr_evt = EventFd::new(libc::EFD_NONBLOCK).unwrap();
 
-        let mut rtc = RTC::new(Arc::new(Box::new(TestInterrupt::new(
+        let mut rtc = Rtc::new(Arc::new(Box::new(TestInterrupt::new(
             intr_evt.try_clone().unwrap(),
         ))));
         let mut data = [0; 4];
 
         // Read and write to the MR register.
         write_le_u32(&mut data, 123);
-        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCMR, &mut data);
+        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCMR, &data);
         rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCMR, &mut data);
-        let v = read_le_u32(&data[..]);
+        let v = read_le_u32(&data);
         assert_eq!(v, 123);
 
         // Read and write to the LR register.
         let v = get_time(ClockType::Real);
         write_le_u32(&mut data, (v / NANOS_PER_SECOND) as u32);
         let previous_now_before = rtc.previous_now;
-        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCLR, &mut data);
+        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCLR, &data);
 
         assert!(rtc.previous_now > previous_now_before);
 
         rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCLR, &mut data);
-        let v_read = read_le_u32(&data[..]);
+        let v_read = read_le_u32(&data);
         assert_eq!((v / NANOS_PER_SECOND) as u32, v_read);
 
         // Read and write to IMSC register.
         // Test with non zero value.
         let non_zero = 1;
         write_le_u32(&mut data, non_zero);
-        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &mut data);
+        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &data);
         // The interrupt line should be on.
         assert!(rtc.interrupt.notifier(0).unwrap().read().unwrap() == 1);
         rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &mut data);
-        let v = read_le_u32(&data[..]);
+        let v = read_le_u32(&data);
         assert_eq!(non_zero & 1, v);
 
         // Now test with 0.
         write_le_u32(&mut data, 0);
-        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &mut data);
+        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &data);
         rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &mut data);
-        let v = read_le_u32(&data[..]);
+        let v = read_le_u32(&data);
         assert_eq!(0, v);
 
         // Read and write to the ICR register.
         write_le_u32(&mut data, 1);
-        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCICR, &mut data);
+        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCICR, &data);
         // The interrupt line should be on.
         assert!(rtc.interrupt.notifier(0).unwrap().read().unwrap() > 1);
-        let v_before = read_le_u32(&data[..]);
+        let v_before = read_le_u32(&data);
 
         rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCICR, &mut data);
-        let v = read_le_u32(&data[..]);
+        let v = read_le_u32(&data);
         // ICR is a  write only register. Data received should stay equal to data sent.
         assert_eq!(v, v_before);
 
         // Attempts to turn off the RTC should not go through.
         write_le_u32(&mut data, 0);
-        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCCR, &mut data);
+        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCCR, &data);
         rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCCR, &mut data);
-        let v = read_le_u32(&data[..]);
+        let v = read_le_u32(&data);
         assert_eq!(v, 1);
 
         // Attempts to write beyond the writable space. Using here the space used to read
         // the CID and PID from.
         write_le_u32(&mut data, 0);
-        rtc.write(LEGACY_RTC_MAPPED_IO_START, AMBA_ID_LOW, &mut data);
+        rtc.write(LEGACY_RTC_MAPPED_IO_START, AMBA_ID_LOW, &data);
         // However, reading from the AMBA_ID_LOW should succeed upon read.
 
         let mut data = [0; 4];

devices/src/legacy/serial.rs

@@ -5,15 +5,15 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE-BSD-3-Clause file.
 
-use anyhow::anyhow;
 use std::collections::VecDeque;
 use std::sync::{Arc, Barrier};
 use std::{io, result};
+use versionize::{VersionMap, Versionize, VersionizeResult};
+use versionize_derive::Versionize;
 use vm_device::interrupt::InterruptSourceGroup;
 use vm_device::BusDevice;
 use vm_migration::{
-    Migratable, MigratableError, Pausable, Snapshot, SnapshotDataSection, Snapshottable,
-    Transportable,
+    Migratable, MigratableError, Pausable, Snapshot, Snapshottable, Transportable, VersionMapped,
 };
 use vmm_sys_util::errno::Result;
 
@@ -74,7 +74,7 @@ pub struct Serial {
     out: Option<Box<dyn io::Write + Send>>,
 }
 
-#[derive(Serialize, Deserialize)]
+#[derive(Versionize)]
 pub struct SerialState {
     interrupt_enable: u8,
     interrupt_identification: u8,
@@ -84,8 +84,9 @@ pub struct SerialState {
     modem_status: u8,
     scratch: u8,
     baud_divisor: u16,
-    in_buffer: VecDeque<u8>,
+    in_buffer: Vec<u8>,
 }
+impl VersionMapped for SerialState {}
 
 impl Serial {
     pub fn new(
@@ -227,7 +228,7 @@ impl Serial {
             modem_status: self.modem_status,
             scratch: self.scratch,
             baud_divisor: self.baud_divisor,
-            in_buffer: self.in_buffer.clone(),
+            in_buffer: self.in_buffer.clone().into(),
         }
     }
 
@@ -240,7 +241,7 @@ impl Serial {
         self.modem_status = state.modem_status;
         self.scratch = state.scratch;
         self.baud_divisor = state.baud_divisor;
-        self.in_buffer = state.in_buffer.clone();
+        self.in_buffer = state.in_buffer.clone().into();
     }
 }
 
@@ -292,38 +293,12 @@ impl Snapshottable for Serial {
     }
 
     fn snapshot(&mut self) -> std::result::Result<Snapshot, MigratableError> {
-        let snapshot =
-            serde_json::to_vec(&self.state()).map_err(|e| MigratableError::Snapshot(e.into()))?;
-
-        let mut serial_snapshot = Snapshot::new(self.id.as_str());
-        serial_snapshot.add_data_section(SnapshotDataSection {
-            id: format!("{}-section", self.id),
-            snapshot,
-        });
-
-        Ok(serial_snapshot)
+        Snapshot::new_from_versioned_state(&self.id, &self.state())
     }
 
     fn restore(&mut self, snapshot: Snapshot) -> std::result::Result<(), MigratableError> {
-        if let Some(serial_section) = snapshot.snapshot_data.get(&format!("{}-section", self.id)) {
-            let serial_state = match serde_json::from_slice(&serial_section.snapshot) {
-                Ok(state) => state,
-                Err(error) => {
-                    return Err(MigratableError::Restore(anyhow!(
-                        "Could not deserialize SERIAL {}",
-                        error
-                    )))
-                }
-            };
-
-            self.set_state(&serial_state);
-
-            return Ok(());
-        }
-
-        Err(MigratableError::Restore(anyhow!(
-            "Could not find the serial snapshot section"
-        )))
+        self.set_state(&snapshot.to_versioned_state(&self.id)?);
+        Ok(())
     }
 }
 

devices/src/legacy/uart_pl011.rs

@@ -0,0 +1,482 @@
+// Copyright 2021 Arm Limited (or its affiliates). All rights reserved.
+// SPDX-License-Identifier: Apache-2.0
+
+//! ARM PrimeCell UART(PL011)
+//!
+//! This module implements an ARM PrimeCell UART(PL011).
+//!
+
+use crate::{read_le_u32, write_le_u32};
+use std::collections::VecDeque;
+use std::fmt;
+use std::sync::{Arc, Barrier};
+use std::{io, result};
+use versionize::{VersionMap, Versionize, VersionizeResult};
+use versionize_derive::Versionize;
+use vm_device::interrupt::InterruptSourceGroup;
+use vm_device::BusDevice;
+use vm_migration::{
+    Migratable, MigratableError, Pausable, Snapshot, Snapshottable, Transportable, VersionMapped,
+};
+
+/* Registers */
+const UARTDR: u64 = 0;
+const UARTRSR_UARTECR: u64 = 1;
+const UARTFR: u64 = 6;
+const UARTILPR: u64 = 8;
+const UARTIBRD: u64 = 9;
+const UARTFBRD: u64 = 10;
+const UARTLCR_H: u64 = 11;
+const UARTCR: u64 = 12;
+const UARTIFLS: u64 = 13;
+const UARTIMSC: u64 = 14;
+const UARTRIS: u64 = 15;
+const UARTMIS: u64 = 16;
+const UARTICR: u64 = 17;
+const UARTDMACR: u64 = 18;
+
+const PL011_INT_TX: u32 = 0x20;
+const PL011_INT_RX: u32 = 0x10;
+
+const PL011_FLAG_RXFF: u32 = 0x40;
+const PL011_FLAG_RXFE: u32 = 0x10;
+
+const PL011_ID: [u8; 8] = [0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1];
+// We are only interested in the margins.
+const AMBA_ID_LOW: u64 = 0x3f8;
+const AMBA_ID_HIGH: u64 = 0x401;
+
+#[derive(Debug)]
+pub enum Error {
+    BadWriteOffset(u64),
+    DmaNotImplemented,
+    InterruptFailure(io::Error),
+    WriteAllFailure(io::Error),
+    FlushFailure(io::Error),
+}
+
+impl fmt::Display for Error {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        match self {
+            Error::BadWriteOffset(offset) => write!(f, "pl011_write: Bad Write Offset: {}", offset),
+            Error::DmaNotImplemented => write!(f, "pl011: DMA not implemented."),
+            Error::InterruptFailure(e) => write!(f, "Failed to trigger interrupt: {}", e),
+            Error::WriteAllFailure(e) => write!(f, "Failed to write: {}", e),
+            Error::FlushFailure(e) => write!(f, "Failed to flush: {}", e),
+        }
+    }
+}
+
+type Result<T> = result::Result<T, Error>;
+
+/// A PL011 device following the PL011 specification.
+pub struct Pl011 {
+    id: String,
+    flags: u32,
+    lcr: u32,
+    rsr: u32,
+    cr: u32,
+    dmacr: u32,
+    int_enabled: u32,
+    int_level: u32,
+    read_fifo: VecDeque<u8>,
+    ilpr: u32,
+    ibrd: u32,
+    fbrd: u32,
+    ifl: u32,
+    read_count: u32,
+    read_trigger: u32,
+    irq: Arc<Box<dyn InterruptSourceGroup>>,
+    out: Option<Box<dyn io::Write + Send>>,
+}
+
+#[derive(Versionize)]
+pub struct Pl011State {
+    flags: u32,
+    lcr: u32,
+    rsr: u32,
+    cr: u32,
+    dmacr: u32,
+    int_enabled: u32,
+    int_level: u32,
+    read_fifo: Vec<u8>,
+    ilpr: u32,
+    ibrd: u32,
+    fbrd: u32,
+    ifl: u32,
+    read_count: u32,
+    read_trigger: u32,
+}
+
+impl VersionMapped for Pl011State {}
+
+impl Pl011 {
+    /// Constructs an AMBA PL011 UART device.
+    pub fn new(
+        id: String,
+        irq: Arc<Box<dyn InterruptSourceGroup>>,
+        out: Option<Box<dyn io::Write + Send>>,
+    ) -> Self {
+        Self {
+            id,
+            flags: 0x90u32,
+            lcr: 0u32,
+            rsr: 0u32,
+            cr: 0x300u32,
+            dmacr: 0u32,
+            int_enabled: 0u32,
+            int_level: 0u32,
+            read_fifo: VecDeque::new(),
+            ilpr: 0u32,
+            ibrd: 0u32,
+            fbrd: 0u32,
+            ifl: 0x12u32,
+            read_count: 0u32,
+            read_trigger: 1u32,
+            irq,
+            out,
+        }
+    }
+
+    fn state(&self) -> Pl011State {
+        Pl011State {
+            flags: self.flags,
+            lcr: self.lcr,
+            rsr: self.rsr,
+            cr: self.cr,
+            dmacr: self.dmacr,
+            int_enabled: self.int_enabled,
+            int_level: self.int_level,
+            read_fifo: self.read_fifo.clone().into(),
+            ilpr: self.ilpr,
+            ibrd: self.ibrd,
+            fbrd: self.fbrd,
+            ifl: self.ifl,
+            read_count: self.read_count,
+            read_trigger: self.read_trigger,
+        }
+    }
+
+    fn set_state(&mut self, state: &Pl011State) {
+        self.flags = state.flags;
+        self.lcr = state.lcr;
+        self.rsr = state.rsr;
+        self.cr = state.cr;
+        self.dmacr = state.dmacr;
+        self.int_enabled = state.int_enabled;
+        self.int_level = state.int_level;
+        self.read_fifo = state.read_fifo.clone().into();
+        self.ilpr = state.ilpr;
+        self.ibrd = state.ibrd;
+        self.fbrd = state.fbrd;
+        self.ifl = state.ifl;
+        self.read_count = state.read_count;
+        self.read_trigger = state.read_trigger;
+    }
+
+    /// Queues raw bytes for the guest to read and signals the interrupt
+    pub fn queue_input_bytes(&mut self, c: &[u8]) -> vmm_sys_util::errno::Result<()> {
+        self.read_fifo.extend(c);
+        self.read_count += c.len() as u32;
+        self.flags &= !PL011_FLAG_RXFE;
+
+        if ((self.lcr & 0x10) == 0) || (self.read_count == 16) {
+            self.flags |= PL011_FLAG_RXFF;
+        }
+
+        if self.read_count >= self.read_trigger {
+            self.int_level |= PL011_INT_RX;
+            self.trigger_interrupt()?;
+        }
+
+        Ok(())
+    }
+
+    fn pl011_get_baudrate(&self) -> u32 {
+        if self.fbrd == 0 {
+            return 0;
+        }
+
+        let clk = 24_000_000; // We set the APB_PLCK to 24M in device tree
+        (clk / ((self.ibrd << 6) + self.fbrd)) << 2
+    }
+
+    fn pl011_trace_baudrate_change(&self) {
+        debug!(
+            "=== New baudrate: {:#?} (clk: {:#?}Hz, ibrd: {:#?}, fbrd: {:#?}) ===",
+            self.pl011_get_baudrate(),
+            24_000_000, // We set the APB_PLCK to 24M in device tree
+            self.ibrd,
+            self.fbrd
+        );
+    }
+
+    fn pl011_set_read_trigger(&mut self) {
+        self.read_trigger = 1;
+    }
+
+    fn handle_write(&mut self, offset: u64, val: u32) -> Result<()> {
+        match offset >> 2 {
+            UARTDR => {
+                self.int_level |= PL011_INT_TX;
+                if let Some(out) = self.out.as_mut() {
+                    out.write_all(&[val.to_le_bytes()[0]])
+                        .map_err(Error::WriteAllFailure)?;
+                    out.flush().map_err(Error::FlushFailure)?;
+                }
+            }
+            UARTRSR_UARTECR => {
+                self.rsr = 0;
+            }
+            UARTFR => { /* Writes to Flag register are ignored.*/ }
+            UARTILPR => {
+                self.ilpr = val;
+            }
+            UARTIBRD => {
+                self.ibrd = val;
+                self.pl011_trace_baudrate_change();
+            }
+            UARTFBRD => {
+                self.fbrd = val;
+                self.pl011_trace_baudrate_change();
+            }
+            UARTLCR_H => {
+                /* Reset the FIFO state on FIFO enable or disable */
+                if ((self.lcr ^ val) & 0x10) != 0 {
+                    self.read_count = 0;
+                }
+                self.lcr = val;
+                self.pl011_set_read_trigger();
+            }
+            UARTCR => {
+                self.cr = val;
+            }
+            UARTIFLS => {
+                self.ifl = val;
+                self.pl011_set_read_trigger();
+            }
+            UARTIMSC => {
+                self.int_enabled = val;
+                self.trigger_interrupt().map_err(Error::InterruptFailure)?;
+            }
+            UARTICR => {
+                self.int_level &= !val;
+                self.trigger_interrupt().map_err(Error::InterruptFailure)?;
+            }
+            UARTDMACR => {
+                self.dmacr = val;
+                if (val & 3) != 0 {
+                    return Err(Error::DmaNotImplemented);
+                }
+            }
+            off => {
+                return Err(Error::BadWriteOffset(off));
+            }
+        }
+        Ok(())
+    }
+
+    fn trigger_interrupt(&mut self) -> result::Result<(), io::Error> {
+        self.irq.trigger(0)
+    }
+}
+
+impl BusDevice for Pl011 {
+    fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
+        let v;
+        let mut read_ok = true;
+        if (AMBA_ID_LOW..AMBA_ID_HIGH).contains(&(offset >> 2)) {
+            let index = ((offset - 0xfe0) >> 2) as usize;
+            v = u32::from(PL011_ID[index]);
+        } else {
+            v = match offset >> 2 {
+                UARTDR => {
+                    let c: u32;
+                    let r: u32;
+
+                    self.flags &= !PL011_FLAG_RXFF;
+                    c = self.read_fifo.pop_front().unwrap_or_default().into();
+                    if self.read_count > 0 {
+                        self.read_count -= 1;
+                    }
+                    if self.read_count == 0 {
+                        self.flags |= PL011_FLAG_RXFE;
+                    }
+                    if self.read_count == (self.read_trigger - 1) {
+                        self.int_level &= !PL011_INT_RX;
+                    }
+                    self.rsr = c >> 8;
+                    r = c;
+                    r
+                }
+                UARTRSR_UARTECR => self.rsr,
+                UARTFR => self.flags,
+                UARTILPR => self.ilpr,
+                UARTIBRD => self.ibrd,
+                UARTFBRD => self.fbrd,
+                UARTLCR_H => self.lcr,
+                UARTCR => self.cr,
+                UARTIFLS => self.ifl,
+                UARTIMSC => self.int_enabled,
+                UARTRIS => self.int_level,
+                UARTMIS => (self.int_level & self.int_enabled),
+                UARTDMACR => self.dmacr,
+                _ => {
+                    read_ok = false;
+                    0
+                }
+            }
+        }
+
+        if read_ok && data.len() <= 4 {
+            write_le_u32(data, v);
+        } else {
+            warn!(
+                "Invalid PL011 read: offset {}, data length {}",
+                offset,
+                data.len()
+            );
+        }
+    }
+
+    fn write(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
+        if data.len() <= 4 {
+            let v = read_le_u32(data);
+            if let Err(e) = self.handle_write(offset, v) {
+                warn!("Failed to write to PL011 device: {}", e);
+            }
+        } else {
+            warn!(
+                "Invalid PL011 write: offset {}, data length {}",
+                offset,
+                data.len()
+            );
+        }
+
+        None
+    }
+}
+
+impl Snapshottable for Pl011 {
+    fn id(&self) -> String {
+        self.id.clone()
+    }
+
+    fn snapshot(&mut self) -> std::result::Result<Snapshot, MigratableError> {
+        Snapshot::new_from_versioned_state(&self.id, &self.state())
+    }
+
+    fn restore(&mut self, snapshot: Snapshot) -> std::result::Result<(), MigratableError> {
+        self.set_state(&snapshot.to_versioned_state(&self.id)?);
+        Ok(())
+    }
+}
+
+impl Pausable for Pl011 {}
+impl Transportable for Pl011 {}
+impl Migratable for Pl011 {}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+    use std::io;
+    use std::sync::{Arc, Mutex};
+    use vm_device::interrupt::{InterruptIndex, InterruptSourceConfig};
+    use vmm_sys_util::eventfd::EventFd;
+
+    const SERIAL_NAME: &str = "serial";
+
+    struct TestInterrupt {
+        event_fd: EventFd,
+    }
+
+    impl InterruptSourceGroup for TestInterrupt {
+        fn trigger(&self, _index: InterruptIndex) -> result::Result<(), std::io::Error> {
+            self.event_fd.write(1)
+        }
+        fn update(
+            &self,
+            _index: InterruptIndex,
+            _config: InterruptSourceConfig,
+        ) -> result::Result<(), std::io::Error> {
+            Ok(())
+        }
+        fn notifier(&self, _index: InterruptIndex) -> Option<EventFd> {
+            Some(self.event_fd.try_clone().unwrap())
+        }
+    }
+
+    impl TestInterrupt {
+        fn new(event_fd: EventFd) -> Self {
+            TestInterrupt { event_fd }
+        }
+    }
+
+    #[derive(Clone)]
+    struct SharedBuffer {
+        buf: Arc<Mutex<Vec<u8>>>,
+    }
+
+    impl SharedBuffer {
+        fn new() -> SharedBuffer {
+            SharedBuffer {
+                buf: Arc::new(Mutex::new(Vec::new())),
+            }
+        }
+    }
+
+    impl io::Write for SharedBuffer {
+        fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
+            self.buf.lock().unwrap().write(buf)
+        }
+        fn flush(&mut self) -> io::Result<()> {
+            self.buf.lock().unwrap().flush()
+        }
+    }
+
+    #[test]
+    fn pl011_output() {
+        let intr_evt = EventFd::new(0).unwrap();
+        let pl011_out = SharedBuffer::new();
+        let mut pl011 = Pl011::new(
+            String::from(SERIAL_NAME),
+            Arc::new(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap()))),
+            Some(Box::new(pl011_out.clone())),
+        );
+
+        pl011.write(0, UARTDR as u64, &[b'x', b'y']);
+        pl011.write(0, UARTDR as u64, &[b'a']);
+        pl011.write(0, UARTDR as u64, &[b'b']);
+        pl011.write(0, UARTDR as u64, &[b'c']);
+        assert_eq!(
+            pl011_out.buf.lock().unwrap().as_slice(),
+            &[b'x', b'a', b'b', b'c']
+        );
+    }
+
+    #[test]
+    fn pl011_input() {
+        let intr_evt = EventFd::new(0).unwrap();
+        let pl011_out = SharedBuffer::new();
+        let mut pl011 = Pl011::new(
+            String::from(SERIAL_NAME),
+            Arc::new(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap()))),
+            Some(Box::new(pl011_out)),
+        );
+
+        // write 1 to the interrupt event fd, so that read doesn't block in case the event fd
+        // counter doesn't change (for 0 it blocks)
+        assert!(intr_evt.write(1).is_ok());
+        pl011.queue_input_bytes(&[b'a', b'b', b'c']).unwrap();
+
+        assert_eq!(intr_evt.read().unwrap(), 2);
+
+        let mut data = [0u8];
+        pl011.read(0, UARTDR as u64, &mut data);
+        assert_eq!(data[0], b'a');
+        pl011.read(0, UARTDR as u64, &mut data);
+        assert_eq!(data[0], b'b');
+        pl011.read(0, UARTDR as u64, &mut data);
+        assert_eq!(data[0], b'c');
+    }
+}

devices/src/lib.rs

@@ -6,24 +6,11 @@
 // found in the LICENSE-BSD-3-Clause file.
 
 //! Emulates virtual and hardware devices.
-extern crate anyhow;
+
 #[macro_use]
 extern crate bitflags;
-extern crate byteorder;
-extern crate epoll;
-extern crate libc;
 #[macro_use]
 extern crate log;
-#[cfg(feature = "acpi")]
-extern crate acpi_tables;
-extern crate serde;
-extern crate vm_device;
-extern crate vm_memory;
-extern crate vm_migration;
-extern crate vmm_sys_util;
-#[macro_use]
-extern crate serde_derive;
-extern crate serde_json;
 
 #[cfg(feature = "acpi")]
 pub mod acpi;
@@ -35,7 +22,7 @@ pub mod ioapic;
 pub mod legacy;
 
 #[cfg(feature = "acpi")]
-pub use self::acpi::{AcpiGEDDevice, AcpiPMTimerDevice, AcpiShutdownDevice};
+pub use self::acpi::{AcpiGedDevice, AcpiPmTimerDevice, AcpiShutdownDevice};
 
 bitflags! {
     pub struct AcpiNotificationFlags: u8 {
@@ -46,3 +33,63 @@ bitflags! {
         const POWER_BUTTON_CHANGED = 0b1000;
     }
 }
+
+#[allow(unused_macros)]
+#[cfg(target_arch = "aarch64")]
+macro_rules! generate_read_fn {
+    ($fn_name: ident, $data_type: ty, $byte_type: ty, $type_size: expr, $endian_type: ident) => {
+        #[allow(dead_code)]
+        pub fn $fn_name(input: &[$byte_type]) -> $data_type {
+            assert!($type_size == std::mem::size_of::<$data_type>());
+            let mut array = [0u8; $type_size];
+            for (byte, read) in array.iter_mut().zip(input.iter().cloned()) {
+                *byte = read as u8;
+            }
+            <$data_type>::$endian_type(array)
+        }
+    };
+}
+
+#[allow(unused_macros)]
+#[cfg(target_arch = "aarch64")]
+macro_rules! generate_write_fn {
+    ($fn_name: ident, $data_type: ty, $byte_type: ty, $endian_type: ident) => {
+        #[allow(dead_code)]
+        pub fn $fn_name(buf: &mut [$byte_type], n: $data_type) {
+            for (byte, read) in buf
+                .iter_mut()
+                .zip(<$data_type>::$endian_type(n).iter().cloned())
+            {
+                *byte = read as $byte_type;
+            }
+        }
+    };
+}
+
+#[cfg(target_arch = "aarch64")]
+generate_read_fn!(read_le_u16, u16, u8, 2, from_le_bytes);
+#[cfg(target_arch = "aarch64")]
+generate_read_fn!(read_le_u32, u32, u8, 4, from_le_bytes);
+#[cfg(target_arch = "aarch64")]
+generate_read_fn!(read_le_u64, u64, u8, 8, from_le_bytes);
+#[cfg(target_arch = "aarch64")]
+generate_read_fn!(read_le_i32, i32, i8, 4, from_le_bytes);
+
+#[cfg(target_arch = "aarch64")]
+generate_read_fn!(read_be_u16, u16, u8, 2, from_be_bytes);
+#[cfg(target_arch = "aarch64")]
+generate_read_fn!(read_be_u32, u32, u8, 4, from_be_bytes);
+
+#[cfg(target_arch = "aarch64")]
+generate_write_fn!(write_le_u16, u16, u8, to_le_bytes);
+#[cfg(target_arch = "aarch64")]
+generate_write_fn!(write_le_u32, u32, u8, to_le_bytes);
+#[cfg(target_arch = "aarch64")]
+generate_write_fn!(write_le_u64, u64, u8, to_le_bytes);
+#[cfg(target_arch = "aarch64")]
+generate_write_fn!(write_le_i32, i32, i8, to_le_bytes);
+
+#[cfg(target_arch = "aarch64")]
+generate_write_fn!(write_be_u16, u16, u8, to_be_bytes);
+#[cfg(target_arch = "aarch64")]
+generate_write_fn!(write_be_u32, u32, u8, to_be_bytes);

docs/arm64.md

@@ -1,58 +1,116 @@
-# How to build and run Cloud-hypervisor on AArch64
+# How to build and test Cloud Hypervisor on AArch64
 
-Cloud-hypervisor is partially enabled on AArch64 architecture.
-Although all features are not ready yet, you can begin to test Cloud-hypervisor on a AArch64 host by following this guide.
+This document introduces how to build and test Cloud Hypervisor on AArch64 servers. Currently Cloud Hypervisor cannot be tested on Raspberry PI. Because on AArch64, Cloud Hypervisor requires GICv3-ITS device for PCIe MSI interrupt handling. But GICv3-ITS has not been equipped on any Raspberry PI product so far.
+
+Now Cloud Hypervisor supports 2 ways of booting on AArch64: UEFI booting and direct-kernel booting. The document covers both of the ways.
+
+All the steps are based on Ubuntu. We use the Ubuntu cloud image for guest VM disk.
+
+## Getting started
+
+We create a folder to build and run Cloud Hypervisor at `$HOME/cloud-hypervisor`
+
+```shell
+$ export CLOUDH=$HOME/cloud-hypervisor
+$ mkdir $CLOUDH
+```
 
 ## Prerequisites
 
-On AArch64 machines, Cloud-hypervisor depends on an external library `libfdt-dev` for generating Flattened Device Tree (FDT).
+You need to install some prerequisite packages to build and test Cloud Hypervisor.
 
-The long-term plan is to replace `libfdt-dev` with some pure-Rust component to get rid of such dependency.
+### Tools
 
 ```bash
-sudo apt-get update
-sudo apt-get install libfdt-dev
+# Install rust tool chain
+$ curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh
+# Install the tools used for building guest kernel, EDK2 and converting guest disk
+$ sudo apt-get update
+$ sudo apt-get install git build-essential m4 bison flex uuid-dev qemu-utils
 ```
 
-## Build
-
-Using PCI devices requires GICv3-ITS for MSI messaging. GICv3-ITS is very common in modern servers.
+### Building Cloud Hypervisor
 
 ```bash
-cargo build --no-default-features --features kvm
+$ pushd $CLOUDH
+$ git clone https://github.com/cloud-hypervisor/cloud-hypervisor.git
+$ cd cloud-hypervisor
+$ cargo build
+$ popd
 ```
 
-## Image
+### Disk image
 
-Download kernel binary and rootfs image from AWS.
+Download the Ubuntu cloud image and convert the image type.
 
 ```bash
-wget https://s3.amazonaws.com/spec.ccfc.min/img/aarch64/ubuntu_with_ssh/fsfiles/xenial.rootfs.ext4 -O rootfs.ext4
-wget https://s3.amazonaws.com/spec.ccfc.min/img/aarch64/ubuntu_with_ssh/kernel/vmlinux.bin -O kernel.bin
+$ pushd $CLOUDH
+$ wget https://cloud-images.ubuntu.com/focal/current/focal-server-cloudimg-arm64.img
+$ qemu-img convert -p -f qcow2 -O raw focal-server-cloudimg-arm64.img focal-server-cloudimg-arm64.raw
+$ popd
 ```
 
-## Containerized build
+## UEFI booting
 
-If you want to build and test Cloud Hypervisor without having to install all the required dependencies, you can also turn to the development script: dev_cli.sh.
+This part introduces how to build EDK2 firmware and boot Cloud Hypervisor with it.
 
-To build the development container:
+### Building EDK2
 
 ```bash
-./scripts/dev_cli.sh build-container
+$ pushd $CLOUDH
+
+# Clone source code repos
+$ git clone --depth 1 https://github.com/tianocore/edk2.git -b master
+$ cd edk2
+$ git submodule update --init
+$ cd ..
+$ git clone --depth 1 https://github.com/tianocore/edk2-platforms.git -b master
+$ git clone --depth 1 https://github.com/acpica/acpica.git -b master
+
+# Build tools
+$ export PACKAGES_PATH="$PWD/edk2:$PWD/edk2-platforms"
+$ export IASL_PREFIX="$PWD/acpica/generate/unix/bin/"
+$ make -C acpica
+$ cd edk2/
+$ . edksetup.sh
+$ cd ..
+$ make -C edk2/BaseTools
+
+# Build EDK2
+$ build -a AARCH64 -t GCC5 -p ArmVirtPkg/ArmVirtCloudHv.dsc -b RELEASE
+
+$ popd
 ```
 
-To build Cloud-hypervisor in the container:
+If the build goes well, the EDK2 binary is available at `edk2/Build/ArmVirtCloudHv-AARCH64/RELEASE_GCC5/FV/CLOUDHV_EFI.fd`.
+
+### Booting the guest VM
 
 ```bash
-./scripts/dev_cli.sh build
+$ pushd $CLOUDH
+$ sudo RUST_BACKTRACE=1 $CLOUDH/cloud-hypervisor/target/debug/cloud-hypervisor --api-socket /tmp/cloud-hypervisor.sock --kernel $CLOUDH/edk2/edk2/Build/ArmVirtCloudHv-AARCH64/RELEASE_GCC5/FV/CLOUDHV_EFI.fd --disk path=$CLOUDH/focal-server-cloudimg-arm64.raw --cpus boot=4 --memory size=4096M --serial tty --console off --log-file log.log -vvv --net tap=,mac=12:34:56:78:90:01,ip=192.168.1.1,mask=255.255.255.0
+$ popd
 ```
 
-## Run
+## Direct-kernel booting
 
-Assuming you have built Cloud-hypervisor with the development container, a VM can be started with command:
+Alternativelly, you can build your own kernel for guest VM. This way, UEFI is not involved and ACPI cannot be enabled.
+
+### Building kernel
 
 ```bash
-sudo build/cargo_target/aarch64-unknown-linux-gnu/debug/cloud-hypervisor --kernel kernel.bin --disk path=rootfs.ext4 --cmdline "keep_bootcon console=hvc0 reboot=k panic=1 root=/dev/vda rw" --cpus boot=4 --memory size=512M --serial file=serial.log --log-file log.log -vvv
+$ pushd $CLOUDH
+$ git clone --depth 1 "https://github.com/cloud-hypervisor/linux.git" -b ch-5.12
+$ cd linux
+$ cp $CLOUDH/cloud-hypervisor/resources/linux-config-aarch64 .config
+$ make -j `nproc`
+$ popd
 ```
 
-If the build was done out of the container, replace the binary path with `target/debug/cloud-hypervisor`.
+### Booting the guest VM
+
+```bash
+$ pushd $CLOUDH
+$ sudo $CLOUDH/cloud-hypervisor/target/debug/cloud-hypervisor --api-socket /tmp/cloud-hypervisor.sock --kernel $CLOUDH/linux/arch/arm64/boot/Image --disk path=focal-server-cloudimg-arm64.raw --cmdline "keep_bootcon console=ttyAMA0 reboot=k panic=1 root=/dev/vda1 rw" --cpus boot=4 --memory size=4096M --serial tty --console off --log-file log.log -vvv --net "tap=,mac=,ip=,mask="
+$ popd
+```

docs/custom-image.md

@@ -78,7 +78,7 @@ Ubuntu distributions.
 
 ```bash
 apt update
-apt install fio iperf iperf3 socat
+apt install fio iperf iperf3 socat stress
 ```
 
 ### Remove counterproductive packages

docs/device_model.md

@@ -28,9 +28,13 @@ This document describes the device model supported by `cloud-hypervisor`.
 ### Serial port
 
 Simple emulation of a serial port by reading and writing to specific port I/O
-addresses. Used as the default console for Linux when booting with the option
-`console=ttyS0`, the serial port can be very useful to gather early logs from
-the operating system booted inside the VM.
+addresses. The serial port can be very useful to gather early logs from the
+operating system booted inside the VM.
+
+For x86_64, The default serial port is from an emulated 16550A device. It can
+be used as the default console for Linux when booting with the option
+`console=ttyS0`. For AArch64, the default serial port is from an emulated
+PL011 UART device. The related command line for AArch64 is `console=ttyAMA0`.
 
 This device is always built-in, and it is disabled by default. It can be
 enabled with the `--serial` option, as long as its parameter is not `off`.
@@ -44,6 +48,10 @@ This device is built-in by default, but it can be compiled out with Rust
 features. When compiled in, it is always enabled, and cannot be disabled
 from the command line.
 
+For AArch64 machines, an ARM PrimeCell Real Time Clock(PL031) is implemented.
+This device is built-in by default for the AArch64 platform, and it is always
+enabled, and cannot be disabled from the command line.
+
 ### I/O APIC
 
 `cloud-hypervisor` supports a so-called split IRQ chip implementation by
@@ -65,6 +73,11 @@ enabled by default, the handling of reboot/shutdown goes through the dedicated
 ACPI device. In case ACPI is disabled, this device is enabled to bring to the
 VM some reboot/shutdown support.
 
+### ARM PrimeCell General Purpose Input/Output (PL061)
+
+Simplified ARM PrimeCell GPIO (PL061) implementation. Only supports key 3 to
+trigger a graceful shutdown of the AArch64 guest.
+
 ### ACPI device
 
 This is a dedicated device for handling ACPI shutdown and reboot when ACPI is
@@ -100,9 +113,8 @@ selecting `--serial tty --console off` from the command line.
 ### virtio-iommu
 
 As we want to improve our nested guests support, we added support for exposing
-a [paravirtualized IOMMU](https://github.com/cloud-hypervisor/cloud-hypervisor/blob/master/docs/iommu.md)
-device through virtio. This allows for a safer nested virtio and directly
-assigned devices support.
+a [paravirtualized IOMMU](iommu.md) device through virtio. This allows for a
+safer nested virtio and directly assigned devices support.
 
 This device is always built-in, and it is enabled based on the presence of the
 parameter `iommu=on` in any of the virtio or VFIO devices. If at least one of
@@ -171,8 +183,8 @@ This device is always built-in, and it is enabled when `vhost_user=true` and
 shared file system, allowing for an efficient and reliable way of sharing
 a filesystem between the host and the cloud-hypervisor guest.
 
-See our [filesystem sharing](https://github.com/cloud-hypervisor/cloud-hypervisor/blob/master/docs/fs.md)
-documentation for more details on how to use virtio-fs with cloud-hypervisor.
+See our [filesystem sharing](fs.md) documentation for more details on how to
+use virtio-fs with cloud-hypervisor.
 
 This device is always built-in, and it is enabled based on the presence of the
 flag `--fs`.
@@ -193,9 +205,8 @@ VFIO (Virtual Function I/O) is a kernel framework that exposes direct device
 access to userspace. `cloud-hypervisor` uses VFIO to directly assign host
 physical devices into its guest.
 
-See our [VFIO documentation](https://github.com/cloud-hypervisor/cloud-hypervisor/blob/master/docs/vfio.md)
-for more details on how to directly assign host devices to `cloud-hypervisor`
-guests.
+See our [VFIO documentation](vfio.md) for more details on how to directly
+assign host devices to `cloud-hypervisor` guests.
 
 Because VFIO implies `vfio-pci` in the `cloud-hypervisor` context, the VFIO
 support is built-in when the `pci` feature is selected. And because the `pci`

docs/fs.md

@@ -12,7 +12,7 @@ This virtual device relies on the _vhost-user_ protocol, which assumes the backe
 
 _Build virtiofsd_
 ```bash
-git clone --depth 1 "https://github.com/sboeuf/qemu.git" -b "virtio-fs" $VIRTIOFSD_DIR
+git clone --depth 1 "https://gitlab.com/virtio-fs/qemu.git" -b "qemu5.0-virtiofs-dax" $VIRTIOFSD_DIR
 cd $VIRTIOFSD_DIR
 ./configure --prefix=$PWD --target-list=x86_64-softmmu
 make virtiofsd -j `nproc`
@@ -35,45 +35,42 @@ The `cache=none` option should be the default when using `virtiofsd` with the __
 
 The `cache=always` option will allow for the guest page cache to be used, which will increase the memory footprint of the guest. This option should be used only for specific use cases where a single VM is going to be running on a host.
 
-### The kernel
+### Kernel support
 
-In order to leverage __virtio-fs__ support from within the guest, and because the code has not been merged in upstream Linux kernel yet, it is required to build a custom kernel embedding the patches.
-
-The following branch `virtio-fs-virtio-iommu` on the repository https://github.com/cloud-hypervisor/linux.git includes all the needed patches to support __virtio-fs__.
-
-Make sure to build a kernel out of this branch that can be then used to boot the VM.
+Modern Linux kernels starting (at least v5.10) have support for virtio-fs. Use
+of older kernels, with additional patches, are not supported.
 
 ## How to share directories with cloud-hypervisor
 
 ### Start the VM
 Once the daemon is running, the option `--fs` from __cloud-hypervisor__ needs to be used.
 
-Direct kernel boot option is preferred since we need to provide the custom kernel including the __virtio-fs__ patches. We could boot from `hypervisor-fw` if we had previously edited the image to replace the kernel binary.
+Direct kernel boot is the preferred option, but we can boot from an EFI cloud image if it contains a recent enough kernel.
 
-Because _vhost-user_ expects a dedicated process (__virtiofsd__ in this case) to be able to access the guest RAM to communicate through the _virtqueues_ with the driver running in the guest, `--memory` option needs to be slightly modified. It needs to specify a backing file for the memory so that an external process can access it.
+Because _vhost-user_ expects a dedicated process (__virtiofsd__ in this case) to be able to access the guest RAM to communicate through the _virtqueues_ with the driver running in the guest, `--memory` option needs to be slightly modified. It must specify `shared=on` to share the memory pages so that an external process can access them.
 
-Assuming you have `focal-server-cloudimg-amd64.raw` and `custom-vmlinux.bin` on your system, here is the __cloud-hypervisor__ command you need to run:
+Assuming you have `focal-server-cloudimg-amd64.raw` and `vmlinux` on your system, here is the __cloud-hypervisor__ command you need to run:
 ```bash
 ./cloud-hypervisor \
-    --cpus 4 \
-    --memory "size=512M,shared=on" \
+    --cpus boot=1 \
+    --memory size=1G,shared=on \
     --disk path=focal-server-cloudimg-amd64.raw \
-    --kernel custom-vmlinux.bin \
-    --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
+    --kernel vmlinux \
+    --cmdline "console=hvc0 root=/dev/vda1 rw" \
     --fs tag=myfs,socket=/tmp/virtiofs,num_queues=1,queue_size=512
 ```
 
 By default, DAX is enabled with a cache window of 8GiB. You can specify a custom size (let's say 4GiB for this example) for the cache by explicitly setting DAX and the cache size:
 
 ```bash
---fs tag=virtiofs,socket=/tmp/virtiofs,num_queues=1,queue_size=512,dax=on,cache_size=4G
+--fs tag=myfs,socket=/tmp/virtiofs,num_queues=1,queue_size=512,dax=on,cache_size=4G
 
 ```
 
 In case you don't want to use a shared window of cache to pass the shared files content, this means you will have to explicitly disable DAX with `dax=off`. Note that in this case, the `cache_size` parameter will be ignored.
 
 ```bash
---fs tag=virtiofs,socket=/tmp/virtiofs,num_queues=1,queue_size=512,dax=off
+--fs tag=myfs,socket=/tmp/virtiofs,num_queues=1,queue_size=512,dax=off
 
 ```
 

docs/hotplug.md

@@ -27,16 +27,16 @@ $ ./cloud-hypervisor/target/release/cloud-hypervisor \
 	--memory size=1024M \
 	--net "tap=,mac=,ip=,mask=" \
 	--rng \
-    --api-socket=/tmp/ch-socket
+	--api-socket=/tmp/ch-socket
 $ popd
 ```
 
-Notice the addition of `--api-socket=/tmp/ch-socket` and a `max` parameter on `--cpus boot=4.max=8`.
+Notice the addition of `--api-socket=/tmp/ch-socket` and a `max` parameter on `--cpus boot=4,max=8`.
 
 To ask the VMM to add additional vCPUs then use the resize API:
 
 ```shell
-curl -H "Accept: application/json" -H "Content-Type: application/json" -i -XPUT --unix-socket /tmp/ch-socket -d "{ \"desired_vcpus\":8}" http://localhost/api/v1/vm.resize
+./ch-remote --api-socket=/tmp/ch-socket resize --cpus 8
 ```
 
 The extra vCPU threads will be created and advertised to the running kernel. The kernel does not bring up the CPUs immediately and instead the user must "online" them from inside the VM:
@@ -56,19 +56,23 @@ After a reboot the added CPUs will remain.
 Removing CPUs works similarly by reducing the number in the "desired_vcpus" field of the reisze API. The CPUs will be automatically offlined inside the guest so there is no need to run any commands inside the guest:
 
 ```shell
-curl -H "Accept: application/json" -H "Content-Type: application/json" -i -XPUT --unix-socket /tmp/ch-socket -d "{ \"desired_vcpus\":2}" http://localhost/api/v1/vm.resize
+./ch-remote --api-socket=/tmp/ch-socket resize --cpus 2
 ```
 
 As per adding CPUs to the guest, after a reboot the VM will be running with the reduced number of vCPUs.
 
 ## Memory Hot Plug
 
+### ACPI method
+
 Extra memory can be added from a running Cloud Hypervisor instance. This is controlled by two mechanisms:
 
 1. Allocating some of the guest physical address space for hotplug memory.
 2. Making a HTTP API request to the VMM to ask for a new amount of RAM to be assigned to the VM. In the case of expanding the memory for the VM the new memory will be hotplugged into the running VM, if reducing the size of the memory then change will take effect after the next reboot.
 
-To use memory hotplug start the VM specifying some size RAM in the "hotplug_size" parameter to the memory configuration. Not all the memory specified in this parameter will be available to hotplug as there are spacing and alignment requirements so it is recommended to make it larger than the hotplug RAM needed.
+To use memory hotplug start the VM specifying some size RAM in the `hotplug_size` parameter to the memory configuration. Not all the memory specified in this parameter will be available to hotplug as there are spacing and alignment requirements so it is recommended to make it larger than the hotplug RAM needed.
+
+Because the ACPI method is the default, there is no need to add the extra option `hotplug_method=acpi`.
 
 ```shell
 $ pushd $CLOUDH
@@ -81,7 +85,7 @@ $ ./cloud-hypervisor/target/release/cloud-hypervisor \
 	--memory size=1024M,hotplug_size=8192M \
 	--net "tap=,mac=,ip=,mask=" \
 	--rng \
-    --api-socket=/tmp/ch-socket
+	--api-socket=/tmp/ch-socket
 $ popd
 ```
 
@@ -91,10 +95,10 @@ Before issuing the API request it is necessary to run the following command insi
 root@ch-guest ~ # echo online | sudo tee /sys/devices/system/memory/auto_online_blocks
 ```
 
-To ask the VMM to add expand the RAM for the VM  (request is in bytes):
+To ask the VMM to expand the RAM for the VM:
 
 ```shell
-curl -H "Accept: application/json" -H "Content-Type: application/json" -i -XPUT --unix-socket /tmp/ch-socket -d "{ \"desired_vcpus\": 4, \"desired_ram\" : 3221225472}" http://localhost/api/v1/vm.resize
+./ch-remote --api-socket=/tmp/ch-socket resize --memory 3G
 ```
 
 The new memory is now available to use inside the VM:
@@ -111,3 +115,134 @@ Due to guest OS limitations is is necessary to ensure that amount of memory adde
 The same API can also be used to reduce the desired RAM for a VM but the change will not be applied until the VM is rebooted.
 
 Memory and CPU resizing can be combined together into the same HTTP API request.
+
+### virtio-mem method
+
+Extra memory can be added and removed from a running Cloud Hypervisor instance. This is controlled by two mechanisms:
+
+1. Allocating some of the guest physical address space for hotplug memory.
+2. Making a HTTP API request to the VMM to ask for a new amount of RAM to be assigned to the VM.
+
+To use memory hotplug start the VM specifying some size RAM in the `hotplug_size` parameter along with `hotplug_method=virtio-mem` to the memory configuration.
+
+```shell
+$ pushd $CLOUDH
+$ sudo setcap cap_net_admin+ep ./cloud-hypervisor/target/release/cloud-hypervisor
+$ ./cloud-hypervisor/target/release/cloud-hypervisor \
+	--kernel custom-vmlinux.bin \
+	--cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
+	--disk path=focal-server-cloudimg-amd64.raw \
+	--memory size=1024M,hotplug_size=8192M,hotplug_method=virtio-mem \
+	--net "tap=,mac=,ip=,mask=" \
+	--api-socket=/tmp/ch-socket
+$ popd
+```
+
+To ask the VMM to expand the RAM for the VM (request is in bytes):
+
+```shell
+./ch-remote --api-socket=/tmp/ch-socket resize --memory 3G
+```
+
+The new memory is now available to use inside the VM:
+
+```shell
+free -h
+              total        used        free      shared  buff/cache   available
+Mem:          3.0Gi        71Mi       2.8Gi       0.0Ki        47Mi       2.8Gi
+Swap:          32Mi          0B        32Mi
+```
+
+The same API can also be used to reduce the desired RAM for a VM. It is important to note that reducing RAM size might only partially work, as the guest might be using some of it.
+
+## PCI Device Hot Plug
+
+Extra PCI devices can be added and removed from a running Cloud Hypervisor instance. This is controlled by making a HTTP API request to the VMM to ask for the additional device to be added, or for the existing device to be removed.
+
+To use PCI device hotplug start the VM with the HTTP server.
+
+```shell
+$ sudo setcap cap_net_admin+ep ./cloud-hypervisor/target/release/cloud-hypervisor
+$ ./cloud-hypervisor/target/release/cloud-hypervisor \
+	--kernel custom-vmlinux.bin \
+	--cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
+	--disk path=focal-server-cloudimg-amd64.raw \
+	--cpus boot=4 \
+	--memory size=1024M \
+	--net "tap=,mac=,ip=,mask=" \
+	--api-socket=/tmp/ch-socket
+```
+
+Notice the addition of `--api-socket=/tmp/ch-socket`.
+
+### Add VFIO Device
+
+To ask the VMM to add additional VFIO device then use the `add-device` API.
+
+```shell
+./ch-remote --api-socket=/tmp/ch-socket add-device path=/sys/bus/pci/devices/0000:01:00.0/
+```
+
+### Add Disk Device
+
+To ask the VMM to add additional disk device then use the `add-disk` API.
+
+```shell
+./ch-remote --api-socket=/tmp/ch-socket add-disk path=/foo/bar/cloud.img
+```
+
+### Add Fs Device
+
+To ask the VMM to add additional fs device then use the `add-fs` API.
+
+```shell
+./ch-remote --api-socket=/tmp/ch-socket add-fs tag=myfs,socket=/foo/bar/virtiofs.sock
+```
+
+### Add Net Device
+
+To ask the VMM to add additional network device then use the `add-net` API.
+
+```shell
+./ch-remote --api-socket=/tmp/ch-socket add-net tap=chtap0
+```
+
+### Add Pmem Device
+
+To ask the VMM to add additional PMEM device then use the `add-pmem` API.
+
+```shell
+./ch-remote --api-socket=/tmp/ch-socket add-pmem file=/foo/bar.cloud.img
+```
+
+### Add Vsock Device
+
+To ask the VMM to add additional vsock device then use the `add-vsock` API.
+
+```shell
+./ch-remote --api-socket=/tmp/ch-socket add-vsock cid=3,socket=/foo/bar/vsock.sock
+```
+
+### Common Across All PCI Devices
+
+The extra PCI device will be created and advertised to the running kernel. The new device can be found by checking the list of PCI devices.
+
+```shell
+root@ch-guest ~ # lspci
+00:00.0 Host bridge: Intel Corporation Device 0d57
+00:01.0 Unassigned class [ffff]: Red Hat, Inc. Virtio console (rev 01)
+00:02.0 Mass storage controller: Red Hat, Inc. Virtio block device (rev 01)
+00:03.0 Unassigned class [ffff]: Red Hat, Inc. Virtio RNG (rev 01)
+```
+
+After a reboot the added PCI device will remain.
+
+### Remove PCI device
+
+Removing a PCI device works the same way for all kind of PCI devices. The unique identifier related to the device must be provided. This identifier can be provided by the user when adding the new device, or by default Cloud Hypervisor will assign one.
+
+```shell
+./ch-remote --api-socket=/tmp/ch-socket remove-device _disk0
+```
+
+As per adding a PCI device to the guest, after a reboot the VM will be running without the removed PCI device.

docs/intel_sgx.md

@@ -19,7 +19,7 @@ following [instructions](https://github.com/intel/linux-sgx).
 
 ## Cloud-Hypervisor support
 
-Assuming the host exposes `/dev/sgx_virt_epc`, we can pass SGX enclaves through
+Assuming the host exposes `/dev/sgx_vepc`, we can pass SGX enclaves through
 the guest.
 
 In order to use SGX enclaves within a Cloud-Hypervisor VM, we must define one
@@ -32,9 +32,9 @@ memory, the second one being 32MiB with no pre-allocated memory.
     --cpus boot=1 \
     --memory size=1G \
     --disk path=focal-server-cloudimg-amd64.raw \
-    --kernel bzImage \
+    --kernel vmlinux \
     --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
-    --sgx-epc size=64M,prefault=on size=32M,prefault=off
+    --sgx-epc id=epc0,size=64M,prefault=on id=epc1,size=32M,prefault=off
 ```
 
 Once booted, and assuming your guest kernel contains the patches from the
@@ -43,7 +43,7 @@ have been correctly created under `/dev/sgx`:
 
 ```bash
 ls /dev/sgx*
-/dev/sgx_enclave  /dev/sgx_provision  /dev/sgx_virt_epc
+/dev/sgx_enclave  /dev/sgx_provision  /dev/sgx_vepc
 ```
 
 From this point, it is possible to run any SGX application from the guest, as
@@ -51,5 +51,5 @@ it will access `/dev/sgx_enclave` device to create dedicated SGX enclaves.
 
 Note: There is only one contiguous SGX EPC region, which contains all SGX EPC
 sections. This region is exposed through ACPI and marked as reserved through
-the e820 table. It is treated yet as another device, which means it should
+the e820 table. It is treated as yet another device, which means it should
 appear at the end of the guest address space.

docs/io_throttling.md

@@ -0,0 +1,44 @@
+# I/O Throttling
+
+Cloud Hypervisor now supports I/O throttling on virtio-block and virtio-net
+devices. This support is based on the [`rate-limiter` module](https://github.com/firecracker-microvm/firecracker/tree/master/src/rate_limiter)
+from Firecracker. This document explains the user interface of this
+feature, and highlights some internal implementations that can help users
+better understand the expected behavior of I/O throttling in practice.
+
+Cloud Hypervisor allows to limit both the I/O bandwidth (e.g. bytes/s)
+and I/O operations (ops/s) independently. For virtio-net devices, while
+sharing the same "rate limit" from user inputs (on both bandwidth and
+operations), the RX and TX queues are throttled independently.
+To limit the I/O bandwidth, Cloud Hypervisor
+provides three user options, i.e., `bw_size` (bytes), `bw_one_time_burst`
+(bytes), and `bw_refill_time` (ms). Both `bw_size` and `bw_refill_time`
+are required, while `bw_one_time_burst` is optional.
+Internally, these options define a TokenBucket with a maximum capacity
+(`bw_size` bytes), an initial burst size (`bw_one_time_burst`) and an
+interval for refilling purposes (`bw_refill_time`). The "refill-rate" is
+`bw_size` bytes per `bw_refill_time` ms, and it is the constant rate at
+which the tokens replenish. The refill process only starts happening
+after the initial burst budget is consumed. Consumption from the token
+bucket is unbounded in speed which allows for bursts bound in size by
+the amount of tokens available. Once the token bucket is empty,
+consumption speed is bound by the "refill-rate". Similarly, Cloud
+Hypervisor provides another three options for limiting I/O operations,
+i.e., `ops_size` (I/O operations), `bw_one_time_burst` (I/O operations),
+and `bw_refill_time` (ms).
+
+One caveat in the I/O throttling is that every-time the bucket gets
+empty, it will stop I/O operations for a fixed amount of time
+(`cool_down_time`). The `cool_down_time` now is fixed at `100 ms`, it
+can have big implications to the actual rate limit (which can be a lot
+different the expected "refill-rate" derived from user inputs). For
+example, to have a 1000 IOPS limit on a virtio-blk device, users should
+be able to provide either of the following two options:
+`ops_size=1000,ops_refill_time=1000` or
+`ops_size=10,ops_refill_time=10`. However, the actual IOPS limits are
+likely to be ~1000 IOPS and ~100 IOPS respectively. The reason is the
+actual rate limit users get can be as low as
+`ops_size/(ops_refill_time+cool_down_time)`. As a result, it is
+generally advisable to keep `bw/ops_refill_time` larger than `100 ms`
+(`cool_down_time`) to make sure the actual rate limit is close to users'
+expectation ("refill-rate").

docs/iommu.md

@@ -89,7 +89,7 @@ virtual IOMMU:
     --cpus boot=1 \
     --memory size=512M \
     --disk path=focal-server-cloudimg-amd64.raw,iommu=on \
-    --kernel custom-bzImage \
+    --kernel custom-vmlinux \
     --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
 ```
 
@@ -166,7 +166,7 @@ be consumed.
     --cpus boot=1 \
     --memory size=8G,hugepages=on \
     --disk path=focal-server-cloudimg-amd64.raw \
-    --kernel custom-bzImage \
+    --kernel custom-vmlinux \
     --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw hugepagesz=2M hugepages=2048" \
     --net tap=,mac=,iommu=on
 ```
@@ -183,7 +183,7 @@ passing through is `0000:00:01.0`.
     --cpus boot=1 \
     --memory size=8G,hugepages=on \
     --disk path=focal-server-cloudimg-amd64.raw \
-    --kernel custom-bzImage \
+    --kernel custom-vmlinux \
     --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw kvm-intel.nested=1 vfio_iommu_type1.allow_unsafe_interrupts rw hugepagesz=2M hugepages=2048" \
     --device path=/sys/bus/pci/devices/0000:00:01.0,iommu=on
 ```
@@ -194,6 +194,7 @@ guest, and bind it to VFIO (it should appear as `0000:00:04.0`).
 ```bash
 echo 0000:00:04.0 > /sys/bus/pci/devices/0000\:00\:04.0/driver/unbind
 echo 8086 1502 > /sys/bus/pci/drivers/vfio-pci/new_id
+echo 0000:00:04.0 > /sys/bus/pci/drivers/vfio-pci/bind
 ```
 
 Last thing is to start the L2 guest with the huge pages memory backend.
@@ -203,7 +204,7 @@ Last thing is to start the L2 guest with the huge pages memory backend.
     --cpus boot=1 \
     --memory size=4G,hugepages=on \
     --disk path=focal-server-cloudimg-amd64.raw \
-    --kernel custom-bzImage \
+    --kernel custom-vmlinux \
     --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
     --device path=/sys/bus/pci/devices/0000:00:04.0
 ```

docs/live_migration.md

@@ -0,0 +1,139 @@
+# Live Migration
+
+This document gives two examples of how to use the live migration
+support in Cloud Hypervisor:
+
+1. local migration - migrating between two VMs running on the same
+   machine;
+1. nested-vm migration - migrating between two nested VMs whose host VMs
+   are running on the same machine.
+
+## Local Migration
+Launch the source VM (on the host machine):
+```bash
+$ target/release/cloud-hypervisor
+    --kernel ~/workloads/vmlinux \
+    --disk path=~/workloads/focal.raw \
+    --cpus boot=1 --memory size=1G \
+    --cmdline "root=/dev/vda1 console=ttyS0"  \
+    --serial tty --console off --api-socket=/tmp/api1
+```
+
+Launch the destination VM from the same directory (on the host machine):
+```bash
+$ target/release/cloud-hypervisor --api-socket=/tmp/api2
+```
+
+Get ready for receiving migration for the destination VM (on the host machine):
+```bash
+$ target/release/ch-remote --api-socket=/tmp/api2 receive-migration unix:/tmp/sock
+```
+
+Start to send migration for the source VM (on the host machine):
+```bash
+$ target/release/ch-remote --api-socket=/tmp/api1 send-migration unix:/tmp/sock
+```
+
+When the above commands completed, the source VM should be successfully
+migrated to the destination VM. Now the destination VM is running while
+the source VM is paused.
+
+## Nested-VM Migration
+
+Launch VM 1 (on the host machine) with an extra virtio-blk device for
+exposing a guest image for the nested source VM:
+> Note: the example below also attached an additional virtio-blk device
+> with a dummy image for testing purpose (which is optional).
+```bash
+$ head -c 1M < /dev/urandom > tmp.img # create a dummy image for testing
+$ sudo /target/release/cloud-hypervisor \
+        --serial tty --console off \
+        --cpus boot=1 --memory size=512M \
+        --kernel vmlinux \
+        --cmdline "root=/dev/vda1 console=ttyS0"  \
+        --disk path=focal-1.raw path=focal-nested.raw path=tmp.img\
+        --net ip=192.168.101.1
+```
+
+Launch VM 2 (on the host machine) with an extra virtio-blk device for
+exposing the same guest image for the nested destination VM:
+```bash
+$ sudo /target/release/cloud-hypervisor \
+        --serial tty --console off \
+        --cpus boot=1 --memory size=512M \
+        --kernel vmlinux \
+        --cmdline "root=/dev/vda1 console=ttyS0"  \
+        --disk path=focal-2.raw path=focal-nested.raw path=tmp.img\
+        --net ip=192.168.102.1
+```
+
+Launch the nested source VM (inside the guest OS of the VM 1) :
+```bash
+vm-1:~$ sudo ./cloud-hypervisor \
+        --serial tty --console off \
+        --memory size=128M \
+        --kernel vmlinux \
+        --cmdline "console=ttyS0 root=/dev/vda1" \
+        --disk path=/dev/vdb path=/dev/vdc \
+        --api-socket=/tmp/api1 \
+        --net ip=192.168.100.1
+vm-1:~$ # setup the guest network if needed
+vm-1:~$ sudo ip addr add 192.168.101.2/24 dev ens4
+vm-1:~$ sudo ip link set up dev ens4
+vm-1:~$ sudo ip r add default via 192.168.101.1
+```
+Optional: Run the guest workload below (on the guest OS of the nested source VM),
+which performs intensive virtio-blk operations. Now the console of the nested
+source VM should repeatedly print `"equal"`, and our goal is migrating
+this VM and the running workload without interruption.
+```bash
+#/bin/bash
+
+# On the guest OS of the nested source VM
+
+input="/dev/vdb"
+result=$(md5sum $input)
+tmp=$(md5sum $input)
+
+while  [[ "$result" == "$tmp" ]]
+do
+    echo "equal"
+    tmp=$(md5sum $input)
+done
+
+echo "not equal"
+echo "result = $result"
+echo "tmp = $tmp"
+```
+
+Launch the nested destination VM (inside the guest OS of the VM 2):
+```bash
+vm-2:~$ sudo ./cloud-hypervisor --api-socket=/tmp/api2
+vm-2:~$ # setup the guest network with the following commands if needed
+vm-2:~$ sudo ip addr add 192.168.102.2/24 dev ens4
+vm-2:~$ sudo ip link set up dev ens4
+vm-2:~$ sudo ip r add default via 192.168.102.1
+vm-2:~$ ping 192.168.101.2 # This should succeed
+```
+> Note: If the above ping failed, please check the iptables rule on the
+> host machine, e.g. whether the policy for the `FORWARD` chain is set
+> to `DROP` (which is the default setting configured by Docker).
+
+Get ready for receiving migration for the nested destination VM (inside
+the guest OS of the VM 2):
+```bash
+vm-2:~$ sudo ./ch-remote --api-socket=/tmp/api2 receive-migration unix:/tmp/sock2
+vm-2:~$ sudo socat TCP-LISTEN:6000,reuseaddr UNIX-CLIENT:/tmp/sock2
+```
+
+Start to send migration for the nested source VM (inside the guest OS of
+the VM 1):
+```bash
+vm-1:~$ sudo socat UNIX-LISTEN:/tmp/sock1,reuseaddr TCP:192.168.102.2:6000
+vm-1:~$ sudo ./ch-remote --api-socket=/tmp/api1 send-migration unix:/tmp/sock1
+```
+
+When the above commands completed, the source VM should be successfully
+migrated to the destination VM without interrupting our testing guest
+workload. Now the destination VM is running the testing guest workload
+while the source VM is paused.

docs/macvtap-bridge.md

@@ -1,6 +1,6 @@
 # Using MACVTAP to Bridge onto Host Network
 
-Cloud Hypervisor supports using a MACVTAP device which is derived from a MACVLAN. Full details of configuring MACVLAN or MACVTAP is out of scope of this document. However the example below indicates how to bridge the guest directly onto the the network the host is on. Due to the lack of hairpin mode it not usually possible to reach the guest directly from the host.
+Cloud Hypervisor supports using a MACVTAP device which is derived from a MACVLAN. Full details of configuring MACVLAN or MACVTAP is out of scope of this document. However the example below indicates how to bridge the guest directly onto the network the host is on. Due to the lack of hairpin mode it not usually possible to reach the guest directly from the host.
 
 ```bash
 # The MAC address must be attached to the macvtap and be used inside the guest

docs/memory.md

@@ -343,15 +343,16 @@ it allows for specifying the distance between each NUMA node.
 
 ```rust
 struct NumaConfig {
-    id: u32,
+    guest_numa_id: u32,
     cpus: Option<Vec<u8>>,
     distances: Option<Vec<NumaDistance>>,
     memory_zones: Option<Vec<String>>,
+    sgx_epc_sections: Option<Vec<String>>,
 }
 ```
 
 ```
---numa <numa>	Settings related to a given NUMA node "id=<node_id>,cpus=<cpus_id>,distances=<list_of_distances_to_destination_nodes>,memory_zones=<list_of_memory_zones>"
+--numa <numa>	Settings related to a given NUMA node "guest_numa_id=<node_id>,cpus=<cpus_id>,distances=<list_of_distances_to_destination_nodes>,memory_zones=<list_of_memory_zones>,sgx_epc_sections=<list_of_sgx_epc_sections>"
 ```
 
 ### `guest_numa_id`
@@ -394,8 +395,7 @@ _Example_
 
 ```
 --cpus boot=8
---numa guest_numa_id=0,cpus=1-3:7
---numa guest_numa_id=1,cpus=0:4-6
+--numa guest_numa_id=0,cpus=1-3:7 guest_numa_id=1,cpus=0:4-6
 ```
 
 ### `distances`
@@ -420,9 +420,7 @@ different distances, it can be described with the following example.
 _Example_
 
 ```
---numa guest_numa_id=0,distances=1@15:2@25
---numa guest_numa_id=1,distances=0@15:2@20
---numa guest_numa_id=2,distances=0@25:1@20
+--numa guest_numa_id=0,distances=1@15:2@25 guest_numa_id=1,distances=0@15:2@20 guest_numa_id=2,distances=0@25:1@20
 ```
 
 ### `memory_zones`
@@ -445,9 +443,30 @@ _Example_
 
 ```
 --memory size=0
---memory-zone id=mem0,size=1G
---memory-zone id=mem1,size=1G
---memory-zone id=mem2,size=1G
---numa guest_numa_id=0,memory_zones=mem0:mem2
---numa guest_numa_id=1,memory_zones=mem1
+--memory-zone id=mem0,size=1G id=mem1,size=1G id=mem2,size=1G
+--numa guest_numa_id=0,memory_zones=mem0:mem2 guest_numa_id=1,memory_zones=mem1
 ```
+
+### `sgx_epc_sections`
+
+List of SGX EPC sections attached to the guest NUMA node identified by the
+`guest_numa_id` option. This allows for describing a list of SGX EPC sections
+which must be seen by the guest as belonging to the NUMA node `guest_numa_id`.
+
+Multiple values can be provided to define the list. Each value is a string
+referring to an existing SGX EPC section identifier. Values are separated from
+each other with the `:` separator.
+
+_Example_
+
+```
+--sgx-epc id=epc0,size=32M id=epc1,size=64M id=epc2,size=32M
+--numa guest_numa_id=0,sgx_epc_sections=epc1 guest_numa_id=1,sgx_epc_sections=epc0:epc2
+```
+
+### PCI bus
+
+Cloud Hypervisor supports only one PCI bus, which is why it has been tied to
+the NUMA node 0 by default. It is the user responsibility to organize the NUMA
+nodes correctly so that vCPUs and guest RAM which should be located on the same
+NUMA node as the PCI bus end up on the NUMA node 0.

docs/networking.md

@@ -2,7 +2,7 @@
 
 cloud-hypervisor can emulate one or more virtual network interfaces, represented at the hypervisor host by [tap devices](https://www.kernel.org/doc/Documentation/networking/tuntap.txt). This guide briefly describes, in a manual and distribution neutral way, how to setup and use networking with cloud-hypervisor.
 
-## Multiple queue support for net devices ##
+## Multiple queue support for net devices
 
 While multiple vcpus defined for guest, to gain the benefit of vcpu scalable to improve performance, it suggests to define multiple queue pairs for net devices, one Tx/Rx queue pair per one vcpu, that means the number of queue pairs at least is equal to the vcpu count. In that case, after virtnet driver set cpu affinity for virtqueues in guest kernel, vcpus could handle interrupt from different virtqueue pairs in parallel.
 
@@ -23,7 +23,7 @@ Use one `--net` command-line argument from cloud-hypervisor to specify the emula
 
 ```bash
 ./cloud-hypervisor \
-    --cpus 4 \
+    --cpus boot=4 \
     --memory "size=512M" \
     --disk path=focal-server-cloudimg-amd64.raw \
     --kernel my-vmlinux.bin \
@@ -34,14 +34,14 @@ Use one `--net` command-line argument from cloud-hypervisor to specify the emula
 
 The `--net` argument takes 1 or more space-separated strings of key value pairs containing the following 4 keys or fields:
 
-| Name       | Purpose                    | Optional  |
-| -----------|----------------------------| ----------|
-| tap        | tap device name            | Yes       |
-| mac        | vNIC mac address           | Yes       |
-| ip         | tap IP IP address          | yes       |
-| mask       | tap IP netmask             | Yes       |
-| num_queues | the number of queues       | yes       |
-| queue_size | the size of each queue     | Yes       |
+| Name       | Purpose                | Optional |
+| ---------- | ---------------------- | -------- |
+| tap        | tap device name        | Yes      |
+| mac        | vNIC mac address       | Yes      |
+| ip         | tap IP IP address      | yes      |
+| mask       | tap IP netmask         | Yes      |
+| num_queues | the number of queues   | yes      |
+| queue_size | the size of each queue | Yes      |
 
 num_queues is the total number of tx and rx queues, the default value is 2, and it could be increased by multiples of 2. Additionally, num_queues is suggested to be as 2 times of vcpu count. The default value for queue_size is 256.
 
@@ -104,6 +104,7 @@ bridge name     bridge id               STP enabled     interfaces
 ich-dpl         8000.067afc1b9a67       no              ich1
 ich-int         8000.725412ffce6f       no              ich0
 ```
+
 This completes the layer 2 wiring: The cloud-hypervisor is now connected to the hypervisor host via the 2 linux bridges.
 
 ## IP (Layer 3) provisioning
@@ -116,6 +117,7 @@ On the hypervisor host add the network gateway IP address of each network to the
 root@host:~# ip addr add 192.168.4.1/24 dev ich-int
 root@host:~# ip addr add 10.0.1.1/24 dev ich-dpl
 ```
+
 The routing table of the hypervisor host should now also have corresponding routing entries:
 
 ```bash
@@ -127,9 +129,10 @@ Destination     Gateway         Genmask         Flags Metric Ref    Use Iface
 192.168.4.0     0.0.0.0         255.255.255.0   U     0      0        0 ich-int
 192.168.178.0   0.0.0.0         255.255.255.0   U     600    0        0 wlan1
 ```
+
 ### Virtual Machine
 
-Within the virtual machine set the vNIC's to up state and provision the corresponding IP addresses on the 2 vNIC's. The steps outlined below use the ip command as an example. Alternative distribution specific procedures can also apply.   
+Within the virtual machine set the vNIC's to up state and provision the corresponding IP addresses on the 2 vNIC's. The steps outlined below use the ip command as an example. Alternative distribution specific procedures can also apply.
 
 ```bash
 root@guest:~# ip link set up enp0s2
@@ -165,7 +168,7 @@ root@192.168.4.2's password:
 Linux cloud-hypervisor 5.2.0 #2 SMP Thu Jul 11 08:08:16 CEST 2019 x86_64
 
 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
-permitted by applicable law.                                                         
+permitted by applicable law.
 
 
 Last login: Fri Jul 12 13:27:56 2019 from 192.168.4.1
@@ -189,7 +192,7 @@ nameserver 192.168.178.1
 make sure that the default gateway of the hypervisor host (in this example host 192.168.178.1 which is an adsl router) has an entry in the routing table for the 192.168.4.0/24 network otherwise IP connectivity will not work.
 
 ```bash
-root@guest:~# nslookup  ftp.nl.debian.org       
+root@guest:~# nslookup  ftp.nl.debian.org
 Server:         192.168.178.1
 Address:        192.168.178.1#53
 

docs/profiling.md

@@ -1,6 +1,6 @@
 # Profiling
 
-`perf` can be used to profile the `cloud-hypervisor` binary but it is necessary to make some modifications to the the build in order to produce a binary that gives useful results.
+`perf` can be used to profile the `cloud-hypervisor` binary but it is necessary to make some modifications to the build in order to produce a binary that gives useful results.
 
 ## Building a suitable binary
 

docs/seccomp.md

@@ -0,0 +1,68 @@
+# Seccomp filtering
+
+As a means to harden Cloud Hypervisor's security, the project leverages seccomp
+filtering.
+
+## What is seccomp filtering
+
+A seccomp filter is a way for a process to tell the kernel which system calls
+are authorized.
+In case this process calls into a prohibited system call, the kernel will kill
+the process right away.
+
+## How does it apply to Cloud Hypervisor
+
+Cloud Hypervisor is a multi threaded application. It spawns dedicated threads
+for virtual CPUs, virtio devices and HTTP server, along with the main thread
+representing the VMM.
+
+Each of these threads has a limited scope of what it is expected to perform,
+which is why different filters are applied to each of them.
+
+By default, Cloud Hypervisor enables seccomp filtering as the project believes
+that security should not be an option.
+
+For development and debugging purposes, one might want to disable this feature
+or log the faulty system call.
+
+### Disabling seccomp filters
+
+Append `--seccomp false` to Cloud Hypervisor's command line to prevent seccomp
+filtering from being applied.
+
+### Logging prohibited system calls
+
+In the context of debug, one alternative to disabling seccomp filtering is to
+log faulty system calls that would have caused the application to be killed by
+the kernel.
+
+Append `--seccomp log` to Cloud Hypervisor's command line to enable faulty
+system calls to be logged.
+
+The kernel running on the host machine must have the `audit` parameter enabled.
+If this is not the case, update kernel boot options by appending `audit=1`.
+
+Unauthorized system calls will be logged to the journal similarly to the
+following example
+
+```
+type=SECCOMP msg=audit(1423263412.694:7878): auid=1000 uid=1000 gid=1000 ses=3 subj=unconfined_u:unconfined_r:cloud_hypervisor:s0-s0:c0.c1023 pid=1193 comm="cloud-hypervisor" exe="/usr/bin/cloud-hypervisor" sig=0 arch=c000003e syscall=47 compat=0 ip=0x7f4f63982604 code=0x50000
+```
+
+Provided `ausyscall` has been installed on the host, the system call can be
+identified with
+
+```
+$ ausyscall 47
+recvmsg
+```
+
+### Further debug with `strace`
+
+One more way of debugging seccomp related issues is to use the `strace` tool as
+it will log every system call issued by the process. It is important to use
+`-f` option in order to trace each and every thread belonging to the process.
+
+```
+strace -f ./cloud-hypervisor ...
+```

docs/snapshot_restore.md

@@ -20,7 +20,7 @@ First thing, we must run a Cloud-Hypervisor VM:
     --api-socket /tmp/cloud-hypervisor.sock \
     --cpus boot=4 \
     --memory size=4G \
-    --kernel bzImage \
+    --kernel vmlinux \
     --cmdline "root=/dev/vda1 console=hvc0 rw" \
     --disk path=focal-server-cloudimg-amd64.raw
 ```

docs/vfio.md

@@ -11,7 +11,7 @@ by the VFIO kernel drivers. However, by default, a host device will be bound to
 its native driver, which is not the VFIO one.
 
 As a consequence, a device must be unbound from its native driver before passing
-it to `cloud-hypervisor` for assigning it to a guess.
+it to `cloud-hypervisor` for assigning it to a guest.
 
 ### Example
 
@@ -54,6 +54,7 @@ $ lspci -n -s 01:00.0
 01:00.0 ff00: 10ec:525a (rev 01)
 
 $ echo 10ec 525a > /sys/bus/pci/drivers/vfio-pci/new_id
+$ echo 0000:01:00.0 > /sys/bus/pci/drivers/vfio-pci/bind
 ```
 
 Now the device is managed by the VFIO framework.

docs/vhost-user-blk-testing.md

@@ -35,38 +35,52 @@ Here are some good references for detailing them.
 
 ## Test environment
 
-The below test environment is based on ubuntu release(16.04.1 LTS), as for other system, please check related document.
-The test runs with multiple queue (MQ) support enabled, using 4 queues defined for both SPDK and the virtual machine.
-Here are the details on how the test can be run.
+The below test environment is based on Ubuntu release (20.04.1 LTS), as for other system, please check related documents.
+This test runs with multiple queue (MQ) support enabled, using 4 queues defined for both SPDK and the virtual machine.
+Here are the detailed instructions.
 
-### The hugepages settings in host linux
-Add "default_hugepagesz=1G hugepagesz=1G hugepages=2" into host linux cmdline.
-As for how to change Ubuntu linux cmdline in grub file, please ref below link:
-https://www.ostechnix.com/configure-grub-2-boot-loader-settings-ubuntu-16-04/
-reboot Ubuntu
-sudo mount -t hugetlbfs -o pagesize=1G none /dev/hugepages
+### The hugepages settings on the host
+Allocate enough persistent huge pages (e.g. 2GiB) on the host:
+
+```bash
+# Assume the default hugepage size is 2MiB
+echo 1024 | sudo tee /proc/sys/vm/nr_hugepages
+# Confirm the value of "Hugepagesize" and "HugePages_Total"
+cat /proc/meminfo | grep -i huge
+```
 
 ### Download the SPDK code
+```bash
 git clone https://github.com/spdk/spdk
 cd spdk
 git submodule update --init
+```
 
 ### Create the build dep
-./scripts/pkgdep.sh
 
-### Build spdk
+```bash
+./scripts/pkgdep.sh
+```
+
+### Build SPDK
+```bash
 ./configure
 make
+```
 
-### Set the SPDk environment
+### Set the SPDK environment
+```bash
 sudo HUGEMEM=2048 scripts/setup.sh
-sudo ./app/vhost/vhost -S /var/tmp -s 1024 -m 0x3 &
+sudo ./build/bin/vhost -S /var/tmp -s 1024 -m 0x3 &
+```
 
 ### Create 512M block device
+```bash
 sudo scripts/rpc.py bdev_malloc_create 512 512 -b Malloc0
 sudo scripts/rpc.py vhost_create_blk_controller --cpumask 0x1 vhost.1 Malloc0
+```
 
-_Launch the VM_
+### Launch the VM
 
 VMs run in client mode. They connect to the socket created by the `dpdkvhostuser` in the SPDK backend.
 ```bash
@@ -89,9 +103,9 @@ login in guest
 # Use lsblk command to find out vhost-user-blk device
 lsblk
 NAME    MAJ:MIN RM  SIZE RO TYPE MOUNTPOINT
-vda     252:0    0  2.2G  0 disk 
+vda     252:0    0  2.2G  0 disk
 ├─vda1  252:1    0  2.1G  0 part /
-├─vda14 252:14   0    4M  0 part 
+├─vda14 252:14   0    4M  0 part
 └─vda15 252:15   0  106M  0 part /boot/efi
 vdb    253:16   0  512M  0 disk
 

docs/vhost-user-net-testing.md

@@ -1,27 +1,30 @@
 # How to test Vhost-user net with OpenVSwitch/DPDK
 
-The purpose of this document is to illustrate how to test vhost-user-net in cloud-hypervisor with OVS/DPDK as the backend.
+The purpose of this document is to illustrate how to test vhost-user-net
+in cloud-hypervisor with OVS/DPDK as the backend. This document was
+tested with Open vSwitch v2.13.1, DPDK v19.11.3, and Cloud Hypervisor
+v15.0 on Ubuntu 20.04.1 (host kernel v5.4.0).
 
 ## Framework
 
 It's a simple test to validate the communication between two virtual machine, connecting them to vhost-user ports respectively provided by `OVS/DPDK`.
 ```
-             +----+----------+          +-------------+-----------+-------------+          +----------+----+  
-             |    |          |          |             |           |             |          |          |    | 
-             |    |vhost-user|----------| vhost-user  |   ovs     | vhost-user  |----------|vhost-user|    |           
-             |    |net device|          | port 1      |           | port 2      |          |net device|    |           
-             |    |          |          |             |           |             |          |          |    |           
-             |    +----------+          +-------------+-----------+-------------+          +----------+    |           
-             |               |          |                                       |          |               |           
-             |vm1            |          |                  dpdk                 |          |           vm2 |           
-             |               |          |                                       |          |               |           
-          +--+---------------------------------------------------------------------------------------------+--+        
-          |  |                                       hugepages                                             |  |        
-          |  +---------------------------------------------------------------------------------------------+  |        
-          |                                                                                                   |        
-          |                                              host                                                 |        
-          |                                                                                                   |  
-          +---------------------------------------------------------------------------------------------------+        
+             +----+----------+          +-------------+-----------+-------------+          +----------+----+
+             |    |          |          |             |           |             |          |          |    |
+             |    |vhost-user|----------| vhost-user  |   ovs     | vhost-user  |----------|vhost-user|    |
+             |    |net device|          | port 1      |           | port 2      |          |net device|    |
+             |    |          |          |             |           |             |          |          |    |
+             |    +----------+          +-------------+-----------+-------------+          +----------+    |
+             |               |          |                                       |          |               |
+             |vm1            |          |                  dpdk                 |          |           vm2 |
+             |               |          |                                       |          |               |
+          +--+---------------------------------------------------------------------------------------------+--+
+          |  |                                       hugepages                                             |  |
+          |  +---------------------------------------------------------------------------------------------+  |
+          |                                                                                                   |
+          |                                              host                                                 |
+          |                                                                                                   |
+          +---------------------------------------------------------------------------------------------------+
 ```
 ## Prerequisites
 
@@ -30,44 +33,54 @@ Prior to running the test, the following steps need to be performed.
 - Install DPDK
 - Install OVS
 
-Here are some good references for detailing them.
-- Red Hat
-	* https://wiki.qemu.org/Documentation/vhost-user-ovs-dpdk
-- Ubuntu server
-	* https://help.ubuntu.com/lts/serverguide/DPDK.html
-	* https://software.intel.com/en-us/articles/set-up-open-vswitch-with-dpdk-on-ubuntu-server
+Here is a good reference for setting up OVS with DPDK from scratch:
+https://docs.openvswitch.org/en/latest/intro/install/dpdk/.
 
+On Ubuntu systems (18.04 or newer), the OpenVswitch-DPDK package can be
+easily installed with:
+```bash
+sudo apt-get update
+sudo apt-get install openvswitch-switch-dpdk
+sudo update-alternatives --set ovs-vswitchd /usr/lib/openvswitch-switch-dpdk/ovs-vswitchd-dpdk
+```
 ## Test
-The test runs with multiple queue (MQ) support enabled, using 2 pairs of TX/RX queues defined for both OVS and the virtual machine. Here are the details on how the test can be run.
+The test runs with multiple queue (MQ) support enabled, using 2 pairs of
+TX/RX queues defined for both OVS and the virtual machine. Here are the
+detailed instructions.
 
 _Setup OVS_
 
-`ovs_test.sh` is created to setup and start OVS. OVS will provide the `dpdkvhostuser` backend running in server mode.
+Here is an example how to configure a basic OpenVswitch using DPDK:
 ```bash
-mkdir -p /var/run/openvswitch
+# load the ovs kernel module
 modprobe openvswitch
-killall ovsdb-server ovs-vswitchd
-rm -f /var/run/openvswitch/vhost-user*
-rm -f /etc/openvswitch/conf.db
-export DB_SOCK=/var/run/openvswitch/db.sock
-ovsdb-tool create /etc/openvswitch/conf.db /usr/share/openvswitch/vswitch.ovsschema
-ovsdb-server --remote=punix:$DB_SOCK --remote=db:Open_vSwitch,Open_vSwitch,manager_options --pidfile --detach
-ovs-vsctl --no-wait init
-ovs-vsctl --no-wait set Open_vSwitch . other_config:dpdk-lcore-mask=0xf
-ovs-vsctl --no-wait set Open_vSwitch . other_config:dpdk-socket-mem=1024
-ovs-vsctl --no-wait set Open_vSwitch . other_config:dpdk-init=true
-ovs-vsctl --no-wait set Open_vSwitch . other_config:pmd-cpu-mask=0xf
-ovs-vswitchd unix:$DB_SOCK --pidfile --detach --log-file=/var/log/openvswitch/ovs-vswitchd.log
+sudo service openvswitch-switch start
+ovs-vsctl init
+ovs-vsctl set Open_vSwitch . other_config:dpdk-init=true
+# run on core 0-3 only
+ovs-vsctl set Open_vSwitch . other_config:dpdk-lcore-mask=0xf
+# allocate 2G huge pages (to NUMA 0 only)
+ovs-vsctl set Open_vSwitch . other_config:dpdk-socket-mem=1024
+# run PMD (Pull Mode Driver) threads on core 0-3 only
+ovs-vsctl set Open_vSwitch . other_config:pmd-cpu-mask=0xf
+sudo service openvswitch-switch restart
+# double check the configurations
+ovs-vsctl list Open_vSwitch
+```
+
+Here is an example how to create a bridge and add two DPDK ports to it
+(for later use via Cloud Hypervisor):
+```bash
+# create a bridge
 ovs-vsctl add-br ovsbr0 -- set bridge ovsbr0 datapath_type=netdev
+# create two DPDK ports and add them to the bridge
 ovs-vsctl add-port ovsbr0 vhost-user1 -- set Interface vhost-user1 type=dpdkvhostuser
-ovs-vsctl add-port ovsbr0 vhost-user2 -- set Interface vhost-user2 type=dpdkvhostuser
+ovs-vsctl add-port ovsbr0 vhost-user2 -- set Interface vhost-user2
+type=dpdkvhostuser
+# set the number of rx queues
 ovs-vsctl set Interface vhost-user1 options:n_rxq=2
 ovs-vsctl set Interface vhost-user2 options:n_rxq=2
 ```
-_Run ovs_test.sh_
-```bash
-./ovs_test.sh
-```
 
 _Launch the VMs_
 
@@ -89,19 +102,21 @@ VMs run in client mode. They connect to the socket created by the `dpdkvhostuser
         --kernel vmlinux \
         --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
         --disk path=focal-server-cloudimg-amd64.raw   \
-        --net "mac=52:54:20:11:C5:02,vhost_user=true,socket=/var/run/openvswitch/vhost-user2,num_queues=4"
+        --net mac=52:54:20:11:C5:02,vhost_user=true,socket=/var/run/openvswitch/vhost-user2,num_queues=4
 ```
 
 _Setup VM1_
 ```bash
 # From inside the guest
-sudo ip addr add 172.100.0.1/24 dev enp0s3
+sudo ip addr add 172.100.0.1/24 dev ens2
+sudo ip link set up dev ens2
 ```
 
 _Setup VM2_
 ```bash
 # From inside the guest
-sudo ip addr add 172.100.0.2/24 dev enp0s3
+sudo ip addr add 172.100.0.2/24 dev ens2
+sudo ip link set up dev ens2
 ```
 
 _Ping VM1 from VM2_
@@ -129,4 +144,3 @@ _Run VM2 as client_
 # From inside the guest
 iperf3 -c 172.100.0.1 -t 30 -p 4444 &
 ```
-

docs/virtiofs-root.md

@@ -0,0 +1,92 @@
+# HOWTO VirtioFS rootfs
+
+A quick guide for using virtiofs as a cloud-hypervisor guest's rootfs (i.e.
+with no root block device). This document is a quick getting started guide.
+There are many more steps to take to make this a production ready, secure
+setup.
+
+## Prerequisites
+
+1. virtiofsd from the qemu project
+   * We are using the Qemu version for now
+   * There is a Rust version being worked on that may be a better option in the future
+   * Part of the qemu-system-common package on Ubuntu
+   * Part of the qemu-common package on Fedora
+2. cloud-hypervisor - the newer the better, but I tested with 0.12
+3. a rootfs - This howto uses an alpine rootfs available here:
+   * https://dl-cdn.alpinelinux.org/alpine/v3.13/releases/x86_64/alpine-minirootfs-3.13.2-x86_64.tar.gz
+   * Others should work
+
+## To create the VM rootfs
+
+```bash
+mkdir rootfs/
+cd rootfs
+# this needs sudo to be able to set root permissions on fs components
+sudo tar -xf /path/to/alpine-minirootfs-3.13.1-x86_64.tar.gz
+# this will get created when the VM actually boots by the dhcp client
+# but we need it in the chroot to download packages
+sudo cp /etc/resolv.conf etc/
+# the alpine mini rootfs is meant for docker containers, we need a few extra
+# things for a working rootfs
+sudo chroot $PWD apk add openrc busybox-initscripts
+# we are using the paravirt console in cloud-hypervisor, so enable it in init
+# append it after the other console since it doesn't work just appending it
+sudo sed -i '/vt100/a \n# paravirt console\nhvc0::respawn:/sbin/getty -L hvc0 115200 vt100' etc/inittab
+# set no password for root user... you obviously don't want to do this for
+# any sort of production setup
+sudo sed -i 's/root:!::0:::::/root:::0:::::/' etc/shadow
+# set up init scripts
+for i in acpid crond
+    sudo ln -sf /etc/init.d/$i etc/runlevels/default/$i
+end
+for i in bootmisc hostname hwclock loadkmap modules networking swap sysctl syslog urandom
+    sudo ln -sf /etc/init.d/$i etc/runlevels/boot/$i
+end
+
+for i in killprocs mount-ro savecache
+    sudo ln -sf /etc/init.d/$i etc/runlevels/shutdown/$i
+end
+
+for i in devfs dmesg hwdrivers mdev
+    sudo ln -sf /etc/init.d/$i etc/runlevels/sysinit/$i
+end
+# setup network config
+echo 'auto lo
+iface lo inet loopback
+
+auto eth0
+iface eth0 inet dhcp
+' | sudo tee etc/network/interfaces
+
+```
+
+## To run the VM
+
+```bash
+# starting in the directory above rootfs
+sudo virtiofsd --socket-path=$PWD/virtiofs-rootfs.sock -o source=$PWD/rootfs -o cache=none &
+sudo cloud-hypervisor \
+    --cpus boot=1,max=1 \
+    --kernel vmlinux \
+    --fs tag=/dev/root,socket=$PWD/virtiofs-rootfs.sock \
+    --memory size=2G,shared=on \
+    --cmdline "console=hvc0 rootfstype=virtiofs root=/dev/root ro debug" \
+    --api-socket $PWD/ch.sock \
+    --rng \
+    --net ...
+```
+
+Note: an important part of the above is the `tag=/dev/root` and
+`root=/dev/root` parts. For whatever reason, it would only work with that as
+the tag.
+
+Note: another important bit is that the memory is shared. This is required for
+virtiofs
+
+## Message from the author
+
+If you find any issues or have suggestions, feel free to reach out to @iggy on
+the cloud-hypervisor slack. Also if this works for you, I'd like to know as
+well. It would also be nice to get steps for preparing other distribution root
+filesystems.

docs/windows.md

@@ -184,6 +184,16 @@ Set-Service -Name sshd -StartupType ‘Automatic’
 
 This allows for SSH login from a remote machine, for example through the `administrator` user: `ssh administrator@192.168.249.2`. For a more detailed OpenSSH guide, please follow the MSDN article from the [links](#links) section.
 
+## Hotplug capability
+
+CPU hotplug is supported. The VM operating system needs to support hotplug and be appropriately licensed. SKU limitations like constraints on the number of cores are to be taken into consideration. Note, that Windows doesn't support CPU hot-remove. When `ch-remote` is invoked to reduce the number of CPUs, the result will be visible after the OS reboot within the same hypervisor instance.
+
+RAM hotplug is supported. Note, that while the `pnpmem.sys` driver in use supports RAM hot-remove, the RAM being unplugged has to be not in use and have no reserved pages. In most cases it means, hot-remove won't work. Same as with the CPU hot-remove, when `ch-remote` is invoked to reduce the RAM size, the result will be visible after the OS reboot.
+
+Network device hotplug and hot-remove are supported.
+
+Disk hotplug and hot-remove are supported. After the device has been hotplugged, it will need to be onlined from within the guest. Among other tools, powershell applets `Get-Disk` and `Set-Disk` can be used for the disk configuration and activation.
+
 ## Debugging
 
 The Windows guest debugging process relies heavily on QEMU and [socat](http://www.dest-unreach.org/socat/). The procedure requires two Windows VMs:

event_monitor/Cargo.toml

@@ -0,0 +1,11 @@
+[package]
+name = "event_monitor"
+version = "0.1.0"
+authors = ["The Cloud Hypervisor Authors"]
+edition = "2018"
+
+[dependencies]
+libc = "0.2.98"
+serde = {version = ">=1.0.27", features = ["rc"] }
+serde_derive = ">=1.0.27"
+serde_json = ">=1.0.9"

event_monitor/src/lib.rs

@@ -0,0 +1,77 @@
+// Copyright © 2021 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#[macro_use]
+extern crate serde_derive;
+
+use std::borrow::Cow;
+use std::collections::HashMap;
+use std::fs::File;
+use std::os::unix::io::AsRawFd;
+use std::time::{Duration, Instant};
+
+static mut MONITOR: Option<(File, Instant)> = None;
+
+/// This function must only be called once from the main process before any threads
+/// are created to avoid race conditions
+pub fn set_monitor(file: File) -> Result<(), std::io::Error> {
+    assert!(unsafe { MONITOR.is_none() });
+    let fd = file.as_raw_fd();
+    let ret = unsafe {
+        let mut flags = libc::fcntl(fd, libc::F_GETFL);
+        flags |= libc::O_NONBLOCK;
+        libc::fcntl(fd, libc::F_SETFL, flags)
+    };
+    if ret < 0 {
+        return Err(std::io::Error::last_os_error());
+    }
+    unsafe {
+        MONITOR = Some((file, Instant::now()));
+    };
+    Ok(())
+}
+
+#[derive(Serialize)]
+struct Event<'a> {
+    timestamp: Duration,
+    source: &'a str,
+    event: &'a str,
+    properties: Option<&'a HashMap<Cow<'a, str>, Cow<'a, str>>>,
+}
+
+pub fn event_log(source: &str, event: &str, properties: Option<&HashMap<Cow<str>, Cow<str>>>) {
+    if let Some((file, start)) = unsafe { MONITOR.as_ref() } {
+        let e = Event {
+            timestamp: start.elapsed(),
+            source,
+            event,
+            properties,
+        };
+        serde_json::to_writer_pretty(file, &e).ok();
+    }
+}
+
+/*
+    Through the use of Cow<'a, str> it is possible to use String as well as
+    &str as the parameters:
+    e.g.
+    event!("cpu_manager", "create_vcpu", "id", cpu_id.to_string());
+*/
+#[macro_export]
+macro_rules! event {
+    ($source:expr, $event:expr) => {
+        $crate::event_log($source, $event, None)
+    };
+    ($source:expr, $event:expr, $($key:expr, $value:expr),*) => {
+        {
+            let mut properties = ::std::collections::HashMap::new();
+            $(
+                properties.insert($key.into(), $value.into());
+            )+
+            $crate::event_log($source, $event, Some(&properties))
+        }
+     };
+
+}

fuzz/Cargo.lock

@@ -0,0 +1,847 @@
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+# It is not intended for manual editing.
+version = 3
+
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+
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+ "serde",
+ "thiserror",
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+ "versionize_derive",
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+ "thiserror",
+ "versionize",
+ "versionize_derive",
+ "virtio-bindings",
+ "vm-memory",
+ "vm-virtio",
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+ "vec_map",
+]
+
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+ "seccomp",
+ "serde_json",
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+ "thiserror",
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+ "vmm-sys-util",
+]
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+[[package]]
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+ "libfuzzer-sys",
+ "qcow",
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+ "vm-memory",
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+version = "0.1.0"
+source = "git+https://github.com/firecracker-microvm/firecracker?tag=v0.24.4#8f44986a0e956a77f2b2324c12f73bec16130c82"
+dependencies = [
+ "libc",
+]
+
+[[package]]
+name = "serde"
+version = "1.0.126"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ec7505abeacaec74ae4778d9d9328fe5a5d04253220a85c4ee022239fc996d03"
+
+[[package]]
+name = "serde_derive"
+version = "1.0.126"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "963a7dbc9895aeac7ac90e74f34a5d5261828f79df35cbed41e10189d3804d43"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
+[[package]]
+name = "serde_json"
+version = "1.0.64"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "799e97dc9fdae36a5c8b8f2cae9ce2ee9fdce2058c57a93e6099d919fd982f79"
+dependencies = [
+ "itoa",
+ "ryu",
+ "serde",
+]
+
+[[package]]
+name = "signal-hook"
+version = "0.3.9"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "470c5a6397076fae0094aaf06a08e6ba6f37acb77d3b1b91ea92b4d6c8650c39"
+dependencies = [
+ "libc",
+ "signal-hook-registry",
+]
+
+[[package]]
+name = "signal-hook-registry"
+version = "1.4.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e51e73328dc4ac0c7ccbda3a494dfa03df1de2f46018127f60c693f2648455b0"
+dependencies = [
+ "libc",
+]
+
+[[package]]
+name = "static_assertions"
+version = "1.1.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a2eb9349b6444b326872e140eb1cf5e7c522154d69e7a0ffb0fb81c06b37543f"
+
+[[package]]
+name = "strsim"
+version = "0.8.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "8ea5119cdb4c55b55d432abb513a0429384878c15dde60cc77b1c99de1a95a6a"
+
+[[package]]
+name = "syn"
+version = "1.0.74"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "1873d832550d4588c3dbc20f01361ab00bfe741048f71e3fecf145a7cc18b29c"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "unicode-xid",
+]
+
+[[package]]
+name = "term_size"
+version = "0.3.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "1e4129646ca0ed8f45d09b929036bafad5377103edd06e50bf574b353d2b08d9"
+dependencies = [
+ "libc",
+ "winapi",
+]
+
+[[package]]
+name = "textwrap"
+version = "0.11.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d326610f408c7a4eb6f51c37c330e496b08506c9457c9d34287ecc38809fb060"
+dependencies = [
+ "term_size",
+ "unicode-width",
+]
+
+[[package]]
+name = "thiserror"
+version = "1.0.26"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "93119e4feac1cbe6c798c34d3a53ea0026b0b1de6a120deef895137c0529bfe2"
+dependencies = [
+ "thiserror-impl",
+]
+
+[[package]]
+name = "thiserror-impl"
+version = "1.0.26"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "060d69a0afe7796bf42e9e2ff91f5ee691fb15c53d38b4b62a9a53eb23164745"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
+[[package]]
+name = "unicode-width"
+version = "0.1.8"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9337591893a19b88d8d87f2cec1e73fad5cdfd10e5a6f349f498ad6ea2ffb1e3"
+
+[[package]]
+name = "unicode-xid"
+version = "0.2.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "8ccb82d61f80a663efe1f787a51b16b5a51e3314d6ac365b08639f52387b33f3"
+
+[[package]]
+name = "uuid"
+version = "0.8.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "bc5cf98d8186244414c848017f0e2676b3fcb46807f6668a97dfe67359a3c4b7"
+
+[[package]]
+name = "vec_map"
+version = "0.8.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f1bddf1187be692e79c5ffeab891132dfb0f236ed36a43c7ed39f1165ee20191"
+
+[[package]]
+name = "versionize"
+version = "0.1.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7429cf68de8f091b667d27323ed323afd39584a56d533995b12ddd748e5e6ca9"
+dependencies = [
+ "bincode",
+ "crc64",
+ "proc-macro2",
+ "quote",
+ "serde",
+ "serde_derive",
+ "syn",
+ "versionize_derive",
+ "vmm-sys-util",
+]
+
+[[package]]
+name = "versionize_derive"
+version = "0.1.4"
+source = "git+https://github.com/cloud-hypervisor/versionize_derive?branch=ch#ae35ef7a3ddabd3371ab8ac0193a383aff6e4b1b"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
+[[package]]
+name = "vfio-bindings"
+version = "0.2.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "4a21f546f2bda37f5a8cfb138c87f95b8e34d2d78d6a7a92ba3785f4e08604a7"
+dependencies = [
+ "vmm-sys-util",
+]
+
+[[package]]
+name = "vfio-ioctls"
+version = "0.1.0"
+source = "git+https://github.com/rust-vmm/vfio-ioctls?branch=master#9b84069e9f419c5369b9a313859cac7e9828d331"
+dependencies = [
+ "byteorder",
+ "kvm-bindings",
+ "kvm-ioctls",
+ "log",
+ "vfio-bindings",
+ "vm-memory",
+ "vmm-sys-util",
+]
+
+[[package]]
+name = "vhost"
+version = "0.1.0"
+source = "git+https://github.com/rust-vmm/vhost?branch=master#9982541776a603d30556a06df55e8c0491072763"
+dependencies = [
+ "bitflags",
+ "libc",
+ "vmm-sys-util",
+]
+
+[[package]]
+name = "virtio-bindings"
+version = "0.1.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "3ff512178285488516ed85f15b5d0113a7cdb89e9e8a760b269ae4f02b84bd6b"
+
+[[package]]
+name = "virtio-devices"
+version = "0.1.0"
+dependencies = [
+ "anyhow",
+ "arc-swap",
+ "block_util",
+ "byteorder",
+ "epoll",
+ "event_monitor",
+ "io-uring",
+ "libc",
+ "log",
+ "net_gen",
+ "net_util",
+ "pci",
+ "rate_limiter",
+ "seccomp",
+ "serde",
+ "serde_derive",
+ "serde_json",
+ "versionize",
+ "versionize_derive",
+ "vhost",
+ "virtio-bindings",
+ "vm-allocator",
+ "vm-device",
+ "vm-memory",
+ "vm-migration",
+ "vm-virtio",
+ "vmm-sys-util",
+]
+
+[[package]]
+name = "vm-allocator"
+version = "0.1.0"
+dependencies = [
+ "arch",
+ "libc",
+ "vm-memory",
+]
+
+[[package]]
+name = "vm-device"
+version = "0.1.0"
+dependencies = [
+ "anyhow",
+ "serde",
+ "serde_derive",
+ "serde_json",
+ "thiserror",
+ "vfio-ioctls",
+ "vm-memory",
+ "vmm-sys-util",
+]
+
+[[package]]
+name = "vm-fdt"
+version = "0.1.0"
+source = "git+https://github.com/rust-vmm/vm-fdt?branch=master#13ab882e2f8387753064351c69fbe35c422b448b"
+
+[[package]]
+name = "vm-memory"
+version = "0.5.0"
+source = "git+https://github.com/rust-vmm/vm-memory?rev=5bd7138758183a73ac0da27ce40c004d95f1a7e9#5bd7138758183a73ac0da27ce40c004d95f1a7e9"
+dependencies = [
+ "arc-swap",
+ "libc",
+ "winapi",
+]
+
+[[package]]
+name = "vm-migration"
+version = "0.1.0"
+dependencies = [
+ "anyhow",
+ "serde",
+ "serde_derive",
+ "serde_json",
+ "thiserror",
+ "versionize",
+ "versionize_derive",
+ "vm-memory",
+]
+
+[[package]]
+name = "vm-virtio"
+version = "0.1.0"
+dependencies = [
+ "log",
+ "virtio-bindings",
+ "vm-memory",
+]
+
+[[package]]
+name = "vmm"
+version = "0.1.0"
+dependencies = [
+ "acpi_tables",
+ "anyhow",
+ "arc-swap",
+ "arch",
+ "bitflags",
+ "block_util",
+ "clap",
+ "devices",
+ "epoll",
+ "event_monitor",
+ "hypervisor",
+ "lazy_static",
+ "libc",
+ "linux-loader",
+ "log",
+ "micro_http",
+ "net_util",
+ "option_parser",
+ "pci",
+ "qcow",
+ "seccomp",
+ "serde",
+ "serde_derive",
+ "serde_json",
+ "signal-hook",
+ "thiserror",
+ "uuid",
+ "versionize",
+ "versionize_derive",
+ "vfio-ioctls",
+ "virtio-devices",
+ "vm-allocator",
+ "vm-device",
+ "vm-memory",
+ "vm-migration",
+ "vm-virtio",
+ "vmm-sys-util",
+]
+
+[[package]]
+name = "vmm-sys-util"
+version = "0.8.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "01cf11afbc4ebc0d5c7a7748a77d19e2042677fc15faa2f4ccccb27c18a60605"
+dependencies = [
+ "bitflags",
+ "libc",
+ "serde",
+ "serde_derive",
+]
+
+[[package]]
+name = "winapi"
+version = "0.3.9"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5c839a674fcd7a98952e593242ea400abe93992746761e38641405d28b00f419"
+dependencies = [
+ "winapi-i686-pc-windows-gnu",
+ "winapi-x86_64-pc-windows-gnu",
+]
+
+[[package]]
+name = "winapi-i686-pc-windows-gnu"
+version = "0.4.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ac3b87c63620426dd9b991e5ce0329eff545bccbbb34f3be09ff6fb6ab51b7b6"
+
+[[package]]
+name = "winapi-x86_64-pc-windows-gnu"
+version = "0.4.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "712e227841d057c1ee1cd2fb22fa7e5a5461ae8e48fa2ca79ec42cfc1931183f"

fuzz/Cargo.toml

@@ -10,18 +10,23 @@ cargo-fuzz = true
 
 [dependencies]
 block_util = { path = "../block_util" }
-libc = "0.2.72"
-libfuzzer-sys = "0.3"
+libc = "0.2.98"
+libfuzzer-sys = "0.4.2"
 qcow = { path = "../qcow" }
-seccomp = { git = "https://github.com/firecracker-microvm/firecracker", tag = "v0.22.0" }
+seccomp = { git = "https://github.com/firecracker-microvm/firecracker", tag = "v0.24.4" }
 virtio-devices = { path = "../virtio-devices" }
-vmm-sys-util = ">=0.3.1"
+vmm-sys-util = "0.8.0"
 vm-virtio = { path = "../vm-virtio" }
 vm-memory = "0.5.0"
 
 [dependencies.cloud-hypervisor]
 path = ".."
 
+[patch.crates-io]
+kvm-bindings = { git = "https://github.com/cloud-hypervisor/kvm-bindings", branch = "ch-v0.4.0", features = ["with-serde", "fam-wrappers"] }
+vm-memory = { git = "https://github.com/rust-vmm/vm-memory", rev = "5bd7138758183a73ac0da27ce40c004d95f1a7e9"}
+versionize_derive = { git = "https://github.com/cloud-hypervisor/versionize_derive", branch = "ch" }
+
 # Prevent this from interfering with workspaces
 [workspace]
 members = ["."]

fuzz/fuzz_targets/block.rs

@@ -95,6 +95,7 @@ fuzz_target!(|bytes| {
         2,
         256,
         SeccompAction::Allow,
+        None,
     )
     .unwrap();
 

hypervisor/Cargo.toml

@@ -6,21 +6,20 @@ edition = "2018"
 license = "Apache-2.0 OR BSD-3-Clause"
 
 [features]
-kvm = []
-mshv = []
+kvm = ["kvm-ioctls", "kvm-bindings"]
+mshv = ["mshv-ioctls", "mshv-bindings"]
+tdx = []
 
 [dependencies]
 anyhow = "1.0"
 epoll = ">=4.0.1"
 thiserror = "1.0"
-libc = "0.2.86"
+libc = "0.2.98"
 log = "0.4.14"
-kvm-ioctls = { git = "https://github.com/cloud-hypervisor/kvm-ioctls", branch = "ch" }
-kvm-bindings = { git = "https://github.com/cloud-hypervisor/kvm-bindings", branch = "ch", features = ["with-serde", "fam-wrappers"] }
-
-mshv-bindings = {git = "https://github.com/cloud-hypervisor/mshv", branch = "master", features = ["with-serde", "fam-wrappers"] }
-mshv-ioctls = { git = "https://github.com/cloud-hypervisor/mshv", branch = "master" }
-
+kvm-ioctls = {  version = "0.9.0", optional = true }
+kvm-bindings = { git = "https://github.com/cloud-hypervisor/kvm-bindings", branch = "ch-v0.4.0", features = ["with-serde", "fam-wrappers"], optional  = true }
+mshv-bindings = {git = "https://github.com/cloud-hypervisor/mshv", branch = "master", features = ["with-serde", "fam-wrappers"], optional  = true }
+mshv-ioctls = { git = "https://github.com/cloud-hypervisor/mshv", branch = "master", optional  = true}
 serde = {version = ">=1.0.27", features = ["rc"] }
 serde_derive = ">=1.0.27"
 serde_json = ">=1.0.9"
@@ -28,9 +27,9 @@ vm-memory = { version = "0.5.0", features = ["backend-mmap", "backend-atomic"] }
 vmm-sys-util = { version = ">=0.5.0", features = ["with-serde"] }
 
 [target.'cfg(target_arch = "x86_64")'.dependencies.iced-x86]
-version = "1.10"
+version = "1.13"
 default-features = false
 features = ["std", "decoder", "op_code_info", "instr_info", "fast_fmt"]
 
 [dev-dependencies]
-env_logger = "0.8.3"
+env_logger = "0.9.0"

hypervisor/src/arch/emulator/mod.rs

@@ -4,8 +4,6 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 
-extern crate thiserror;
-
 use core::fmt::Debug;
 use std::fmt::{self, Display};
 use thiserror::Error;
@@ -47,8 +45,8 @@ pub enum PlatformError {
     #[error("Set CPU state failure: {0}")]
     SetCpuStateFailure(#[source] anyhow::Error),
 
-    #[error("Unmapped virtual address: {0}")]
-    UnmappedGVA(#[source] anyhow::Error),
+    #[error("Translate virtual address: {0}")]
+    TranslateVirtualAddress(#[source] anyhow::Error),
 
     #[error("Unsupported CPU Mode: {0}")]
     UnsupportedCpuMode(#[source] anyhow::Error),

hypervisor/src/arch/x86/emulator/instructions/cmp.rs

@@ -4,14 +4,12 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 
-#![allow(non_camel_case_types)]
+#![allow(non_camel_case_types, clippy::upper_case_acronyms)]
 
 //
 // CMP-Compare Two Operands
 //
 
-extern crate iced_x86;
-
 use crate::arch::emulator::{EmulationError, PlatformEmulator};
 use crate::arch::x86::emulator::instructions::*;
 use crate::arch::x86::regs::*;
@@ -229,7 +227,7 @@ mod tests {
         let ip: u64 = 0x1000;
         let cpu_id = 0;
         let insn = [0x38, 0xc4]; // cmp ah,al
-        let mut vmm = MockVMM::new(ip, vec![(Register::RAX, rax)], None);
+        let mut vmm = MockVmm::new(ip, vec![(Register::RAX, rax)], None);
         assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
 
         let rflags: u64 = vmm.cpu_state(cpu_id).unwrap().flags() & FLAGS_MASK;
@@ -243,7 +241,7 @@ mod tests {
         let ip: u64 = 0x1000;
         let cpu_id = 0;
         let insn = [0x83, 0xf8, 0x64]; // cmp eax,100
-        let mut vmm = MockVMM::new(ip, vec![(Register::RAX, rax)], None);
+        let mut vmm = MockVmm::new(ip, vec![(Register::RAX, rax)], None);
         assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
 
         let rflags: u64 = vmm.cpu_state(cpu_id).unwrap().flags() & FLAGS_MASK;
@@ -257,7 +255,7 @@ mod tests {
         let ip: u64 = 0x1000;
         let cpu_id = 0;
         let insn = [0x83, 0xf8, 0xff]; // cmp eax,-1
-        let mut vmm = MockVMM::new(ip, vec![(Register::RAX, rax)], None);
+        let mut vmm = MockVmm::new(ip, vec![(Register::RAX, rax)], None);
         assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
 
         let rflags: u64 = vmm.cpu_state(cpu_id).unwrap().flags() & FLAGS_MASK;
@@ -272,7 +270,7 @@ mod tests {
         let ip: u64 = 0x1000;
         let cpu_id = 0;
         let insn = [0x48, 0x39, 0xd8, 0x00, 0xc3]; // cmp rax,rbx + two bytes garbage
-        let mut vmm = MockVMM::new(ip, vec![(Register::RAX, rax), (Register::RBX, rbx)], None);
+        let mut vmm = MockVmm::new(ip, vec![(Register::RAX, rax), (Register::RBX, rbx)], None);
         assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
 
         let rflags: u64 = vmm.cpu_state(cpu_id).unwrap().flags() & FLAGS_MASK;
@@ -295,7 +293,7 @@ mod tests {
             let rax = d.0;
             let rbx = d.1;
             let insn = [0x48, 0x39, 0xd8]; // cmp rax,rbx
-            let mut vmm = MockVMM::new(
+            let mut vmm = MockVmm::new(
                 0x1000,
                 vec![(Register::RAX, rax), (Register::RBX, rbx)],
                 None,
@@ -323,7 +321,7 @@ mod tests {
             let rax = d.0;
             let rbx = d.1;
             let insn = [0x39, 0xd8]; // cmp eax,ebx
-            let mut vmm = MockVMM::new(
+            let mut vmm = MockVmm::new(
                 0x1000,
                 vec![(Register::RAX, rax), (Register::RBX, rbx)],
                 None,

hypervisor/src/arch/x86/emulator/instructions/mod.rs

@@ -4,8 +4,6 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 
-extern crate iced_x86;
-
 use crate::arch::emulator::{EmulationError, PlatformEmulator, PlatformError};
 use crate::arch::x86::emulator::CpuStateManager;
 use crate::arch::x86::Exception;
@@ -13,6 +11,8 @@ use iced_x86::*;
 
 pub mod cmp;
 pub mod mov;
+pub mod movs;
+pub mod or;
 
 fn get_op<T: CpuStateManager>(
     insn: &Instruction,
@@ -130,7 +130,7 @@ fn memory_operand_address<T: CpuStateManager>(
         address += index;
     }
 
-    address += insn.memory_displacement() as u64;
+    address += insn.memory_displacement64();
 
     // Translate to a linear address.
     state.linearize(insn.memory_segment(), address, write)

hypervisor/src/arch/x86/emulator/instructions/mov.rs

@@ -12,8 +12,6 @@
 //   Copies the second operand (source operand) to the first operand (destination operand).
 //
 
-extern crate iced_x86;
-
 use crate::arch::emulator::{EmulationError, PlatformEmulator};
 use crate::arch::x86::emulator::instructions::*;
 use crate::arch::x86::Exception;
@@ -71,7 +69,7 @@ macro_rules! mov_rm_imm {
 }
 
 macro_rules! movzx {
-    ($src_op_size:ty, $dest_op_size:ty) => {
+    ($dest_op_size:ty, $src_op_size:ty) => {
         fn emulate(
             &self,
             insn: &Instruction,
@@ -254,7 +252,7 @@ mod tests {
         let ip: u64 = 0x1000;
         let cpu_id = 0;
         let insn = [0x48, 0x89, 0xd8];
-        let mut vmm = MockVMM::new(ip, vec![(Register::RBX, rbx)], None);
+        let mut vmm = MockVmm::new(ip, vec![(Register::RBX, rbx)], None);
         assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
 
         let rax: u64 = vmm
@@ -272,7 +270,7 @@ mod tests {
         let ip: u64 = 0x1000;
         let cpu_id = 0;
         let insn = [0x48, 0xb8, 0x44, 0x33, 0x22, 0x11, 0x44, 0x33, 0x22, 0x11];
-        let mut vmm = MockVMM::new(ip, vec![], None);
+        let mut vmm = MockVmm::new(ip, vec![], None);
         assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
 
         let rax: u64 = vmm
@@ -292,7 +290,7 @@ mod tests {
         let cpu_id = 0;
         let memory: [u8; 8] = target_rax.to_le_bytes();
         let insn = [0x48, 0x8b, 0x04, 0x00];
-        let mut vmm = MockVMM::new(ip, vec![(Register::RAX, rax)], Some((rax + rax, &memory)));
+        let mut vmm = MockVmm::new(ip, vec![(Register::RAX, rax)], Some((rax + rax, &memory)));
         assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
 
         rax = vmm
@@ -310,7 +308,7 @@ mod tests {
         let ip: u64 = 0x1000;
         let cpu_id = 0;
         let insn = [0xb0, 0x11];
-        let mut vmm = MockVMM::new(ip, vec![], None);
+        let mut vmm = MockVmm::new(ip, vec![], None);
         assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
 
         let al = vmm
@@ -328,7 +326,7 @@ mod tests {
         let ip: u64 = 0x1000;
         let cpu_id = 0;
         let insn = [0xb8, 0x11, 0x00, 0x00, 0x00];
-        let mut vmm = MockVMM::new(ip, vec![], None);
+        let mut vmm = MockVmm::new(ip, vec![], None);
         assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
 
         let eax = vmm
@@ -346,7 +344,7 @@ mod tests {
         let ip: u64 = 0x1000;
         let cpu_id = 0;
         let insn = [0x48, 0xc7, 0xc0, 0x44, 0x33, 0x22, 0x11];
-        let mut vmm = MockVMM::new(ip, vec![], None);
+        let mut vmm = MockVmm::new(ip, vec![], None);
         assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
 
         let rax: u64 = vmm
@@ -365,7 +363,7 @@ mod tests {
         let ip: u64 = 0x1000;
         let cpu_id = 0;
         let insn = [0x88, 0x30];
-        let mut vmm = MockVMM::new(
+        let mut vmm = MockVmm::new(
             ip,
             vec![(Register::RAX, rax), (Register::DH, dh.into())],
             None,
@@ -386,7 +384,7 @@ mod tests {
         let ip: u64 = 0x1000;
         let cpu_id = 0;
         let insn = [0x89, 0x30];
-        let mut vmm = MockVMM::new(
+        let mut vmm = MockVmm::new(
             ip,
             vec![(Register::RAX, rax), (Register::ESI, esi.into())],
             None,
@@ -408,7 +406,7 @@ mod tests {
         let ip: u64 = 0x1000;
         let cpu_id = 0;
         let insn = [0x89, 0x3c, 0x05, 0x01, 0x00, 0x00, 0x00];
-        let mut vmm = MockVMM::new(
+        let mut vmm = MockVmm::new(
             ip,
             vec![(Register::RAX, rax), (Register::EDI, edi.into())],
             None,
@@ -431,7 +429,7 @@ mod tests {
         let ip: u64 = 0x1000;
         let cpu_id = 0;
         let insn = [0x8b, 0x40, 0x10];
-        let mut vmm = MockVMM::new(
+        let mut vmm = MockVmm::new(
             ip,
             vec![(Register::RAX, rax)],
             Some((rax + displacement, &memory)),
@@ -456,7 +454,7 @@ mod tests {
         let cpu_id = 0;
         let insn = [0x8a, 0x40, 0x10];
         let memory: [u8; 1] = al.to_le_bytes();
-        let mut vmm = MockVMM::new(
+        let mut vmm = MockVmm::new(
             ip,
             vec![(Register::RAX, rax)],
             Some((rax + displacement, &memory)),
@@ -485,7 +483,7 @@ mod tests {
             0x48, 0xc7, 0xc0, 0x00, 0x01, 0x00, 0x00, // mov rax, 0x100
             0x48, 0x8b, 0x58, 0x10, // mov rbx, qword ptr [rax+10h]
         ];
-        let mut vmm = MockVMM::new(ip, vec![], Some((rax + displacement, &memory)));
+        let mut vmm = MockVmm::new(ip, vec![], Some((rax + displacement, &memory)));
         assert!(vmm.emulate_insn(cpu_id, &insn, Some(2)).is_ok());
 
         let rbx: u64 = vmm
@@ -511,7 +509,7 @@ mod tests {
             0x48, 0x8b, 0x58, 0x10, // mov rbx, qword ptr [rax+10h]
         ];
 
-        let mut vmm = MockVMM::new(ip, vec![], Some((rax + displacement, &memory)));
+        let mut vmm = MockVmm::new(ip, vec![], Some((rax + displacement, &memory)));
         // Only run the first instruction.
         assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
 
@@ -542,7 +540,7 @@ mod tests {
             0x48, 0xc7, 0xc0, 0x00, 0x02, 0x00, 0x00, // mov rax, 0x200
         ];
 
-        let mut vmm = MockVMM::new(ip, vec![], Some((rax + displacement, &memory)));
+        let mut vmm = MockVmm::new(ip, vec![], Some((rax + displacement, &memory)));
         // Run the 2 first instructions.
         assert!(vmm.emulate_insn(cpu_id, &insn, Some(2)).is_ok());
 
@@ -571,7 +569,7 @@ mod tests {
         let ip: u64 = 0x1000;
         let cpu_id = 0;
         let insn = [0x0f, 0xb6, 0xc3];
-        let mut vmm = MockVMM::new(ip, vec![(Register::BX, bx as u64)], None);
+        let mut vmm = MockVmm::new(ip, vec![(Register::BX, bx as u64)], None);
         assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
 
         let eax: u64 = vmm
@@ -589,7 +587,7 @@ mod tests {
         let ip: u64 = 0x1000;
         let cpu_id = 0;
         let insn = [0x0f, 0xb6, 0xc7];
-        let mut vmm = MockVMM::new(ip, vec![(Register::BX, bx as u64)], None);
+        let mut vmm = MockVmm::new(ip, vec![(Register::BX, bx as u64)], None);
         assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
 
         let eax: u64 = vmm
@@ -609,7 +607,7 @@ mod tests {
         let cpu_id = 0;
         let insn = [0x0f, 0xb7, 0x03];
         let memory: [u8; 1] = value.to_le_bytes();
-        let mut vmm = MockVMM::new(ip, vec![(Register::RBX, rbx)], Some((rbx, &memory)));
+        let mut vmm = MockVmm::new(ip, vec![(Register::RBX, rbx)], Some((rbx, &memory)));
         assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
 
         let eax: u64 = vmm

hypervisor/src/arch/x86/emulator/instructions/movs.rs

@@ -0,0 +1,145 @@
+//
+// Copyright © 2021 Microsoft
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#![allow(non_camel_case_types)]
+
+//
+// MOVS - Move Data from String to String
+//
+
+use crate::arch::emulator::{EmulationError, PlatformEmulator};
+use crate::arch::x86::emulator::instructions::*;
+use crate::arch::x86::regs::DF;
+use crate::arch::x86::Exception;
+
+pub struct Movsd_m32_m32;
+impl<T: CpuStateManager> InstructionHandler<T> for Movsd_m32_m32 {
+    fn emulate(
+        &self,
+        insn: &Instruction,
+        state: &mut T,
+        platform: &mut dyn PlatformEmulator<CpuState = T>,
+    ) -> Result<(), EmulationError<Exception>> {
+        let mut count: u64 = if insn.has_rep_prefix() {
+            state
+                .read_reg(Register::ECX)
+                .map_err(|e| EmulationError::InvalidOperand(anyhow!(e)))?
+        } else {
+            1
+        };
+
+        let mut rsi = state
+            .read_reg(Register::RSI)
+            .map_err(|e| EmulationError::InvalidOperand(anyhow!(e)))?;
+        let mut rdi = state
+            .read_reg(Register::RDI)
+            .map_err(|e| EmulationError::InvalidOperand(anyhow!(e)))?;
+
+        let df = (state.flags() & DF) != 0;
+        let len = std::mem::size_of::<u32>();
+
+        while count > 0 {
+            let mut memory: [u8; 4] = [0; 4];
+
+            let src = state
+                .linearize(Register::DS, rsi, false)
+                .map_err(|e| EmulationError::InvalidOperand(anyhow!(e)))?;
+            let dst = state
+                .linearize(Register::ES, rdi, true)
+                .map_err(|e| EmulationError::InvalidOperand(anyhow!(e)))?;
+
+            platform
+                .read_memory(src, &mut memory[0..len])
+                .map_err(EmulationError::PlatformEmulationError)?;
+            platform
+                .write_memory(dst, &memory[0..len])
+                .map_err(EmulationError::PlatformEmulationError)?;
+
+            if df {
+                rsi = rsi.wrapping_sub(len as u64);
+                rdi = rdi.wrapping_sub(len as u64);
+            } else {
+                rsi = rsi.wrapping_add(len as u64);
+                rdi = rdi.wrapping_add(len as u64);
+            }
+            count -= 1;
+        }
+
+        state
+            .write_reg(Register::RSI, rsi)
+            .map_err(|e| EmulationError::InvalidOperand(anyhow!(e)))?;
+        state
+            .write_reg(Register::RDI, rdi)
+            .map_err(|e| EmulationError::InvalidOperand(anyhow!(e)))?;
+        if insn.has_rep_prefix() {
+            state
+                .write_reg(Register::ECX, 0)
+                .map_err(|e| EmulationError::InvalidOperand(anyhow!(e)))?;
+        }
+
+        Ok(())
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    #![allow(unused_mut)]
+    use super::*;
+    use crate::arch::x86::emulator::mock_vmm::*;
+
+    #[test]
+    fn test_rep_movsd_m32_m32() {
+        let ip: u64 = 0x1000;
+        let memory: [u8; 24] = [
+            0x78, 0x56, 0x34, 0x12, // 0x12345678
+            0xdd, 0xcc, 0xbb, 0xaa, // 0xaabbccdd
+            0xa5, 0x5a, 0xa5, 0x5a, // 0x5aa55aa5
+            0x00, 0x00, 0x00, 0x00, // 0x00000000
+            0x00, 0x00, 0x00, 0x00, // 0x00000000
+            0x00, 0x00, 0x00, 0x00, // 0x00000000
+        ];
+        let insn = [0xf3, 0xa5]; // rep movsd
+        let regs = vec![(Register::ECX, 3), (Register::ESI, 0), (Register::EDI, 0xc)];
+        let mut data = [0u8; 4];
+
+        let mut vmm = MockVmm::new(ip, regs, Some((0, &memory)));
+
+        assert!(vmm.emulate_first_insn(0, &insn).is_ok());
+
+        vmm.read_memory(0xc, &mut data).unwrap();
+        assert_eq!(0x12345678, <u32>::from_le_bytes(data));
+        vmm.read_memory(0xc + 4, &mut data).unwrap();
+        assert_eq!(0xaabbccdd, <u32>::from_le_bytes(data));
+        vmm.read_memory(0xc + 8, &mut data).unwrap();
+        assert_eq!(0x5aa55aa5, <u32>::from_le_bytes(data));
+        // The rest should be default value 0 from MockVmm
+        vmm.read_memory(0xc + 12, &mut data).unwrap();
+        assert_eq!(0x0, <u32>::from_le_bytes(data));
+    }
+
+    #[test]
+    fn test_movsd_m32_m32() {
+        let ip: u64 = 0x1000;
+        let memory: [u8; 4] = [
+            0x78, 0x56, 0x34, 0x12, // 0x12345678
+        ];
+        let insn = [0xa5]; // movsd
+        let regs = vec![(Register::ESI, 0), (Register::EDI, 0x8)];
+        let mut data = [0u8; 4];
+
+        let mut vmm = MockVmm::new(ip, regs, Some((0, &memory)));
+
+        assert!(vmm.emulate_first_insn(0, &insn).is_ok());
+
+        vmm.read_memory(0x8, &mut data).unwrap();
+        assert_eq!(0x12345678, <u32>::from_le_bytes(data));
+        // The rest should be default value 0 from MockVmm
+        vmm.read_memory(0x4, &mut data).unwrap();
+        assert_eq!(0x0, <u32>::from_le_bytes(data));
+        vmm.read_memory(0x8 + 8, &mut data).unwrap();
+        assert_eq!(0x0, <u32>::from_le_bytes(data));
+    }
+}

hypervisor/src/arch/x86/emulator/instructions/or.rs

@@ -0,0 +1,83 @@
+//
+// Copyright © 2021 Microsoft
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#![allow(non_camel_case_types)]
+
+//
+// OR - Logical inclusive OR
+//
+
+use crate::arch::emulator::{EmulationError, PlatformEmulator};
+use crate::arch::x86::emulator::instructions::*;
+use crate::arch::x86::Exception;
+
+macro_rules! or_rm_r {
+    ($bound:ty) => {
+        fn emulate(
+            &self,
+            insn: &Instruction,
+            state: &mut T,
+            platform: &mut dyn PlatformEmulator<CpuState = T>,
+        ) -> Result<(), EmulationError<Exception>> {
+            let src_reg_value = get_op(&insn, 1, std::mem::size_of::<$bound>(), state, platform)
+                .map_err(EmulationError::PlatformEmulationError)?;
+
+            let dst_value = get_op(&insn, 0, std::mem::size_of::<$bound>(), state, platform)
+                .map_err(EmulationError::PlatformEmulationError)?;
+
+            let result = src_reg_value | dst_value;
+
+            set_op(
+                &insn,
+                0,
+                std::mem::size_of::<$bound>(),
+                state,
+                platform,
+                result,
+            )
+            .map_err(EmulationError::PlatformEmulationError)?;
+
+            Ok(())
+        }
+    };
+}
+
+pub struct Or_rm8_r8;
+impl<T: CpuStateManager> InstructionHandler<T> for Or_rm8_r8 {
+    or_rm_r!(u8);
+}
+
+#[cfg(test)]
+mod tests {
+    #![allow(unused_mut)]
+    use super::*;
+
+    use crate::arch::x86::emulator::mock_vmm::*;
+
+    #[test]
+    // or byte ptr [rax+1h], sil
+    fn test_or_rm8_r8() {
+        let rax = 0;
+        let insn = [0x40, 0x08, 0x70, 0x1];
+        let cpu_id = 0;
+        let ip: u64 = 0x1000;
+        let sil = 0xaa;
+        let memory = [0x0, 0x55];
+
+        let mut vmm = MockVmm::new(
+            ip,
+            vec![(Register::SIL, sil), (Register::RAX, rax)],
+            Some((0, &memory)),
+        );
+
+        assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
+
+        let mut out: [u8; 1] = [0; 1];
+
+        vmm.read_memory(rax + 1, &mut out).unwrap();
+        assert_eq!(u8::from_le_bytes(out), 0xff);
+    }
+}

hypervisor/src/arch/x86/emulator/mod.rs

@@ -4,8 +4,6 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 
-extern crate iced_x86;
-
 use crate::arch::emulator::{EmulationError, EmulationResult, PlatformEmulator, PlatformError};
 use crate::arch::x86::emulator::instructions::*;
 use crate::arch::x86::regs::*;
@@ -524,7 +522,11 @@ impl<'a, T: CpuStateManager> Emulator<'a, T> {
             (mov, Movzx_r32_rm8),
             (mov, Movzx_r64_rm8),
             (mov, Movzx_r32_rm16),
-            (mov, Movzx_r64_rm16)
+            (mov, Movzx_r64_rm16),
+            // MOVS
+            (movs, Movsd_m32_m32),
+            // OR
+            (or, Or_rm8_r8)
         );
 
         handler
@@ -638,8 +640,6 @@ impl<'a, T: CpuStateManager> Emulator<'a, T> {
 mod mock_vmm {
     #![allow(unused_mut)]
 
-    extern crate env_logger;
-
     use super::*;
     use crate::arch::emulator::{EmulationError, PlatformEmulator};
     use crate::arch::x86::emulator::{Emulator, EmulatorCpuState as CpuState};
@@ -648,17 +648,17 @@ mod mock_vmm {
     use std::sync::{Arc, Mutex};
 
     #[derive(Debug, Clone)]
-    pub struct MockVMM {
+    pub struct MockVmm {
         memory: Vec<u8>,
         state: Arc<Mutex<CpuState>>,
     }
 
-    unsafe impl Sync for MockVMM {}
+    unsafe impl Sync for MockVmm {}
 
     pub type MockResult = Result<(), EmulationError<Exception>>;
 
-    impl MockVMM {
-        pub fn new(ip: u64, regs: Vec<(Register, u64)>, memory: Option<(u64, &[u8])>) -> MockVMM {
+    impl MockVmm {
+        pub fn new(ip: u64, regs: Vec<(Register, u64)>, memory: Option<(u64, &[u8])>) -> MockVmm {
             let _ = env_logger::try_init();
             let cs_reg = segment_from_gdt(gdt_entry(0xc09b, 0, 0xffffffff), 1);
             let ds_reg = segment_from_gdt(gdt_entry(0xc093, 0, 0xffffffff), 2);
@@ -672,13 +672,13 @@ mod mock_vmm {
                 initial_state.write_reg(reg, value).unwrap();
             }
 
-            let mut vmm = MockVMM {
+            let mut vmm = MockVmm {
                 memory: vec![0; 8192],
                 state: Arc::new(Mutex::new(initial_state)),
             };
 
             if let Some(mem) = memory {
-                vmm.write_memory(mem.0, &mem.1).unwrap();
+                vmm.write_memory(mem.0, mem.1).unwrap();
             }
 
             vmm
@@ -693,7 +693,7 @@ mod mock_vmm {
             let ip = self.cpu_state(cpu_id).unwrap().ip();
             let mut emulator = Emulator::new(self);
 
-            let new_state = emulator.emulate_insn_stream(cpu_id, &insn, num_insn)?;
+            let new_state = emulator.emulate_insn_stream(cpu_id, insn, num_insn)?;
             if num_insn.is_none() {
                 assert_eq!(ip + insn.len() as u64, new_state.ip());
             }
@@ -708,7 +708,7 @@ mod mock_vmm {
         }
     }
 
-    impl PlatformEmulator for MockVMM {
+    impl PlatformEmulator for MockVmm {
         type CpuState = CpuState;
 
         fn read_memory(&self, gva: u64, data: &mut [u8]) -> Result<(), PlatformError> {
@@ -716,7 +716,7 @@ mod mock_vmm {
                 "Memory read {} bytes from [{:#x} -> {:#x}]",
                 data.len(),
                 gva,
-                gva
+                gva + data.len() as u64 - 1
             );
             data.copy_from_slice(&self.memory[gva as usize..gva as usize + data.len()]);
             Ok(())
@@ -727,7 +727,7 @@ mod mock_vmm {
                 "Memory write {} bytes at [{:#x} -> {:#x}]",
                 data.len(),
                 gva,
-                gva
+                gva + data.len() as u64 - 1
             );
             self.memory[gva as usize..gva as usize + data.len()].copy_from_slice(data);
 
@@ -790,7 +790,7 @@ mod tests {
             0x48, 0xc7, 0xc0, 0x00, // mov rax, 0x1000 -- Missing bytes: 0x00, 0x10, 0x00, 0x00,
         ];
 
-        let mut vmm = MockVMM::new(ip, vec![], Some((ip, &memory)));
+        let mut vmm = MockVmm::new(ip, vec![], Some((ip, &memory)));
         assert!(vmm.emulate_insn(cpu_id, &insn, Some(2)).is_ok());
 
         let rax: u64 = vmm
@@ -825,7 +825,7 @@ mod tests {
             0x48, 0x8b, // Truncated mov rbx, qword ptr [rax+10h] -- missing [0x58, 0x10]
         ];
 
-        let mut vmm = MockVMM::new(ip, vec![], Some((ip, &memory)));
+        let mut vmm = MockVmm::new(ip, vec![], Some((ip, &memory)));
         assert!(vmm.emulate_insn(cpu_id, &insn, Some(2)).is_ok());
 
         let rbx: u64 = vmm
@@ -855,7 +855,7 @@ mod tests {
             0x48, 0xc7, 0xc0, 0x00, // mov rax, 0x1000 -- Missing bytes: 0x00, 0x10, 0x00, 0x00,
         ];
 
-        let mut vmm = MockVMM::new(ip, vec![], Some((ip, &memory)));
+        let mut vmm = MockVmm::new(ip, vec![], Some((ip, &memory)));
         assert!(vmm.emulate_first_insn(cpu_id, &insn).is_err());
     }
 }

hypervisor/src/arch/x86/mod.rs

@@ -11,27 +11,14 @@
 // Copyright © 2020, Microsoft Corporation
 //
 
+pub mod emulator;
 pub mod gdt;
-
 #[allow(non_upper_case_globals)]
 #[allow(non_camel_case_types)]
 #[allow(non_snake_case)]
 #[allow(non_upper_case_globals)]
-#[allow(unused)]
-#[allow(
-    clippy::unreadable_literal,
-    clippy::redundant_static_lifetimes,
-    clippy::trivially_copy_pass_by_ref,
-    clippy::useless_transmute,
-    clippy::should_implement_trait,
-    clippy::transmute_ptr_to_ptr,
-    clippy::unreadable_literal,
-    clippy::redundant_static_lifetimes
-)]
 pub mod msr_index;
 
-pub mod emulator;
-
 // MTRR constants
 pub const MTRR_ENABLE: u64 = 0x800; // IA32_MTRR_DEF_TYPE MSR: E (MTRRs enabled) flag, bit 11
 pub const MTRR_MEM_TYPE_WB: u64 = 0x6;
@@ -40,7 +27,7 @@ pub const MTRR_MEM_TYPE_WB: u64 = 0x6;
 pub const NUM_IOAPIC_PINS: usize = 24;
 
 // X86 Exceptions
-#[allow(dead_code)]
+#[allow(dead_code, clippy::upper_case_acronyms)]
 #[derive(Clone, Debug)]
 pub enum Exception {
     DE = 0,  // Divide Error

hypervisor/src/arch/x86/regs.rs

@@ -22,6 +22,7 @@ pub const PF_SHIFT: usize = 2;
 pub const AF_SHIFT: usize = 4;
 pub const ZF_SHIFT: usize = 6;
 pub const SF_SHIFT: usize = 7;
+pub const DF_SHIFT: usize = 10;
 pub const OF_SHIFT: usize = 11;
 
 pub const CF: u64 = 1 << CF_SHIFT;
@@ -29,4 +30,5 @@ pub const PF: u64 = 1 << PF_SHIFT;
 pub const AF: u64 = 1 << AF_SHIFT;
 pub const ZF: u64 = 1 << ZF_SHIFT;
 pub const SF: u64 = 1 << SF_SHIFT;
+pub const DF: u64 = 1 << DF_SHIFT;
 pub const OF: u64 = 1 << OF_SHIFT;

hypervisor/src/cpu.rs

@@ -21,8 +21,12 @@ use crate::x86_64::{
 use crate::CpuState;
 #[cfg(feature = "kvm")]
 use crate::MpState;
+#[cfg(all(feature = "mshv", target_arch = "x86_64"))]
+use crate::SuspendRegisters;
 #[cfg(target_arch = "x86_64")]
 use crate::Xsave;
+#[cfg(feature = "mshv")]
+use mshv_bindings::*;
 use thiserror::Error;
 
 #[derive(Error, Debug)]
@@ -40,6 +44,11 @@ pub enum HypervisorCpuError {
     #[error("Failed to get standard registers: {0}")]
     GetStandardRegs(#[source] anyhow::Error),
     ///
+    /// Getting suspend registers error
+    ///
+    #[error("Failed to get suspend registers: {0}")]
+    GetSuspendRegs(#[source] anyhow::Error),
+    ///
     /// Setting special register error
     ///
     #[error("Failed to set special registers: {0}")]
@@ -172,7 +181,7 @@ pub enum HypervisorCpuError {
     /// Enabling HyperV SynIC error
     ///
     #[error("Failed to enable HyperV SynIC")]
-    EnableHyperVSynIC(#[source] anyhow::Error),
+    EnableHyperVSyncIc(#[source] anyhow::Error),
     ///
     /// Getting AArch64 core register error
     ///
@@ -198,6 +207,17 @@ pub enum HypervisorCpuError {
     ///
     #[error("Failed to set system register: {0}")]
     SetSysRegister(#[source] anyhow::Error),
+    ///
+    /// GVA translation error
+    ///
+    #[error("Failed to translate GVA: {0}")]
+    TranslateVirtualAddress(#[source] anyhow::Error),
+    ///
+    /// Failed to initialize TDX on CPU
+    ///
+    #[cfg(feature = "tdx")]
+    #[error("Failed to initialize TDX: {0}")]
+    InitializeTdx(#[source] std::io::Error),
 }
 
 #[derive(Debug)]
@@ -398,4 +418,19 @@ pub trait Vcpu: Send + Sync {
     /// Triggers the running of the current virtual CPU returning an exit reason.
     ///
     fn run(&self) -> std::result::Result<VmExit, HypervisorCpuError>;
+    #[cfg(all(feature = "mshv", target_arch = "x86_64"))]
+    ///
+    /// Translate guest virtual address to guest physical address
+    ///
+    fn translate_gva(&self, gva: u64, flags: u64) -> Result<(u64, hv_translate_gva_result)>;
+    ///
+    /// Initialize TDX support on the vCPU
+    ///
+    #[cfg(feature = "tdx")]
+    fn tdx_init(&self, hob_address: u64) -> Result<()>;
+    #[cfg(all(feature = "mshv", target_arch = "x86_64"))]
+    ///
+    /// Return suspend registers(explicit and intercept suspend registers)
+    ///
+    fn get_suspend_regs(&self) -> Result<SuspendRegisters>;
 }

hypervisor/src/hypervisor.rs

@@ -12,10 +12,7 @@ use crate::vm::Vm;
 use crate::x86_64::CpuId;
 #[cfg(target_arch = "x86_64")]
 use crate::x86_64::MsrList;
-#[cfg(all(feature = "kvm", target_arch = "x86_64"))]
-use kvm_ioctls::Cap;
 use std::sync::Arc;
-
 use thiserror::Error;
 
 #[derive(Error, Debug)]
@@ -43,16 +40,6 @@ pub enum HypervisorError {
     #[error("Failed to get API Version: {0}")]
     GetApiVersion(#[source] anyhow::Error),
     ///
-    /// Vcpu mmap error
-    ///
-    #[error("Failed to get Vcpu Mmap: {0}")]
-    GetVcpuMmap(#[source] anyhow::Error),
-    ///
-    /// Max Vcpu error
-    ///
-    #[error("Failed to get number of max vcpus: {0}")]
-    GetMaxVcpu(#[source] anyhow::Error),
-    ///
     /// CpuId error
     ///
     #[error("Failed to get cpuid: {0}")]
@@ -67,6 +54,11 @@ pub enum HypervisorError {
     ///
     #[error("Incompatible API version")]
     IncompatibleApiVersion,
+    ///
+    /// Checking extensions failed
+    ///
+    #[error("Checking extensions:{0}")]
+    CheckExtensions(#[source] anyhow::Error),
 }
 
 ///
@@ -85,39 +77,32 @@ pub trait Hypervisor: Send + Sync {
     /// Return a hypervisor-agnostic Vm trait object
     ///
     fn create_vm(&self) -> Result<Arc<dyn Vm>>;
-    #[cfg(feature = "kvm")]
     ///
-    /// Returns the size of the memory mapping required to use the vcpu's structures
+    /// Create a Vm of a specific type using the underlying hypervisor
+    /// Return a hypervisor-agnostic Vm trait object
     ///
-    fn get_vcpu_mmap_size(&self) -> Result<usize>;
-    #[cfg(feature = "kvm")]
-    ///
-    /// Gets the recommended maximum number of VCPUs per VM.
-    ///
-    fn get_max_vcpus(&self) -> Result<usize>;
-    #[cfg(feature = "kvm")]
-    ///
-    /// Gets the recommended number of VCPUs per VM.
-    ///
-    fn get_nr_vcpus(&self) -> Result<usize>;
-    #[cfg(all(feature = "kvm", target_arch = "x86_64"))]
-    ///
-    /// Checks if a particular `Cap` is available.
-    ///
-    fn check_capability(&self, c: Cap) -> bool;
+    fn create_vm_with_type(&self, _vm_type: u64) -> Result<Arc<dyn Vm>> {
+        unreachable!()
+    }
     #[cfg(target_arch = "x86_64")]
     ///
     /// Get the supported CpuID
     ///
     fn get_cpuid(&self) -> Result<CpuId>;
-    #[cfg(not(feature = "mshv"))]
     ///
     /// Check particular extensions if any
     ///
-    fn check_required_extensions(&self) -> Result<()>;
+    fn check_required_extensions(&self) -> Result<()> {
+        Ok(())
+    }
     #[cfg(target_arch = "x86_64")]
     ///
     /// Retrieve the list of MSRs supported by the hypervisor.
     ///
     fn get_msr_list(&self) -> Result<MsrList>;
+    #[cfg(target_arch = "aarch64")]
+    ///
+    /// Retrieve AArch64 host maximum IPA size supported by KVM.
+    ///
+    fn get_host_ipa_limit(&self) -> i32;
 }

hypervisor/src/kvm/aarch64/mod.rs

@@ -32,19 +32,17 @@ pub use {kvm_ioctls::Cap, kvm_ioctls::Kvm};
 
 // This macro gets the offset of a structure (i.e `str`) member (i.e `field`) without having
 // an instance of that structure.
-// It uses a null pointer to retrieve the offset to the field.
-// Inspired by C solution: `#define offsetof(str, f) ((size_t)(&((str *)0)->f))`.
-// Doing `offset__of!(user_pt_regs, pstate)` in our rust code will trigger the following:
-// unsafe { &(*(0 as *const user_pt_regs)).pstate as *const _ as usize }
-// The dereference expression produces an lvalue, but that lvalue is not actually read from,
-// we're just doing pointer math on it, so in theory, it should safe.
 #[macro_export]
 macro_rules! offset__of {
-    ($str:ty, $field:ident) => {
-        unsafe { &(*std::ptr::null::<$str>()).$field as *const _ as usize }
-    };
-}
+    ($str:ty, $($field:ident)+) => ({
+        let tmp: std::mem::MaybeUninit<$str> = std::mem::MaybeUninit::uninit();
+        let tmp = unsafe { tmp.assume_init() };
+        let base = &tmp as *const _ as usize;
+        let member =  &tmp.$($field)* as *const _ as usize;
 
+        member - base
+    });
+}
 // Get the ID of a core register
 #[macro_export]
 macro_rules! arm64_core_reg_id {

hypervisor/src/kvm/mod.rs

@@ -16,11 +16,16 @@ pub use crate::aarch64::{
 use crate::cpu;
 use crate::device;
 use crate::hypervisor;
+use crate::vec_with_array_field;
 use crate::vm::{self, VmmOps};
 #[cfg(target_arch = "aarch64")]
 use crate::{arm64_core_reg_id, offset__of};
 use kvm_ioctls::{NoDatamatch, VcpuFd, VmFd};
 use serde_derive::{Deserialize, Serialize};
+#[cfg(target_arch = "aarch64")]
+use std::convert::TryInto;
+#[cfg(target_arch = "x86_64")]
+use std::fs::File;
 use std::os::unix::io::{AsRawFd, RawFd};
 use std::result;
 #[cfg(target_arch = "x86_64")]
@@ -32,49 +37,46 @@ use vmm_sys_util::eventfd::EventFd;
 // x86_64 dependencies
 #[cfg(target_arch = "x86_64")]
 pub mod x86_64;
-
+#[cfg(target_arch = "x86_64")]
+use crate::arch::x86::NUM_IOAPIC_PINS;
+#[cfg(target_arch = "aarch64")]
+use aarch64::{RegList, Register, StandardRegisters};
+#[cfg(target_arch = "x86_64")]
+use kvm_bindings::{
+    kvm_enable_cap, kvm_msr_entry, MsrList, KVM_CAP_HYPERV_SYNIC, KVM_CAP_SPLIT_IRQCHIP,
+};
 #[cfg(target_arch = "x86_64")]
 use x86_64::{
     check_required_kvm_extensions, FpuState, SpecialRegisters, StandardRegisters, KVM_TSS_ADDRESS,
 };
-
-#[cfg(target_arch = "aarch64")]
-use aarch64::{RegList, Register, StandardRegisters};
-
 #[cfg(target_arch = "x86_64")]
 pub use x86_64::{
     CpuId, CpuIdEntry, ExtendedControlRegisters, LapicState, MsrEntries, VcpuKvmState as CpuState,
     Xsave, CPUID_FLAG_VALID_INDEX,
 };
-
-#[cfg(target_arch = "x86_64")]
-use kvm_bindings::{
-    kvm_enable_cap, kvm_msr_entry, MsrList, KVM_CAP_HYPERV_SYNIC, KVM_CAP_SPLIT_IRQCHIP,
-};
-
-#[cfg(target_arch = "x86_64")]
-use crate::arch::x86::NUM_IOAPIC_PINS;
-
 // aarch64 dependencies
 #[cfg(target_arch = "aarch64")]
 pub mod aarch64;
+pub use kvm_bindings;
+#[cfg(feature = "tdx")]
+use kvm_bindings::KVMIO;
+pub use kvm_bindings::{
+    kvm_create_device, kvm_device_type_KVM_DEV_TYPE_VFIO, kvm_irq_routing, kvm_irq_routing_entry,
+    kvm_userspace_memory_region, KVM_IRQ_ROUTING_IRQCHIP, KVM_IRQ_ROUTING_MSI,
+    KVM_MEM_LOG_DIRTY_PAGES, KVM_MEM_READONLY, KVM_MSI_VALID_DEVID,
+};
 #[cfg(target_arch = "aarch64")]
 use kvm_bindings::{
     kvm_regs, user_fpsimd_state, user_pt_regs, KVM_NR_SPSR, KVM_REG_ARM64, KVM_REG_ARM_CORE,
     KVM_REG_SIZE_U128, KVM_REG_SIZE_U32, KVM_REG_SIZE_U64,
 };
-#[cfg(target_arch = "aarch64")]
-use std::mem;
-
-pub use kvm_bindings;
-pub use kvm_bindings::{
-    kvm_create_device, kvm_device_type_KVM_DEV_TYPE_VFIO, kvm_irq_routing, kvm_irq_routing_entry,
-    kvm_userspace_memory_region, KVM_IRQ_ROUTING_MSI, KVM_MEM_LOG_DIRTY_PAGES, KVM_MEM_READONLY,
-    KVM_MSI_VALID_DEVID,
-};
 pub use kvm_ioctls;
 pub use kvm_ioctls::{Cap, Kvm};
-
+#[cfg(target_arch = "aarch64")]
+use std::mem;
+use thiserror::Error;
+#[cfg(feature = "tdx")]
+use vmm_sys_util::{ioctl::ioctl_with_val, ioctl_expr, ioctl_ioc_nr, ioctl_iowr_nr};
 ///
 /// Export generically-named wrappers of kvm-bindings for Unix-based platforms
 ///
@@ -86,6 +88,24 @@ pub use {
     kvm_bindings::kvm_vcpu_events as VcpuEvents, kvm_ioctls::DeviceFd, kvm_ioctls::IoEventAddress,
     kvm_ioctls::VcpuExit,
 };
+
+#[cfg(target_arch = "x86_64")]
+const KVM_CAP_SGX_ATTRIBUTE: u32 = 196;
+
+#[cfg(feature = "tdx")]
+ioctl_iowr_nr!(KVM_MEMORY_ENCRYPT_OP, KVMIO, 0xba, std::os::raw::c_ulong);
+
+#[cfg(feature = "tdx")]
+#[repr(u32)]
+enum TdxCommand {
+    #[allow(dead_code)]
+    Capabilities = 0,
+    InitVm,
+    InitVcpu,
+    InitMemRegion,
+    Finalize,
+}
+
 #[derive(Clone, Copy, Debug, PartialEq, Deserialize, Serialize)]
 pub struct KvmVmState {}
 
@@ -98,36 +118,6 @@ pub struct KvmVm {
     state: KvmVmState,
 }
 
-// Returns a `Vec<T>` with a size in bytes at least as large as `size_in_bytes`.
-fn vec_with_size_in_bytes<T: Default>(size_in_bytes: usize) -> Vec<T> {
-    let rounded_size = (size_in_bytes + size_of::<T>() - 1) / size_of::<T>();
-    let mut v = Vec::with_capacity(rounded_size);
-    v.resize_with(rounded_size, T::default);
-    v
-}
-
-// The kvm API has many structs that resemble the following `Foo` structure:
-//
-// ```
-// #[repr(C)]
-// struct Foo {
-//    some_data: u32
-//    entries: __IncompleteArrayField<__u32>,
-// }
-// ```
-//
-// In order to allocate such a structure, `size_of::<Foo>()` would be too small because it would not
-// include any space for `entries`. To make the allocation large enough while still being aligned
-// for `Foo`, a `Vec<Foo>` is created. Only the first element of `Vec<Foo>` would actually be used
-// as a `Foo`. The remaining memory in the `Vec<Foo>` is for `entries`, which must be contiguous
-// with `Foo`. This function is used to make the `Vec<Foo>` with enough space for `count` entries.
-use std::mem::size_of;
-fn vec_with_array_field<T: Default, F>(count: usize) -> Vec<T> {
-    let element_space = count * size_of::<F>();
-    let vec_size_bytes = size_of::<T>() + element_space;
-    vec_with_size_in_bytes(vec_size_bytes)
-}
-
 ///
 /// Implementation of Vm trait for KVM
 /// Example:
@@ -241,7 +231,7 @@ impl vm::Vm for KvmVm {
         unsafe {
             let entries_slice: &mut [kvm_irq_routing_entry] =
                 irq_routing[0].entries.as_mut_slice(entries.len());
-            entries_slice.copy_from_slice(&entries);
+            entries_slice.copy_from_slice(entries);
         }
 
         self.fd
@@ -249,7 +239,7 @@ impl vm::Vm for KvmVm {
             .map_err(|e| vm::HypervisorVmError::SetGsiRouting(e.into()))
     }
     ///
-    /// Creates a memory region structure that can be used with set_user_memory_region
+    /// Creates a memory region structure that can be used with {create/remove}_user_memory_region
     ///
     fn make_user_memory_region(
         &self,
@@ -274,14 +264,29 @@ impl vm::Vm for KvmVm {
         }
     }
     ///
-    /// Creates/modifies a guest physical memory slot.
+    /// Creates a guest physical memory region.
     ///
-    fn set_user_memory_region(&self, user_memory_region: MemoryRegion) -> vm::Result<()> {
+    fn create_user_memory_region(&self, user_memory_region: MemoryRegion) -> vm::Result<()> {
         // Safe because guest regions are guaranteed not to overlap.
         unsafe {
             self.fd
                 .set_user_memory_region(user_memory_region)
-                .map_err(|e| vm::HypervisorVmError::SetUserMemory(e.into()))
+                .map_err(|e| vm::HypervisorVmError::CreateUserMemory(e.into()))
+        }
+    }
+    ///
+    /// Removes a guest physical memory region.
+    ///
+    fn remove_user_memory_region(&self, user_memory_region: MemoryRegion) -> vm::Result<()> {
+        let mut region = user_memory_region;
+
+        // Setting the size to 0 means "remove"
+        region.memory_size = 0;
+        // Safe because guest regions are guaranteed not to overlap.
+        unsafe {
+            self.fd
+                .set_user_memory_region(region)
+                .map_err(|e| vm::HypervisorVmError::RemoveUserMemory(e.into()))
         }
     }
     ///
@@ -324,6 +329,18 @@ impl vm::Vm for KvmVm {
             .map_err(|e| vm::HypervisorVmError::EnableSplitIrq(e.into()))?;
         Ok(())
     }
+    #[cfg(target_arch = "x86_64")]
+    fn enable_sgx_attribute(&self, file: File) -> vm::Result<()> {
+        let mut cap = kvm_enable_cap {
+            cap: KVM_CAP_SGX_ATTRIBUTE,
+            ..Default::default()
+        };
+        cap.args[0] = file.as_raw_fd() as u64;
+        self.fd
+            .enable_cap(&cap)
+            .map_err(|e| vm::HypervisorVmError::EnableSgxAttribute(e.into()))?;
+        Ok(())
+    }
     /// Retrieve guest clock.
     #[cfg(target_arch = "x86_64")]
     fn get_clock(&self) -> vm::Result<ClockData> {
@@ -374,14 +391,117 @@ impl vm::Vm for KvmVm {
             .get_dirty_log(slot, memory_size as usize)
             .map_err(|e| vm::HypervisorVmError::GetDirtyLog(e.into()))
     }
+
+    ///
+    /// Initialize TDX for this VM
+    ///
+    #[cfg(feature = "tdx")]
+    fn tdx_init(&self, cpuid: &CpuId, max_vcpus: u32) -> vm::Result<()> {
+        #[repr(C)]
+        struct TdxInitVm {
+            max_vcpus: u32,
+            reserved: u32,
+            attributes: u64,
+            cpuid: u64,
+        }
+        let data = TdxInitVm {
+            max_vcpus,
+            reserved: 0,
+            attributes: 1, // TDX1_TD_ATTRIBUTE_DEBUG,
+            cpuid: cpuid.as_fam_struct_ptr() as u64,
+        };
+
+        tdx_command(
+            &self.fd.as_raw_fd(),
+            TdxCommand::InitVm,
+            0,
+            &data as *const _ as u64,
+        )
+        .map_err(vm::HypervisorVmError::InitializeTdx)
+    }
+
+    ///
+    /// Finalize the TDX setup for this VM
+    ///
+    #[cfg(feature = "tdx")]
+    fn tdx_finalize(&self) -> vm::Result<()> {
+        tdx_command(&self.fd.as_raw_fd(), TdxCommand::Finalize, 0, 0)
+            .map_err(vm::HypervisorVmError::FinalizeTdx)
+    }
+
+    ///
+    /// Initialize memory regions for the TDX VM
+    ///
+    #[cfg(feature = "tdx")]
+    fn tdx_init_memory_region(
+        &self,
+        host_address: u64,
+        guest_address: u64,
+        size: u64,
+        measure: bool,
+    ) -> vm::Result<()> {
+        #[repr(C)]
+        struct TdxInitMemRegion {
+            host_address: u64,
+            guest_address: u64,
+            pages: u64,
+        }
+        let data = TdxInitMemRegion {
+            host_address,
+            guest_address,
+            pages: size / 4096,
+        };
+
+        tdx_command(
+            &self.fd.as_raw_fd(),
+            TdxCommand::InitMemRegion,
+            if measure { 1 } else { 0 },
+            &data as *const _ as u64,
+        )
+        .map_err(vm::HypervisorVmError::InitMemRegionTdx)
+    }
 }
+
+#[cfg(feature = "tdx")]
+fn tdx_command(
+    fd: &RawFd,
+    command: TdxCommand,
+    metadata: u32,
+    data: u64,
+) -> std::result::Result<(), std::io::Error> {
+    #[repr(C)]
+    struct TdxIoctlCmd {
+        command: TdxCommand,
+        metadata: u32,
+        data: u64,
+    }
+    let cmd = TdxIoctlCmd {
+        command,
+        metadata,
+        data,
+    };
+    let ret = unsafe {
+        ioctl_with_val(
+            fd,
+            KVM_MEMORY_ENCRYPT_OP(),
+            &cmd as *const TdxIoctlCmd as std::os::raw::c_ulong,
+        )
+    };
+
+    if ret < 0 {
+        return Err(std::io::Error::last_os_error());
+    }
+    Ok(())
+}
+
 /// Wrapper over KVM system ioctls.
 pub struct KvmHypervisor {
     kvm: Kvm,
 }
 /// Enum for KVM related error
-#[derive(Debug)]
+#[derive(Debug, Error)]
 pub enum KvmError {
+    #[error("Capability missing: {0:?}")]
     CapabilityMissing(Cap),
 }
 pub type KvmResult<T> = result::Result<T, KvmError>;
@@ -407,18 +527,18 @@ impl KvmHypervisor {
 /// let vm = hypervisor.create_vm().expect("new VM fd creation failed");
 ///
 impl hypervisor::Hypervisor for KvmHypervisor {
-    /// Create a KVM vm object and return the object as Vm trait object
+    /// Create a KVM vm object of a specific VM type and return the object as Vm trait object
     /// Example
     /// # extern crate hypervisor;
     /// # use hypervisor::KvmHypervisor;
     /// use hypervisor::KvmVm;
     /// let hypervisor = KvmHypervisor::new().unwrap();
-    /// let vm = hypervisor.create_vm().unwrap()
+    /// let vm = hypervisor.create_vm_with_type(KvmVmType::LegacyVm).unwrap()
     ///
-    fn create_vm(&self) -> hypervisor::Result<Arc<dyn vm::Vm>> {
+    fn create_vm_with_type(&self, vm_type: u64) -> hypervisor::Result<Arc<dyn vm::Vm>> {
         let fd: VmFd;
         loop {
-            match self.kvm.create_vm() {
+            match self.kvm.create_vm_with_type(vm_type) {
                 Ok(res) => fd = res,
                 Err(e) => {
                     if e.errno() == libc::EINTR {
@@ -440,7 +560,7 @@ impl hypervisor::Hypervisor for KvmHypervisor {
         {
             let msr_list = self.get_msr_list()?;
             let num_msrs = msr_list.as_fam_struct_ref().nmsrs as usize;
-            let mut msrs = MsrEntries::new(num_msrs);
+            let mut msrs = MsrEntries::new(num_msrs).unwrap();
             let indices = msr_list.as_slice();
             let msr_entries = msrs.as_mut_slice();
             for (pos, index) in indices.iter().enumerate() {
@@ -463,38 +583,34 @@ impl hypervisor::Hypervisor for KvmHypervisor {
         }
     }
 
-    fn check_required_extensions(&self) -> hypervisor::Result<()> {
-        check_required_kvm_extensions(&self.kvm).expect("Missing KVM capabilities");
-        Ok(())
+    /// Create a KVM vm object and return the object as Vm trait object
+    /// Example
+    /// # extern crate hypervisor;
+    /// # use hypervisor::KvmHypervisor;
+    /// use hypervisor::KvmVm;
+    /// let hypervisor = KvmHypervisor::new().unwrap();
+    /// let vm = hypervisor.create_vm().unwrap()
+    ///
+    fn create_vm(&self) -> hypervisor::Result<Arc<dyn vm::Vm>> {
+        #[allow(unused_mut)]
+        let mut vm_type: u64 = 0; // Create with default platform type
+
+        // When KVM supports Cap::ArmVmIPASize, it is better to get the IPA
+        // size from the host and use that when creating the VM, which may
+        // avoid unnecessary VM creation failures.
+        #[cfg(target_arch = "aarch64")]
+        if self.kvm.check_extension(Cap::ArmVmIPASize) {
+            vm_type = self.kvm.get_host_ipa_limit().try_into().unwrap();
+        }
+
+        self.create_vm_with_type(vm_type)
     }
 
-    ///
-    ///  Returns the size of the memory mapping required to use the vcpu's `kvm_run` structure.
-    ///
-    fn get_vcpu_mmap_size(&self) -> hypervisor::Result<usize> {
-        self.kvm
-            .get_vcpu_mmap_size()
-            .map_err(|e| hypervisor::HypervisorError::GetVcpuMmap(e.into()))
-    }
-    ///
-    /// Gets the recommended maximum number of VCPUs per VM.
-    ///
-    fn get_max_vcpus(&self) -> hypervisor::Result<usize> {
-        Ok(self.kvm.get_max_vcpus())
-    }
-    ///
-    /// Gets the recommended number of VCPUs per VM.
-    ///
-    fn get_nr_vcpus(&self) -> hypervisor::Result<usize> {
-        Ok(self.kvm.get_nr_vcpus())
-    }
-    #[cfg(target_arch = "x86_64")]
-    ///
-    /// Checks if a particular `Cap` is available.
-    ///
-    fn check_capability(&self, c: Cap) -> bool {
-        self.kvm.check_extension(c)
+    fn check_required_extensions(&self) -> hypervisor::Result<()> {
+        check_required_kvm_extensions(&self.kvm)
+            .map_err(|e| hypervisor::HypervisorError::CheckExtensions(e.into()))
     }
+
     #[cfg(target_arch = "x86_64")]
     ///
     /// X86 specific call to get the system supported CPUID values.
@@ -504,6 +620,7 @@ impl hypervisor::Hypervisor for KvmHypervisor {
             .get_supported_cpuid(kvm_bindings::KVM_MAX_CPUID_ENTRIES)
             .map_err(|e| hypervisor::HypervisorError::GetCpuId(e.into()))
     }
+
     #[cfg(target_arch = "x86_64")]
     ///
     /// Retrieve the list of MSRs supported by KVM.
@@ -513,6 +630,13 @@ impl hypervisor::Hypervisor for KvmHypervisor {
             .get_msr_index_list()
             .map_err(|e| hypervisor::HypervisorError::GetMsrList(e.into()))
     }
+    #[cfg(target_arch = "aarch64")]
+    ///
+    /// Retrieve AArch64 host maximum IPA size supported by KVM.
+    ///
+    fn get_host_ipa_limit(&self) -> i32 {
+        self.kvm.get_host_ipa_limit()
+    }
 }
 /// Vcpu struct for KVM
 pub struct KvmVcpu {
@@ -612,7 +736,7 @@ impl cpu::Vcpu for KvmVcpu {
         };
         self.fd
             .enable_cap(&cap)
-            .map_err(|e| cpu::HypervisorCpuError::EnableHyperVSynIC(e.into()))
+            .map_err(|e| cpu::HypervisorCpuError::EnableHyperVSyncIc(e.into()))
     }
     ///
     /// X86 specific call to retrieve the CPUID registers.
@@ -709,7 +833,7 @@ impl cpu::Vcpu for KvmVcpu {
     ///
     fn set_xcrs(&self, xcrs: &ExtendedControlRegisters) -> cpu::Result<()> {
         self.fd
-            .set_xcrs(&xcrs)
+            .set_xcrs(xcrs)
             .map_err(|e| cpu::HypervisorCpuError::SetXcsr(e.into()))
     }
     ///
@@ -1043,7 +1167,7 @@ impl cpu::Vcpu for KvmVcpu {
     fn system_registers(&self, state: &mut Vec<Register>) -> cpu::Result<()> {
         // Call KVM_GET_REG_LIST to get all registers available to the guest. For ArmV8 there are
         // around 500 registers.
-        let mut reg_list = RegList::new(512);
+        let mut reg_list = RegList::new(500).unwrap();
         self.fd
             .get_reg_list(&mut reg_list)
             .map_err(|e| cpu::HypervisorCpuError::GetRegList(e.into()))?;
@@ -1177,7 +1301,7 @@ impl cpu::Vcpu for KvmVcpu {
         let msrs = if num_msrs != expected_num_msrs {
             let mut faulty_msr_index = num_msrs;
             let mut msr_entries_tmp =
-                MsrEntries::from_entries(&msr_entries.as_slice()[..faulty_msr_index]);
+                MsrEntries::from_entries(&msr_entries.as_slice()[..faulty_msr_index]).unwrap();
 
             loop {
                 warn!(
@@ -1187,7 +1311,7 @@ impl cpu::Vcpu for KvmVcpu {
 
                 let start_pos = faulty_msr_index + 1;
                 let mut sub_msr_entries =
-                    MsrEntries::from_entries(&msr_entries.as_slice()[start_pos..]);
+                    MsrEntries::from_entries(&msr_entries.as_slice()[start_pos..]).unwrap();
                 let expected_num_msrs = sub_msr_entries.as_fam_struct_ref().nmsrs as usize;
                 let num_msrs = self.get_msrs(&mut sub_msr_entries)?;
 
@@ -1311,7 +1435,8 @@ impl cpu::Vcpu for KvmVcpu {
                 );
 
                 let start_pos = faulty_msr_index + 1;
-                let sub_msr_entries = MsrEntries::from_entries(&state.msrs.as_slice()[start_pos..]);
+                let sub_msr_entries =
+                    MsrEntries::from_entries(&state.msrs.as_slice()[start_pos..]).unwrap();
                 let expected_num_msrs = sub_msr_entries.as_fam_struct_ref().nmsrs as usize;
                 let num_msrs = self.set_msrs(&sub_msr_entries)?;
 
@@ -1338,6 +1463,15 @@ impl cpu::Vcpu for KvmVcpu {
 
         Ok(())
     }
+
+    ///
+    /// Initialize TDX for this CPU
+    ///
+    #[cfg(feature = "tdx")]
+    fn tdx_init(&self, hob_address: u64) -> cpu::Result<()> {
+        tdx_command(&self.fd.as_raw_fd(), TdxCommand::InitVcpu, 0, hob_address)
+            .map_err(cpu::HypervisorCpuError::InitializeTdx)
+    }
 }
 
 /// Device struct for KVM

hypervisor/src/kvm/x86_64/mod.rs

@@ -111,6 +111,7 @@ pub fn boot_msr_entries() -> MsrEntries {
         ),
         msr_data!(msr_index::MSR_MTRRdefType, MTRR_ENABLE | MTRR_MEM_TYPE_WB),
     ])
+    .unwrap()
 }
 
 ///

hypervisor/src/lib.rs

@@ -23,10 +23,6 @@ extern crate anyhow;
 #[cfg(target_arch = "x86_64")]
 #[macro_use]
 extern crate log;
-extern crate serde;
-extern crate serde_derive;
-extern crate serde_json;
-extern crate thiserror;
 
 /// Architecture specific definitions
 #[macro_use]
@@ -72,3 +68,33 @@ pub fn new() -> std::result::Result<Arc<dyn Hypervisor>, HypervisorError> {
 
     Ok(Arc::new(hv))
 }
+
+// Returns a `Vec<T>` with a size in bytes at least as large as `size_in_bytes`.
+fn vec_with_size_in_bytes<T: Default>(size_in_bytes: usize) -> Vec<T> {
+    let rounded_size = (size_in_bytes + size_of::<T>() - 1) / size_of::<T>();
+    let mut v = Vec::with_capacity(rounded_size);
+    v.resize_with(rounded_size, T::default);
+    v
+}
+
+// The kvm API has many structs that resemble the following `Foo` structure:
+//
+// ```
+// #[repr(C)]
+// struct Foo {
+//    some_data: u32
+//    entries: __IncompleteArrayField<__u32>,
+// }
+// ```
+//
+// In order to allocate such a structure, `size_of::<Foo>()` would be too small because it would not
+// include any space for `entries`. To make the allocation large enough while still being aligned
+// for `Foo`, a `Vec<Foo>` is created. Only the first element of `Vec<Foo>` would actually be used
+// as a `Foo`. The remaining memory in the `Vec<Foo>` is for `entries`, which must be contiguous
+// with `Foo`. This function is used to make the `Vec<Foo>` with enough space for `count` entries.
+use std::mem::size_of;
+pub fn vec_with_array_field<T: Default, F>(count: usize) -> Vec<T> {
+    let element_space = count * size_of::<F>();
+    let vec_size_bytes = size_of::<T>() + element_space;
+    vec_with_size_in_bytes(vec_size_bytes)
+}

hypervisor/src/mshv/mod.rs

@@ -5,17 +5,16 @@
 
 use crate::arch::emulator::{PlatformEmulator, PlatformError};
 
-use thiserror::Error;
-
 #[cfg(target_arch = "x86_64")]
 use crate::arch::x86::emulator::{Emulator, EmulatorCpuState};
 use crate::cpu;
 use crate::cpu::Vcpu;
 use crate::hypervisor;
+use crate::vec_with_array_field;
 use crate::vm::{self, VmmOps};
 pub use mshv_bindings::*;
 pub use mshv_ioctls::IoEventAddress;
-use mshv_ioctls::{set_registers_64, InterruptRequest, Mshv, NoDatamatch, VcpuFd, VmFd};
+use mshv_ioctls::{set_registers_64, Mshv, NoDatamatch, VcpuFd, VmFd};
 use serde_derive::{Deserialize, Serialize};
 use std::sync::Arc;
 use vm::DataMatch;
@@ -29,7 +28,8 @@ pub use x86_64::VcpuMshvState as CpuState;
 #[cfg(target_arch = "x86_64")]
 pub use x86_64::*;
 
-use std::collections::HashMap;
+#[cfg(target_arch = "x86_64")]
+use std::fs::File;
 use std::os::unix::io::AsRawFd;
 use std::sync::RwLock;
 
@@ -93,7 +93,7 @@ impl hypervisor::Hypervisor for MshvHypervisor {
 
         let msr_list = self.get_msr_list()?;
         let num_msrs = msr_list.as_fam_struct_ref().nmsrs as usize;
-        let mut msrs = MsrEntries::new(num_msrs);
+        let mut msrs = MsrEntries::new(num_msrs).unwrap();
         let indices = msr_list.as_slice();
         let msr_entries = msrs.as_mut_slice();
         for (pos, index) in indices.iter().enumerate() {
@@ -101,12 +101,9 @@ impl hypervisor::Hypervisor for MshvHypervisor {
         }
         let vm_fd = Arc::new(fd);
 
-        let gsi_routes = Arc::new(RwLock::new(HashMap::new()));
-
         Ok(Arc::new(MshvVm {
             fd: vm_fd,
             msrs,
-            gsi_routes,
             hv_state: hv_state_init(),
             vmmops: None,
         }))
@@ -115,7 +112,7 @@ impl hypervisor::Hypervisor for MshvHypervisor {
     /// Get the supported CpuID
     ///
     fn get_cpuid(&self) -> hypervisor::Result<CpuId> {
-        Ok(CpuId::new(1))
+        Ok(CpuId::new(1).unwrap())
     }
     #[cfg(target_arch = "x86_64")]
     ///
@@ -128,38 +125,6 @@ impl hypervisor::Hypervisor for MshvHypervisor {
     }
 }
 
-#[derive(Clone)]
-// A software emulated TLB.
-// This is mostly used by the instruction emulator to cache gva to gpa translations
-// passed from the hypervisor.
-struct SoftTLB {
-    addr_map: HashMap<u64, u64>,
-}
-
-impl SoftTLB {
-    fn new() -> SoftTLB {
-        SoftTLB {
-            addr_map: HashMap::new(),
-        }
-    }
-
-    // Adds a gva -> gpa mapping into the TLB.
-    fn add_mapping(&mut self, gva: u64, gpa: u64) {
-        *self.addr_map.entry(gva).or_insert(gpa) = gpa;
-    }
-
-    // Do the actual gva -> gpa translation
-    fn translate(&self, gva: u64) -> Result<u64, PlatformError> {
-        self.addr_map
-            .get(&gva)
-            .ok_or_else(|| PlatformError::UnmappedGVA(anyhow!("{:#?}", gva)))
-            .map(|v| *v)
-
-        // TODO Check if we could fallback to e.g. an hypercall for doing
-        // the translation for us.
-    }
-}
-#[allow(clippy::type_complexity)]
 #[allow(dead_code)]
 /// Vcpu struct for Microsoft Hypervisor
 pub struct MshvVcpu {
@@ -167,7 +132,6 @@ pub struct MshvVcpu {
     vp_index: u8,
     cpuid: CpuId,
     msrs: MsrEntries,
-    gsi_routes: Arc<RwLock<HashMap<u32, MshvIrqRoutingEntry>>>,
     hv_state: Arc<RwLock<HvState>>, // Mshv State
     vmmops: Option<Arc<Box<dyn vm::VmmOps>>>,
 }
@@ -273,7 +237,7 @@ impl cpu::Vcpu for MshvVcpu {
     ///
     fn set_xcrs(&self, xcrs: &ExtendedControlRegisters) -> cpu::Result<()> {
         self.fd
-            .set_xcrs(&xcrs)
+            .set_xcrs(xcrs)
             .map_err(|e| cpu::HypervisorCpuError::SetXcsr(e.into()))
     }
     #[cfg(target_arch = "x86_64")]
@@ -322,17 +286,52 @@ impl cpu::Vcpu for MshvVcpu {
                 hv_message_type_HVMSG_X64_IO_PORT_INTERCEPT => {
                     let info = x.to_ioport_info().unwrap();
                     let access_info = info.access_info;
+                    let len = unsafe { access_info.__bindgen_anon_1.access_size() } as usize;
+                    let is_write = info.header.intercept_access_type == 1;
+                    let port = info.port_number;
+                    let mut data: [u8; 4] = [0; 4];
+                    let mut ret_rax = info.rax;
+
+                    /*
+                     * XXX: Ignore QEMU fw_cfg (0x5xx) and debug console (0x402) ports.
+                     *
+                     * Cloud Hypervisor doesn't support fw_cfg at the moment. It does support 0x402
+                     * under the "fwdebug" feature flag. But that feature is not enabled by default
+                     * and is considered legacy.
+                     *
+                     * OVMF unconditionally pokes these IO ports with string IO.
+                     *
+                     * Instead of trying to implement string IO support now which does not do much
+                     * now, skip those ports explicitly to avoid panicking.
+                     *
+                     * Proper string IO support can be added once we gain the ability to translate
+                     * guest virtual addresses to guest physical addresses on MSHV.
+                     */
+                    match port {
+                        0x402 | 0x510 | 0x511 | 0x514 => {
+                            let insn_len = info.header.instruction_length() as u64;
+
+                            /* Advance RIP and update RAX */
+                            let arr_reg_name_value = [
+                                (
+                                    hv_register_name::HV_X64_REGISTER_RIP,
+                                    info.header.rip + insn_len,
+                                ),
+                                (hv_register_name::HV_X64_REGISTER_RAX, ret_rax),
+                            ];
+                            set_registers_64!(self.fd, arr_reg_name_value)
+                                .map_err(|e| cpu::HypervisorCpuError::SetRegister(e.into()))?;
+                            return Ok(cpu::VmExit::Ignore);
+                        }
+                        _ => {}
+                    }
+
                     if unsafe { access_info.__bindgen_anon_1.string_op() } == 1 {
                         panic!("String IN/OUT not supported");
                     }
                     if unsafe { access_info.__bindgen_anon_1.rep_prefix() } == 1 {
                         panic!("Rep IN/OUT not supported");
                     }
-                    let len = unsafe { access_info.__bindgen_anon_1.access_size() } as usize;
-                    let is_write = info.header.intercept_access_type == 1;
-                    let port = info.port_number;
-                    let mut data: [u8; 4] = [0; 4];
-                    let mut ret_rax = info.rax;
 
                     if is_write {
                         let data = (info.rax as u32).to_le_bytes();
@@ -376,14 +375,9 @@ impl cpu::Vcpu for MshvVcpu {
 
                     let mut context = MshvEmulatorContext {
                         vcpu: self,
-                        tlb: SoftTLB::new(),
+                        map: (info.guest_virtual_address, info.guest_physical_address),
                     };
 
-                    // Add the GVA <-> GPA mapping.
-                    context
-                        .tlb
-                        .add_mapping(info.guest_virtual_address, info.guest_physical_address);
-
                     // Create a new emulator.
                     let mut emul = Emulator::new(&mut context);
 
@@ -401,22 +395,22 @@ impl cpu::Vcpu for MshvVcpu {
                 }
                 hv_message_type_HVMSG_X64_CPUID_INTERCEPT => {
                     let info = x.to_cpuid_info().unwrap();
-                    debug!("cpuid eax: {:x}", info.rax);
+                    debug!("cpuid eax: {:x}", { info.rax });
                     Ok(cpu::VmExit::Ignore)
                 }
                 hv_message_type_HVMSG_X64_MSR_INTERCEPT => {
                     let info = x.to_msr_info().unwrap();
                     if info.header.intercept_access_type == 0 {
-                        debug!("msr read: {:x}", info.msr_number);
+                        debug!("msr read: {:x}", { info.msr_number });
                     } else {
-                        debug!("msr write: {:x}", info.msr_number);
+                        debug!("msr write: {:x}", { info.msr_number });
                     }
                     Ok(cpu::VmExit::Ignore)
                 }
                 hv_message_type_HVMSG_X64_EXCEPTION_INTERCEPT => {
                     //TODO: Handler for VMCALL here.
                     let info = x.to_exception_info().unwrap();
-                    debug!("Exception Info {:?}", info.exception_vector);
+                    debug!("Exception Info {:?}", { info.exception_vector });
                     Ok(cpu::VmExit::Ignore)
                 }
                 exit => Err(cpu::HypervisorCpuError::RunVcpu(anyhow!(
@@ -481,7 +475,7 @@ impl cpu::Vcpu for MshvVcpu {
     ///
     fn set_xsave(&self, xsave: &Xsave) -> cpu::Result<()> {
         self.fd
-            .set_xsave(*xsave)
+            .set_xsave(xsave)
             .map_err(|e| cpu::HypervisorCpuError::SetXsaveState(e.into()))
     }
     ///
@@ -530,11 +524,56 @@ impl cpu::Vcpu for MshvVcpu {
             xsave,
         })
     }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Translate guest virtual address to guest physical address
+    ///
+    fn translate_gva(&self, gva: u64, flags: u64) -> cpu::Result<(u64, hv_translate_gva_result)> {
+        let r = self
+            .fd
+            .translate_gva(gva, flags)
+            .map_err(|e| cpu::HypervisorCpuError::TranslateVirtualAddress(e.into()))?;
+
+        Ok(r)
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// X86 specific call that returns the vcpu's current "suspend registers".
+    ///
+    fn get_suspend_regs(&self) -> cpu::Result<SuspendRegisters> {
+        self.fd
+            .get_suspend_regs()
+            .map_err(|e| cpu::HypervisorCpuError::GetSuspendRegs(e.into()))
+    }
 }
 
 struct MshvEmulatorContext<'a> {
     vcpu: &'a MshvVcpu,
-    tlb: SoftTLB,
+    map: (u64, u64), // Initial GVA to GPA mapping provided by the hypervisor
+}
+
+impl<'a> MshvEmulatorContext<'a> {
+    // Do the actual gva -> gpa translation
+    #[allow(non_upper_case_globals)]
+    fn translate(&self, gva: u64) -> Result<u64, PlatformError> {
+        if self.map.0 == gva {
+            return Ok(self.map.1);
+        }
+
+        // TODO: More fine-grained control for the flags
+        let flags = HV_TRANSLATE_GVA_VALIDATE_READ | HV_TRANSLATE_GVA_VALIDATE_WRITE;
+
+        let r = self
+            .vcpu
+            .translate_gva(gva, flags.into())
+            .map_err(|e| PlatformError::TranslateVirtualAddress(anyhow!(e)))?;
+
+        let result_code = unsafe { r.1.__bindgen_anon_1.result_code };
+        match result_code {
+            hv_translate_gva_result_code_HV_TRANSLATE_GVA_SUCCESS => Ok(r.0),
+            _ => Err(PlatformError::TranslateVirtualAddress(anyhow!(result_code))),
+        }
+    }
 }
 
 /// Platform emulation for Hyper-V
@@ -542,7 +581,7 @@ impl<'a> PlatformEmulator for MshvEmulatorContext<'a> {
     type CpuState = EmulatorCpuState;
 
     fn read_memory(&self, gva: u64, data: &mut [u8]) -> Result<(), PlatformError> {
-        let gpa = self.tlb.translate(gva)?;
+        let gpa = self.translate(gva)?;
         debug!(
             "mshv emulator: memory read {} bytes from [{:#x} -> {:#x}]",
             data.len(),
@@ -551,16 +590,18 @@ impl<'a> PlatformEmulator for MshvEmulatorContext<'a> {
         );
 
         if let Some(vmmops) = &self.vcpu.vmmops {
-            vmmops
-                .mmio_read(gpa, data)
-                .map_err(|e| PlatformError::MemoryReadFailure(e.into()))?;
+            if vmmops.guest_mem_read(gpa, data).is_err() {
+                vmmops
+                    .mmio_read(gpa, data)
+                    .map_err(|e| PlatformError::MemoryReadFailure(e.into()))?;
+            }
         }
 
         Ok(())
     }
 
     fn write_memory(&mut self, gva: u64, data: &[u8]) -> Result<(), PlatformError> {
-        let gpa = self.tlb.translate(gva)?;
+        let gpa = self.translate(gva)?;
         debug!(
             "mshv emulator: memory write {} bytes at [{:#x} -> {:#x}]",
             data.len(),
@@ -569,9 +610,11 @@ impl<'a> PlatformEmulator for MshvEmulatorContext<'a> {
         );
 
         if let Some(vmmops) = &self.vcpu.vmmops {
-            vmmops
-                .mmio_write(gpa, data)
-                .map_err(|e| PlatformError::MemoryWriteFailure(e.into()))?;
+            if vmmops.guest_mem_write(gpa, data).is_err() {
+                vmmops
+                    .mmio_write(gpa, data)
+                    .map_err(|e| PlatformError::MemoryWriteFailure(e.into()))?;
+            }
         }
 
         Ok(())
@@ -622,7 +665,7 @@ impl<'a> PlatformEmulator for MshvEmulatorContext<'a> {
     }
 
     fn gva_to_gpa(&self, gva: u64) -> Result<u64, PlatformError> {
-        self.tlb.translate(gva)
+        self.translate(gva)
     }
 
     fn fetch(&self, _ip: u64, _instruction_bytes: &mut [u8]) -> Result<(), PlatformError> {
@@ -630,14 +673,11 @@ impl<'a> PlatformEmulator for MshvEmulatorContext<'a> {
     }
 }
 
-#[allow(clippy::type_complexity)]
 #[allow(dead_code)]
 /// Wrapper over Mshv VM ioctls.
 pub struct MshvVm {
     fd: Arc<VmFd>,
     msrs: MsrEntries,
-    // GSI routing information
-    gsi_routes: Arc<RwLock<HashMap<u32, MshvIrqRoutingEntry>>>,
     // Hypervisor State
     hv_state: Arc<RwLock<HvState>>,
     vmmops: Option<Arc<Box<dyn vm::VmmOps>>>,
@@ -678,19 +718,9 @@ impl vm::Vm for MshvVm {
     fn register_irqfd(&self, fd: &EventFd, gsi: u32) -> vm::Result<()> {
         debug!("register_irqfd fd {} gsi {}", fd.as_raw_fd(), gsi);
 
-        let gsi_routes = self.gsi_routes.read().unwrap();
-
-        if let Some(e) = gsi_routes.get(&gsi) {
-            let msi = e
-                .get_msi_routing()
-                .map_err(|e| vm::HypervisorVmError::RegisterIrqFd(e.into()))?;
-            let request = msi.to_interrupt_request();
-            self.fd
-                .register_irqfd(&fd, gsi, &request)
-                .map_err(|e| vm::HypervisorVmError::RegisterIrqFd(e.into()))?;
-        } else {
-            error!("No routing info found for GSI {}", gsi)
-        }
+        self.fd
+            .register_irqfd(fd, gsi)
+            .map_err(|e| vm::HypervisorVmError::RegisterIrqFd(e.into()))?;
 
         Ok(())
     }
@@ -701,7 +731,7 @@ impl vm::Vm for MshvVm {
         debug!("unregister_irqfd fd {} gsi {}", fd.as_raw_fd(), gsi);
 
         self.fd
-            .unregister_irqfd(&fd, gsi)
+            .unregister_irqfd(fd, gsi)
             .map_err(|e| vm::HypervisorVmError::UnregisterIrqFd(e.into()))?;
 
         Ok(())
@@ -721,9 +751,8 @@ impl vm::Vm for MshvVm {
         let vcpu = MshvVcpu {
             fd: vcpu_fd,
             vp_index: id,
-            cpuid: CpuId::new(1),
+            cpuid: CpuId::new(1).unwrap(),
             msrs: self.msrs.clone(),
-            gsi_routes: self.gsi_routes.clone(),
             hv_state: self.hv_state.clone(),
             vmmops,
         };
@@ -733,6 +762,10 @@ impl vm::Vm for MshvVm {
     fn enable_split_irq(&self) -> vm::Result<()> {
         Ok(())
     }
+    #[cfg(target_arch = "x86_64")]
+    fn enable_sgx_attribute(&self, _file: File) -> vm::Result<()> {
+        Ok(())
+    }
     fn register_ioevent(
         &self,
         fd: &EventFd,
@@ -771,11 +804,19 @@ impl vm::Vm for MshvVm {
             .map_err(|e| vm::HypervisorVmError::UnregisterIoEvent(e.into()))
     }
 
-    /// Creates/modifies a guest physical memory slot.
-    fn set_user_memory_region(&self, user_memory_region: MemoryRegion) -> vm::Result<()> {
+    /// Creates a guest physical memory region.
+    fn create_user_memory_region(&self, user_memory_region: MemoryRegion) -> vm::Result<()> {
         self.fd
             .map_user_memory(user_memory_region)
-            .map_err(|e| vm::HypervisorVmError::SetUserMemory(e.into()))?;
+            .map_err(|e| vm::HypervisorVmError::CreateUserMemory(e.into()))?;
+        Ok(())
+    }
+
+    /// Removes a guest physical memory region.
+    fn remove_user_memory_region(&self, user_memory_region: MemoryRegion) -> vm::Result<()> {
+        self.fd
+            .unmap_user_memory(user_memory_region)
+            .map_err(|e| vm::HypervisorVmError::RemoveUserMemory(e.into()))?;
         Ok(())
     }
 
@@ -807,17 +848,20 @@ impl vm::Vm for MshvVm {
         )))
     }
 
-    fn set_gsi_routing(&self, irq_routing: &[IrqRoutingEntry]) -> vm::Result<()> {
-        let mut routes = self.gsi_routes.write().unwrap();
+    fn set_gsi_routing(&self, entries: &[IrqRoutingEntry]) -> vm::Result<()> {
+        let mut msi_routing =
+            vec_with_array_field::<mshv_msi_routing, mshv_msi_routing_entry>(entries.len());
+        msi_routing[0].nr = entries.len() as u32;
 
-        routes.drain();
-
-        for r in irq_routing {
-            debug!("gsi routing {:x?}", r);
-            routes.insert(r.gsi, *r);
+        unsafe {
+            let entries_slice: &mut [mshv_msi_routing_entry] =
+                msi_routing[0].entries.as_mut_slice(entries.len());
+            entries_slice.copy_from_slice(entries);
         }
 
-        Ok(())
+        self.fd
+            .set_msi_routing(&msi_routing[0])
+            .map_err(|e| vm::HypervisorVmError::SetGsiRouting(e.into()))
     }
     ///
     /// Get the Vm state. Return VM specific data
@@ -843,104 +887,6 @@ impl vm::Vm for MshvVm {
 }
 pub use hv_cpuid_entry as CpuIdEntry;
 
-#[derive(Copy, Clone, Debug)]
-pub struct MshvIrqRoutingMsi {
-    pub address_lo: u32,
-    pub address_hi: u32,
-    pub data: u32,
-}
-
-#[derive(Copy, Clone, Debug)]
-pub enum MshvIrqRouting {
-    Msi(MshvIrqRoutingMsi),
-}
-
-#[derive(Error, Debug)]
-pub enum MshvIrqRoutingEntryError {
-    #[error("Invalid MSI address: {0}")]
-    InvalidMsiAddress(#[source] anyhow::Error),
-}
-
-#[derive(Copy, Clone, Debug)]
-pub struct MshvIrqRoutingEntry {
-    pub gsi: u32,
-    pub route: MshvIrqRouting,
-}
-pub type IrqRoutingEntry = MshvIrqRoutingEntry;
-
-impl MshvIrqRoutingEntry {
-    fn get_msi_routing(&self) -> Result<MshvIrqRoutingMsi, MshvIrqRoutingEntryError> {
-        let MshvIrqRouting::Msi(msi) = self.route;
-        if msi.address_hi != 0 {
-            return Err(MshvIrqRoutingEntryError::InvalidMsiAddress(anyhow!(
-                "MSI high address part is not zero"
-            )));
-        }
-        Ok(msi)
-    }
-}
-
-impl MshvIrqRoutingMsi {
-    ///
-    /// See Intel SDM vol3 10.11.1
-    /// We assume APIC ID and Hyper-V Vcpu ID are the same value
-    ///
-
-    fn get_destination(&self) -> u64 {
-        ((self.address_lo >> 12) & 0xff).into()
-    }
-
-    fn get_destination_mode(&self) -> bool {
-        if (self.address_lo >> 2) & 0x1 == 0x1 {
-            return true;
-        }
-        false
-    }
-
-    fn get_vector(&self) -> u8 {
-        (self.data & 0xff) as u8
-    }
-
-    ///
-    ///  True means level triggered
-    ///
-    fn get_trigger_mode(&self) -> bool {
-        if (self.data >> 15) & 0x1 == 0x1 {
-            return true;
-        }
-        false
-    }
-
-    fn get_delivery_mode(&self) -> u8 {
-        ((self.data & 0x700) >> 8) as u8
-    }
-
-    ///
-    ///  Translate from architectural defined delivery mode to Hyper-V type
-    /// See Intel SDM vol3 10.11.2
-    ///
-    fn get_interrupt_type(&self) -> Option<hv_interrupt_type> {
-        match self.get_delivery_mode() {
-            0 => Some(hv_interrupt_type_HV_X64_INTERRUPT_TYPE_FIXED),
-            1 => Some(hv_interrupt_type_HV_X64_INTERRUPT_TYPE_LOWESTPRIORITY),
-            2 => Some(hv_interrupt_type_HV_X64_INTERRUPT_TYPE_SMI),
-            4 => Some(hv_interrupt_type_HV_X64_INTERRUPT_TYPE_NMI),
-            5 => Some(hv_interrupt_type_HV_X64_INTERRUPT_TYPE_INIT),
-            7 => Some(hv_interrupt_type_HV_X64_INTERRUPT_TYPE_EXTINT),
-            _ => None,
-        }
-    }
-
-    pub fn to_interrupt_request(&self) -> InterruptRequest {
-        InterruptRequest {
-            interrupt_type: self.get_interrupt_type().unwrap(),
-            apic_id: self.get_destination(),
-            vector: self.get_vector() as u32,
-            level_triggered: self.get_trigger_mode(),
-            logical_destination_mode: self.get_destination_mode(),
-            long_mode: false,
-        }
-    }
-}
+pub type IrqRoutingEntry = mshv_msi_routing_entry;
 
 pub const CPUID_FLAG_VALID_INDEX: u32 = 0;

hypervisor/src/mshv/x86_64/mod.rs

@@ -7,9 +7,10 @@
 // Copyright 2018-2019 CrowdStrike, Inc.
 //
 //
-
-use crate::arch::x86::{msr_index, SegmentRegisterOps};
+use crate::arch::x86::{msr_index, SegmentRegisterOps, MTRR_ENABLE, MTRR_MEM_TYPE_WB};
 use serde_derive::{Deserialize, Serialize};
+use std::fmt;
+
 ///
 /// Export generically-named wrappers of mshv_bindings for Unix-based platforms
 ///
@@ -19,8 +20,8 @@ pub use {
     mshv_bindings::FloatingPointUnit as FpuState, mshv_bindings::LapicState,
     mshv_bindings::MsrList, mshv_bindings::Msrs as MsrEntries, mshv_bindings::Msrs,
     mshv_bindings::SegmentRegister, mshv_bindings::SpecialRegisters,
-    mshv_bindings::StandardRegisters, mshv_bindings::VcpuEvents, mshv_bindings::XSave as Xsave,
-    mshv_bindings::Xcrs as ExtendedControlRegisters,
+    mshv_bindings::StandardRegisters, mshv_bindings::SuspendRegisters, mshv_bindings::VcpuEvents,
+    mshv_bindings::XSave as Xsave, mshv_bindings::Xcrs as ExtendedControlRegisters,
 };
 
 #[derive(Clone, Serialize, Deserialize)]
@@ -36,6 +37,30 @@ pub struct VcpuMshvState {
     pub xsave: Xsave,
 }
 
+impl fmt::Display for VcpuMshvState {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        let expected_num_msrs = self.msrs.as_fam_struct_ref().nmsrs as usize;
+        let mut msr_entries = vec![vec![0; 2]; expected_num_msrs];
+
+        for (i, entry) in self.msrs.as_slice().iter().enumerate() {
+            msr_entries[i][1] = entry.data;
+            msr_entries[i][0] = entry.index as u64;
+        }
+        write!(f, "Number of MSRs: {}: MSRs: {:#010X?}, -- VCPU Events: {:?} -- Standard registers: {:?} Special Registers: {:?} ---- Floating Point Unit: {:?} --- Extended Control Register: {:?} --- Local APIC: {:?} --- DBG: {:?} --- Xsave: {:?}",
+                msr_entries.len(),
+                msr_entries,
+                self.vcpu_events,
+                self.regs,
+                self.sregs,
+                self.fpu,
+                self.xcrs,
+                self.lapic,
+                self.dbg,
+                self.xsave,
+        )
+    }
+}
+
 pub struct CreateDevice {}
 pub struct DeviceAttr {}
 pub struct IrqRouting {}
@@ -118,5 +143,7 @@ pub fn boot_msr_entries() -> MsrEntries {
         msr!(msr_index::MSR_KERNEL_GS_BASE),
         msr!(msr_index::MSR_SYSCALL_MASK),
         msr!(msr_index::MSR_IA32_TSC),
+        msr_data!(msr_index::MSR_MTRRdefType, MTRR_ENABLE | MTRR_MEM_TYPE_WB),
     ])
+    .unwrap()
 }

hypervisor/src/vm.rs

@@ -12,6 +12,8 @@
 use crate::aarch64::VcpuInit;
 use crate::cpu::Vcpu;
 use crate::device::Device;
+#[cfg(feature = "tdx")]
+use crate::x86_64::CpuId;
 #[cfg(all(feature = "kvm", target_arch = "x86_64"))]
 use crate::ClockData;
 #[cfg(feature = "kvm")]
@@ -23,6 +25,8 @@ use crate::KvmVmState as VmState;
 use crate::{IoEventAddress, IrqRoutingEntry, MemoryRegion};
 #[cfg(feature = "kvm")]
 use kvm_ioctls::Cap;
+#[cfg(target_arch = "x86_64")]
+use std::fs::File;
 use std::sync::Arc;
 use thiserror::Error;
 use vmm_sys_util::eventfd::EventFd;
@@ -36,9 +40,9 @@ pub enum DataMatch {
     DataMatch64(u64),
 }
 
-impl Into<u64> for DataMatch {
-    fn into(self) -> u64 {
-        match self {
+impl From<DataMatch> for u64 {
+    fn from(dm: DataMatch) -> u64 {
+        match dm {
             DataMatch::DataMatch32(dm) => dm.into(),
             DataMatch::DataMatch64(dm) => dm,
         }
@@ -90,10 +94,15 @@ pub enum HypervisorVmError {
     #[error("Failed to set GSI routing: {0}")]
     SetGsiRouting(#[source] anyhow::Error),
     ///
-    /// Set user memory error
+    /// Create user memory error
     ///
-    #[error("Failed to set user memory: {0}")]
-    SetUserMemory(#[source] anyhow::Error),
+    #[error("Failed to create user memory: {0}")]
+    CreateUserMemory(#[source] anyhow::Error),
+    ///
+    /// Remove user memory region error
+    ///
+    #[error("Failed to remove user memory: {0}")]
+    RemoveUserMemory(#[source] anyhow::Error),
     ///
     /// Create device error
     ///
@@ -110,6 +119,11 @@ pub enum HypervisorVmError {
     #[error("Failed to enable split Irq: {0}")]
     EnableSplitIrq(#[source] anyhow::Error),
     ///
+    /// Enable SGX attribute error
+    ///
+    #[error("Failed to enable SGX attribute: {0}")]
+    EnableSgxAttribute(#[source] anyhow::Error),
+    ///
     /// Get clock error
     ///
     #[error("Failed to get clock: {0}")]
@@ -163,6 +177,25 @@ pub enum HypervisorVmError {
     ///
     #[error("Failed to assert virtual Interrupt: {0}")]
     AsserttVirtualInterrupt(#[source] anyhow::Error),
+
+    #[cfg(feature = "tdx")]
+    ///
+    /// Error initializing TDX on the VM
+    ///
+    #[error("Failed to initialize TDX: {0}")]
+    InitializeTdx(#[source] std::io::Error),
+    #[cfg(feature = "tdx")]
+    ///
+    /// Error finalizing the TDX configuration on the VM
+    ///
+    #[error("Failed to finalize TDX: {0}")]
+    FinalizeTdx(#[source] std::io::Error),
+    #[cfg(feature = "tdx")]
+    ///
+    /// Error initializing the TDX memory region
+    ///
+    #[error("Failed to initialize memory region TDX: {0}")]
+    InitMemRegionTdx(#[source] std::io::Error),
 }
 ///
 /// Result type for returning from a function
@@ -197,7 +230,7 @@ pub trait Vm: Send + Sync {
     fn unregister_ioevent(&self, fd: &EventFd, addr: &IoEventAddress) -> Result<()>;
     /// Sets the GSI routing table entries, overwriting any previously set
     fn set_gsi_routing(&self, entries: &[IrqRoutingEntry]) -> Result<()>;
-    /// Creates a memory region structure that can be used with set_user_memory_region
+    /// Creates a memory region structure that can be used with {create/remove}_user_memory_region
     fn make_user_memory_region(
         &self,
         slot: u32,
@@ -207,8 +240,10 @@ pub trait Vm: Send + Sync {
         readonly: bool,
         log_dirty_pages: bool,
     ) -> MemoryRegion;
-    /// Creates/modifies a guest physical memory slot.
-    fn set_user_memory_region(&self, user_memory_region: MemoryRegion) -> Result<()>;
+    /// Creates a guest physical memory slot.
+    fn create_user_memory_region(&self, user_memory_region: MemoryRegion) -> Result<()>;
+    /// Removes a guest physical memory slot.
+    fn remove_user_memory_region(&self, user_memory_region: MemoryRegion) -> Result<()>;
     #[cfg(feature = "kvm")]
     /// Creates an emulated device in the kernel.
     fn create_device(&self, device: &mut CreateDevice) -> Result<Arc<dyn Device>>;
@@ -218,6 +253,8 @@ pub trait Vm: Send + Sync {
     /// Enable split Irq capability
     #[cfg(target_arch = "x86_64")]
     fn enable_split_irq(&self) -> Result<()>;
+    #[cfg(target_arch = "x86_64")]
+    fn enable_sgx_attribute(&self, file: File) -> Result<()>;
     /// Retrieve guest clock.
     #[cfg(all(feature = "kvm", target_arch = "x86_64"))]
     fn get_clock(&self) -> Result<ClockData>;
@@ -235,6 +272,21 @@ pub trait Vm: Send + Sync {
     fn set_state(&self, state: VmState) -> Result<()>;
     /// Get dirty pages bitmap
     fn get_dirty_log(&self, slot: u32, memory_size: u64) -> Result<Vec<u64>>;
+    #[cfg(feature = "tdx")]
+    /// Initalize TDX on this VM
+    fn tdx_init(&self, cpuid: &CpuId, max_vcpus: u32) -> Result<()>;
+    #[cfg(feature = "tdx")]
+    /// Finalize the configuration of TDX on this VM
+    fn tdx_finalize(&self) -> Result<()>;
+    #[cfg(feature = "tdx")]
+    /// Initalize a TDX memory region for this VM
+    fn tdx_init_memory_region(
+        &self,
+        host_address: u64,
+        guest_address: u64,
+        size: u64,
+        measure: bool,
+    ) -> Result<()>;
 }
 
 pub trait VmmOps: Send + Sync {

net_gen/Cargo.toml

@@ -2,6 +2,7 @@
 name = "net_gen"
 version = "0.1.0"
 authors = ["The Chromium OS Authors"]
+edition = "2018"
 
 [dependencies]
 vmm-sys-util = ">=0.3.1"

net_gen/src/if_tun.rs

@@ -1,24 +1,27 @@
-// Copyright 2017 The Chromium OS Authors. All rights reserved.
-// Use of this source code is governed by a BSD-style license that can be
-// found in the THIRD-PARTY file.
+// Copyright © 2021 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0
+//
 
-/* automatically generated by rust-bindgen */
+// bindgen /usr/include/linux/if_tun.h --no-layout-tests
+
+/* automatically generated by rust-bindgen 0.58.1 */
 
 #[repr(C)]
 #[derive(Default)]
-pub struct __IncompleteArrayField<T>(::std::marker::PhantomData<T>);
+pub struct __IncompleteArrayField<T>(::std::marker::PhantomData<T>, [T; 0]);
 impl<T> __IncompleteArrayField<T> {
     #[inline]
-    pub fn new() -> Self {
-        __IncompleteArrayField(::std::marker::PhantomData)
+    pub const fn new() -> Self {
+        __IncompleteArrayField(::std::marker::PhantomData, [])
     }
     #[inline]
-    pub unsafe fn as_ptr(&self) -> *const T {
-        ::std::mem::transmute(self)
+    pub fn as_ptr(&self) -> *const T {
+        self as *const _ as *const T
     }
     #[inline]
-    pub unsafe fn as_mut_ptr(&mut self) -> *mut T {
-        ::std::mem::transmute(self)
+    pub fn as_mut_ptr(&mut self) -> *mut T {
+        self as *mut _ as *mut T
     }
     #[inline]
     pub unsafe fn as_slice(&self, len: usize) -> &[T] {
@@ -30,191 +33,203 @@ impl<T> __IncompleteArrayField<T> {
     }
 }
 impl<T> ::std::fmt::Debug for __IncompleteArrayField<T> {
-    fn fmt(&self, fmt: &mut ::std::fmt::Formatter) -> ::std::fmt::Result {
+    fn fmt(&self, fmt: &mut ::std::fmt::Formatter<'_>) -> ::std::fmt::Result {
         fmt.write_str("__IncompleteArrayField")
     }
 }
-impl<T> ::std::clone::Clone for __IncompleteArrayField<T> {
-    #[inline]
-    fn clone(&self) -> Self {
-        Self::new()
-    }
-}
-impl<T> ::std::marker::Copy for __IncompleteArrayField<T> {}
-pub const __BITS_PER_LONG: ::std::os::raw::c_uint = 64;
-pub const __FD_SETSIZE: ::std::os::raw::c_uint = 1024;
-pub const ETH_ALEN: ::std::os::raw::c_uint = 6;
-pub const ETH_HLEN: ::std::os::raw::c_uint = 14;
-pub const ETH_ZLEN: ::std::os::raw::c_uint = 60;
-pub const ETH_DATA_LEN: ::std::os::raw::c_uint = 1500;
-pub const ETH_FRAME_LEN: ::std::os::raw::c_uint = 1514;
-pub const ETH_FCS_LEN: ::std::os::raw::c_uint = 4;
-pub const ETH_P_LOOP: ::std::os::raw::c_uint = 96;
-pub const ETH_P_PUP: ::std::os::raw::c_uint = 512;
-pub const ETH_P_PUPAT: ::std::os::raw::c_uint = 513;
-pub const ETH_P_TSN: ::std::os::raw::c_uint = 8944;
-pub const ETH_P_IP: ::std::os::raw::c_uint = 2048;
-pub const ETH_P_X25: ::std::os::raw::c_uint = 2053;
-pub const ETH_P_ARP: ::std::os::raw::c_uint = 2054;
-pub const ETH_P_BPQ: ::std::os::raw::c_uint = 2303;
-pub const ETH_P_IEEEPUP: ::std::os::raw::c_uint = 2560;
-pub const ETH_P_IEEEPUPAT: ::std::os::raw::c_uint = 2561;
-pub const ETH_P_BATMAN: ::std::os::raw::c_uint = 17157;
-pub const ETH_P_DEC: ::std::os::raw::c_uint = 24576;
-pub const ETH_P_DNA_DL: ::std::os::raw::c_uint = 24577;
-pub const ETH_P_DNA_RC: ::std::os::raw::c_uint = 24578;
-pub const ETH_P_DNA_RT: ::std::os::raw::c_uint = 24579;
-pub const ETH_P_LAT: ::std::os::raw::c_uint = 24580;
-pub const ETH_P_DIAG: ::std::os::raw::c_uint = 24581;
-pub const ETH_P_CUST: ::std::os::raw::c_uint = 24582;
-pub const ETH_P_SCA: ::std::os::raw::c_uint = 24583;
-pub const ETH_P_TEB: ::std::os::raw::c_uint = 25944;
-pub const ETH_P_RARP: ::std::os::raw::c_uint = 32821;
-pub const ETH_P_ATALK: ::std::os::raw::c_uint = 32923;
-pub const ETH_P_AARP: ::std::os::raw::c_uint = 33011;
-pub const ETH_P_8021Q: ::std::os::raw::c_uint = 33024;
-pub const ETH_P_IPX: ::std::os::raw::c_uint = 33079;
-pub const ETH_P_IPV6: ::std::os::raw::c_uint = 34525;
-pub const ETH_P_PAUSE: ::std::os::raw::c_uint = 34824;
-pub const ETH_P_SLOW: ::std::os::raw::c_uint = 34825;
-pub const ETH_P_WCCP: ::std::os::raw::c_uint = 34878;
-pub const ETH_P_MPLS_UC: ::std::os::raw::c_uint = 34887;
-pub const ETH_P_MPLS_MC: ::std::os::raw::c_uint = 34888;
-pub const ETH_P_ATMMPOA: ::std::os::raw::c_uint = 34892;
-pub const ETH_P_PPP_DISC: ::std::os::raw::c_uint = 34915;
-pub const ETH_P_PPP_SES: ::std::os::raw::c_uint = 34916;
-pub const ETH_P_LINK_CTL: ::std::os::raw::c_uint = 34924;
-pub const ETH_P_ATMFATE: ::std::os::raw::c_uint = 34948;
-pub const ETH_P_PAE: ::std::os::raw::c_uint = 34958;
-pub const ETH_P_AOE: ::std::os::raw::c_uint = 34978;
-pub const ETH_P_8021AD: ::std::os::raw::c_uint = 34984;
-pub const ETH_P_802_EX1: ::std::os::raw::c_uint = 34997;
-pub const ETH_P_TIPC: ::std::os::raw::c_uint = 35018;
-pub const ETH_P_8021AH: ::std::os::raw::c_uint = 35047;
-pub const ETH_P_MVRP: ::std::os::raw::c_uint = 35061;
-pub const ETH_P_1588: ::std::os::raw::c_uint = 35063;
-pub const ETH_P_PRP: ::std::os::raw::c_uint = 35067;
-pub const ETH_P_FCOE: ::std::os::raw::c_uint = 35078;
-pub const ETH_P_TDLS: ::std::os::raw::c_uint = 35085;
-pub const ETH_P_FIP: ::std::os::raw::c_uint = 35092;
-pub const ETH_P_80221: ::std::os::raw::c_uint = 35095;
-pub const ETH_P_LOOPBACK: ::std::os::raw::c_uint = 36864;
-pub const ETH_P_QINQ1: ::std::os::raw::c_uint = 37120;
-pub const ETH_P_QINQ2: ::std::os::raw::c_uint = 37376;
-pub const ETH_P_QINQ3: ::std::os::raw::c_uint = 37632;
-pub const ETH_P_EDSA: ::std::os::raw::c_uint = 56026;
-pub const ETH_P_AF_IUCV: ::std::os::raw::c_uint = 64507;
-pub const ETH_P_802_3_MIN: ::std::os::raw::c_uint = 1536;
-pub const ETH_P_802_3: ::std::os::raw::c_uint = 1;
-pub const ETH_P_AX25: ::std::os::raw::c_uint = 2;
-pub const ETH_P_ALL: ::std::os::raw::c_uint = 3;
-pub const ETH_P_802_2: ::std::os::raw::c_uint = 4;
-pub const ETH_P_SNAP: ::std::os::raw::c_uint = 5;
-pub const ETH_P_DDCMP: ::std::os::raw::c_uint = 6;
-pub const ETH_P_WAN_PPP: ::std::os::raw::c_uint = 7;
-pub const ETH_P_PPP_MP: ::std::os::raw::c_uint = 8;
-pub const ETH_P_LOCALTALK: ::std::os::raw::c_uint = 9;
-pub const ETH_P_CAN: ::std::os::raw::c_uint = 12;
-pub const ETH_P_CANFD: ::std::os::raw::c_uint = 13;
-pub const ETH_P_PPPTALK: ::std::os::raw::c_uint = 16;
-pub const ETH_P_TR_802_2: ::std::os::raw::c_uint = 17;
-pub const ETH_P_MOBITEX: ::std::os::raw::c_uint = 21;
-pub const ETH_P_CONTROL: ::std::os::raw::c_uint = 22;
-pub const ETH_P_IRDA: ::std::os::raw::c_uint = 23;
-pub const ETH_P_ECONET: ::std::os::raw::c_uint = 24;
-pub const ETH_P_HDLC: ::std::os::raw::c_uint = 25;
-pub const ETH_P_ARCNET: ::std::os::raw::c_uint = 26;
-pub const ETH_P_DSA: ::std::os::raw::c_uint = 27;
-pub const ETH_P_TRAILER: ::std::os::raw::c_uint = 28;
-pub const ETH_P_PHONET: ::std::os::raw::c_uint = 245;
-pub const ETH_P_IEEE802154: ::std::os::raw::c_uint = 246;
-pub const ETH_P_CAIF: ::std::os::raw::c_uint = 247;
-pub const ETH_P_XDSA: ::std::os::raw::c_uint = 248;
-pub const BPF_LD: ::std::os::raw::c_uint = 0;
-pub const BPF_LDX: ::std::os::raw::c_uint = 1;
-pub const BPF_ST: ::std::os::raw::c_uint = 2;
-pub const BPF_STX: ::std::os::raw::c_uint = 3;
-pub const BPF_ALU: ::std::os::raw::c_uint = 4;
-pub const BPF_JMP: ::std::os::raw::c_uint = 5;
-pub const BPF_RET: ::std::os::raw::c_uint = 6;
-pub const BPF_MISC: ::std::os::raw::c_uint = 7;
-pub const BPF_W: ::std::os::raw::c_uint = 0;
-pub const BPF_H: ::std::os::raw::c_uint = 8;
-pub const BPF_B: ::std::os::raw::c_uint = 16;
-pub const BPF_IMM: ::std::os::raw::c_uint = 0;
-pub const BPF_ABS: ::std::os::raw::c_uint = 32;
-pub const BPF_IND: ::std::os::raw::c_uint = 64;
-pub const BPF_MEM: ::std::os::raw::c_uint = 96;
-pub const BPF_LEN: ::std::os::raw::c_uint = 128;
-pub const BPF_MSH: ::std::os::raw::c_uint = 160;
-pub const BPF_ADD: ::std::os::raw::c_uint = 0;
-pub const BPF_SUB: ::std::os::raw::c_uint = 16;
-pub const BPF_MUL: ::std::os::raw::c_uint = 32;
-pub const BPF_DIV: ::std::os::raw::c_uint = 48;
-pub const BPF_OR: ::std::os::raw::c_uint = 64;
-pub const BPF_AND: ::std::os::raw::c_uint = 80;
-pub const BPF_LSH: ::std::os::raw::c_uint = 96;
-pub const BPF_RSH: ::std::os::raw::c_uint = 112;
-pub const BPF_NEG: ::std::os::raw::c_uint = 128;
-pub const BPF_MOD: ::std::os::raw::c_uint = 144;
-pub const BPF_XOR: ::std::os::raw::c_uint = 160;
-pub const BPF_JA: ::std::os::raw::c_uint = 0;
-pub const BPF_JEQ: ::std::os::raw::c_uint = 16;
-pub const BPF_JGT: ::std::os::raw::c_uint = 32;
-pub const BPF_JGE: ::std::os::raw::c_uint = 48;
-pub const BPF_JSET: ::std::os::raw::c_uint = 64;
-pub const BPF_K: ::std::os::raw::c_uint = 0;
-pub const BPF_X: ::std::os::raw::c_uint = 8;
-pub const BPF_MAXINSNS: ::std::os::raw::c_uint = 4096;
-pub const BPF_MAJOR_VERSION: ::std::os::raw::c_uint = 1;
-pub const BPF_MINOR_VERSION: ::std::os::raw::c_uint = 1;
-pub const BPF_A: ::std::os::raw::c_uint = 16;
-pub const BPF_TAX: ::std::os::raw::c_uint = 0;
-pub const BPF_TXA: ::std::os::raw::c_uint = 128;
-pub const BPF_MEMWORDS: ::std::os::raw::c_uint = 16;
-pub const SKF_AD_OFF: ::std::os::raw::c_int = -4096;
-pub const SKF_AD_PROTOCOL: ::std::os::raw::c_uint = 0;
-pub const SKF_AD_PKTTYPE: ::std::os::raw::c_uint = 4;
-pub const SKF_AD_IFINDEX: ::std::os::raw::c_uint = 8;
-pub const SKF_AD_NLATTR: ::std::os::raw::c_uint = 12;
-pub const SKF_AD_NLATTR_NEST: ::std::os::raw::c_uint = 16;
-pub const SKF_AD_MARK: ::std::os::raw::c_uint = 20;
-pub const SKF_AD_QUEUE: ::std::os::raw::c_uint = 24;
-pub const SKF_AD_HATYPE: ::std::os::raw::c_uint = 28;
-pub const SKF_AD_RXHASH: ::std::os::raw::c_uint = 32;
-pub const SKF_AD_CPU: ::std::os::raw::c_uint = 36;
-pub const SKF_AD_ALU_XOR_X: ::std::os::raw::c_uint = 40;
-pub const SKF_AD_VLAN_TAG: ::std::os::raw::c_uint = 44;
-pub const SKF_AD_VLAN_TAG_PRESENT: ::std::os::raw::c_uint = 48;
-pub const SKF_AD_PAY_OFFSET: ::std::os::raw::c_uint = 52;
-pub const SKF_AD_RANDOM: ::std::os::raw::c_uint = 56;
-pub const SKF_AD_VLAN_TPID: ::std::os::raw::c_uint = 60;
-pub const SKF_AD_MAX: ::std::os::raw::c_uint = 64;
-pub const SKF_NET_OFF: ::std::os::raw::c_int = -1048576;
-pub const SKF_LL_OFF: ::std::os::raw::c_int = -2097152;
-pub const BPF_NET_OFF: ::std::os::raw::c_int = -1048576;
-pub const BPF_LL_OFF: ::std::os::raw::c_int = -2097152;
-pub const TUN_READQ_SIZE: ::std::os::raw::c_uint = 500;
-pub const TUN_TYPE_MASK: ::std::os::raw::c_uint = 15;
-pub const IFF_TUN: ::std::os::raw::c_uint = 1;
-pub const IFF_TAP: ::std::os::raw::c_uint = 2;
-pub const IFF_NO_PI: ::std::os::raw::c_uint = 4096;
-pub const IFF_ONE_QUEUE: ::std::os::raw::c_uint = 8192;
-pub const IFF_VNET_HDR: ::std::os::raw::c_uint = 16384;
-pub const IFF_TUN_EXCL: ::std::os::raw::c_uint = 32768;
-pub const IFF_MULTI_QUEUE: ::std::os::raw::c_uint = 256;
-pub const IFF_ATTACH_QUEUE: ::std::os::raw::c_uint = 512;
-pub const IFF_DETACH_QUEUE: ::std::os::raw::c_uint = 1024;
-pub const IFF_PERSIST: ::std::os::raw::c_uint = 2048;
-pub const IFF_NOFILTER: ::std::os::raw::c_uint = 4096;
-pub const TUN_TX_TIMESTAMP: ::std::os::raw::c_uint = 1;
-pub const TUN_F_CSUM: ::std::os::raw::c_uint = 1;
-pub const TUN_F_TSO4: ::std::os::raw::c_uint = 2;
-pub const TUN_F_TSO6: ::std::os::raw::c_uint = 4;
-pub const TUN_F_TSO_ECN: ::std::os::raw::c_uint = 8;
-pub const TUN_F_UFO: ::std::os::raw::c_uint = 16;
-pub const TUN_PKT_STRIP: ::std::os::raw::c_uint = 1;
-pub const TUN_FLT_ALLMULTI: ::std::os::raw::c_uint = 1;
+pub const __BITS_PER_LONG: u32 = 64;
+pub const __FD_SETSIZE: u32 = 1024;
+pub const ETH_ALEN: u32 = 6;
+pub const ETH_TLEN: u32 = 2;
+pub const ETH_HLEN: u32 = 14;
+pub const ETH_ZLEN: u32 = 60;
+pub const ETH_DATA_LEN: u32 = 1500;
+pub const ETH_FRAME_LEN: u32 = 1514;
+pub const ETH_FCS_LEN: u32 = 4;
+pub const ETH_MIN_MTU: u32 = 68;
+pub const ETH_MAX_MTU: u32 = 65535;
+pub const ETH_P_LOOP: u32 = 96;
+pub const ETH_P_PUP: u32 = 512;
+pub const ETH_P_PUPAT: u32 = 513;
+pub const ETH_P_TSN: u32 = 8944;
+pub const ETH_P_ERSPAN2: u32 = 8939;
+pub const ETH_P_IP: u32 = 2048;
+pub const ETH_P_X25: u32 = 2053;
+pub const ETH_P_ARP: u32 = 2054;
+pub const ETH_P_BPQ: u32 = 2303;
+pub const ETH_P_IEEEPUP: u32 = 2560;
+pub const ETH_P_IEEEPUPAT: u32 = 2561;
+pub const ETH_P_BATMAN: u32 = 17157;
+pub const ETH_P_DEC: u32 = 24576;
+pub const ETH_P_DNA_DL: u32 = 24577;
+pub const ETH_P_DNA_RC: u32 = 24578;
+pub const ETH_P_DNA_RT: u32 = 24579;
+pub const ETH_P_LAT: u32 = 24580;
+pub const ETH_P_DIAG: u32 = 24581;
+pub const ETH_P_CUST: u32 = 24582;
+pub const ETH_P_SCA: u32 = 24583;
+pub const ETH_P_TEB: u32 = 25944;
+pub const ETH_P_RARP: u32 = 32821;
+pub const ETH_P_ATALK: u32 = 32923;
+pub const ETH_P_AARP: u32 = 33011;
+pub const ETH_P_8021Q: u32 = 33024;
+pub const ETH_P_ERSPAN: u32 = 35006;
+pub const ETH_P_IPX: u32 = 33079;
+pub const ETH_P_IPV6: u32 = 34525;
+pub const ETH_P_PAUSE: u32 = 34824;
+pub const ETH_P_SLOW: u32 = 34825;
+pub const ETH_P_WCCP: u32 = 34878;
+pub const ETH_P_MPLS_UC: u32 = 34887;
+pub const ETH_P_MPLS_MC: u32 = 34888;
+pub const ETH_P_ATMMPOA: u32 = 34892;
+pub const ETH_P_PPP_DISC: u32 = 34915;
+pub const ETH_P_PPP_SES: u32 = 34916;
+pub const ETH_P_LINK_CTL: u32 = 34924;
+pub const ETH_P_ATMFATE: u32 = 34948;
+pub const ETH_P_PAE: u32 = 34958;
+pub const ETH_P_AOE: u32 = 34978;
+pub const ETH_P_8021AD: u32 = 34984;
+pub const ETH_P_802_EX1: u32 = 34997;
+pub const ETH_P_PREAUTH: u32 = 35015;
+pub const ETH_P_TIPC: u32 = 35018;
+pub const ETH_P_LLDP: u32 = 35020;
+pub const ETH_P_MRP: u32 = 35043;
+pub const ETH_P_MACSEC: u32 = 35045;
+pub const ETH_P_8021AH: u32 = 35047;
+pub const ETH_P_MVRP: u32 = 35061;
+pub const ETH_P_1588: u32 = 35063;
+pub const ETH_P_NCSI: u32 = 35064;
+pub const ETH_P_PRP: u32 = 35067;
+pub const ETH_P_FCOE: u32 = 35078;
+pub const ETH_P_IBOE: u32 = 35093;
+pub const ETH_P_TDLS: u32 = 35085;
+pub const ETH_P_FIP: u32 = 35092;
+pub const ETH_P_80221: u32 = 35095;
+pub const ETH_P_HSR: u32 = 35119;
+pub const ETH_P_NSH: u32 = 35151;
+pub const ETH_P_LOOPBACK: u32 = 36864;
+pub const ETH_P_QINQ1: u32 = 37120;
+pub const ETH_P_QINQ2: u32 = 37376;
+pub const ETH_P_QINQ3: u32 = 37632;
+pub const ETH_P_EDSA: u32 = 56026;
+pub const ETH_P_DSA_8021Q: u32 = 56027;
+pub const ETH_P_IFE: u32 = 60734;
+pub const ETH_P_AF_IUCV: u32 = 64507;
+pub const ETH_P_802_3_MIN: u32 = 1536;
+pub const ETH_P_802_3: u32 = 1;
+pub const ETH_P_AX25: u32 = 2;
+pub const ETH_P_ALL: u32 = 3;
+pub const ETH_P_802_2: u32 = 4;
+pub const ETH_P_SNAP: u32 = 5;
+pub const ETH_P_DDCMP: u32 = 6;
+pub const ETH_P_WAN_PPP: u32 = 7;
+pub const ETH_P_PPP_MP: u32 = 8;
+pub const ETH_P_LOCALTALK: u32 = 9;
+pub const ETH_P_CAN: u32 = 12;
+pub const ETH_P_CANFD: u32 = 13;
+pub const ETH_P_PPPTALK: u32 = 16;
+pub const ETH_P_TR_802_2: u32 = 17;
+pub const ETH_P_MOBITEX: u32 = 21;
+pub const ETH_P_CONTROL: u32 = 22;
+pub const ETH_P_IRDA: u32 = 23;
+pub const ETH_P_ECONET: u32 = 24;
+pub const ETH_P_HDLC: u32 = 25;
+pub const ETH_P_ARCNET: u32 = 26;
+pub const ETH_P_DSA: u32 = 27;
+pub const ETH_P_TRAILER: u32 = 28;
+pub const ETH_P_PHONET: u32 = 245;
+pub const ETH_P_IEEE802154: u32 = 246;
+pub const ETH_P_CAIF: u32 = 247;
+pub const ETH_P_XDSA: u32 = 248;
+pub const ETH_P_MAP: u32 = 249;
+pub const __UAPI_DEF_ETHHDR: u32 = 1;
+pub const BPF_LD: u32 = 0;
+pub const BPF_LDX: u32 = 1;
+pub const BPF_ST: u32 = 2;
+pub const BPF_STX: u32 = 3;
+pub const BPF_ALU: u32 = 4;
+pub const BPF_JMP: u32 = 5;
+pub const BPF_RET: u32 = 6;
+pub const BPF_MISC: u32 = 7;
+pub const BPF_W: u32 = 0;
+pub const BPF_H: u32 = 8;
+pub const BPF_B: u32 = 16;
+pub const BPF_IMM: u32 = 0;
+pub const BPF_ABS: u32 = 32;
+pub const BPF_IND: u32 = 64;
+pub const BPF_MEM: u32 = 96;
+pub const BPF_LEN: u32 = 128;
+pub const BPF_MSH: u32 = 160;
+pub const BPF_ADD: u32 = 0;
+pub const BPF_SUB: u32 = 16;
+pub const BPF_MUL: u32 = 32;
+pub const BPF_DIV: u32 = 48;
+pub const BPF_OR: u32 = 64;
+pub const BPF_AND: u32 = 80;
+pub const BPF_LSH: u32 = 96;
+pub const BPF_RSH: u32 = 112;
+pub const BPF_NEG: u32 = 128;
+pub const BPF_MOD: u32 = 144;
+pub const BPF_XOR: u32 = 160;
+pub const BPF_JA: u32 = 0;
+pub const BPF_JEQ: u32 = 16;
+pub const BPF_JGT: u32 = 32;
+pub const BPF_JGE: u32 = 48;
+pub const BPF_JSET: u32 = 64;
+pub const BPF_K: u32 = 0;
+pub const BPF_X: u32 = 8;
+pub const BPF_MAXINSNS: u32 = 4096;
+pub const BPF_MAJOR_VERSION: u32 = 1;
+pub const BPF_MINOR_VERSION: u32 = 1;
+pub const BPF_A: u32 = 16;
+pub const BPF_TAX: u32 = 0;
+pub const BPF_TXA: u32 = 128;
+pub const BPF_MEMWORDS: u32 = 16;
+pub const SKF_AD_OFF: i32 = -4096;
+pub const SKF_AD_PROTOCOL: u32 = 0;
+pub const SKF_AD_PKTTYPE: u32 = 4;
+pub const SKF_AD_IFINDEX: u32 = 8;
+pub const SKF_AD_NLATTR: u32 = 12;
+pub const SKF_AD_NLATTR_NEST: u32 = 16;
+pub const SKF_AD_MARK: u32 = 20;
+pub const SKF_AD_QUEUE: u32 = 24;
+pub const SKF_AD_HATYPE: u32 = 28;
+pub const SKF_AD_RXHASH: u32 = 32;
+pub const SKF_AD_CPU: u32 = 36;
+pub const SKF_AD_ALU_XOR_X: u32 = 40;
+pub const SKF_AD_VLAN_TAG: u32 = 44;
+pub const SKF_AD_VLAN_TAG_PRESENT: u32 = 48;
+pub const SKF_AD_PAY_OFFSET: u32 = 52;
+pub const SKF_AD_RANDOM: u32 = 56;
+pub const SKF_AD_VLAN_TPID: u32 = 60;
+pub const SKF_AD_MAX: u32 = 64;
+pub const SKF_NET_OFF: i32 = -1048576;
+pub const SKF_LL_OFF: i32 = -2097152;
+pub const BPF_NET_OFF: i32 = -1048576;
+pub const BPF_LL_OFF: i32 = -2097152;
+pub const TUN_READQ_SIZE: u32 = 500;
+pub const TUN_TYPE_MASK: u32 = 15;
+pub const IFF_TUN: u32 = 1;
+pub const IFF_TAP: u32 = 2;
+pub const IFF_NAPI: u32 = 16;
+pub const IFF_NAPI_FRAGS: u32 = 32;
+pub const IFF_NO_PI: u32 = 4096;
+pub const IFF_ONE_QUEUE: u32 = 8192;
+pub const IFF_VNET_HDR: u32 = 16384;
+pub const IFF_TUN_EXCL: u32 = 32768;
+pub const IFF_MULTI_QUEUE: u32 = 256;
+pub const IFF_ATTACH_QUEUE: u32 = 512;
+pub const IFF_DETACH_QUEUE: u32 = 1024;
+pub const IFF_PERSIST: u32 = 2048;
+pub const IFF_NOFILTER: u32 = 4096;
+pub const TUN_TX_TIMESTAMP: u32 = 1;
+pub const TUN_F_CSUM: u32 = 1;
+pub const TUN_F_TSO4: u32 = 2;
+pub const TUN_F_TSO6: u32 = 4;
+pub const TUN_F_TSO_ECN: u32 = 8;
+pub const TUN_F_UFO: u32 = 16;
+pub const TUN_PKT_STRIP: u32 = 1;
+pub const TUN_FLT_ALLMULTI: u32 = 1;
 pub type __s8 = ::std::os::raw::c_schar;
 pub type __u8 = ::std::os::raw::c_uchar;
 pub type __s16 = ::std::os::raw::c_short;
@@ -224,38 +239,10 @@ pub type __u32 = ::std::os::raw::c_uint;
 pub type __s64 = ::std::os::raw::c_longlong;
 pub type __u64 = ::std::os::raw::c_ulonglong;
 #[repr(C)]
-#[derive(Debug, Default, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct __kernel_fd_set {
     pub fds_bits: [::std::os::raw::c_ulong; 16usize],
 }
-#[test]
-fn bindgen_test_layout___kernel_fd_set() {
-    assert_eq!(
-        ::std::mem::size_of::<__kernel_fd_set>(),
-        128usize,
-        concat!("Size of: ", stringify!(__kernel_fd_set))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<__kernel_fd_set>(),
-        8usize,
-        concat!("Alignment of ", stringify!(__kernel_fd_set))
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const __kernel_fd_set)).fds_bits as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(__kernel_fd_set),
-            "::",
-            stringify!(fds_bits)
-        )
-    );
-}
-impl Clone for __kernel_fd_set {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 pub type __kernel_sighandler_t =
     ::std::option::Option<unsafe extern "C" fn(arg1: ::std::os::raw::c_int)>;
 pub type __kernel_key_t = ::std::os::raw::c_int;
@@ -279,41 +266,15 @@ pub type __kernel_size_t = __kernel_ulong_t;
 pub type __kernel_ssize_t = __kernel_long_t;
 pub type __kernel_ptrdiff_t = __kernel_long_t;
 #[repr(C)]
-#[derive(Debug, Default, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct __kernel_fsid_t {
     pub val: [::std::os::raw::c_int; 2usize],
 }
-#[test]
-fn bindgen_test_layout___kernel_fsid_t() {
-    assert_eq!(
-        ::std::mem::size_of::<__kernel_fsid_t>(),
-        8usize,
-        concat!("Size of: ", stringify!(__kernel_fsid_t))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<__kernel_fsid_t>(),
-        4usize,
-        concat!("Alignment of ", stringify!(__kernel_fsid_t))
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const __kernel_fsid_t)).val as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(__kernel_fsid_t),
-            "::",
-            stringify!(val)
-        )
-    );
-}
-impl Clone for __kernel_fsid_t {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 pub type __kernel_off_t = __kernel_long_t;
 pub type __kernel_loff_t = ::std::os::raw::c_longlong;
+pub type __kernel_old_time_t = __kernel_long_t;
 pub type __kernel_time_t = __kernel_long_t;
+pub type __kernel_time64_t = ::std::os::raw::c_longlong;
 pub type __kernel_clock_t = __kernel_long_t;
 pub type __kernel_timer_t = ::std::os::raw::c_int;
 pub type __kernel_clockid_t = ::std::os::raw::c_int;
@@ -328,272 +289,38 @@ pub type __le64 = __u64;
 pub type __be64 = __u64;
 pub type __sum16 = __u16;
 pub type __wsum = __u32;
+pub type __poll_t = ::std::os::raw::c_uint;
 #[repr(C, packed)]
-#[derive(Debug, Default, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct ethhdr {
     pub h_dest: [::std::os::raw::c_uchar; 6usize],
     pub h_source: [::std::os::raw::c_uchar; 6usize],
     pub h_proto: __be16,
 }
-#[test]
-fn bindgen_test_layout_ethhdr() {
-    assert_eq!(
-        ::std::mem::size_of::<ethhdr>(),
-        14usize,
-        concat!("Size of: ", stringify!(ethhdr))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<ethhdr>(),
-        1usize,
-        concat!("Alignment of ", stringify!(ethhdr))
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const ethhdr)).h_dest as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(ethhdr),
-            "::",
-            stringify!(h_dest)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const ethhdr)).h_source as *const _ as usize },
-        6usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(ethhdr),
-            "::",
-            stringify!(h_source)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const ethhdr)).h_proto as *const _ as usize },
-        12usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(ethhdr),
-            "::",
-            stringify!(h_proto)
-        )
-    );
-}
-impl Clone for ethhdr {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[repr(C)]
-#[derive(Debug, Default, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct sock_filter {
     pub code: __u16,
     pub jt: __u8,
     pub jf: __u8,
     pub k: __u32,
 }
-#[test]
-fn bindgen_test_layout_sock_filter() {
-    assert_eq!(
-        ::std::mem::size_of::<sock_filter>(),
-        8usize,
-        concat!("Size of: ", stringify!(sock_filter))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<sock_filter>(),
-        4usize,
-        concat!("Alignment of ", stringify!(sock_filter))
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const sock_filter)).code as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(sock_filter),
-            "::",
-            stringify!(code)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const sock_filter)).jt as *const _ as usize },
-        2usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(sock_filter),
-            "::",
-            stringify!(jt)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const sock_filter)).jf as *const _ as usize },
-        3usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(sock_filter),
-            "::",
-            stringify!(jf)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const sock_filter)).k as *const _ as usize },
-        4usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(sock_filter),
-            "::",
-            stringify!(k)
-        )
-    );
-}
-impl Clone for sock_filter {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct sock_fprog {
     pub len: ::std::os::raw::c_ushort,
     pub filter: *mut sock_filter,
 }
-#[test]
-fn bindgen_test_layout_sock_fprog() {
-    assert_eq!(
-        ::std::mem::size_of::<sock_fprog>(),
-        16usize,
-        concat!("Size of: ", stringify!(sock_fprog))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<sock_fprog>(),
-        8usize,
-        concat!("Alignment of ", stringify!(sock_fprog))
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const sock_fprog)).len as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(sock_fprog),
-            "::",
-            stringify!(len)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const sock_fprog)).filter as *const _ as usize },
-        8usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(sock_fprog),
-            "::",
-            stringify!(filter)
-        )
-    );
-}
-impl Clone for sock_fprog {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
-impl Default for sock_fprog {
-    fn default() -> Self {
-        unsafe { ::std::mem::zeroed() }
-    }
-}
 #[repr(C)]
-#[derive(Debug, Default, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct tun_pi {
     pub flags: __u16,
     pub proto: __be16,
 }
-#[test]
-fn bindgen_test_layout_tun_pi() {
-    assert_eq!(
-        ::std::mem::size_of::<tun_pi>(),
-        4usize,
-        concat!("Size of: ", stringify!(tun_pi))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<tun_pi>(),
-        2usize,
-        concat!("Alignment of ", stringify!(tun_pi))
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const tun_pi)).flags as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(tun_pi),
-            "::",
-            stringify!(flags)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const tun_pi)).proto as *const _ as usize },
-        2usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(tun_pi),
-            "::",
-            stringify!(proto)
-        )
-    );
-}
-impl Clone for tun_pi {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[repr(C)]
-#[derive(Debug, Default, Copy)]
+#[derive(Debug)]
 pub struct tun_filter {
     pub flags: __u16,
     pub count: __u16,
     pub addr: __IncompleteArrayField<[__u8; 6usize]>,
 }
-#[test]
-fn bindgen_test_layout_tun_filter() {
-    assert_eq!(
-        ::std::mem::size_of::<tun_filter>(),
-        4usize,
-        concat!("Size of: ", stringify!(tun_filter))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<tun_filter>(),
-        2usize,
-        concat!("Alignment of ", stringify!(tun_filter))
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const tun_filter)).flags as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(tun_filter),
-            "::",
-            stringify!(flags)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const tun_filter)).count as *const _ as usize },
-        2usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(tun_filter),
-            "::",
-            stringify!(count)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const tun_filter)).addr as *const _ as usize },
-        4usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(tun_filter),
-            "::",
-            stringify!(addr)
-        )
-    );
-}
-impl Clone for tun_filter {
-    fn clone(&self) -> Self {
-        *self
-    }
-}