build, release-notes.md: Document 0.9.0 release

Update release notes and version number for the new release.

Signed-off-by: Rob Bradford <robert.bradford@intel.com>

.github/workflows/build.yaml

@@ -0,0 +1,29 @@
+name: Cloud Hypervisor Build
+on: [pull_request, create]
+
+jobs:
+  build:
+    if: github.event_name == 'pull_request'
+    name: Build
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        rust:
+          - stable
+          - beta
+          - nightly
+        target:
+          - x86_64-unknown-linux-gnu
+          - x86_64-unknown-linux-musl
+    steps:
+      - name: Code checkout
+        uses: actions/checkout@v2
+      - name: Install Rust toolchain (${{ matrix.rust }})
+        uses: actions-rs/toolchain@v1
+        with:
+            toolchain: ${{ matrix.rust }}
+            target: ${{ matrix.target }}
+            override: true
+
+      - name: Build
+        run: cargo build --all --release --target=${{ matrix.target }}

.github/workflows/cross-build.yaml

@@ -0,0 +1,32 @@
+name: Cloud Hypervisor Cross Build
+on: [pull_request, create]
+
+jobs:
+  build:
+    if: github.event_name == 'pull_request'
+    name: Build
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        rust:
+          - stable
+        target:
+          - aarch64-unknown-linux-gnu
+          - aarch64-unknown-linux-musl
+    steps:
+      - name: Code checkout
+        uses: actions/checkout@v2
+      - name: Install Rust toolchain (${{ matrix.rust }})
+        uses: actions-rs/toolchain@v1
+        with:
+            toolchain: ${{ matrix.rust }}
+            target: ${{ matrix.target }}
+            override: true
+      - name: Install arm64 libfdt
+        run: wget http://ftp.us.debian.org/debian/pool/main/d/device-tree-compiler/libfdt-dev_1.6.0-1_arm64.deb && dpkg-deb -xv libfdt-dev_1.6.0-1_arm64.deb ./tlibfdtdev && sudo mkdir /tmmmp && mkdir target && mkdir target/debug && mkdir target/debug/deps && sudo cp ./tlibfdtdev/usr/lib/aarch64-linux-gnu/libfdt.a target/debug/deps/libfdt.a && echo "libfdt installed"
+      - name: Build
+        uses: actions-rs/cargo@v1
+        with:
+          use-cross: true
+          command: build
+          args: --target=${{ matrix.target }} --no-default-features --features "mmio,kvm"

.github/workflows/release.yaml

@@ -0,0 +1,67 @@
+name: Cloud Hypervisor Release
+on: [create]
+
+jobs:
+  release:
+    if: github.event_name == 'create' && github.event.ref_type == 'tag'
+    name: Release
+    runs-on: ubuntu-latest
+    steps:
+      - name: Code checkout
+        uses: actions/checkout@v2
+      - name: Install Rust toolchain (x86_64-unknown-linux-gnu)
+        uses: actions-rs/toolchain@v1
+        with:
+            toolchain: stable
+            target: x86_64-unknown-linux-gnu
+      - name: Install Rust toolchain (x86_64-unknown-linux-musl)
+        uses: actions-rs/toolchain@v1
+        with:
+            toolchain: stable
+            target: x86_64-unknown-linux-musl
+      - name: Build
+        run: cargo build --all --release --target=x86_64-unknown-linux-gnu
+      - name: Static Build
+        run: cargo build --all --release --target=x86_64-unknown-linux-musl
+      - name: Strip cloud-hypervisor binaries
+        run: strip target/*/release/cloud-hypervisor
+      - name: Create Release
+        id: create_release
+        uses: actions/create-release@v1
+        env:
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+        with:
+          tag_name: ${{ github.ref }}
+          release_name: ${{ github.ref }}
+          draft: true
+          prerelease: true
+      - name: Upload cloud-hypervisor
+        id: upload-release-cloud-hypervisor
+        uses: actions/upload-release-asset@v1
+        env:
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+        with:
+          upload_url: ${{ steps.create_release.outputs.upload_url }}
+          asset_path: target/x86_64-unknown-linux-gnu/release/cloud-hypervisor
+          asset_name: cloud-hypervisor
+          asset_content_type: application/octet-stream
+      - name: Upload static cloud-hypervisor
+        id: upload-release-static-cloud-hypervisor
+        uses: actions/upload-release-asset@v1
+        env:
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+        with:
+          upload_url: ${{ steps.create_release.outputs.upload_url }}
+          asset_path: target/x86_64-unknown-linux-musl/release/cloud-hypervisor
+          asset_name: cloud-hypervisor-static
+          asset_content_type: application/octet-stream
+      - name: Upload ch-remote
+        id: upload-release-ch-remote
+        uses: actions/upload-release-asset@v1
+        env:
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+        with:
+          upload_url: ${{ steps.create_release.outputs.upload_url }}
+          asset_path: target/x86_64-unknown-linux-gnu/release/ch-remote
+          asset_name: ch-remote
+          asset_content_type: application/octet-stream

.gitignore

@@ -1,3 +1,4 @@
+/build
 /target
 **/*.rs.bk
 **/Cargo.lock

.rustfmt.toml

@@ -0,0 +1 @@
+edition = "2018"

.travis.yml

@@ -1,16 +0,0 @@
-language: rust
-
-rust:
-  - stable
-
-script:
-  - cargo build --release
-  
-deploy:
-  provider: releases
-  api_key: $GITHUB_OAUTH_TOKEN
-  file: target/release/cloud-hypervisor
-  skip_cleanup: true
-  draft: true
-  on:
-    tags: true

Cargo.toml

@@ -1,50 +1,73 @@
 [package]
 name = "cloud-hypervisor"
-version = "0.4.0"
+version = "0.9.0"
 authors = ["The Cloud Hypervisor Authors"]
 edition = "2018"
 default-run = "cloud-hypervisor"
+build = "build.rs"
+
+[profile.release]
+lto = true
 
 [dependencies]
-clap = "2.33.0"
-epoll = ">=4.0.1"
-lazy_static = "1.4.0"
-libc = "0.2.66"
-log = { version = "0.4.8", features = ["std"] }
-net_gen = { path = "net_gen" }
-net_util = { path = "net_util" }
-qcow = { path = "qcow" }
-vhost_user_backend = { path = "vhost_user_backend"}
-vhost_user_fs = { path = "vhost_user_fs"}
-virtio-bindings = "0.1.0"
+clap = { version = "2.33.2", features = ["wrap_help"] }
+hypervisor = { path = "hypervisor" }
+libc = "0.2.74"
+log = { version = "0.4.11", features = ["std"] }
+seccomp = { git = "https://github.com/firecracker-microvm/firecracker", tag = "v0.22.0" }
+serde_json = "1.0.57"
+vhost_user_block = { path = "vhost_user_block"}
+vhost_user_net = { path = "vhost_user_net"}
 vmm = { path = "vmm" }
-vm-device = { path = "vm-device" }
-vm-memory = { git = "https://github.com/rust-vmm/vm-memory" }
-vmm-sys-util = ">=0.3.1"
-vm-virtio = { path = "vm-virtio" }
+vmm-sys-util = "0.6.1"
+
+[patch.crates-io]
+vm-memory = { git = "https://github.com/cloud-hypervisor/vm-memory", branch = "ch" }
 
 [dev-dependencies]
-ssh2 = "0.6.0"
-dirs = "2.0.2"
+ssh2 = "0.8.2"
+dirs = "3.0.1"
 credibility = "0.1.3"
-tempdir= "0.3.7"
+tempdir = "0.3.7"
 lazy_static= "1.4.0"
-
-[dependencies.vhost_rs]
-path = "vhost_rs"
-features = ["vhost-user-slave"]
+tempfile = "3.1.0"
+serde_json = "1.0.57"
+net_util = { path = "net_util" }
 
 [features]
-default = ["acpi", "pci", "cmos"]
+default = ["acpi", "pci", "cmos", "kvm"]
 acpi = ["vmm/acpi"]
 pci = ["vmm/pci_support"]
 mmio = ["vmm/mmio_support"]
 cmos = ["vmm/cmos"]
+fwdebug = ["vmm/fwdebug"]
+kvm = ["vmm/kvm"]
+io_uring = ["vmm/io_uring"]
 
 # Integration tests require a special environment to run in
 integration_tests = []
 
 [workspace]
 members = [
+    "acpi_tables",
+    "arch",
+    "arch_gen",
+    "block_util",
+    "devices",
+    "hypervisor",
+    "net_gen",
+    "net_util",
+    "option_parser",
+    "pci",
+    "qcow",
     "vhost_user_backend",
+    "vhost_user_block",
+    "vhost_user_fs",
+    "vhost_user_net",
+    "virtio-devices",
+    "vmm",
+    "vm-allocator",
+    "vm-device",
+    "vm-migration",
+    "vm-virtio"
 ]

Jenkinsfile

@@ -1,7 +1,7 @@
 pipeline{
 	agent none
 	stages {
-		stage ('Master build') {
+		stage ('Early checks') {
 			agent { node { label 'master' } }
 			stages {
 				stage ('Check for RFC/WIP builds') {
@@ -14,55 +14,103 @@ pipeline{
 					}
 				}
 				stage ('Cancel older builds') {
+					when { not { branch 'master' } }
 					steps {
 						cancelPreviousBuilds()
 					}
 				}
 			}
 		}
-		stage ('Worker build') {
-			agent { node { label 'bionic' } }
-			options {
-				timeout(time: 1, unit: 'HOURS')
+		stage ('Build') {
+			failFast true
+            parallel {
+				stage ('Master build') {
+					agent { node { label 'master' } }
+					stages {
+						stage ('Checkout') {
+							steps {
+								checkout scm
+							}
+						}
+						stage ('Run Cargo tests') {
+							steps {
+								sh "scripts/dev_cli.sh tests --cargo"
+							}
+						}
+						stage ('Run OpenAPI tests') {
+							steps {
+								sh "scripts/run_openapi_tests.sh"
+							}
+						}
+					}
+				}	
+				stage ('Worker build') {
+					agent { node { label 'bionic' } }
+					options {
+						timeout(time: 1, unit: 'HOURS')
+					}
+					stages {
+						stage ('Checkout') {
+							steps {
+								checkout scm
+							}
+						}
+						stage ('Run unit tests') {
+							steps {
+								sh "scripts/dev_cli.sh tests --unit"
+							}
+						}
+						stage ('Run integration tests') {
+							options {
+								retry(3)
+							}
+							steps {
+								sh "scripts/dev_cli.sh tests --integration"
+							}
+						}
+					}
+				}
+				stage ('Worker build (musl)') {
+					agent { node { label 'bionic' } }
+					options {
+						timeout(time: 1, unit: 'HOURS')
+					}
+					stages {
+						stage ('Checkout') {
+							steps {
+								checkout scm
+							}
+						}
+						stage ('Run unit tests for musl') {
+							steps {
+								sh "scripts/dev_cli.sh tests --unit --libc musl"
+							}
+						}
+						stage ('Run integration tests for musl') {
+							options {
+								retry(3)
+							}
+							steps {
+								sh "scripts/dev_cli.sh tests --integration --libc musl"
+							}
+						}
+					}
+				}
 			}
-			stages {
-				stage ('Checkout') {
-					steps {
-						checkout scm
-					}
+		}
+	}
+	post {
+		regression {
+			script {
+				if (env.BRANCH_NAME == 'master') {
+					slackSend (color: '#ff0000', message: '"master" branch build is now failing')
 				}
-				stage ('Install system packages') {
-					steps {
-						sh "sudo DEBIAN_FRONTEND=noninteractive apt-get install -yq build-essential mtools libssl-dev pkg-config"
-							sh "sudo apt-get install -yq flex bison libelf-dev qemu-utils qemu-system libglib2.0-dev libpixman-1-dev libseccomp-dev libcap-ng-dev socat"
-							sh "sudo snap install docker"
-					}
-				}
-				stage ('Install Rust') {
-					steps {
-						sh "nohup curl https://sh.rustup.rs -sSf | sh -s -- -y"
-					}
-				}
-				stage ('Run Cargo tests') {
-					steps {
-						sh "scripts/run_cargo_tests.sh"
-					}
-				}
-				stage ('Run OpenAPI tests') {
-					steps {
-						sh "scripts/run_openapi_tests.sh"
-					}
-				}
-				stage ('Run unit tests') {
-					steps {
-						sh "scripts/run_unit_tests.sh"
-					}
-				}
-				stage ('Run integration tests') {
-					steps {
-						sh "sudo mount -t tmpfs tmpfs /tmp"
-							sh "scripts/run_integration_tests.sh"
-					}
+			}
+		}
+		fixed {
+			script {
+				if (env.BRANCH_NAME == 'master') {
+					slackSend (color: '#00ff00', message: '"master" branch build is now fixed')
 				}
 			}
 		}

README.md

@@ -19,6 +19,7 @@
 4. [rust-vmm dependency](#4-rust-vmm-dependency)
 	* [Firecracker and crosvm](#firecracker-and-crosvm)
 5. [Community](#5-community)
+	* [Contribute](#contribute)
 	* [Join us](#join-us)
 6. [Security](#6-security)
 
@@ -86,6 +87,34 @@ $ popd
 
 This will build a `cloud-hypervisor` binary under `$CLOUDH/cloud-hypervisor/target/release/cloud-hypervisor`.
 
+### Containerized builds and tests
+
+If you want to build and test Cloud Hypervisor without having to install all the
+required dependencies (The rust toolchain, cargo tools, etc), you can also use
+Cloud Hypervisor's development script: `dev_cli.sh`. Please note that upon its
+first invocation, this script will pull a fairly large container image.
+
+For example, to build the Cloud Hypervisor release binary:
+
+```shell
+$ pushd $CLOUDH
+$ cd cloud-hypervisor
+$ ./scripts/dev_cli.sh build --release
+```
+
+With `dev_cli.sh`, one can also run the Cloud Hypervisor CI locally. This can be
+very convenient for debugging CI errors without having to fully rely on the
+Cloud Hypervisor CI infrastructure.
+
+For example, to run the Cloud Hypervisor unit tests:
+
+```shell
+$ ./scripts/dev_cli.sh tests --unit
+```
+
+Run the `./scripts/dev_cli.sh --help` command to view all the supported
+development script commands and their related options.
+
 ## Run
 
 You can run a guest VM by either using an existing cloud image or booting into your own kernel and disk image.
@@ -99,13 +128,13 @@ Firmware](https://github.com/cloud-hypervisor/rust-hypervisor-firmware) project
 an ELF
 formatted KVM firmware for `cloud-hypervisor` to directly boot into.
 
-We need to get the latest `rust-hypervisor-firmware` release and also a working cloud image. Here we will use a Clear Linux image:
+We need to get the latest `rust-hypervisor-firmware` release and also a working cloud image. Here we will use a Ubuntu image:
 
 ```shell
 $ pushd $CLOUDH
-$ wget https://download.clearlinux.org/releases/31890/clear/clear-31890-kvm.img.xz
-$ unxz clear-31890-kvm.img.xz
-$ wget https://github.com/cloud-hypervisor/rust-hypervisor-firmware/releases/download/0.2.6/hypervisor-fw
+$ wget https://cloud-images.ubuntu.com/focal/current/focal-server-cloudimg-amd64.img
+$ qemu-img convert -p -f qcow2 -O raw focal-server-cloudimg-amd64.img focal-server-cloudimg-amd64.raw
+$ wget https://github.com/cloud-hypervisor/rust-hypervisor-firmware/releases/download/0.2.8/hypervisor-fw
 $ popd
 ```
 
@@ -114,7 +143,7 @@ $ pushd $CLOUDH
 $ sudo setcap cap_net_admin+ep ./cloud-hypervisor/target/release/cloud-hypervisor
 $ ./cloud-hypervisor/target/release/cloud-hypervisor \
 	--kernel ./hypervisor-fw \
-	--disk path=clear-31890-kvm.img \
+	--disk path=focal-server-cloudimg-amd64.raw \
 	--cpus boot=4 \
 	--memory size=1024M \
 	--net "tap=,mac=,ip=,mask=" \
@@ -129,18 +158,19 @@ Multiple arguments can be given to the `--disk` parameter.
 #### Building your kernel
 
 `cloud-hypervisor` also supports direct kernel boot into a `vmlinux` ELF kernel
-image. You want to build such an image first:
+image. In order to support virtio-fs and virtio-iommu we have our own development branch. You are of course able to use your own kernel but these instructions will continue with the version that we develop and test against.
+
+To build the kernel:
 
 ```shell
 
-# Clone a 5.0 Linux kernel
+# Clone the Cloud Hypervisor Linux branch
 $ pushd $CLOUDH
-$ git clone git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git linux-cloud-hypervisor
-$ cd linux-cloud-hypervisor
-$ git reset --hard v5.0
+$ git clone --depth 1 https://github.com/cloud-hypervisor/linux.git -b virtio-fs-virtio-iommu-virtio-mem-5.6-rc4 linux-cloud-hypervisor
+$ pushd linux-cloud-hypervisor
 
 # Use the cloud-hypervisor kernel config to build your kernel
-$ cp $CLOUDH/cloud-hypervisor/resources/linux-5.0-config .config
+$ cp $CLOUDH/cloud-hypervisor/resources/linux-config-x86_64 .config
 $ make bzImage -j `nproc`
 $ popd
 ```
@@ -149,18 +179,18 @@ The `vmlinux` kernel image will then be located at `linux-cloud-hypervisor/arch/
 
 #### Disk image
 
-For the disk image, we will use a Clear Linux cloud image that contains a root partition:
+For the disk image, we will use a Ubuntu cloud image that contains a root partition:
 
 ```shell
 $ pushd $CLOUDH
-$ wget https://download.clearlinux.org/releases/31890/clear/clear-31890-kvm.img.xz
-$ unxz clear-31890-kvm.img.xz
+$ wget https://cloud-images.ubuntu.com/focal/current/focal-server-cloudimg-amd64.img
+$ qemu-img convert -p -f qcow2 -O raw focal-server-cloudimg-amd64.img focal-server-cloudimg-amd64.raw
 $ popd
 ```
 
 #### Booting the guest VM
 
-Now we can directly boot into our custom kernel and make it use the Clear Linux root partition.
+Now we can directly boot into our custom kernel and make it use the Ubuntu root partition.
 If we want to have 4 vCPUs and 512 MBytes of memory:
 
 ```shell
@@ -168,8 +198,8 @@ $ pushd $CLOUDH
 $ sudo setcap cap_net_admin+ep ./cloud-hypervisor/target/release/cloud-hypervisor
 $ ./cloud-hypervisor/target/release/cloud-hypervisor \
 	--kernel ./linux-cloud-hypervisor/arch/x86/boot/compressed/vmlinux.bin \
-	--disk path=clear-31890-kvm.img \
-	--cmdline "console=hvc0 reboot=k panic=1 nomodules i8042.noaux i8042.nomux i8042.nopnp i8042.dumbkbd root=/dev/vda3" \
+	--disk path=focal-server-cloudimg-amd64.raw \
+	--cmdline "console=hvc0 root=/dev/vda1 rw" \
 	--cpus boot=4 \
 	--memory size=1024M \
 	--net "tap=,mac=,ip=,mask=" \
@@ -188,8 +218,8 @@ $ ./cloud-hypervisor/target/release/cloud-hypervisor \
 	--kernel ./linux-cloud-hypervisor/arch/x86/boot/compressed/vmlinux.bin \
 	--console off \
 	--serial tty \
-	--disk path=clear-31890-kvm.img \
-	--cmdline "console=ttyS0 reboot=k panic=1 nomodules i8042.noaux i8042.nomux i8042.nopnp i8042.dumbkbd root=/dev/vda3" \
+	--disk path=focal-server-cloudimg-amd64.raw \
+	--cmdline "console=ttyS0 root=/dev/vda1 rw" \
 	--cpus boot=4 \
 	--memory size=1024M \
 	--net "tap=,mac=,ip=,mask=" \
@@ -200,10 +230,9 @@ $ ./cloud-hypervisor/target/release/cloud-hypervisor \
 
 `cloud-hypervisor` is in a very early, pre-alpha stage. Use at your own risk!
 
-As of 2019-12-12, the following cloud images are supported:
-* [Clear Linux](https://download.clearlinux.org/current/) (cloudguest and kvm)
+As of 2020-07-02, the following cloud images are supported:
 * [Ubuntu Bionic](https://cloud-images.ubuntu.com/bionic/current/) (cloudimg)
-* [Ubuntu Eoan](https://cloud-images.ubuntu.com/eoan/current/) (cloudimg)
+* [Ubuntu Focal](https://cloud-images.ubuntu.com/focal/current/) (cloudimg)
 
 Direct kernel boot to userspace should work with most rootfs.
 
@@ -258,6 +287,11 @@ crates as possible.
 
 # 5. Community
 
+The Cloud Hypervisor project follows the governance, and community guidelines described in
+the [Community](https://github.com/cloud-hypervisor/community) repository.
+
+## Contribute
+
 We are working on building a global, diverse and collaborative community around the Cloud Hypervisor project.
 Anyone who is interested in [contributing](CONTRIBUTING.md) to the project is welcome to participate.
 

acpi_tables/Cargo.toml

@@ -5,5 +5,5 @@ authors = ["The Cloud Hypervisor Authors"]
 edition = "2018"
 
 [dependencies]
-vm-memory = { git = "https://github.com/rust-vmm/vm-memory" }
+vm-memory = "0.2.1"
 

acpi_tables/src/aml.rs

@@ -3,6 +3,8 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 
+use std::marker::PhantomData;
+
 pub trait Aml {
     fn to_aml_bytes(&self) -> Vec<u8>;
 }
@@ -1158,6 +1160,46 @@ impl Aml for Buffer {
     }
 }
 
+pub struct CreateField<'a, T> {
+    buffer: &'a dyn Aml,
+    offset: &'a dyn Aml,
+    field: Path,
+    phantom: PhantomData<&'a T>,
+}
+
+impl<'a, T> CreateField<'a, T> {
+    pub fn new(buffer: &'a dyn Aml, offset: &'a dyn Aml, field: Path) -> Self {
+        CreateField::<T> {
+            buffer,
+            offset,
+            field,
+            phantom: PhantomData::default(),
+        }
+    }
+}
+
+impl<'a> Aml for CreateField<'a, u64> {
+    fn to_aml_bytes(&self) -> Vec<u8> {
+        let mut bytes = Vec::new();
+        bytes.push(0x8f); /* CreateQWordFieldOp */
+        bytes.extend_from_slice(&self.buffer.to_aml_bytes());
+        bytes.extend_from_slice(&self.offset.to_aml_bytes());
+        bytes.extend_from_slice(&self.field.to_aml_bytes());
+        bytes
+    }
+}
+
+impl<'a> Aml for CreateField<'a, u32> {
+    fn to_aml_bytes(&self) -> Vec<u8> {
+        let mut bytes = Vec::new();
+        bytes.push(0x8a); /* CreateDWordFieldOp */
+        bytes.extend_from_slice(&self.buffer.to_aml_bytes());
+        bytes.extend_from_slice(&self.offset.to_aml_bytes());
+        bytes.extend_from_slice(&self.field.to_aml_bytes());
+        bytes
+    }
+}
+
 #[cfg(test)]
 mod tests {
     use super::*;
@@ -1888,4 +1930,59 @@ mod tests {
             &buffer_data[..]
         )
     }
+
+    #[test]
+    fn test_create_field() {
+        /*
+        Method (MCRS, 0, Serialized)
+        {
+            Name (MR64, ResourceTemplate ()
+            {
+                QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+                    0x0000000000000000, // Granularity
+                    0x0000000000000000, // Range Minimum
+                    0xFFFFFFFFFFFFFFFE, // Range Maximum
+                    0x0000000000000000, // Translation Offset
+                    0xFFFFFFFFFFFFFFFF, // Length
+                    ,, _Y00, AddressRangeMemory, TypeStatic)
+            })
+            CreateQWordField (MR64, \_SB.MHPC.MCRS._Y00._MIN, MIN)  // _MIN: Minimum Base Address
+            CreateQWordField (MR64, \_SB.MHPC.MCRS._Y00._MAX, MAX)  // _MAX: Maximum Base Address
+            CreateQWordField (MR64, \_SB.MHPC.MCRS._Y00._LEN, LEN)  // _LEN: Length
+        }
+        */
+        let data = [
+            0x14, 0x41, 0x06, 0x4D, 0x43, 0x52, 0x53, 0x08, 0x08, 0x4D, 0x52, 0x36, 0x34, 0x11,
+            0x33, 0x0A, 0x30, 0x8A, 0x2B, 0x00, 0x00, 0x0C, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+            0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xFF,
+            0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF,
+            0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x79, 0x00, 0x8F, 0x4D, 0x52, 0x36, 0x34,
+            0x0A, 0x0E, 0x4D, 0x49, 0x4E, 0x5F, 0x8F, 0x4D, 0x52, 0x36, 0x34, 0x0A, 0x16, 0x4D,
+            0x41, 0x58, 0x5F, 0x8F, 0x4D, 0x52, 0x36, 0x34, 0x0A, 0x26, 0x4C, 0x45, 0x4E, 0x5F,
+        ];
+
+        assert_eq!(
+            Method::new(
+                "MCRS".into(),
+                0,
+                true,
+                vec![
+                    &Name::new(
+                        "MR64".into(),
+                        &ResourceTemplate::new(vec![&AddressSpace::new_memory(
+                            AddressSpaceCachable::Cacheable,
+                            true,
+                            0x0000_0000_0000_0000u64,
+                            0xFFFF_FFFF_FFFF_FFFEu64
+                        )])
+                    ),
+                    &CreateField::<u64>::new(&Path::new("MR64"), &14usize, "MIN_".into()),
+                    &CreateField::<u64>::new(&Path::new("MR64"), &22usize, "MAX_".into()),
+                    &CreateField::<u64>::new(&Path::new("MR64"), &38usize, "LEN_".into()),
+                ]
+            )
+            .to_aml_bytes(),
+            &data[..]
+        );
+    }
 }

acpi_tables/src/sdt.rs

@@ -13,12 +13,12 @@ pub struct GenericAddress {
 }
 
 impl GenericAddress {
-    pub fn io_port_address(address: u16) -> Self {
+    pub fn io_port_address<T>(address: u16) -> Self {
         GenericAddress {
             address_space_id: 1,
-            register_bit_width: 8,
+            register_bit_width: 8 * std::mem::size_of::<T>() as u8,
             register_bit_offset: 0,
-            access_size: 1,
+            access_size: std::mem::size_of::<T>() as u8,
             address: u64::from(address),
         }
     }

arch/Cargo.toml

@@ -5,23 +5,21 @@ authors = ["The Chromium OS Authors"]
 
 [features]
 default = []
+acpi = ["acpi_tables"]
 
 [dependencies]
-byteorder = "1.3.2"
-kvm-bindings = "0.2.0"
-kvm-ioctls = "0.4.0"
-libc = "0.2.60"
-
+anyhow = "1.0"
+byteorder = "1.3.4"
+hypervisor = { path = "../hypervisor" }
+libc = "0.2.74"
+log = "0.4.11"
+vm-memory = { version = "0.2.1", features = ["backend-mmap"] }
 acpi_tables = { path = "../acpi_tables", optional = true }
 arch_gen = { path = "../arch_gen" }
 
-[dependencies.vm-memory]
-git = "https://github.com/rust-vmm/vm-memory"
-features = ["backend-mmap"]
-
 [dependencies.linux-loader]
 git = "https://github.com/rust-vmm/linux-loader"
 features = ["elf", "bzimage"]
 
 [dev-dependencies]
-rand = "0.7.0"
+rand = "0.7.3"

arch/src/aarch64/fdt.rs

@@ -0,0 +1,595 @@
+// Copyright 2020 Arm Limited (or its affiliates). All rights reserved.
+// Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style license that can be
+// found in the THIRD-PARTY file.
+
+use libc::{c_char, c_int, c_void};
+use std::collections::HashMap;
+use std::ffi::{CStr, CString, NulError};
+use std::fmt::Debug;
+use std::ptr::null;
+use std::{io, result};
+
+use super::super::DeviceType;
+use super::super::InitramfsConfig;
+use super::get_fdt_addr;
+use super::gic::GICDevice;
+use super::layout::{
+    FDT_MAX_SIZE, MEM_32BIT_DEVICES_SIZE, MEM_32BIT_DEVICES_START, PCI_MMCONFIG_SIZE,
+    PCI_MMCONFIG_START,
+};
+use crate::aarch64::fdt::Error::CstringFDTTransform;
+use vm_memory::{Address, Bytes, GuestAddress, GuestMemory, GuestMemoryError, GuestMemoryMmap};
+
+// This is a value for uniquely identifying the FDT node declaring the interrupt controller.
+const GIC_PHANDLE: u32 = 1;
+// This is a value for uniquely identifying the FDT node declaring the MSI controller.
+const MSI_PHANDLE: u32 = 2;
+// This is a value for uniquely identifying the FDT node containing the clock definition.
+const CLOCK_PHANDLE: u32 = 3;
+
+// Read the documentation specified when appending the root node to the FDT.
+const ADDRESS_CELLS: u32 = 0x2;
+const SIZE_CELLS: u32 = 0x2;
+
+// As per kvm tool and
+// https://www.kernel.org/doc/Documentation/devicetree/bindings/interrupt-controller/arm%2Cgic.txt
+// Look for "The 1st cell..."
+const GIC_FDT_IRQ_TYPE_SPI: u32 = 0;
+const GIC_FDT_IRQ_TYPE_PPI: u32 = 1;
+
+// From https://elixir.bootlin.com/linux/v4.9.62/source/include/dt-bindings/interrupt-controller/irq.h#L17
+const IRQ_TYPE_EDGE_RISING: u32 = 1;
+const IRQ_TYPE_LEVEL_HI: u32 = 4;
+
+// This links to libfdt which handles the creation of the binary blob
+// flattened device tree (fdt) that is passed to the kernel and indicates
+// the hardware configuration of the machine.
+#[link(name = "fdt")]
+extern "C" {
+    fn fdt_create(buf: *mut c_void, bufsize: c_int) -> c_int;
+    fn fdt_finish_reservemap(fdt: *mut c_void) -> c_int;
+    fn fdt_begin_node(fdt: *mut c_void, name: *const c_char) -> c_int;
+    fn fdt_property(fdt: *mut c_void, name: *const c_char, val: *const c_void, len: c_int)
+        -> c_int;
+    fn fdt_end_node(fdt: *mut c_void) -> c_int;
+    fn fdt_open_into(fdt: *const c_void, buf: *mut c_void, bufsize: c_int) -> c_int;
+    fn fdt_finish(fdt: *const c_void) -> c_int;
+    fn fdt_pack(fdt: *mut c_void) -> c_int;
+}
+
+/// Trait for devices to be added to the Flattened Device Tree.
+pub trait DeviceInfoForFDT {
+    /// Returns the address where this device will be loaded.
+    fn addr(&self) -> u64;
+    /// Returns the associated interrupt for this device.
+    fn irq(&self) -> u32;
+    /// Returns the amount of memory that needs to be reserved for this device.
+    fn length(&self) -> u64;
+}
+
+/// Errors thrown while configuring the Flattened Device Tree for aarch64.
+#[derive(Debug)]
+pub enum Error {
+    /// Failed to append node to the FDT.
+    AppendFDTNode(io::Error),
+    /// Failed to append a property to the FDT.
+    AppendFDTProperty(io::Error),
+    /// Syscall for creating FDT failed.
+    CreateFDT(io::Error),
+    /// Failed to obtain a C style string.
+    CstringFDTTransform(NulError),
+    /// Failure in calling syscall for terminating this FDT.
+    FinishFDTReserveMap(io::Error),
+    /// Failure in writing FDT in memory.
+    WriteFDTToMemory(GuestMemoryError),
+}
+type Result<T> = result::Result<T, Error>;
+
+/// Creates the flattened device tree for this aarch64 VM.
+pub fn create_fdt<T: DeviceInfoForFDT + Clone + Debug>(
+    guest_mem: &GuestMemoryMmap,
+    cmdline: &CStr,
+    vcpu_mpidr: Vec<u64>,
+    device_info: &HashMap<(DeviceType, String), T>,
+    gic_device: &Box<dyn GICDevice>,
+    initrd: &Option<InitramfsConfig>,
+    pci_space_address: &Option<(u64, u64)>,
+) -> Result<Vec<u8>> {
+    // Alocate stuff necessary for the holding the blob.
+    let mut fdt = vec![0; FDT_MAX_SIZE];
+
+    allocate_fdt(&mut fdt)?;
+
+    // For an explanation why these nodes were introduced in the blob take a look at
+    // https://github.com/torvalds/linux/blob/master/Documentation/devicetree/booting-without-of.txt#L845
+    // Look for "Required nodes and properties".
+
+    // Header or the root node as per above mentioned documentation.
+    append_begin_node(&mut fdt, "")?;
+    append_property_string(&mut fdt, "compatible", "linux,dummy-virt")?;
+    // For info on #address-cells and size-cells read "Note about cells and address representation"
+    // from the above mentioned txt file.
+    append_property_u32(&mut fdt, "#address-cells", ADDRESS_CELLS)?;
+    append_property_u32(&mut fdt, "#size-cells", SIZE_CELLS)?;
+    // This is not mandatory but we use it to point the root node to the node
+    // containing description of the interrupt controller for this VM.
+    append_property_u32(&mut fdt, "interrupt-parent", GIC_PHANDLE)?;
+    create_cpu_nodes(&mut fdt, &vcpu_mpidr)?;
+    create_memory_node(&mut fdt, guest_mem)?;
+    create_chosen_node(&mut fdt, cmdline, initrd)?;
+    create_gic_node(&mut fdt, gic_device)?;
+    create_timer_node(&mut fdt)?;
+    create_clock_node(&mut fdt)?;
+    create_psci_node(&mut fdt)?;
+    create_devices_node(&mut fdt, device_info)?;
+    if let Some((pci_device_base, pci_device_size)) = pci_space_address {
+        create_pci_nodes(&mut fdt, *pci_device_base, *pci_device_size)?;
+    }
+
+    // End Header node.
+    append_end_node(&mut fdt)?;
+
+    // Allocate another buffer so we can format and then write fdt to guest.
+    let mut fdt_final = vec![0; FDT_MAX_SIZE];
+    finish_fdt(&mut fdt, &mut fdt_final)?;
+
+    // Write FDT to memory.
+    let fdt_address = GuestAddress(get_fdt_addr(&guest_mem));
+    guest_mem
+        .write_slice(fdt_final.as_slice(), fdt_address)
+        .map_err(Error::WriteFDTToMemory)?;
+    Ok(fdt_final)
+}
+
+// Following are auxiliary functions for allocating and finishing the FDT.
+fn allocate_fdt(fdt: &mut Vec<u8>) -> Result<()> {
+    // Safe since we allocated this array with FDT_MAX_SIZE.
+    let mut fdt_ret = unsafe { fdt_create(fdt.as_mut_ptr() as *mut c_void, FDT_MAX_SIZE as c_int) };
+
+    if fdt_ret != 0 {
+        return Err(Error::CreateFDT(io::Error::last_os_error()));
+    }
+
+    // The flattened device trees created with fdt_create() contains a list of
+    // reserved memory areas. We need to call `fdt_finish_reservemap` so as to make sure that there is a
+    // terminator in the reservemap list and whatever happened to be at the
+    // start of the FDT data section would end up being interpreted as
+    // reservemap entries.
+    // Safe since we previously allocated this array.
+    fdt_ret = unsafe { fdt_finish_reservemap(fdt.as_mut_ptr() as *mut c_void) };
+    if fdt_ret != 0 {
+        return Err(Error::FinishFDTReserveMap(io::Error::last_os_error()));
+    }
+    Ok(())
+}
+
+fn finish_fdt(from_fdt: &mut Vec<u8>, to_fdt: &mut Vec<u8>) -> Result<()> {
+    // Safe since we allocated `fdt_final` and previously passed in its size.
+    let mut fdt_ret = unsafe { fdt_finish(from_fdt.as_mut_ptr() as *mut c_void) };
+    if fdt_ret != 0 {
+        return Err(Error::FinishFDTReserveMap(io::Error::last_os_error()));
+    }
+
+    // Safe because we allocated both arrays with the correct size.
+    fdt_ret = unsafe {
+        fdt_open_into(
+            from_fdt.as_mut_ptr() as *mut c_void,
+            to_fdt.as_mut_ptr() as *mut c_void,
+            FDT_MAX_SIZE as i32,
+        )
+    };
+    if fdt_ret != 0 {
+        return Err(Error::FinishFDTReserveMap(io::Error::last_os_error()));
+    }
+
+    // Safe since we allocated `to_fdt`.
+    fdt_ret = unsafe { fdt_pack(to_fdt.as_mut_ptr() as *mut c_void) };
+    if fdt_ret != 0 {
+        return Err(Error::FinishFDTReserveMap(io::Error::last_os_error()));
+    }
+    Ok(())
+}
+
+// Following are auxiliary functions for appending nodes to FDT.
+fn append_begin_node(fdt: &mut Vec<u8>, name: &str) -> Result<()> {
+    let cstr_name = CString::new(name).map_err(CstringFDTTransform)?;
+
+    // Safe because we allocated fdt and converted name to a CString
+    let fdt_ret = unsafe { fdt_begin_node(fdt.as_mut_ptr() as *mut c_void, cstr_name.as_ptr()) };
+    if fdt_ret != 0 {
+        return Err(Error::AppendFDTNode(io::Error::last_os_error()));
+    }
+    Ok(())
+}
+
+fn append_end_node(fdt: &mut Vec<u8>) -> Result<()> {
+    // Safe because we allocated fdt.
+    let fdt_ret = unsafe { fdt_end_node(fdt.as_mut_ptr() as *mut c_void) };
+    if fdt_ret != 0 {
+        return Err(Error::AppendFDTNode(io::Error::last_os_error()));
+    }
+    Ok(())
+}
+
+// Following are auxiliary functions for appending property nodes to the nodes of the FDT.
+fn append_property_u32(fdt: &mut Vec<u8>, name: &str, val: u32) -> Result<()> {
+    append_property(fdt, name, &to_be32(val))
+}
+
+fn append_property_u64(fdt: &mut Vec<u8>, name: &str, val: u64) -> Result<()> {
+    append_property(fdt, name, &to_be64(val))
+}
+
+fn append_property_string(fdt: &mut Vec<u8>, name: &str, value: &str) -> Result<()> {
+    let cstr_value = CString::new(value).map_err(CstringFDTTransform)?;
+    append_property_cstring(fdt, name, &cstr_value)
+}
+
+fn append_property_cstring(fdt: &mut Vec<u8>, name: &str, cstr_value: &CStr) -> Result<()> {
+    let value_bytes = cstr_value.to_bytes_with_nul();
+    let cstr_name = CString::new(name).map_err(CstringFDTTransform)?;
+    // Safe because we allocated fdt, converted name and value to CStrings
+    let fdt_ret = unsafe {
+        fdt_property(
+            fdt.as_mut_ptr() as *mut c_void,
+            cstr_name.as_ptr(),
+            value_bytes.as_ptr() as *mut c_void,
+            value_bytes.len() as i32,
+        )
+    };
+    if fdt_ret != 0 {
+        return Err(Error::AppendFDTProperty(io::Error::last_os_error()));
+    }
+    Ok(())
+}
+
+fn append_property_null(fdt: &mut Vec<u8>, name: &str) -> Result<()> {
+    let cstr_name = CString::new(name).map_err(CstringFDTTransform)?;
+
+    // Safe because we allocated fdt, converted name to a CString
+    let fdt_ret = unsafe {
+        fdt_property(
+            fdt.as_mut_ptr() as *mut c_void,
+            cstr_name.as_ptr(),
+            null(),
+            0,
+        )
+    };
+    if fdt_ret != 0 {
+        return Err(Error::AppendFDTProperty(io::Error::last_os_error()));
+    }
+    Ok(())
+}
+
+fn append_property(fdt: &mut Vec<u8>, name: &str, val: &[u8]) -> Result<()> {
+    let cstr_name = CString::new(name).map_err(CstringFDTTransform)?;
+    let val_ptr = val.as_ptr() as *const c_void;
+
+    // Safe because we allocated fdt and converted name to a CString
+    let fdt_ret = unsafe {
+        fdt_property(
+            fdt.as_mut_ptr() as *mut c_void,
+            cstr_name.as_ptr(),
+            val_ptr,
+            val.len() as i32,
+        )
+    };
+    if fdt_ret != 0 {
+        return Err(Error::AppendFDTProperty(io::Error::last_os_error()));
+    }
+    Ok(())
+}
+
+// Auxiliary functions for writing u32/u64 numbers in big endian order.
+fn to_be32(input: u32) -> [u8; 4] {
+    u32::to_be_bytes(input)
+}
+
+fn to_be64(input: u64) -> [u8; 8] {
+    u64::to_be_bytes(input)
+}
+
+// Helper functions for generating a properly formatted byte vector using 32-bit/64-bit cells.
+fn generate_prop32(cells: &[u32]) -> Vec<u8> {
+    let mut ret: Vec<u8> = Vec::new();
+    for &e in cells {
+        ret.extend(to_be32(e).iter());
+    }
+    ret
+}
+
+fn generate_prop64(cells: &[u64]) -> Vec<u8> {
+    let mut ret: Vec<u8> = Vec::new();
+    for &e in cells {
+        ret.extend(to_be64(e).iter());
+    }
+    ret
+}
+
+// Following are the auxiliary function for creating the different nodes that we append to our FDT.
+fn create_cpu_nodes(fdt: &mut Vec<u8>, vcpu_mpidr: &Vec<u64>) -> Result<()> {
+    // See https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/arm/cpus.yaml.
+    append_begin_node(fdt, "cpus")?;
+    // As per documentation, on ARM v8 64-bit systems value should be set to 2.
+    append_property_u32(fdt, "#address-cells", 0x02)?;
+    append_property_u32(fdt, "#size-cells", 0x0)?;
+    let num_cpus = vcpu_mpidr.len();
+
+    for cpu_index in 0..num_cpus {
+        let cpu_name = format!("cpu@{:x}", cpu_index);
+        append_begin_node(fdt, &cpu_name)?;
+        append_property_string(fdt, "device_type", "cpu")?;
+        append_property_string(fdt, "compatible", "arm,arm-v8")?;
+        if num_cpus > 1 {
+            // This is required on armv8 64-bit. See aforementioned documentation.
+            append_property_string(fdt, "enable-method", "psci")?;
+        }
+        // Set the field to first 24 bits of the MPIDR - Multiprocessor Affinity Register.
+        // See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0488c/BABHBJCI.html.
+        append_property_u64(fdt, "reg", vcpu_mpidr[cpu_index] & 0x7FFFFF)?;
+        append_end_node(fdt)?;
+    }
+    append_end_node(fdt)?;
+    Ok(())
+}
+
+fn create_memory_node(fdt: &mut Vec<u8>, guest_mem: &GuestMemoryMmap) -> Result<()> {
+    let mem_size = guest_mem.last_addr().raw_value() - super::layout::RAM_64BIT_START + 1;
+    // See https://github.com/torvalds/linux/blob/master/Documentation/devicetree/booting-without-of.txt#L960
+    // for an explanation of this.
+    let mem_reg_prop = generate_prop64(&[super::layout::RAM_64BIT_START as u64, mem_size as u64]);
+
+    append_begin_node(fdt, "memory")?;
+    append_property_string(fdt, "device_type", "memory")?;
+    append_property(fdt, "reg", &mem_reg_prop)?;
+    append_end_node(fdt)?;
+    Ok(())
+}
+
+fn create_chosen_node(
+    fdt: &mut Vec<u8>,
+    cmdline: &CStr,
+    initrd: &Option<InitramfsConfig>,
+) -> Result<()> {
+    append_begin_node(fdt, "chosen")?;
+    append_property_cstring(fdt, "bootargs", cmdline)?;
+
+    if let Some(initrd_config) = initrd {
+        append_property_u64(
+            fdt,
+            "linux,initrd-start",
+            initrd_config.address.raw_value() as u64,
+        )?;
+        append_property_u64(
+            fdt,
+            "linux,initrd-end",
+            initrd_config.address.raw_value() + initrd_config.size as u64,
+        )?;
+    }
+
+    append_end_node(fdt)?;
+
+    Ok(())
+}
+
+fn create_gic_node(fdt: &mut Vec<u8>, gic_device: &Box<dyn GICDevice>) -> Result<()> {
+    let gic_reg_prop = generate_prop64(gic_device.device_properties());
+
+    append_begin_node(fdt, "intc")?;
+    append_property_string(fdt, "compatible", gic_device.fdt_compatibility())?;
+    append_property_null(fdt, "interrupt-controller")?;
+    // "interrupt-cells" field specifies the number of cells needed to encode an
+    // interrupt source. The type shall be a <u32> and the value shall be 3 if no PPI affinity description
+    // is required.
+    append_property_u32(fdt, "#interrupt-cells", 3)?;
+    append_property(fdt, "reg", &gic_reg_prop)?;
+    append_property_u32(fdt, "phandle", GIC_PHANDLE)?;
+    append_property_u32(fdt, "#address-cells", 2)?;
+    append_property_u32(fdt, "#size-cells", 2)?;
+    append_property_null(fdt, "ranges")?;
+    let gic_intr = [
+        GIC_FDT_IRQ_TYPE_PPI,
+        gic_device.fdt_maint_irq(),
+        IRQ_TYPE_LEVEL_HI,
+    ];
+    let gic_intr_prop = generate_prop32(&gic_intr);
+
+    append_property(fdt, "interrupts", &gic_intr_prop)?;
+
+    if gic_device.msi_compatible() {
+        append_begin_node(fdt, "msic")?;
+        append_property_string(fdt, "compatible", gic_device.msi_compatiblility())?;
+        append_property_null(fdt, "msi-controller")?;
+        append_property_u32(fdt, "phandle", MSI_PHANDLE)?;
+        let msi_reg_prop = generate_prop64(gic_device.msi_properties());
+        append_property(fdt, "reg", &msi_reg_prop)?;
+        append_end_node(fdt)?;
+    }
+
+    append_end_node(fdt)?;
+
+    Ok(())
+}
+
+fn create_clock_node(fdt: &mut Vec<u8>) -> Result<()> {
+    // The Advanced Peripheral Bus (APB) is part of the Advanced Microcontroller Bus Architecture
+    // (AMBA) protocol family. It defines a low-cost interface that is optimized for minimal power
+    // consumption and reduced interface complexity.
+    // PCLK is the clock source and this node defines exactly the clock for the APB.
+    append_begin_node(fdt, "apb-pclk")?;
+    append_property_string(fdt, "compatible", "fixed-clock")?;
+    append_property_u32(fdt, "#clock-cells", 0x0)?;
+    append_property_u32(fdt, "clock-frequency", 24000000)?;
+    append_property_string(fdt, "clock-output-names", "clk24mhz")?;
+    append_property_u32(fdt, "phandle", CLOCK_PHANDLE)?;
+    append_end_node(fdt)?;
+
+    Ok(())
+}
+
+fn create_timer_node(fdt: &mut Vec<u8>) -> Result<()> {
+    // See
+    // https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/interrupt-controller/arch_timer.txt
+    // These are fixed interrupt numbers for the timer device.
+    let irqs = [13, 14, 11, 10];
+    let compatible = "arm,armv8-timer";
+
+    let mut timer_reg_cells: Vec<u32> = Vec::new();
+    for &irq in irqs.iter() {
+        timer_reg_cells.push(GIC_FDT_IRQ_TYPE_PPI);
+        timer_reg_cells.push(irq);
+        timer_reg_cells.push(IRQ_TYPE_LEVEL_HI);
+    }
+    let timer_reg_prop = generate_prop32(timer_reg_cells.as_slice());
+
+    append_begin_node(fdt, "timer")?;
+    append_property_string(fdt, "compatible", compatible)?;
+    append_property_null(fdt, "always-on")?;
+    append_property(fdt, "interrupts", &timer_reg_prop)?;
+    append_end_node(fdt)?;
+
+    Ok(())
+}
+
+fn create_psci_node(fdt: &mut Vec<u8>) -> Result<()> {
+    let compatible = "arm,psci-0.2";
+    append_begin_node(fdt, "psci")?;
+    append_property_string(fdt, "compatible", compatible)?;
+    // Two methods available: hvc and smc.
+    // As per documentation, PSCI calls between a guest and hypervisor may use the HVC conduit instead of SMC.
+    // So, since we are using kvm, we need to use hvc.
+    append_property_string(fdt, "method", "hvc")?;
+    append_end_node(fdt)?;
+
+    Ok(())
+}
+
+fn create_virtio_node<T: DeviceInfoForFDT + Clone + Debug>(
+    fdt: &mut Vec<u8>,
+    dev_info: &T,
+) -> Result<()> {
+    let device_reg_prop = generate_prop64(&[dev_info.addr(), dev_info.length()]);
+    let irq = generate_prop32(&[GIC_FDT_IRQ_TYPE_SPI, dev_info.irq(), IRQ_TYPE_EDGE_RISING]);
+
+    append_begin_node(fdt, &format!("virtio_mmio@{:x}", dev_info.addr()))?;
+    append_property_string(fdt, "compatible", "virtio,mmio")?;
+    append_property(fdt, "reg", &device_reg_prop)?;
+    append_property(fdt, "interrupts", &irq)?;
+    append_property_u32(fdt, "interrupt-parent", GIC_PHANDLE)?;
+    append_end_node(fdt)?;
+
+    Ok(())
+}
+
+fn create_serial_node<T: DeviceInfoForFDT + Clone + Debug>(
+    fdt: &mut Vec<u8>,
+    dev_info: &T,
+) -> Result<()> {
+    let serial_reg_prop = generate_prop64(&[dev_info.addr(), dev_info.length()]);
+    let irq = generate_prop32(&[GIC_FDT_IRQ_TYPE_SPI, dev_info.irq(), IRQ_TYPE_EDGE_RISING]);
+
+    append_begin_node(fdt, &format!("uart@{:x}", dev_info.addr()))?;
+    append_property_string(fdt, "compatible", "ns16550a")?;
+    append_property(fdt, "reg", &serial_reg_prop)?;
+    append_property_u32(fdt, "clocks", CLOCK_PHANDLE)?;
+    append_property_string(fdt, "clock-names", "apb_pclk")?;
+    append_property(fdt, "interrupts", &irq)?;
+    append_end_node(fdt)?;
+
+    Ok(())
+}
+
+fn create_rtc_node<T: DeviceInfoForFDT + Clone + Debug>(
+    fdt: &mut Vec<u8>,
+    dev_info: &T,
+) -> Result<()> {
+    let compatible = b"arm,pl031\0arm,primecell\0";
+    let rtc_reg_prop = generate_prop64(&[dev_info.addr(), dev_info.length()]);
+    let irq = generate_prop32(&[GIC_FDT_IRQ_TYPE_SPI, dev_info.irq(), IRQ_TYPE_LEVEL_HI]);
+    append_begin_node(fdt, &format!("rtc@{:x}", dev_info.addr()))?;
+    append_property(fdt, "compatible", compatible)?;
+    append_property(fdt, "reg", &rtc_reg_prop)?;
+    append_property(fdt, "interrupts", &irq)?;
+    append_property_u32(fdt, "clocks", CLOCK_PHANDLE)?;
+    append_property_string(fdt, "clock-names", "apb_pclk")?;
+    append_end_node(fdt)?;
+
+    Ok(())
+}
+
+fn create_devices_node<T: DeviceInfoForFDT + Clone + Debug>(
+    fdt: &mut Vec<u8>,
+    dev_info: &HashMap<(DeviceType, String), T>,
+) -> Result<()> {
+    // Create one temp Vec to store all virtio devices
+    let mut ordered_virtio_device: Vec<&T> = Vec::new();
+
+    for ((device_type, _device_id), info) in dev_info {
+        match device_type {
+            DeviceType::RTC => create_rtc_node(fdt, info)?,
+            DeviceType::Serial => create_serial_node(fdt, info)?,
+            DeviceType::Virtio(_) => {
+                ordered_virtio_device.push(info);
+            }
+        }
+    }
+
+    // Sort out virtio devices by address from low to high and insert them into fdt table.
+    ordered_virtio_device.sort_by(|a, b| a.addr().cmp(&b.addr()));
+    // Current address allocation strategy in cloud-hypervisor is: the first created device
+    // will be allocated to higher address. Here we reverse the vector to make sure that
+    // the older created device will appear in front of the newer created device in FDT.
+    ordered_virtio_device.reverse();
+    for ordered_device_info in ordered_virtio_device.drain(..) {
+        create_virtio_node(fdt, ordered_device_info)?;
+    }
+
+    Ok(())
+}
+
+fn create_pci_nodes(fdt: &mut Vec<u8>, pci_device_base: u64, pci_device_size: u64) -> Result<()> {
+    // Add node for PCIe controller.
+    // See Documentation/devicetree/bindings/pci/host-generic-pci.txt in the kernel
+    // and https://elinux.org/Device_Tree_Usage.
+    let ranges = generate_prop32(&[
+        // mmio addresses
+        0x2000000,                                // (ss = 10: 32-bit memory space)
+        (MEM_32BIT_DEVICES_START.0 >> 32) as u32, // PCI address
+        MEM_32BIT_DEVICES_START.0 as u32,
+        (MEM_32BIT_DEVICES_START.0 >> 32) as u32, // CPU address
+        MEM_32BIT_DEVICES_START.0 as u32,
+        (MEM_32BIT_DEVICES_SIZE >> 32) as u32, // size
+        MEM_32BIT_DEVICES_SIZE as u32,
+        // device addresses
+        0x3000000,                      // (ss = 11: 64-bit memory space)
+        (pci_device_base >> 32) as u32, // PCI address
+        pci_device_base as u32,
+        (pci_device_base >> 32) as u32, // CPU address
+        pci_device_base as u32,
+        (pci_device_size >> 32) as u32, // size
+        pci_device_size as u32,
+    ]);
+    let bus_range = generate_prop32(&[0, 0]); // Only bus 0
+    let reg = generate_prop64(&[PCI_MMCONFIG_START.0, PCI_MMCONFIG_SIZE]);
+
+    append_begin_node(fdt, "pci")?;
+    append_property_string(fdt, "compatible", "pci-host-ecam-generic")?;
+    append_property_string(fdt, "device_type", "pci")?;
+    append_property(fdt, "ranges", &ranges)?;
+    append_property(fdt, "bus-range", &bus_range)?;
+    append_property_u32(fdt, "#address-cells", 3)?;
+    append_property_u32(fdt, "#size-cells", 2)?;
+    append_property(fdt, "reg", &reg)?;
+    append_property_u32(fdt, "#interrupt-cells", 1)?;
+    append_property_null(fdt, "interrupt-map")?;
+    append_property_null(fdt, "interrupt-map-mask")?;
+    append_property_null(fdt, "dma-coherent")?;
+    append_property_u32(fdt, "msi-parent", MSI_PHANDLE)?;
+    append_end_node(fdt)?;
+
+    Ok(())
+}

arch/src/aarch64/gic.rs

@@ -0,0 +1,174 @@
+// Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+// SPDX-License-Identifier: Apache-2.0
+
+use std::result;
+use std::sync::Arc;
+
+/// Errors thrown while setting up the GIC.
+#[derive(Debug)]
+pub enum Error {
+    /// Error while calling KVM ioctl for setting up the global interrupt controller.
+    CreateGIC(hypervisor::HypervisorVmError),
+    /// Error while setting device attributes for the GIC.
+    SetDeviceAttribute(hypervisor::HypervisorDeviceError),
+}
+type Result<T> = result::Result<T, Error>;
+
+pub trait GICDevice {
+    /// Returns the hypervisor agnostic Device of the GIC device
+    fn device(&self) -> &Arc<dyn hypervisor::Device>;
+
+    /// Returns the fdt compatibility property of the device
+    fn fdt_compatibility(&self) -> &str;
+
+    /// Returns the maint_irq fdt property of the device
+    fn fdt_maint_irq(&self) -> u32;
+
+    /// Returns an array with GIC device properties
+    fn device_properties(&self) -> &[u64];
+
+    /// Returns the number of vCPUs this GIC handles
+    fn vcpu_count(&self) -> u64;
+
+    /// Returns whether the GIC device is MSI compatible or not
+    fn msi_compatible(&self) -> bool {
+        false
+    }
+
+    /// Returns the MSI compatibility property of the device
+    fn msi_compatiblility(&self) -> &str {
+        ""
+    }
+
+    /// Returns the MSI reg property of the device
+    fn msi_properties(&self) -> &[u64] {
+        &[]
+    }
+}
+
+pub mod kvm {
+    use super::GICDevice;
+    use super::Result;
+    use crate::aarch64::gicv2::kvm::KvmGICv2;
+    use crate::aarch64::gicv3::kvm::KvmGICv3;
+    use crate::aarch64::gicv3_its::kvm::KvmGICv3ITS;
+    use crate::layout;
+    use hypervisor::kvm::kvm_bindings;
+    use std::boxed::Box;
+    use std::sync::Arc;
+
+    /// Trait for GIC devices.
+    pub trait KvmGICDevice: Send + Sync + GICDevice {
+        /// Returns the GIC version of the device
+        fn version() -> u32;
+
+        /// Create the GIC device object
+        fn create_device(
+            device: Arc<dyn hypervisor::Device>,
+            vcpu_count: u64,
+        ) -> Box<dyn GICDevice>;
+
+        /// Setup the device-specific attributes
+        fn init_device_attributes(
+            vm: &Arc<dyn hypervisor::Vm>,
+            gic_device: &Box<dyn GICDevice>,
+        ) -> Result<()>;
+
+        /// Initialize a GIC device
+        fn init_device(vm: &Arc<dyn hypervisor::Vm>) -> Result<Arc<dyn hypervisor::Device>> {
+            let mut gic_device = kvm_bindings::kvm_create_device {
+                type_: Self::version(),
+                fd: 0,
+                flags: 0,
+            };
+
+            vm.create_device(&mut gic_device)
+                .map_err(super::Error::CreateGIC)
+        }
+
+        /// Set a GIC device attribute
+        fn set_device_attribute(
+            device: &Arc<dyn hypervisor::Device>,
+            group: u32,
+            attr: u64,
+            addr: u64,
+            flags: u32,
+        ) -> Result<()> {
+            let attr = kvm_bindings::kvm_device_attr {
+                group: group,
+                attr: attr,
+                addr: addr,
+                flags: flags,
+            };
+            device
+                .set_device_attr(&attr)
+                .map_err(super::Error::SetDeviceAttribute)?;
+
+            Ok(())
+        }
+
+        /// Finalize the setup of a GIC device
+        fn finalize_device(gic_device: &Box<dyn GICDevice>) -> Result<()> {
+            /* We need to tell the kernel how many irqs to support with this vgic.
+             * See the `layout` module for details.
+             */
+            let nr_irqs: u32 = layout::IRQ_MAX - layout::IRQ_BASE + 1;
+            let nr_irqs_ptr = &nr_irqs as *const u32;
+            Self::set_device_attribute(
+                gic_device.device(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
+                0,
+                nr_irqs_ptr as u64,
+                0,
+            )?;
+
+            /* Finalize the GIC.
+             * See https://code.woboq.org/linux/linux/virt/kvm/arm/vgic/vgic-kvm-device.c.html#211.
+             */
+            Self::set_device_attribute(
+                gic_device.device(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_CTRL,
+                u64::from(kvm_bindings::KVM_DEV_ARM_VGIC_CTRL_INIT),
+                0,
+                0,
+            )?;
+
+            Ok(())
+        }
+
+        /// Method to initialize the GIC device
+        fn new(vm: &Arc<dyn hypervisor::Vm>, vcpu_count: u64) -> Result<Box<dyn GICDevice>> {
+            let vgic_fd = Self::init_device(vm)?;
+
+            let device = Self::create_device(vgic_fd, vcpu_count);
+
+            Self::init_device_attributes(vm, &device)?;
+
+            Self::finalize_device(&device)?;
+
+            Ok(device)
+        }
+    }
+
+    /// Create a GIC device.
+    ///
+    /// It will try to create by default a GICv3 device. If that fails it will try
+    /// to fall-back to a GICv2 device.
+    pub fn create_gic(
+        vm: &Arc<dyn hypervisor::Vm>,
+        vcpu_count: u64,
+        its_required: bool,
+    ) -> Result<Box<dyn GICDevice>> {
+        if its_required {
+            KvmGICv3ITS::new(vm, vcpu_count)
+        } else {
+            KvmGICv3ITS::new(vm, vcpu_count).or_else(|_| {
+                debug!("Failed to create GICv3-ITS, will try GICv3 instead.");
+                KvmGICv3::new(vm, vcpu_count).or_else(|_| {
+                    debug!("Failed to create GICv3, will try GICv2 instead.");
+                    KvmGICv2::new(vm, vcpu_count)
+                })
+            })
+        }
+    }
+}

arch/src/aarch64/gicv2.rs

@@ -0,0 +1,124 @@
+// Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+// SPDX-License-Identifier: Apache-2.0
+
+pub mod kvm {
+    use crate::aarch64::gic::kvm::KvmGICDevice;
+    use crate::aarch64::gic::{Error, GICDevice};
+    use std::{boxed::Box, result};
+    type Result<T> = result::Result<T, Error>;
+    use crate::layout;
+    use hypervisor::kvm::kvm_bindings;
+    use std::sync::Arc;
+
+    /// Represent a GIC v2 device
+    pub struct KvmGICv2 {
+        /// The hypervisor agnostic device
+        device: Arc<dyn hypervisor::Device>,
+
+        /// GIC device properties, to be used for setting up the fdt entry
+        properties: [u64; 4],
+
+        /// Number of CPUs handled by the device
+        vcpu_count: u64,
+    }
+
+    impl KvmGICv2 {
+        // Unfortunately bindgen omits defines that are based on other defines.
+        // See arch/arm64/include/uapi/asm/kvm.h file from the linux kernel.
+        const KVM_VGIC_V2_DIST_SIZE: u64 = 0x1000;
+        const KVM_VGIC_V2_CPU_SIZE: u64 = 0x2000;
+
+        // Device trees specific constants
+        const ARCH_GIC_V2_MAINT_IRQ: u32 = 8;
+
+        /// Get the address of the GICv2 distributor.
+        const fn get_dist_addr() -> u64 {
+            layout::MAPPED_IO_START - KvmGICv2::KVM_VGIC_V2_DIST_SIZE
+        }
+
+        /// Get the size of the GIC_v2 distributor.
+        const fn get_dist_size() -> u64 {
+            KvmGICv2::KVM_VGIC_V2_DIST_SIZE
+        }
+
+        /// Get the address of the GIC_v2 CPU.
+        const fn get_cpu_addr() -> u64 {
+            KvmGICv2::get_dist_addr() - KvmGICv2::KVM_VGIC_V2_CPU_SIZE
+        }
+
+        /// Get the size of the GIC_v2 CPU.
+        const fn get_cpu_size() -> u64 {
+            KvmGICv2::KVM_VGIC_V2_CPU_SIZE
+        }
+    }
+
+    impl GICDevice for KvmGICv2 {
+        fn device(&self) -> &Arc<dyn hypervisor::Device> {
+            &self.device
+        }
+
+        fn device_properties(&self) -> &[u64] {
+            &self.properties
+        }
+
+        fn fdt_compatibility(&self) -> &str {
+            "arm,gic-400"
+        }
+
+        fn fdt_maint_irq(&self) -> u32 {
+            KvmGICv2::ARCH_GIC_V2_MAINT_IRQ
+        }
+
+        fn vcpu_count(&self) -> u64 {
+            self.vcpu_count
+        }
+    }
+
+    impl KvmGICDevice for KvmGICv2 {
+        fn version() -> u32 {
+            kvm_bindings::kvm_device_type_KVM_DEV_TYPE_ARM_VGIC_V2
+        }
+
+        fn create_device(
+            device: Arc<dyn hypervisor::Device>,
+            vcpu_count: u64,
+        ) -> Box<dyn GICDevice> {
+            Box::new(KvmGICv2 {
+                device: device,
+                properties: [
+                    KvmGICv2::get_dist_addr(),
+                    KvmGICv2::get_dist_size(),
+                    KvmGICv2::get_cpu_addr(),
+                    KvmGICv2::get_cpu_size(),
+                ],
+                vcpu_count: vcpu_count,
+            })
+        }
+
+        fn init_device_attributes(
+            _vm: &Arc<dyn hypervisor::Vm>,
+            gic_device: &Box<dyn GICDevice>,
+        ) -> Result<()> {
+            /* Setting up the distributor attribute.
+            We are placing the GIC below 1GB so we need to substract the size of the distributor. */
+            Self::set_device_attribute(
+                gic_device.device(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ADDR,
+                u64::from(kvm_bindings::KVM_VGIC_V2_ADDR_TYPE_DIST),
+                &KvmGICv2::get_dist_addr() as *const u64 as u64,
+                0,
+            )?;
+
+            /* Setting up the CPU attribute. */
+            Self::set_device_attribute(
+                gic_device.device(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ADDR,
+                u64::from(kvm_bindings::KVM_VGIC_V2_ADDR_TYPE_CPU),
+                &KvmGICv2::get_cpu_addr() as *const u64 as u64,
+                0,
+            )?;
+
+            Ok(())
+        }
+    }
+}

arch/src/aarch64/gicv3.rs

@@ -0,0 +1,128 @@
+// Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+// SPDX-License-Identifier: Apache-2.0
+
+pub mod kvm {
+    use crate::aarch64::gic::kvm::KvmGICDevice;
+    use crate::aarch64::gic::{Error, GICDevice};
+    use crate::layout;
+    use hypervisor::kvm::kvm_bindings;
+    use std::sync::Arc;
+    use std::{boxed::Box, result};
+    type Result<T> = result::Result<T, Error>;
+
+    pub struct KvmGICv3 {
+        /// The hypervisor agnostic device
+        device: Arc<dyn hypervisor::Device>,
+
+        /// GIC device properties, to be used for setting up the fdt entry
+        properties: [u64; 4],
+
+        /// Number of CPUs handled by the device
+        vcpu_count: u64,
+    }
+
+    impl KvmGICv3 {
+        // Unfortunately bindgen omits defines that are based on other defines.
+        // See arch/arm64/include/uapi/asm/kvm.h file from the linux kernel.
+        pub const SZ_64K: u64 = 0x0001_0000;
+        const KVM_VGIC_V3_DIST_SIZE: u64 = KvmGICv3::SZ_64K;
+        const KVM_VGIC_V3_REDIST_SIZE: u64 = (2 * KvmGICv3::SZ_64K);
+
+        // Device trees specific constants
+        pub const ARCH_GIC_V3_MAINT_IRQ: u32 = 9;
+
+        /// Get the address of the GIC distributor.
+        pub fn get_dist_addr() -> u64 {
+            layout::MAPPED_IO_START - KvmGICv3::KVM_VGIC_V3_DIST_SIZE
+        }
+
+        /// Get the size of the GIC distributor.
+        pub fn get_dist_size() -> u64 {
+            KvmGICv3::KVM_VGIC_V3_DIST_SIZE
+        }
+
+        /// Get the address of the GIC redistributors.
+        pub fn get_redists_addr(vcpu_count: u64) -> u64 {
+            KvmGICv3::get_dist_addr() - KvmGICv3::get_redists_size(vcpu_count)
+        }
+
+        /// Get the size of the GIC redistributors.
+        pub fn get_redists_size(vcpu_count: u64) -> u64 {
+            vcpu_count * KvmGICv3::KVM_VGIC_V3_REDIST_SIZE
+        }
+    }
+
+    impl GICDevice for KvmGICv3 {
+        fn device(&self) -> &Arc<dyn hypervisor::Device> {
+            &self.device
+        }
+
+        fn fdt_compatibility(&self) -> &str {
+            "arm,gic-v3"
+        }
+
+        fn fdt_maint_irq(&self) -> u32 {
+            KvmGICv3::ARCH_GIC_V3_MAINT_IRQ
+        }
+
+        fn device_properties(&self) -> &[u64] {
+            &self.properties
+        }
+
+        fn vcpu_count(&self) -> u64 {
+            self.vcpu_count
+        }
+    }
+
+    impl KvmGICDevice for KvmGICv3 {
+        fn version() -> u32 {
+            kvm_bindings::kvm_device_type_KVM_DEV_TYPE_ARM_VGIC_V3
+        }
+
+        fn create_device(
+            device: Arc<dyn hypervisor::Device>,
+            vcpu_count: u64,
+        ) -> Box<dyn GICDevice> {
+            Box::new(KvmGICv3 {
+                device: device,
+                properties: [
+                    KvmGICv3::get_dist_addr(),
+                    KvmGICv3::get_dist_size(),
+                    KvmGICv3::get_redists_addr(vcpu_count),
+                    KvmGICv3::get_redists_size(vcpu_count),
+                ],
+                vcpu_count: vcpu_count,
+            })
+        }
+
+        fn init_device_attributes(
+            _vm: &Arc<dyn hypervisor::Vm>,
+            gic_device: &Box<dyn GICDevice>,
+        ) -> Result<()> {
+            /* Setting up the distributor attribute.
+             We are placing the GIC below 1GB so we need to substract the size of the distributor.
+            */
+            Self::set_device_attribute(
+                gic_device.device(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ADDR,
+                u64::from(kvm_bindings::KVM_VGIC_V3_ADDR_TYPE_DIST),
+                &KvmGICv3::get_dist_addr() as *const u64 as u64,
+                0,
+            )?;
+
+            /* Setting up the redistributors' attribute.
+            We are calculating here the start of the redistributors address. We have one per CPU.
+            */
+            Self::set_device_attribute(
+                gic_device.device(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ADDR,
+                u64::from(kvm_bindings::KVM_VGIC_V3_ADDR_TYPE_REDIST),
+                &KvmGICv3::get_redists_addr(u64::from(gic_device.vcpu_count())) as *const u64
+                    as u64,
+                0,
+            )?;
+
+            Ok(())
+        }
+    }
+}

arch/src/aarch64/gicv3_its.rs

@@ -0,0 +1,133 @@
+// Copyright 2020 ARM Limited
+// SPDX-License-Identifier: Apache-2.0
+
+pub mod kvm {
+    use std::sync::Arc;
+    use std::{boxed::Box, result};
+    type Result<T> = result::Result<T, Error>;
+    use crate::aarch64::gic::kvm::KvmGICDevice;
+    use crate::aarch64::gic::{Error, GICDevice};
+    use crate::aarch64::gicv3::kvm::KvmGICv3;
+    use hypervisor::kvm::kvm_bindings;
+
+    pub struct KvmGICv3ITS {
+        /// The hypervisor agnostic device
+        device: Arc<dyn hypervisor::Device>,
+
+        /// GIC device properties, to be used for setting up the fdt entry
+        gic_properties: [u64; 4],
+
+        /// MSI device properties, to be used for setting up the fdt entry
+        msi_properties: [u64; 2],
+
+        /// Number of CPUs handled by the device
+        vcpu_count: u64,
+    }
+
+    impl KvmGICv3ITS {
+        const KVM_VGIC_V3_ITS_SIZE: u64 = (2 * KvmGICv3::SZ_64K);
+
+        fn get_msi_size() -> u64 {
+            KvmGICv3ITS::KVM_VGIC_V3_ITS_SIZE
+        }
+
+        fn get_msi_addr(vcpu_count: u64) -> u64 {
+            KvmGICv3::get_redists_addr(vcpu_count) - KvmGICv3ITS::get_msi_size()
+        }
+    }
+
+    impl GICDevice for KvmGICv3ITS {
+        fn device(&self) -> &Arc<dyn hypervisor::Device> {
+            &self.device
+        }
+
+        fn fdt_compatibility(&self) -> &str {
+            "arm,gic-v3"
+        }
+
+        fn msi_compatible(&self) -> bool {
+            true
+        }
+
+        fn msi_compatiblility(&self) -> &str {
+            "arm,gic-v3-its"
+        }
+
+        fn fdt_maint_irq(&self) -> u32 {
+            KvmGICv3::ARCH_GIC_V3_MAINT_IRQ
+        }
+
+        fn msi_properties(&self) -> &[u64] {
+            &self.msi_properties
+        }
+
+        fn device_properties(&self) -> &[u64] {
+            &self.gic_properties
+        }
+
+        fn vcpu_count(&self) -> u64 {
+            self.vcpu_count
+        }
+    }
+
+    impl KvmGICDevice for KvmGICv3ITS {
+        fn version() -> u32 {
+            KvmGICv3::version()
+        }
+
+        fn create_device(
+            device: Arc<dyn hypervisor::Device>,
+            vcpu_count: u64,
+        ) -> Box<dyn GICDevice> {
+            Box::new(KvmGICv3ITS {
+                device: device,
+                gic_properties: [
+                    KvmGICv3::get_dist_addr(),
+                    KvmGICv3::get_dist_size(),
+                    KvmGICv3::get_redists_addr(vcpu_count),
+                    KvmGICv3::get_redists_size(vcpu_count),
+                ],
+                msi_properties: [
+                    KvmGICv3ITS::get_msi_addr(vcpu_count),
+                    KvmGICv3ITS::get_msi_size(),
+                ],
+                vcpu_count: vcpu_count,
+            })
+        }
+
+        fn init_device_attributes(
+            vm: &Arc<dyn hypervisor::Vm>,
+            gic_device: &Box<dyn GICDevice>,
+        ) -> Result<()> {
+            KvmGICv3::init_device_attributes(vm, gic_device)?;
+
+            let mut its_device = kvm_bindings::kvm_create_device {
+                type_: kvm_bindings::kvm_device_type_KVM_DEV_TYPE_ARM_VGIC_ITS,
+                fd: 0,
+                flags: 0,
+            };
+
+            let its_fd = vm
+                .create_device(&mut its_device)
+                .map_err(Error::CreateGIC)?;
+
+            Self::set_device_attribute(
+                &its_fd,
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ADDR,
+                u64::from(kvm_bindings::KVM_VGIC_ITS_ADDR_TYPE),
+                &KvmGICv3ITS::get_msi_addr(u64::from(gic_device.vcpu_count())) as *const u64 as u64,
+                0,
+            )?;
+
+            Self::set_device_attribute(
+                &its_fd,
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_CTRL,
+                u64::from(kvm_bindings::KVM_DEV_ARM_VGIC_CTRL_INIT),
+                0,
+                0,
+            )?;
+
+            Ok(())
+        }
+    }
+}

arch/src/aarch64/layout.rs

@@ -1,7 +1,86 @@
+// Copyright 2020 Arm Limited (or its affiliates). All rights reserved.
 // Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 // SPDX-License-Identifier: Apache-2.0
 
-/// Kernel command line start address.
-pub const CMDLINE_START: usize = 0x0;
-/// Kernel command line start address maximum size.
-pub const CMDLINE_MAX_SIZE: usize = 0x0;
+//
+// Memory layout of Aarch64 guest:
+//
+// Physical  +---------------------------------------------------------------+
+// address   |                                                               |
+// end       |                                                               |
+//           ~                   ~                       ~                   ~
+//           |                                                               |
+//           |                      Highmem PCI MMIO space                   |
+//           |                                                               |
+// RAM end   +---------------------------------------------------------------+
+// (dynamic, |                                                               |
+// including |                                                               |
+// hotplug   ~                   ~                       ~                   ~
+// memory)   |                                                               |
+//           |                            DRAM                               |
+//           |                                                               |
+// 2GB       +---------------------------------------------------------------+
+//           |                                                               |
+//           |                           Reserved                            |
+//           |                                                               |
+// 1G+256M   +---------------------------------------------------------------+
+//           |                                                               |
+//           |                        PCI MMCONFIG space                     |
+//           |                                                               |
+// 1GB       +---------------------------------------------------------------+
+//           |                                                               |
+//           |                           PCI MMIO space                      |
+//           |                                                               |
+// 256 M     +---------------------------------------------------------------|
+//           |                                                               |
+//           |                        Legacy devices space                   |
+//           |                                                               |
+// 144 M     +---------------------------------------------------------------|
+//           |                                                               |
+//           |                    Reserverd (now GIC is here)                |
+//           |                                                               |
+// 0GB       +---------------------------------------------------------------+
+//
+//
+
+use vm_memory::{GuestAddress, GuestUsize};
+
+/// Below this address will reside the GIC, above this address will reside the MMIO devices.
+pub const MAPPED_IO_START: u64 = 0x0900_0000;
+
+/// Space 0x0900_0000 ~ 0x1000_0000 is reserved for legacy devices.
+pub const LEGACY_SERIAL_MAPPED_IO_START: u64 = 0x0900_0000;
+pub const LEGACY_RTC_MAPPED_IO_START: u64 = 0x0901_0000;
+
+/// Legacy space will be allocated at once whiling setting up legacy devices.
+pub const LEGACY_DEVICES_MAPPED_IO_SIZE: u64 = 0x0700_0000;
+
+/// Starting from 0x1000_0000 (256MiB), the 768MiB (ends at 1 GiB) is used for PCIE MMIO
+pub const MEM_32BIT_DEVICES_START: GuestAddress = GuestAddress(0x1000_0000);
+pub const MEM_32BIT_DEVICES_SIZE: u64 = 0x3000_0000;
+
+/// PCI MMCONFIG space (start: after the device space at 1 GiB, length: 256MiB)
+pub const PCI_MMCONFIG_START: GuestAddress = GuestAddress(0x4000_0000);
+pub const PCI_MMCONFIG_SIZE: GuestUsize = 256 << 20;
+
+/// Start of RAM on 64 bit ARM.
+pub const RAM_64BIT_START: u64 = 0x8000_0000;
+
+/// Kernel command line maximum size.
+/// As per `arch/arm64/include/uapi/asm/setup.h`.
+pub const CMDLINE_MAX_SIZE: usize = 2048;
+
+/// Maximum size of the device tree blob as specified in https://www.kernel.org/doc/Documentation/arm64/booting.txt.
+pub const FDT_MAX_SIZE: usize = 0x20_0000;
+
+// As per virt/kvm/arm/vgic/vgic-kvm-device.c we need
+// the number of interrupts our GIC will support to be:
+// * bigger than 32
+// * less than 1023 and
+// * a multiple of 32.
+// We are setting up our interrupt controller to support a maximum of 128 interrupts.
+/// First usable interrupt on aarch64.
+pub const IRQ_BASE: u32 = 32;
+
+/// Last usable interrupt on aarch64.
+pub const IRQ_MAX: u32 = 159;

arch/src/aarch64/mod.rs

@@ -1,27 +1,269 @@
+// Copyright 2020 Arm Limited (or its affiliates). All rights reserved.
 // Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 // SPDX-License-Identifier: Apache-2.0
 
+/// Module for the flattened device tree.
+pub mod fdt;
+/// Module for the global interrupt controller configuration.
+pub mod gic;
+mod gicv2;
+mod gicv3;
+mod gicv3_its;
+/// Layout for this aarch64 system.
 pub mod layout;
+/// Logic for configuring aarch64 registers.
+pub mod regs;
 
-use memory_model::{GuestAddress, GuestMemory};
+pub use self::fdt::DeviceInfoForFDT;
+use crate::DeviceType;
+use crate::RegionType;
+use hypervisor::kvm::kvm_bindings;
+use std::collections::HashMap;
+use std::ffi::CStr;
+use std::fmt::Debug;
+use std::sync::Arc;
+use vm_memory::{
+    Address, GuestAddress, GuestAddressSpace, GuestMemory, GuestMemoryAtomic, GuestMemoryMmap,
+    GuestUsize,
+};
 
-/// Stub function that needs to be implemented when aarch64 functionality is added.
-pub fn arch_memory_regions(size: usize) -> Vec<(GuestAddress, usize, RegionType)> {
-    vec![(GuestAddress(0), size, RegionType::Ram)]
+/// Errors thrown while configuring aarch64 system.
+#[derive(Debug)]
+pub enum Error {
+    /// Failed to create a FDT.
+    SetupFDT(fdt::Error),
+
+    /// Failed to create a GIC.
+    SetupGIC(gic::Error),
+
+    /// Failed to compute the initramfs address.
+    InitramfsAddress,
+
+    /// Error configuring the general purpose registers
+    REGSConfiguration(regs::Error),
+
+    /// Error fetching prefered target
+    VcpuArmPreferredTarget(hypervisor::HypervisorVmError),
+
+    /// Error doing Vcpu Init on Arm.
+    VcpuArmInit(hypervisor::HypervisorCpuError),
 }
 
-/// Stub function that needs to be implemented when aarch64 functionality is added.
-pub fn configure_system(
-    _guest_mem: &GuestMemory,
-    _cmdline_addr: GuestAddress,
-    _cmdline_size: usize,
-    _num_cpus: u8,
-    _rsdp_addr: Option<GuestAddress>,
+impl From<Error> for super::Error {
+    fn from(e: Error) -> super::Error {
+        super::Error::AArch64Setup(e)
+    }
+}
+
+#[derive(Debug, Copy, Clone)]
+/// Specifies the entry point address where the guest must start
+/// executing code.
+pub struct EntryPoint {
+    /// Address in guest memory where the guest must start execution
+    pub entry_addr: GuestAddress,
+}
+
+/// Configure the specified VCPU, and return its MPIDR.
+pub fn configure_vcpu(
+    fd: &Arc<dyn hypervisor::Vcpu>,
+    id: u8,
+    vm: &Arc<dyn hypervisor::Vm>,
+    kernel_entry_point: Option<EntryPoint>,
+    vm_memory: &GuestMemoryAtomic<GuestMemoryMmap>,
+) -> super::Result<u64> {
+    let mut kvi: kvm_bindings::kvm_vcpu_init = kvm_bindings::kvm_vcpu_init::default();
+
+    // This reads back the kernel's preferred target type.
+    vm.get_preferred_target(&mut kvi)
+        .map_err(Error::VcpuArmPreferredTarget)?;
+    // We already checked that the capability is supported.
+    kvi.features[0] |= 1 << kvm_bindings::KVM_ARM_VCPU_PSCI_0_2;
+    // Non-boot cpus are powered off initially.
+    if id > 0 {
+        kvi.features[0] |= 1 << kvm_bindings::KVM_ARM_VCPU_POWER_OFF;
+    }
+
+    fd.vcpu_init(&kvi).map_err(Error::VcpuArmInit)?;
+    if let Some(kernel_entry_point) = kernel_entry_point {
+        regs::setup_regs(
+            fd,
+            id,
+            kernel_entry_point.entry_addr.raw_value(),
+            &vm_memory.memory(),
+        )
+        .map_err(Error::REGSConfiguration)?;
+    }
+
+    let mpidr = regs::read_mpidr(fd).map_err(Error::REGSConfiguration)?;
+    Ok(mpidr)
+}
+
+pub fn arch_memory_regions(size: GuestUsize) -> Vec<(GuestAddress, usize, RegionType)> {
+    let mut regions = Vec::new();
+    // 0 ~ 256 MiB: Reserved
+    regions.push((
+        GuestAddress(0),
+        layout::MEM_32BIT_DEVICES_START.0 as usize,
+        RegionType::Reserved,
+    ));
+
+    // 256 MiB ~ 1 G: MMIO space
+    regions.push((
+        layout::MEM_32BIT_DEVICES_START,
+        layout::MEM_32BIT_DEVICES_SIZE as usize,
+        RegionType::SubRegion,
+    ));
+
+    // 1G  ~ 2G: reserved. The leading 256M for PCIe MMCONFIG space
+    regions.push((
+        layout::PCI_MMCONFIG_START,
+        (layout::RAM_64BIT_START - layout::PCI_MMCONFIG_START.0) as usize,
+        RegionType::Reserved,
+    ));
+
+    regions.push((
+        GuestAddress(layout::RAM_64BIT_START),
+        size as usize,
+        RegionType::Ram,
+    ));
+
+    regions
+}
+
+/// Configures the system and should be called once per vm before starting vcpu threads.
+///
+/// # Arguments
+///
+/// * `guest_mem` - The memory to be used by the guest.
+/// * `num_cpus` - Number of virtual CPUs the guest will have.
+pub fn configure_system<T: DeviceInfoForFDT + Clone + Debug>(
+    vm: &Arc<dyn hypervisor::Vm>,
+    guest_mem: &GuestMemoryMmap,
+    cmdline_cstring: &CStr,
+    vcpu_count: u64,
+    vcpu_mpidr: Vec<u64>,
+    device_info: &HashMap<(DeviceType, String), T>,
+    initrd: &Option<super::InitramfsConfig>,
+    pci_space_address: &Option<(u64, u64)>,
 ) -> super::Result<()> {
+    // If pci_space_address is present, it means PCI devices are used ("pci" feature enabled).
+    // Then GITv3-ITS is required for MSI messaging.
+    // Otherwise ("mmio" feature enabled), any version of GIC is OK.
+    let gic_device = gic::kvm::create_gic(vm, vcpu_count, pci_space_address.is_some())
+        .map_err(Error::SetupGIC)?;
+
+    fdt::create_fdt(
+        guest_mem,
+        cmdline_cstring,
+        vcpu_mpidr,
+        device_info,
+        &gic_device,
+        initrd,
+        pci_space_address,
+    )
+    .map_err(Error::SetupFDT)?;
+
     Ok(())
 }
 
-/// Stub function that needs to be implemented when aarch64 functionality is added.
-pub fn get_reserved_mem_addr() -> usize {
-    0
+/// Returns the memory address where the initramfs could be loaded.
+pub fn initramfs_load_addr(
+    guest_mem: &GuestMemoryMmap,
+    initramfs_size: usize,
+) -> super::Result<u64> {
+    let round_to_pagesize = |size| (size + (super::PAGE_SIZE - 1)) & !(super::PAGE_SIZE - 1);
+    match GuestAddress(get_fdt_addr(&guest_mem))
+        .checked_sub(round_to_pagesize(initramfs_size) as u64)
+    {
+        Some(offset) => {
+            if guest_mem.address_in_range(offset) {
+                Ok(offset.raw_value())
+            } else {
+                Err(super::Error::AArch64Setup(Error::InitramfsAddress))
+            }
+        }
+        None => Err(super::Error::AArch64Setup(Error::InitramfsAddress)),
+    }
+}
+
+/// Returns the memory address where the kernel could be loaded.
+pub fn get_kernel_start() -> u64 {
+    layout::RAM_64BIT_START
+}
+
+// Auxiliary function to get the address where the device tree blob is loaded.
+fn get_fdt_addr(mem: &GuestMemoryMmap) -> u64 {
+    // If the memory allocated is smaller than the size allocated for the FDT,
+    // we return the start of the DRAM so that
+    // we allow the code to try and load the FDT.
+
+    if let Some(addr) = mem.last_addr().checked_sub(layout::FDT_MAX_SIZE as u64 - 1) {
+        if mem.address_in_range(addr) {
+            return addr.raw_value();
+        }
+    }
+
+    layout::RAM_64BIT_START
+}
+
+pub fn get_host_cpu_phys_bits() -> u8 {
+    // The value returned here is used to determine the physical address space size
+    // for a VM (IPA size).
+    // In recent kernel versions, the maxium IPA size supported by the host can be
+    // known by querying cap KVM_CAP_ARM_VM_IPA_SIZE. And the IPA size for a
+    // guest can be configured smaller.
+    // But in Cloud-Hypervisor we simply use the maxium value for the VM.
+    // Reference https://lwn.net/Articles/766767/.
+    //
+    // The correct way to query KVM_CAP_ARM_VM_IPA_SIZE is via rust-vmm/kvm-ioctls,
+    // which wraps all IOCTL's and provides easy interface to user hypervisors.
+    // For now the cap hasn't been supported. A separate patch will be submitted to
+    // rust-vmm to add it.
+    // So a hardcoded value is used here as a temporary solution.
+    // It will be replace once rust-vmm/kvm-ioctls is ready.
+    //
+    40
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_arch_memory_regions_dram() {
+        let regions = arch_memory_regions((1usize << 32) as u64); //4GB
+        assert_eq!(4, regions.len());
+        assert_eq!(GuestAddress(layout::RAM_64BIT_START), regions[3].0);
+        assert_eq!(1usize << 32, regions[3].1);
+        assert_eq!(RegionType::Ram, regions[3].2);
+    }
+
+    #[test]
+    fn test_get_fdt_addr() {
+        let mut regions = Vec::new();
+
+        regions.push((
+            GuestAddress(layout::RAM_64BIT_START),
+            (layout::FDT_MAX_SIZE - 0x1000) as usize,
+        ));
+        let mem = GuestMemoryMmap::from_ranges(&regions).expect("Cannot initialize memory");
+        assert_eq!(get_fdt_addr(&mem), layout::RAM_64BIT_START);
+        regions.clear();
+
+        regions.push((
+            GuestAddress(layout::RAM_64BIT_START),
+            (layout::FDT_MAX_SIZE) as usize,
+        ));
+        let mem = GuestMemoryMmap::from_ranges(&regions).expect("Cannot initialize memory");
+        assert_eq!(get_fdt_addr(&mem), layout::RAM_64BIT_START);
+        regions.clear();
+
+        regions.push((
+            GuestAddress(layout::RAM_64BIT_START),
+            (layout::FDT_MAX_SIZE + 0x1000) as usize,
+        ));
+        let mem = GuestMemoryMmap::from_ranges(&regions).expect("Cannot initialize memory");
+        assert_eq!(get_fdt_addr(&mem), 0x1000 + layout::RAM_64BIT_START);
+        regions.clear();
+    }
 }

arch/src/aarch64/regs.rs

@@ -0,0 +1,156 @@
+// Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style license that can be
+// found in the THIRD-PARTY file.
+
+use super::get_fdt_addr;
+use hypervisor::kvm::kvm_bindings::{
+    user_pt_regs, KVM_REG_ARM64, KVM_REG_ARM64_SYSREG, KVM_REG_ARM64_SYSREG_CRM_MASK,
+    KVM_REG_ARM64_SYSREG_CRM_SHIFT, KVM_REG_ARM64_SYSREG_CRN_MASK, KVM_REG_ARM64_SYSREG_CRN_SHIFT,
+    KVM_REG_ARM64_SYSREG_OP0_MASK, KVM_REG_ARM64_SYSREG_OP0_SHIFT, KVM_REG_ARM64_SYSREG_OP1_MASK,
+    KVM_REG_ARM64_SYSREG_OP1_SHIFT, KVM_REG_ARM64_SYSREG_OP2_MASK, KVM_REG_ARM64_SYSREG_OP2_SHIFT,
+    KVM_REG_ARM_CORE, KVM_REG_SIZE_U64,
+};
+use std::sync::Arc;
+use std::{mem, result};
+use vm_memory::GuestMemoryMmap;
+
+/// Errors thrown while setting aarch64 registers.
+#[derive(Debug)]
+pub enum Error {
+    /// Failed to set core register (PC, PSTATE or general purpose ones).
+    SetCoreRegister(hypervisor::HypervisorCpuError),
+    /// Failed to get a system register.
+    GetSysRegister(hypervisor::HypervisorCpuError),
+}
+type Result<T> = result::Result<T, Error>;
+
+#[allow(non_upper_case_globals)]
+// PSR (Processor State Register) bits.
+// Taken from arch/arm64/include/uapi/asm/ptrace.h.
+const PSR_MODE_EL1h: u64 = 0x0000_0005;
+const PSR_F_BIT: u64 = 0x0000_0040;
+const PSR_I_BIT: u64 = 0x0000_0080;
+const PSR_A_BIT: u64 = 0x0000_0100;
+const PSR_D_BIT: u64 = 0x0000_0200;
+// Taken from arch/arm64/kvm/inject_fault.c.
+const PSTATE_FAULT_BITS_64: u64 = PSR_MODE_EL1h | PSR_A_BIT | PSR_F_BIT | PSR_I_BIT | PSR_D_BIT;
+
+// Following are macros that help with getting the ID of a aarch64 core register.
+// The core register are represented by the user_pt_regs structure. Look for it in
+// arch/arm64/include/uapi/asm/ptrace.h.
+
+// This macro gets the offset of a structure (i.e `str`) member (i.e `field`) without having
+// an instance of that structure.
+// It uses a null pointer to retrieve the offset to the field.
+// Inspired by C solution: `#define offsetof(str, f) ((size_t)(&((str *)0)->f))`.
+// Doing `offset__of!(user_pt_regs, pstate)` in our rust code will trigger the following:
+// unsafe { &(*(0 as *const user_pt_regs)).pstate as *const _ as usize }
+// The dereference expression produces an lvalue, but that lvalue is not actually read from,
+// we're just doing pointer math on it, so in theory, it should safe.
+macro_rules! offset__of {
+    ($str:ty, $field:ident) => {
+        unsafe { &(*(0 as *const $str)).$field as *const _ as usize }
+    };
+}
+
+macro_rules! arm64_core_reg {
+    ($reg: tt) => {
+        // As per `kvm_arm_copy_reg_indices`, the id of a core register can be obtained like this:
+        // `const u64 core_reg = KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | i`, where i is obtained with:
+        // `for (i = 0; i < sizeof(struct kvm_regs) / sizeof(__u32); i++) {`
+        // We are using here `user_pt_regs` since this structure contains the core register and it is at
+        // the start of `kvm_regs`.
+        // struct kvm_regs {
+        //	struct user_pt_regs regs;	/* sp = sp_el0 */
+        //
+        //	__u64	sp_el1;
+        //	__u64	elr_el1;
+        //
+        //	__u64	spsr[KVM_NR_SPSR];
+        //
+        //	struct user_fpsimd_state fp_regs;
+        //};
+        // struct user_pt_regs {
+        //	__u64		regs[31];
+        //	__u64		sp;
+        //	__u64		pc;
+        //	__u64		pstate;
+        //};
+        // In our implementation we need: pc, pstate and user_pt_regs->regs[0].
+        KVM_REG_ARM64 as u64
+            | KVM_REG_SIZE_U64 as u64
+            | u64::from(KVM_REG_ARM_CORE)
+            | ((offset__of!(user_pt_regs, $reg) / mem::size_of::<u32>()) as u64)
+    };
+}
+
+// This macro computes the ID of a specific ARM64 system register similar to how
+// the kernel C macro does.
+// https://elixir.bootlin.com/linux/v4.20.17/source/arch/arm64/include/uapi/asm/kvm.h#L203
+macro_rules! arm64_sys_reg {
+    ($name: tt, $op0: tt, $op1: tt, $crn: tt, $crm: tt, $op2: tt) => {
+        const $name: u64 = KVM_REG_ARM64 as u64
+            | KVM_REG_SIZE_U64 as u64
+            | KVM_REG_ARM64_SYSREG as u64
+            | ((($op0 as u64) << KVM_REG_ARM64_SYSREG_OP0_SHIFT)
+                & KVM_REG_ARM64_SYSREG_OP0_MASK as u64)
+            | ((($op1 as u64) << KVM_REG_ARM64_SYSREG_OP1_SHIFT)
+                & KVM_REG_ARM64_SYSREG_OP1_MASK as u64)
+            | ((($crn as u64) << KVM_REG_ARM64_SYSREG_CRN_SHIFT)
+                & KVM_REG_ARM64_SYSREG_CRN_MASK as u64)
+            | ((($crm as u64) << KVM_REG_ARM64_SYSREG_CRM_SHIFT)
+                & KVM_REG_ARM64_SYSREG_CRM_MASK as u64)
+            | ((($op2 as u64) << KVM_REG_ARM64_SYSREG_OP2_SHIFT)
+                & KVM_REG_ARM64_SYSREG_OP2_MASK as u64);
+    };
+}
+
+// Constant imported from the Linux kernel:
+// https://elixir.bootlin.com/linux/v4.20.17/source/arch/arm64/include/asm/sysreg.h#L135
+arm64_sys_reg!(MPIDR_EL1, 3, 0, 0, 0, 5);
+
+/// Configure core registers for a given CPU.
+///
+/// # Arguments
+///
+/// * `vcpu` - Structure for the VCPU that holds the VCPU's fd.
+/// * `cpu_id` - Index of current vcpu.
+/// * `boot_ip` - Starting instruction pointer.
+/// * `mem` - Reserved DRAM for current VM.
+pub fn setup_regs(
+    vcpu: &Arc<dyn hypervisor::Vcpu>,
+    cpu_id: u8,
+    boot_ip: u64,
+    mem: &GuestMemoryMmap,
+) -> Result<()> {
+    // Get the register index of the PSTATE (Processor State) register.
+    vcpu.set_one_reg(arm64_core_reg!(pstate), PSTATE_FAULT_BITS_64)
+        .map_err(Error::SetCoreRegister)?;
+
+    // Other vCPUs are powered off initially awaiting PSCI wakeup.
+    if cpu_id == 0 {
+        // Setting the PC (Processor Counter) to the current program address (kernel address).
+        vcpu.set_one_reg(arm64_core_reg!(pc), boot_ip)
+            .map_err(Error::SetCoreRegister)?;
+
+        // Last mandatory thing to set -> the address pointing to the FDT (also called DTB).
+        // "The device tree blob (dtb) must be placed on an 8-byte boundary and must
+        // not exceed 2 megabytes in size." -> https://www.kernel.org/doc/Documentation/arm64/booting.txt.
+        // We are choosing to place it the end of DRAM. See `get_fdt_addr`.
+        vcpu.set_one_reg(arm64_core_reg!(regs), get_fdt_addr(mem) as u64)
+            .map_err(Error::SetCoreRegister)?;
+    }
+    Ok(())
+}
+
+/// Read the MPIDR - Multiprocessor Affinity Register.
+///
+/// # Arguments
+///
+/// * `vcpu` - Structure for the VCPU that holds the VCPU's fd.
+pub fn read_mpidr(vcpu: &Arc<dyn hypervisor::Vcpu>) -> Result<u64> {
+    vcpu.get_one_reg(MPIDR_EL1).map_err(Error::GetSysRegister)
+}

arch/src/lib.rs

@@ -1,6 +1,11 @@
+// Copyright 2020 Arm Limited (or its affiliates). All rights reserved.
+// Copyright © 2020, Oracle and/or its affiliates.
+//
 // Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 // SPDX-License-Identifier: Apache-2.0
 
+//! Implements platform specific functionality.
+//! Supported platforms: x86_64, aarch64.
 #![allow(
     clippy::unreadable_literal,
     clippy::redundant_static_lifetimes,
@@ -10,31 +15,53 @@
 )]
 
 extern crate byteorder;
-extern crate kvm_bindings;
+extern crate hypervisor;
 extern crate libc;
-
+#[macro_use]
+extern crate log;
 #[cfg(feature = "acpi")]
 extern crate acpi_tables;
 extern crate arch_gen;
-extern crate kvm_ioctls;
 extern crate linux_loader;
 extern crate vm_memory;
 
+use std::fmt;
 use std::result;
 
-#[derive(Debug, PartialEq)]
+/// Type for returning error code.
+#[derive(Debug)]
 pub enum Error {
     #[cfg(target_arch = "x86_64")]
     /// X86_64 specific error triggered during system configuration.
     X86_64Setup(x86_64::Error),
+    #[cfg(target_arch = "aarch64")]
+    /// AArch64 specific error triggered during system configuration.
+    AArch64Setup(aarch64::Error),
     /// The zero page extends past the end of guest_mem.
     ZeroPagePastRamEnd,
     /// Error writing the zero page of guest memory.
-    ZeroPageSetup,
+    ZeroPageSetup(vm_memory::GuestMemoryError),
+    /// The memory map table extends past the end of guest memory.
+    MemmapTablePastRamEnd,
+    /// Error writing memory map table to guest memory.
+    MemmapTableSetup,
+    /// The hvm_start_info structure extends past the end of guest memory.
+    StartInfoPastRamEnd,
+    /// Error writing hvm_start_info to guest memory.
+    StartInfoSetup,
+    /// Failed to compute initramfs address.
+    InitramfsAddress,
+    /// Error writing module entry to guest memory.
+    ModlistSetup(vm_memory::GuestMemoryError),
+    /// RSDP Beyond Guest Memory
+    RSDPPastRamEnd,
 }
+
+/// Type for returning public functions outcome.
 pub type Result<T> = result::Result<T, Error>;
 
-#[derive(PartialEq)]
+/// Type for memory region types.
+#[derive(PartialEq, Debug)]
 pub enum RegionType {
     /// RAM type
     Ram,
@@ -52,13 +79,15 @@ pub enum RegionType {
     Reserved,
 }
 
+/// Module for aarch64 related functionality.
 #[cfg(target_arch = "aarch64")]
 pub mod aarch64;
 
 #[cfg(target_arch = "aarch64")]
 pub use aarch64::{
-    arch_memory_regions, configure_system, get_reserved_mem_addr, layout::CMDLINE_MAX_SIZE,
-    layout::CMDLINE_START,
+    arch_memory_regions, configure_system, configure_vcpu, fdt::DeviceInfoForFDT,
+    get_host_cpu_phys_bits, get_kernel_start, initramfs_load_addr, layout,
+    layout::CMDLINE_MAX_SIZE, layout::IRQ_BASE, layout::IRQ_MAX, EntryPoint,
 };
 
 #[cfg(target_arch = "x86_64")]
@@ -66,5 +95,66 @@ pub mod x86_64;
 
 #[cfg(target_arch = "x86_64")]
 pub use x86_64::{
-    arch_memory_regions, configure_system, layout, layout::CMDLINE_MAX_SIZE, layout::CMDLINE_START,
+    arch_memory_regions, configure_system, configure_vcpu, get_host_cpu_phys_bits,
+    initramfs_load_addr, layout, layout::CMDLINE_MAX_SIZE, layout::CMDLINE_START, regs,
+    BootProtocol, CpuidPatch, CpuidReg, EntryPoint,
 };
+
+/// Safe wrapper for `sysconf(_SC_PAGESIZE)`.
+#[cfg(target_arch = "x86_64")]
+#[inline(always)]
+fn pagesize() -> usize {
+    // Trivially safe
+    unsafe { libc::sysconf(libc::_SC_PAGESIZE) as usize }
+}
+
+/// Type for passing information about the initramfs in the guest memory.
+pub struct InitramfsConfig {
+    /// Load address of initramfs in guest memory
+    pub address: vm_memory::GuestAddress,
+    /// Size of initramfs in guest memory
+    pub size: usize,
+}
+
+/// Types of devices that can get attached to this platform.
+#[derive(Clone, Debug, PartialEq, Eq, Hash, Copy)]
+pub enum DeviceType {
+    /// Device Type: Virtio.
+    Virtio(u32),
+    /// Device Type: Serial.
+    #[cfg(target_arch = "aarch64")]
+    Serial,
+    /// Device Type: RTC.
+    #[cfg(target_arch = "aarch64")]
+    RTC,
+}
+
+/// Default (smallest) memory page size for the supported architectures.
+pub const PAGE_SIZE: usize = 4096;
+
+impl fmt::Display for DeviceType {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        write!(f, "{:?}", self)
+    }
+}
+
+/// Structure to describe MMIO device information
+#[derive(Clone, Debug)]
+#[cfg(target_arch = "aarch64")]
+pub struct MMIODeviceInfo {
+    pub addr: u64,
+    pub irq: u32,
+}
+
+#[cfg(target_arch = "aarch64")]
+impl DeviceInfoForFDT for MMIODeviceInfo {
+    fn addr(&self) -> u64 {
+        self.addr
+    }
+    fn irq(&self) -> u32 {
+        self.irq
+    }
+    fn length(&self) -> u64 {
+        4096 as u64
+    }
+}

arch/src/x86_64/gdt.rs

@@ -1,3 +1,5 @@
+// Copyright © 2020, Oracle and/or its affiliates.
+//
 // Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -6,26 +8,51 @@
 // found in the LICENSE-BSD-3-Clause file.
 
 // For GDT details see arch/x86/include/asm/segment.h
-
-use kvm_bindings::kvm_segment;
+use hypervisor::x86_64::SegmentRegister;
 
 /// Constructor for a conventional segment GDT (or LDT) entry. Derived from the kernel's segment.h.
 pub fn gdt_entry(flags: u16, base: u32, limit: u32) -> u64 {
-    ((((base as u64) & 0xff000000u64) << (56 - 24))
+    (((base as u64) & 0xff000000u64) << (56 - 24))
         | (((flags as u64) & 0x0000f0ffu64) << 40)
         | (((limit as u64) & 0x000f0000u64) << (48 - 16))
         | (((base as u64) & 0x00ffffffu64) << 16)
-        | ((limit as u64) & 0x0000ffffu64))
+        | ((limit as u64) & 0x0000ffffu64)
 }
 
 fn get_base(entry: u64) -> u64 {
-    ((((entry) & 0xFF00000000000000) >> 32)
+    (((entry) & 0xFF00000000000000) >> 32)
         | (((entry) & 0x000000FF00000000) >> 16)
-        | (((entry) & 0x00000000FFFF0000) >> 16))
+        | (((entry) & 0x00000000FFFF0000) >> 16)
 }
 
+// Extract the segment limit from the GDT segment descriptor.
+//
+// In a segment descriptor, the limit field is 20 bits, so it can directly describe
+// a range from 0 to 0xFFFFF (1MByte). When G flag is set (4-KByte page granularity) it
+// scales the value in the limit field by a factor of 2^12 (4Kbytes), making the effective
+// limit range from 0xFFF (4 KBytes) to 0xFFFF_FFFF (4 GBytes).
+//
+// However, the limit field in the VMCS definition is a 32 bit field, and the limit value is not
+// automatically scaled using the G flag. This means that for a desired range of 4GB for a
+// given segment, its limit must be specified as 0xFFFF_FFFF. Therefore the method of obtaining
+// the limit from the GDT entry is not sufficient, since it only provides 20 bits when 32 bits
+// are necessary. Fortunately, we can check if the G flag is set when extracting the limit since
+// the full GDT entry is passed as an argument, and perform the scaling of the limit value to
+// return the full 32 bit value.
+//
+// The scaling mentioned above is required when using PVH boot, since the guest boots in protected
+// (32-bit) mode and must be able to access the entire 32-bit address space. It does not cause issues
+// for the case of direct boot to 64-bit (long) mode, since in 64-bit mode the processor does not
+// perform runtime limit checking on code or data segments.
 fn get_limit(entry: u64) -> u32 {
-    ((((entry) & 0x000F000000000000) >> 32) | ((entry) & 0x000000000000FFFF)) as u32
+    let limit: u32 =
+        ((((entry) & 0x000F000000000000) >> 32) | ((entry) & 0x000000000000FFFF)) as u32;
+
+    // Perform manual limit scaling if G flag is set
+    match get_g(entry) {
+        0 => limit,
+        _ => ((limit << 12) | 0xFFF), // G flag is either 0 or 1
+    }
 }
 
 fn get_g(entry: u64) -> u8 {
@@ -60,14 +87,14 @@ fn get_type(entry: u64) -> u8 {
     ((entry & 0x00000F0000000000) >> 40) as u8
 }
 
-/// Automatically build the kvm struct for SET_SREGS from the kernel bit fields.
+/// Automatically build the struct for SET_SREGS from the kernel bit fields.
 ///
 /// # Arguments
 ///
 /// * `entry` - The gdt entry.
 /// * `table_index` - Index of the entry in the gdt table.
-pub fn kvm_segment_from_gdt(entry: u64, table_index: u8) -> kvm_segment {
-    kvm_segment {
+pub fn segment_from_gdt(entry: u64, table_index: u8) -> SegmentRegister {
+    SegmentRegister {
         base: get_base(entry),
         limit: get_limit(entry),
         selector: (table_index * 8) as u16,
@@ -94,7 +121,7 @@ mod tests {
     #[test]
     fn field_parse() {
         let gdt = gdt_entry(0xA09B, 0x100000, 0xfffff);
-        let seg = kvm_segment_from_gdt(gdt, 0);
+        let seg = segment_from_gdt(gdt, 0);
         // 0xA09B
         // 'A'
         assert_eq!(0x1, seg.g);
@@ -109,7 +136,7 @@ mod tests {
         assert_eq!(0xB, seg.type_);
         // base and limit
         assert_eq!(0x100000, seg.base);
-        assert_eq!(0xfffff, seg.limit);
+        assert_eq!(0xffffffff, seg.limit);
         assert_eq!(0x0, seg.unusable);
     }
 }

arch/src/x86_64/interrupts.rs

@@ -8,27 +8,27 @@
 use std::io::Cursor;
 use std::mem;
 use std::result;
+use std::sync::Arc;
 
 use byteorder::{LittleEndian, ReadBytesExt, WriteBytesExt};
 
-use kvm_bindings::kvm_lapic_state;
-use kvm_ioctls;
+use hypervisor::x86_64::LapicState;
 
 #[derive(Debug)]
 pub enum Error {
-    GetLapic(kvm_ioctls::Error),
-    SetLapic(kvm_ioctls::Error),
+    GetLapic(anyhow::Error),
+    SetLapic(anyhow::Error),
 }
 
-pub type Result<T> = result::Result<T, Error>;
+pub type Result<T> = result::Result<T, hypervisor::HypervisorCpuError>;
 
 // Defines poached from apicdef.h kernel header.
-const APIC_LVT0: usize = 0x350;
-const APIC_LVT1: usize = 0x360;
-const APIC_MODE_NMI: u32 = 0x4;
-const APIC_MODE_EXTINT: u32 = 0x7;
+pub const APIC_LVT0: usize = 0x350;
+pub const APIC_LVT1: usize = 0x360;
+pub const APIC_MODE_NMI: u32 = 0x4;
+pub const APIC_MODE_EXTINT: u32 = 0x7;
 
-fn get_klapic_reg(klapic: &kvm_lapic_state, reg_offset: usize) -> u32 {
+pub fn get_klapic_reg(klapic: &LapicState, reg_offset: usize) -> u32 {
     let sliceu8 = unsafe {
         // This array is only accessed as parts of a u32 word, so interpret it as a u8 array.
         // Cursors are only readable on arrays of u8, not i8(c_char).
@@ -41,7 +41,7 @@ fn get_klapic_reg(klapic: &kvm_lapic_state, reg_offset: usize) -> u32 {
         .expect("Failed to read klapic register")
 }
 
-fn set_klapic_reg(klapic: &mut kvm_lapic_state, reg_offset: usize, value: u32) {
+pub fn set_klapic_reg(klapic: &mut LapicState, reg_offset: usize, value: u32) {
     let sliceu8 = unsafe {
         // This array is only accessed as parts of a u32 word, so interpret it as a u8 array.
         // Cursors are only readable on arrays of u8, not i8(c_char).
@@ -54,16 +54,16 @@ fn set_klapic_reg(klapic: &mut kvm_lapic_state, reg_offset: usize, value: u32) {
         .expect("Failed to write klapic register")
 }
 
-fn set_apic_delivery_mode(reg: u32, mode: u32) -> u32 {
-    (((reg) & !0x700) | ((mode) << 8))
+pub fn set_apic_delivery_mode(reg: u32, mode: u32) -> u32 {
+    ((reg) & !0x700) | ((mode) << 8)
 }
 
 /// Configures LAPICs.  LAPIC0 is set for external interrupts, LAPIC1 is set for NMI.
 ///
 /// # Arguments
 /// * `vcpu` - The VCPU object to configure.
-pub fn set_lint(vcpu: &kvm_ioctls::VcpuFd) -> Result<()> {
-    let mut klapic = vcpu.get_lapic().map_err(Error::GetLapic)?;
+pub fn set_lint(vcpu: &Arc<dyn hypervisor::Vcpu>) -> Result<()> {
+    let mut klapic = vcpu.get_lapic()?;
 
     let lvt_lint0 = get_klapic_reg(&klapic, APIC_LVT0);
     set_klapic_reg(
@@ -78,24 +78,23 @@ pub fn set_lint(vcpu: &kvm_ioctls::VcpuFd) -> Result<()> {
         set_apic_delivery_mode(lvt_lint1, APIC_MODE_NMI),
     );
 
-    vcpu.set_lapic(&klapic).map_err(Error::SetLapic)
+    vcpu.set_lapic(&klapic)
 }
 
 #[cfg(test)]
 mod tests {
-    extern crate kvm_ioctls;
+
     extern crate rand;
     use self::rand::Rng;
 
     use super::*;
-    use kvm_ioctls::Kvm;
 
     const KVM_APIC_REG_SIZE: usize = 0x400;
 
     #[test]
     fn test_set_and_get_klapic_reg() {
         let reg_offset = 0x340;
-        let mut klapic = kvm_lapic_state::default();
+        let mut klapic = LapicState::default();
         set_klapic_reg(&mut klapic, reg_offset, 3);
         let value = get_klapic_reg(&klapic, reg_offset);
         assert_eq!(value, 3);
@@ -105,7 +104,7 @@ mod tests {
     #[should_panic]
     fn test_set_and_get_klapic_out_of_bounds() {
         let reg_offset = KVM_APIC_REG_SIZE + 10;
-        let mut klapic = kvm_lapic_state::default();
+        let mut klapic = LapicState::default();
         set_klapic_reg(&mut klapic, reg_offset, 3);
     }
 
@@ -119,40 +118,4 @@ mod tests {
         let after: Vec<u32> = v.iter().map(|x| ((*x & !0x700) | ((2) << 8))).collect();
         assert_eq!(v, after);
     }
-
-    #[test]
-    fn test_setlint() {
-        let kvm = kvm_ioctls::Kvm::new().unwrap();
-        assert!(kvm.check_extension(kvm_ioctls::Cap::Irqchip));
-        let vm = kvm.create_vm().unwrap();
-        //the get_lapic ioctl will fail if there is no irqchip created beforehand.
-        assert!(vm.create_irq_chip().is_ok());
-        let vcpu = vm.create_vcpu(0).unwrap();
-        let klapic_before: kvm_lapic_state = vcpu.get_lapic().unwrap();
-
-        // Compute the value that is expected to represent LVT0 and LVT1.
-        let lint0 = get_klapic_reg(&klapic_before, APIC_LVT0);
-        let lint1 = get_klapic_reg(&klapic_before, APIC_LVT1);
-        let lint0_mode_expected = set_apic_delivery_mode(lint0, APIC_MODE_EXTINT);
-        let lint1_mode_expected = set_apic_delivery_mode(lint1, APIC_MODE_NMI);
-
-        set_lint(&vcpu).unwrap();
-
-        // Compute the value that represents LVT0 and LVT1 after set_lint.
-        let klapic_actual: kvm_lapic_state = vcpu.get_lapic().unwrap();
-        let lint0_mode_actual = get_klapic_reg(&klapic_actual, APIC_LVT0);
-        let lint1_mode_actual = get_klapic_reg(&klapic_actual, APIC_LVT1);
-        assert_eq!(lint0_mode_expected, lint0_mode_actual);
-        assert_eq!(lint1_mode_expected, lint1_mode_actual);
-    }
-
-    #[test]
-    fn test_setlint_fails() {
-        let kvm = Kvm::new().unwrap();
-        let vm = kvm.create_vm().unwrap();
-        let vcpu = vm.create_vcpu(0).unwrap();
-        // 'get_lapic' ioctl triggered by the 'set_lint' function will fail if there is no
-        // irqchip created beforehand.
-        assert!(set_lint(&vcpu).is_err());
-    }
 }

arch/src/x86_64/layout.rs

@@ -1,3 +1,5 @@
+// Copyright © 2020, Oracle and/or its affiliates.
+//
 // Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -26,6 +28,17 @@ pub const LOW_RAM_START: GuestAddress = GuestAddress(0x0);
 pub const BOOT_GDT_START: GuestAddress = GuestAddress(0x500);
 pub const BOOT_IDT_START: GuestAddress = GuestAddress(0x520);
 
+/// Address for the hvm_start_info struct used in PVH boot
+pub const PVH_INFO_START: GuestAddress = GuestAddress(0x6000);
+
+/// Starting address of array of modules of hvm_modlist_entry type.
+/// Used to enable initrd support using the PVH boot ABI.
+pub const MODLIST_START: GuestAddress = GuestAddress(0x6040);
+
+/// Address of memory map table used in PVH boot. Can overlap
+/// with the zero page address since they are mutually exclusive.
+pub const MEMMAP_START: GuestAddress = GuestAddress(0x7000);
+
 /// The 'zero page', a.k.a linux kernel bootparams.
 pub const ZERO_PAGE_START: GuestAddress = GuestAddress(0x7000);
 
@@ -34,9 +47,10 @@ pub const BOOT_STACK_START: GuestAddress = GuestAddress(0x8000);
 pub const BOOT_STACK_POINTER: GuestAddress = GuestAddress(0x8ff0);
 
 // Initial pagetables.
-pub const PML4_START: GuestAddress = GuestAddress(0x9000);
-pub const PDPTE_START: GuestAddress = GuestAddress(0xa000);
-pub const PDE_START: GuestAddress = GuestAddress(0xb000);
+pub const PML5_START: GuestAddress = GuestAddress(0x9000);
+pub const PML4_START: GuestAddress = GuestAddress(0xa000);
+pub const PDPTE_START: GuestAddress = GuestAddress(0xb000);
+pub const PDE_START: GuestAddress = GuestAddress(0xc000);
 
 /// Kernel command line start address.
 pub const CMDLINE_START: GuestAddress = GuestAddress(0x20000);
@@ -56,6 +70,8 @@ pub const EBDA_START: GuestAddress = GuestAddress(0xa0000);
 // ACPI RSDP table
 pub const RSDP_POINTER: GuestAddress = EBDA_START;
 
+pub const SMBIOS_START: u64 = 0xf0000; // First possible location per the spec.
+
 // == End of "EBDA" range ==
 
 // ** High RAM (start: 1MiB, length: 3071MiB) **
@@ -65,18 +81,18 @@ pub const HIGH_RAM_START: GuestAddress = GuestAddress(0x100000);
 
 // ** 32-bit reserved area (start: 3GiB, length: 1GiB) **
 pub const MEM_32BIT_RESERVED_START: GuestAddress = GuestAddress(0xc000_0000);
-pub const MEM_32BIT_RESERVED_SIZE: GuestUsize = (1024 << 20);
+pub const MEM_32BIT_RESERVED_SIZE: GuestUsize = 1024 << 20;
 
 // == Fixed constants within the "32-bit reserved" range ==
 
 // Sub range: 32-bit PCI devices (start: 3GiB, length: 640Mib)
 pub const MEM_32BIT_DEVICES_START: GuestAddress = MEM_32BIT_RESERVED_START;
-pub const MEM_32BIT_DEVICES_SIZE: GuestUsize = (640 << 20);
+pub const MEM_32BIT_DEVICES_SIZE: GuestUsize = 640 << 20;
 
 // PCI MMCONFIG space (start: after the device space, length: 256MiB)
 pub const PCI_MMCONFIG_START: GuestAddress =
     GuestAddress(MEM_32BIT_DEVICES_START.0 + MEM_32BIT_DEVICES_SIZE);
-pub const PCI_MMCONFIG_SIZE: GuestUsize = (256 << 20);
+pub const PCI_MMCONFIG_SIZE: GuestUsize = 256 << 20;
 
 // IOAPIC
 pub const IOAPIC_START: GuestAddress = GuestAddress(0xfec0_0000);

arch/src/x86_64/mod.rs

@@ -1,26 +1,131 @@
+// Copyright © 2020, Oracle and/or its affiliates.
+//
 // Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 // SPDX-License-Identifier: Apache-2.0
 //
 // Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE-BSD-3-Clause file.
-
+use std::sync::Arc;
 mod gdt;
 pub mod interrupts;
 pub mod layout;
+#[cfg(not(feature = "acpi"))]
 mod mptable;
 pub mod regs;
-
+use crate::InitramfsConfig;
 use crate::RegionType;
+use hypervisor::{CpuId, CpuIdEntry, CPUID_FLAG_VALID_INDEX};
 use linux_loader::loader::bootparam::{boot_params, setup_header};
+use linux_loader::loader::elf::start_info::{
+    hvm_memmap_table_entry, hvm_modlist_entry, hvm_start_info,
+};
 use std::mem;
 use vm_memory::{
-    Address, ByteValued, Bytes, GuestAddress, GuestMemory, GuestMemoryMmap, GuestUsize,
+    Address, ByteValued, Bytes, GuestAddress, GuestAddressSpace, GuestMemory, GuestMemoryAtomic,
+    GuestMemoryMmap, GuestMemoryRegion, GuestUsize,
 };
+mod smbios;
+
+#[derive(Debug, Copy, Clone)]
+pub enum BootProtocol {
+    LinuxBoot,
+    PvhBoot,
+}
+
+impl ::std::fmt::Display for BootProtocol {
+    fn fmt(&self, f: &mut ::std::fmt::Formatter) -> ::std::fmt::Result {
+        match self {
+            BootProtocol::LinuxBoot => write!(f, "Linux 64-bit boot protocol"),
+            BootProtocol::PvhBoot => write!(f, "PVH boot protocol"),
+        }
+    }
+}
+
+#[derive(Debug, Copy, Clone)]
+/// Specifies the entry point address where the guest must start
+/// executing code, as well as which of the supported boot protocols
+/// is to be used to configure the guest initial state.
+pub struct EntryPoint {
+    /// Address in guest memory where the guest must start execution
+    pub entry_addr: GuestAddress,
+    /// Specifies which boot protocol to use
+    pub protocol: BootProtocol,
+    /// This field is used for bzImage to fill zero page
+    pub setup_header: Option<setup_header>,
+}
 
 const E820_RAM: u32 = 1;
 const E820_RESERVED: u32 = 2;
 
+#[derive(Clone)]
+pub struct SgxEpcSection {
+    start: GuestAddress,
+    size: GuestUsize,
+}
+
+impl SgxEpcSection {
+    pub fn new(start: GuestAddress, size: GuestUsize) -> Self {
+        SgxEpcSection { start, size }
+    }
+    pub fn start(&self) -> GuestAddress {
+        self.start
+    }
+    pub fn size(&self) -> GuestUsize {
+        self.size
+    }
+}
+
+#[derive(Clone)]
+pub struct SgxEpcRegion {
+    start: GuestAddress,
+    size: GuestUsize,
+    epc_sections: Vec<SgxEpcSection>,
+}
+
+impl SgxEpcRegion {
+    pub fn new(start: GuestAddress, size: GuestUsize) -> Self {
+        SgxEpcRegion {
+            start,
+            size,
+            epc_sections: Vec::new(),
+        }
+    }
+    pub fn start(&self) -> GuestAddress {
+        self.start
+    }
+    pub fn size(&self) -> GuestUsize {
+        self.size
+    }
+    pub fn epc_sections(&self) -> &Vec<SgxEpcSection> {
+        &self.epc_sections
+    }
+    pub fn push(&mut self, epc_section: SgxEpcSection) {
+        self.epc_sections.push(epc_section);
+    }
+}
+
+// This is a workaround to the Rust enforcement specifying that any implementation of a foreign
+// trait (in this case `DataInit`) where:
+// *    the type that is implementing the trait is foreign or
+// *    all of the parameters being passed to the trait (if there are any) are also foreign
+// is prohibited.
+#[derive(Copy, Clone, Default)]
+struct StartInfoWrapper(hvm_start_info);
+
+// It is safe to initialize StartInfoWrapper which is a wrapper over `hvm_start_info` (a series of ints).
+unsafe impl ByteValued for StartInfoWrapper {}
+
+#[derive(Copy, Clone, Default)]
+struct MemmapTableEntryWrapper(hvm_memmap_table_entry);
+
+unsafe impl ByteValued for MemmapTableEntryWrapper {}
+
+#[derive(Copy, Clone, Default)]
+struct ModlistEntryWrapper(hvm_modlist_entry);
+
+unsafe impl ByteValued for ModlistEntryWrapper {}
+
 // This is a workaround to the Rust enforcement specifying that any implementation of a foreign
 // trait (in this case `DataInit`) where:
 // *    the type that is implementing the trait is foreign or
@@ -32,12 +137,43 @@ struct BootParamsWrapper(boot_params);
 // It is safe to initialize BootParamsWrap which is a wrapper over `boot_params` (a series of ints).
 unsafe impl ByteValued for BootParamsWrapper {}
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug)]
 pub enum Error {
     /// Invalid e820 setup params.
     E820Configuration,
+    #[cfg(not(feature = "acpi"))]
     /// Error writing MP table to memory.
     MpTableSetup(mptable::Error),
+
+    /// Error configuring the general purpose registers
+    REGSConfiguration(regs::Error),
+
+    /// Error configuring the special registers
+    SREGSConfiguration(regs::Error),
+
+    /// Error configuring the floating point related registers
+    FPUConfiguration(regs::Error),
+
+    /// Error configuring the MSR registers
+    MSRSConfiguration(regs::Error),
+
+    /// Failed to set supported CPUs.
+    SetSupportedCpusFailed(anyhow::Error),
+
+    /// Cannot set the local interruption due to bad configuration.
+    LocalIntConfiguration(anyhow::Error),
+
+    /// Error setting up SMBIOS table
+    SmbiosSetup(smbios::Error),
+
+    /// Could not find any SGX EPC section
+    NoSgxEpcSection,
+
+    /// Missing SGX CPU feature
+    MissingSgxFeature,
+
+    /// Missing SGX_LC CPU feature
+    MissingSgxLaunchControlFeature,
 }
 
 impl From<Error> for super::Error {
@@ -46,6 +182,183 @@ impl From<Error> for super::Error {
     }
 }
 
+#[allow(dead_code)]
+#[derive(Copy, Clone)]
+pub enum CpuidReg {
+    EAX,
+    EBX,
+    ECX,
+    EDX,
+}
+
+pub struct CpuidPatch {
+    pub function: u32,
+    pub index: u32,
+    pub flags_bit: Option<u8>,
+    pub eax_bit: Option<u8>,
+    pub ebx_bit: Option<u8>,
+    pub ecx_bit: Option<u8>,
+    pub edx_bit: Option<u8>,
+}
+
+impl CpuidPatch {
+    pub fn set_cpuid_reg(
+        cpuid: &mut CpuId,
+        function: u32,
+        index: Option<u32>,
+        reg: CpuidReg,
+        value: u32,
+    ) {
+        let entries = cpuid.as_mut_slice();
+
+        let mut entry_found = false;
+        for entry in entries.iter_mut() {
+            if entry.function == function && (index == None || index.unwrap() == entry.index) {
+                entry_found = true;
+                match reg {
+                    CpuidReg::EAX => {
+                        entry.eax = value;
+                    }
+                    CpuidReg::EBX => {
+                        entry.ebx = value;
+                    }
+                    CpuidReg::ECX => {
+                        entry.ecx = value;
+                    }
+                    CpuidReg::EDX => {
+                        entry.edx = value;
+                    }
+                }
+            }
+        }
+
+        if entry_found {
+            return;
+        }
+
+        // Entry not found, so let's add it.
+        if let Some(index) = index {
+            let mut entry = CpuIdEntry {
+                function,
+                index,
+                flags: CPUID_FLAG_VALID_INDEX,
+                ..Default::default()
+            };
+            match reg {
+                CpuidReg::EAX => {
+                    entry.eax = value;
+                }
+                CpuidReg::EBX => {
+                    entry.ebx = value;
+                }
+                CpuidReg::ECX => {
+                    entry.ecx = value;
+                }
+                CpuidReg::EDX => {
+                    entry.edx = value;
+                }
+            }
+
+            if let Err(e) = cpuid.push(entry) {
+                error!("Failed adding new CPUID entry: {:?}", e);
+            }
+        }
+    }
+
+    pub fn patch_cpuid(cpuid: &mut CpuId, patches: Vec<CpuidPatch>) {
+        let entries = cpuid.as_mut_slice();
+
+        for entry in entries.iter_mut() {
+            for patch in patches.iter() {
+                if entry.function == patch.function && entry.index == patch.index {
+                    if let Some(flags_bit) = patch.flags_bit {
+                        entry.flags |= 1 << flags_bit;
+                    }
+                    if let Some(eax_bit) = patch.eax_bit {
+                        entry.eax |= 1 << eax_bit;
+                    }
+                    if let Some(ebx_bit) = patch.ebx_bit {
+                        entry.ebx |= 1 << ebx_bit;
+                    }
+                    if let Some(ecx_bit) = patch.ecx_bit {
+                        entry.ecx |= 1 << ecx_bit;
+                    }
+                    if let Some(edx_bit) = patch.edx_bit {
+                        entry.edx |= 1 << edx_bit;
+                    }
+                }
+            }
+        }
+    }
+
+    pub fn is_feature_enabled(
+        cpuid: &CpuId,
+        function: u32,
+        index: u32,
+        reg: CpuidReg,
+        feature_bit: usize,
+    ) -> bool {
+        let entries = cpuid.as_slice();
+        let mask = 1 << feature_bit;
+
+        for entry in entries.iter() {
+            if entry.function == function && entry.index == index {
+                let reg_val: u32;
+                match reg {
+                    CpuidReg::EAX => {
+                        reg_val = entry.eax;
+                    }
+                    CpuidReg::EBX => {
+                        reg_val = entry.ebx;
+                    }
+                    CpuidReg::ECX => {
+                        reg_val = entry.ecx;
+                    }
+                    CpuidReg::EDX => {
+                        reg_val = entry.edx;
+                    }
+                }
+
+                return (reg_val & mask) == mask;
+            }
+        }
+
+        false
+    }
+}
+
+pub fn configure_vcpu(
+    fd: &Arc<dyn hypervisor::Vcpu>,
+    id: u8,
+    kernel_entry_point: Option<EntryPoint>,
+    vm_memory: &GuestMemoryAtomic<GuestMemoryMmap>,
+    cpuid: CpuId,
+) -> super::Result<()> {
+    let mut cpuid = cpuid;
+    CpuidPatch::set_cpuid_reg(&mut cpuid, 0xb, None, CpuidReg::EDX, u32::from(id));
+    CpuidPatch::set_cpuid_reg(&mut cpuid, 0x1f, None, CpuidReg::EDX, u32::from(id));
+    fd.set_cpuid2(&cpuid)
+        .map_err(|e| Error::SetSupportedCpusFailed(e.into()))?;
+
+    regs::setup_msrs(fd).map_err(Error::MSRSConfiguration)?;
+    if let Some(kernel_entry_point) = kernel_entry_point {
+        // Safe to unwrap because this method is called after the VM is configured
+        regs::setup_regs(
+            fd,
+            kernel_entry_point.entry_addr.raw_value(),
+            layout::BOOT_STACK_POINTER.raw_value(),
+            layout::ZERO_PAGE_START.raw_value(),
+            kernel_entry_point.protocol,
+        )
+        .map_err(Error::REGSConfiguration)?;
+        regs::setup_fpu(fd).map_err(Error::FPUConfiguration)?;
+        regs::setup_sregs(&vm_memory.memory(), fd, kernel_entry_point.protocol)
+            .map_err(Error::SREGSConfiguration)?;
+    }
+    interrupts::set_lint(fd).map_err(|e| Error::LocalIntConfiguration(e.into()))?;
+    Ok(())
+}
+
 /// Returns a Vec of the valid memory addresses.
 /// These should be used to configure the GuestMemory structure for the platform.
 /// For x86_64 all addresses are valid from the start of the kernel except a
@@ -106,36 +419,239 @@ pub fn configure_system(
     guest_mem: &GuestMemoryMmap,
     cmdline_addr: GuestAddress,
     cmdline_size: usize,
-    num_cpus: u8,
+    initramfs: &Option<InitramfsConfig>,
+    _num_cpus: u8,
     setup_hdr: Option<setup_header>,
     rsdp_addr: Option<GuestAddress>,
+    boot_prot: BootProtocol,
+    sgx_epc_region: Option<SgxEpcRegion>,
+) -> super::Result<()> {
+    smbios::setup_smbios(guest_mem).map_err(Error::SmbiosSetup)?;
+
+    // Note that this puts the mptable at the last 1k of Linux's 640k base RAM
+    #[cfg(not(feature = "acpi"))]
+    mptable::setup_mptable(guest_mem, _num_cpus).map_err(Error::MpTableSetup)?;
+
+    // Check that the RAM is not smaller than the RSDP start address
+    if let Some(rsdp_addr) = rsdp_addr {
+        if rsdp_addr.0 > guest_mem.last_addr().0 {
+            return Err(super::Error::RSDPPastRamEnd);
+        }
+    }
+
+    match boot_prot {
+        BootProtocol::PvhBoot => {
+            configure_pvh(
+                guest_mem,
+                cmdline_addr,
+                initramfs,
+                rsdp_addr,
+                sgx_epc_region,
+            )?;
+        }
+        BootProtocol::LinuxBoot => {
+            configure_64bit_boot(
+                guest_mem,
+                cmdline_addr,
+                cmdline_size,
+                initramfs,
+                setup_hdr,
+                rsdp_addr,
+                sgx_epc_region,
+            )?;
+        }
+    }
+
+    Ok(())
+}
+
+fn configure_pvh(
+    guest_mem: &GuestMemoryMmap,
+    cmdline_addr: GuestAddress,
+    initramfs: &Option<InitramfsConfig>,
+    rsdp_addr: Option<GuestAddress>,
+    sgx_epc_region: Option<SgxEpcRegion>,
+) -> super::Result<()> {
+    const XEN_HVM_START_MAGIC_VALUE: u32 = 0x336ec578;
+
+    let mut start_info: StartInfoWrapper = StartInfoWrapper(hvm_start_info::default());
+
+    start_info.0.magic = XEN_HVM_START_MAGIC_VALUE;
+    start_info.0.version = 1; // pvh has version 1
+    start_info.0.nr_modules = 0;
+    start_info.0.cmdline_paddr = cmdline_addr.raw_value() as u64;
+    start_info.0.memmap_paddr = layout::MEMMAP_START.raw_value();
+
+    if let Some(rsdp_addr) = rsdp_addr {
+        start_info.0.rsdp_paddr = rsdp_addr.0;
+    }
+
+    if let Some(initramfs_config) = initramfs {
+        // The initramfs has been written to guest memory already, here we just need to
+        // create the module structure that describes it.
+        let ramdisk_mod: ModlistEntryWrapper = ModlistEntryWrapper(hvm_modlist_entry {
+            paddr: initramfs_config.address.raw_value(),
+            size: initramfs_config.size as u64,
+            ..Default::default()
+        });
+
+        start_info.0.nr_modules += 1;
+        start_info.0.modlist_paddr = layout::MODLIST_START.raw_value();
+
+        // Write the modlist struct to guest memory.
+        guest_mem
+            .write_obj(ramdisk_mod, layout::MODLIST_START)
+            .map_err(super::Error::ModlistSetup)?;
+    }
+
+    // Vector to hold the memory maps which needs to be written to guest memory
+    // at MEMMAP_START after all of the mappings are recorded.
+    let mut memmap: Vec<hvm_memmap_table_entry> = Vec::new();
+
+    // Create the memory map entries.
+    add_memmap_entry(&mut memmap, 0, layout::EBDA_START.raw_value(), E820_RAM)?;
+
+    let mem_end = guest_mem.last_addr();
+
+    if mem_end < layout::MEM_32BIT_RESERVED_START {
+        add_memmap_entry(
+            &mut memmap,
+            layout::HIGH_RAM_START.raw_value(),
+            mem_end.unchecked_offset_from(layout::HIGH_RAM_START) + 1,
+            E820_RAM,
+        )?;
+    } else {
+        add_memmap_entry(
+            &mut memmap,
+            layout::HIGH_RAM_START.raw_value(),
+            layout::MEM_32BIT_RESERVED_START.unchecked_offset_from(layout::HIGH_RAM_START),
+            E820_RAM,
+        )?;
+        if mem_end > layout::RAM_64BIT_START {
+            add_memmap_entry(
+                &mut memmap,
+                layout::RAM_64BIT_START.raw_value(),
+                mem_end.unchecked_offset_from(layout::RAM_64BIT_START) + 1,
+                E820_RAM,
+            )?;
+        }
+    }
+
+    add_memmap_entry(
+        &mut memmap,
+        layout::PCI_MMCONFIG_START.0,
+        layout::PCI_MMCONFIG_SIZE,
+        E820_RESERVED,
+    )?;
+
+    if let Some(sgx_epc_region) = sgx_epc_region {
+        add_memmap_entry(
+            &mut memmap,
+            sgx_epc_region.start().raw_value(),
+            sgx_epc_region.size() as u64,
+            E820_RESERVED,
+        )?;
+    }
+
+    start_info.0.memmap_entries = memmap.len() as u32;
+
+    // Copy the vector with the memmap table to the MEMMAP_START address
+    // which is already saved in the memmap_paddr field of hvm_start_info struct.
+    let mut memmap_start_addr = layout::MEMMAP_START;
+
+    guest_mem
+        .checked_offset(
+            memmap_start_addr,
+            mem::size_of::<hvm_memmap_table_entry>() * start_info.0.memmap_entries as usize,
+        )
+        .ok_or(super::Error::MemmapTablePastRamEnd)?;
+
+    // For every entry in the memmap vector, create a MemmapTableEntryWrapper
+    // and write it to guest memory.
+    for memmap_entry in memmap {
+        let map_entry_wrapper: MemmapTableEntryWrapper = MemmapTableEntryWrapper(memmap_entry);
+
+        guest_mem
+            .write_obj(map_entry_wrapper, memmap_start_addr)
+            .map_err(|_| super::Error::MemmapTableSetup)?;
+        memmap_start_addr =
+            memmap_start_addr.unchecked_add(mem::size_of::<hvm_memmap_table_entry>() as u64);
+    }
+
+    // The hvm_start_info struct itself must be stored at PVH_START_INFO
+    // address, and %rbx will be initialized to contain PVH_INFO_START prior to
+    // starting the guest, as required by the PVH ABI.
+    let start_info_addr = layout::PVH_INFO_START;
+
+    guest_mem
+        .checked_offset(start_info_addr, mem::size_of::<hvm_start_info>())
+        .ok_or(super::Error::StartInfoPastRamEnd)?;
+
+    // Write the start_info struct to guest memory.
+    guest_mem
+        .write_obj(start_info, start_info_addr)
+        .map_err(|_| super::Error::StartInfoSetup)?;
+
+    Ok(())
+}
+
+fn add_memmap_entry(
+    memmap: &mut Vec<hvm_memmap_table_entry>,
+    addr: u64,
+    size: u64,
+    mem_type: u32,
+) -> Result<(), Error> {
+    // Add the table entry to the vector
+    memmap.push(hvm_memmap_table_entry {
+        addr,
+        size,
+        type_: mem_type,
+        reserved: 0,
+    });
+
+    Ok(())
+}
+
+fn configure_64bit_boot(
+    guest_mem: &GuestMemoryMmap,
+    cmdline_addr: GuestAddress,
+    cmdline_size: usize,
+    initramfs: &Option<InitramfsConfig>,
+    setup_hdr: Option<setup_header>,
+    rsdp_addr: Option<GuestAddress>,
+    sgx_epc_region: Option<SgxEpcRegion>,
 ) -> super::Result<()> {
     const KERNEL_BOOT_FLAG_MAGIC: u16 = 0xaa55;
     const KERNEL_HDR_MAGIC: u32 = 0x53726448;
     const KERNEL_LOADER_OTHER: u8 = 0xff;
     const KERNEL_MIN_ALIGNMENT_BYTES: u32 = 0x1000000; // Must be non-zero.
 
-    // Note that this puts the mptable at the last 1k of Linux's 640k base RAM
-    mptable::setup_mptable(guest_mem, num_cpus).map_err(Error::MpTableSetup)?;
-
     let mut params: BootParamsWrapper = BootParamsWrapper(boot_params::default());
 
     if let Some(hdr) = setup_hdr {
+        // We should use the header if the loader provides one (e.g. from a bzImage).
         params.0.hdr = hdr;
-        params.0.hdr.cmd_line_ptr = cmdline_addr.raw_value() as u32;
-        params.0.hdr.cmdline_size = cmdline_size as u32;
     } else {
-        params.0.hdr.type_of_loader = KERNEL_LOADER_OTHER;
         params.0.hdr.boot_flag = KERNEL_BOOT_FLAG_MAGIC;
         params.0.hdr.header = KERNEL_HDR_MAGIC;
-        params.0.hdr.cmd_line_ptr = cmdline_addr.raw_value() as u32;
-        params.0.hdr.cmdline_size = cmdline_size as u32;
         params.0.hdr.kernel_alignment = KERNEL_MIN_ALIGNMENT_BYTES;
     };
 
+    // Common bootparams settings
+    if params.0.hdr.type_of_loader == 0 {
+        params.0.hdr.type_of_loader = KERNEL_LOADER_OTHER;
+    }
+    params.0.hdr.cmd_line_ptr = cmdline_addr.raw_value() as u32;
+    params.0.hdr.cmdline_size = cmdline_size as u32;
+
+    if let Some(initramfs_config) = initramfs {
+        params.0.hdr.ramdisk_image = initramfs_config.address.raw_value() as u32;
+        params.0.hdr.ramdisk_size = initramfs_config.size as u32;
+    }
+
     add_e820_entry(&mut params.0, 0, layout::EBDA_START.raw_value(), E820_RAM)?;
 
-    let mem_end = guest_mem.end_addr();
+    let mem_end = guest_mem.last_addr();
     if mem_end < layout::MEM_32BIT_RESERVED_START {
         add_e820_entry(
             &mut params.0,
@@ -167,6 +683,15 @@ pub fn configure_system(
         E820_RESERVED,
     )?;
 
+    if let Some(sgx_epc_region) = sgx_epc_region {
+        add_e820_entry(
+            &mut params.0,
+            sgx_epc_region.start().raw_value(),
+            sgx_epc_region.size() as u64,
+            E820_RESERVED,
+        )?;
+    }
+
     if let Some(rsdp_addr) = rsdp_addr {
         params.0.acpi_rsdp_addr = rsdp_addr.0;
     }
@@ -177,7 +702,7 @@ pub fn configure_system(
         .ok_or(super::Error::ZeroPagePastRamEnd)?;
     guest_mem
         .write_obj(params, zero_page_addr)
-        .map_err(|_| super::Error::ZeroPageSetup)?;
+        .map_err(super::Error::ZeroPageSetup)?;
 
     Ok(())
 }
@@ -202,6 +727,162 @@ fn add_e820_entry(
     Ok(())
 }
 
+/// Returns the memory address where the initramfs could be loaded.
+pub fn initramfs_load_addr(
+    guest_mem: &GuestMemoryMmap,
+    initramfs_size: usize,
+) -> super::Result<u64> {
+    let first_region = guest_mem
+        .find_region(GuestAddress::new(0))
+        .ok_or(super::Error::InitramfsAddress)?;
+    // It's safe to cast to usize because the size of a region can't be greater than usize.
+    let lowmem_size = first_region.len() as usize;
+
+    if lowmem_size < initramfs_size {
+        return Err(super::Error::InitramfsAddress);
+    }
+
+    let aligned_addr: u64 = ((lowmem_size - initramfs_size) & !(crate::pagesize() - 1)) as u64;
+    Ok(aligned_addr)
+}
+
+pub fn get_host_cpu_phys_bits() -> u8 {
+    use std::arch::x86_64;
+    unsafe {
+        let leaf = x86_64::__cpuid(0x8000_0000);
+
+        // Detect and handle AMD SME (Secure Memory Encryption) properly.
+        // Some physical address bits may become reserved when the feature is enabled.
+        // See AMD64 Architecture Programmer's Manual Volume 2, Section 7.10.1
+        let reduced = if leaf.eax >= 0x8000_001f
+            && leaf.ebx == 0x6874_7541    // Vendor ID: AuthenticAMD
+            && leaf.ecx == 0x444d_4163
+            && leaf.edx == 0x6974_6e65
+            && x86_64::__cpuid(0x8000_001f).eax & 0x1 != 0
+        {
+            (x86_64::__cpuid(0x8000_001f).ebx >> 6) & 0x3f
+        } else {
+            0
+        };
+
+        if leaf.eax >= 0x8000_0008 {
+            let leaf = x86_64::__cpuid(0x8000_0008);
+            ((leaf.eax & 0xff) - reduced) as u8
+        } else {
+            36
+        }
+    }
+}
+
+pub fn update_cpuid_topology(
+    cpuid: &mut CpuId,
+    threads_per_core: u8,
+    cores_per_die: u8,
+    dies_per_package: u8,
+) {
+    let thread_width = 8 - (threads_per_core - 1).leading_zeros();
+    let core_width = (8 - (cores_per_die - 1).leading_zeros()) + thread_width;
+    let die_width = (8 - (dies_per_package - 1).leading_zeros()) + core_width;
+
+    // CPU Topology leaf 0xb
+    CpuidPatch::set_cpuid_reg(cpuid, 0xb, Some(0), CpuidReg::EAX, thread_width);
+    CpuidPatch::set_cpuid_reg(
+        cpuid,
+        0xb,
+        Some(0),
+        CpuidReg::EBX,
+        u32::from(threads_per_core),
+    );
+    CpuidPatch::set_cpuid_reg(cpuid, 0xb, Some(0), CpuidReg::ECX, 1 << 8);
+
+    CpuidPatch::set_cpuid_reg(cpuid, 0xb, Some(1), CpuidReg::EAX, die_width);
+    CpuidPatch::set_cpuid_reg(
+        cpuid,
+        0xb,
+        Some(1),
+        CpuidReg::EBX,
+        u32::from(dies_per_package * cores_per_die * threads_per_core),
+    );
+    CpuidPatch::set_cpuid_reg(cpuid, 0xb, Some(1), CpuidReg::ECX, 2 << 8);
+
+    // CPU Topology leaf 0x1f
+    CpuidPatch::set_cpuid_reg(cpuid, 0x1f, Some(0), CpuidReg::EAX, thread_width);
+    CpuidPatch::set_cpuid_reg(
+        cpuid,
+        0x1f,
+        Some(0),
+        CpuidReg::EBX,
+        u32::from(threads_per_core),
+    );
+    CpuidPatch::set_cpuid_reg(cpuid, 0x1f, Some(0), CpuidReg::ECX, 1 << 8);
+
+    CpuidPatch::set_cpuid_reg(cpuid, 0x1f, Some(1), CpuidReg::EAX, core_width);
+    CpuidPatch::set_cpuid_reg(
+        cpuid,
+        0x1f,
+        Some(1),
+        CpuidReg::EBX,
+        u32::from(cores_per_die * threads_per_core),
+    );
+    CpuidPatch::set_cpuid_reg(cpuid, 0x1f, Some(1), CpuidReg::ECX, 2 << 8);
+
+    CpuidPatch::set_cpuid_reg(cpuid, 0x1f, Some(2), CpuidReg::EAX, die_width);
+    CpuidPatch::set_cpuid_reg(
+        cpuid,
+        0x1f,
+        Some(2),
+        CpuidReg::EBX,
+        u32::from(dies_per_package * cores_per_die * threads_per_core),
+    );
+    CpuidPatch::set_cpuid_reg(cpuid, 0x1f, Some(2), CpuidReg::ECX, 5 << 8);
+}
+
+// The goal is to update the CPUID sub-leaves to reflect the number of EPC
+// sections exposed to the guest.
+pub fn update_cpuid_sgx(cpuid: &mut CpuId, epc_sections: Vec<SgxEpcSection>) -> Result<(), Error> {
+    // Something's wrong if there's no EPC section.
+    if epc_sections.is_empty() {
+        return Err(Error::NoSgxEpcSection);
+    }
+    // We can't go further if the hypervisor does not support SGX feature.
+    if !CpuidPatch::is_feature_enabled(cpuid, 0x7, 0, CpuidReg::EBX, 2) {
+        return Err(Error::MissingSgxFeature);
+    }
+    // We can't go further if the hypervisor does not support SGX_LC feature.
+    if !CpuidPatch::is_feature_enabled(cpuid, 0x7, 0, CpuidReg::ECX, 30) {
+        return Err(Error::MissingSgxLaunchControlFeature);
+    }
+
+    // Get host CPUID for leaf 0x12, subleaf 0x2. This is to retrieve EPC
+    // properties such as confidentiality and integrity.
+    let leaf = unsafe { std::arch::x86_64::__cpuid_count(0x12, 0x2) };
+
+    for (i, epc_section) in epc_sections.iter().enumerate() {
+        let subleaf_idx = i + 2;
+        let start = epc_section.start().raw_value();
+        let size = epc_section.size() as u64;
+        let eax = (start & 0xffff_f000) as u32 | 0x1;
+        let ebx = (start >> 32) as u32;
+        let ecx = (size & 0xffff_f000) as u32 | (leaf.ecx & 0xf);
+        let edx = (size >> 32) as u32;
+        // CPU Topology leaf 0x12
+        CpuidPatch::set_cpuid_reg(cpuid, 0x12, Some(subleaf_idx as u32), CpuidReg::EAX, eax);
+        CpuidPatch::set_cpuid_reg(cpuid, 0x12, Some(subleaf_idx as u32), CpuidReg::EBX, ebx);
+        CpuidPatch::set_cpuid_reg(cpuid, 0x12, Some(subleaf_idx as u32), CpuidReg::ECX, ecx);
+        CpuidPatch::set_cpuid_reg(cpuid, 0x12, Some(subleaf_idx as u32), CpuidReg::EDX, edx);
+    }
+
+    // Add one NULL entry to terminate the dynamic list
+    let subleaf_idx = epc_sections.len() + 2;
+    // CPU Topology leaf 0x12
+    CpuidPatch::set_cpuid_reg(cpuid, 0x12, Some(subleaf_idx as u32), CpuidReg::EAX, 0);
+    CpuidPatch::set_cpuid_reg(cpuid, 0x12, Some(subleaf_idx as u32), CpuidReg::EBX, 0);
+    CpuidPatch::set_cpuid_reg(cpuid, 0x12, Some(subleaf_idx as u32), CpuidReg::ECX, 0);
+    CpuidPatch::set_cpuid_reg(cpuid, 0x12, Some(subleaf_idx as u32), CpuidReg::EDX, 0);
+
+    Ok(())
+}
+
 #[cfg(test)]
 mod tests {
     use super::*;
@@ -226,15 +907,19 @@ mod tests {
     #[test]
     fn test_system_configuration() {
         let no_vcpus = 4;
-        let gm = GuestMemoryMmap::new(&vec![(GuestAddress(0), 0x10000)]).unwrap();
-        let config_err = configure_system(&gm, GuestAddress(0), 0, 1, None, None);
-        assert!(config_err.is_err());
-        assert_eq!(
-            config_err.unwrap_err(),
-            super::super::Error::X86_64Setup(super::Error::MpTableSetup(
-                mptable::Error::NotEnoughMemory
-            ))
+        let gm = GuestMemoryMmap::from_ranges(&vec![(GuestAddress(0), 0x10000)]).unwrap();
+        let config_err = configure_system(
+            &gm,
+            GuestAddress(0),
+            0,
+            &None,
+            1,
+            None,
+            Some(layout::RSDP_POINTER),
+            BootProtocol::LinuxBoot,
+            None,
         );
+        assert!(config_err.is_err());
 
         // Now assigning some memory that falls before the 32bit memory hole.
         let mem_size = 128 << 20;
@@ -244,8 +929,32 @@ mod tests {
             .filter(|r| r.2 == RegionType::Ram)
             .map(|r| (r.0, r.1))
             .collect();
-        let gm = GuestMemoryMmap::new(&ram_regions).unwrap();
-        configure_system(&gm, GuestAddress(0), 0, no_vcpus, None, None).unwrap();
+        let gm = GuestMemoryMmap::from_ranges(&ram_regions).unwrap();
+        configure_system(
+            &gm,
+            GuestAddress(0),
+            0,
+            &None,
+            no_vcpus,
+            None,
+            None,
+            BootProtocol::LinuxBoot,
+            None,
+        )
+        .unwrap();
+
+        configure_system(
+            &gm,
+            GuestAddress(0),
+            0,
+            &None,
+            no_vcpus,
+            None,
+            None,
+            BootProtocol::PvhBoot,
+            None,
+        )
+        .unwrap();
 
         // Now assigning some memory that is equal to the start of the 32bit memory hole.
         let mem_size = 3328 << 20;
@@ -255,8 +964,32 @@ mod tests {
             .filter(|r| r.2 == RegionType::Ram)
             .map(|r| (r.0, r.1))
             .collect();
-        let gm = GuestMemoryMmap::new(&ram_regions).unwrap();
-        configure_system(&gm, GuestAddress(0), 0, no_vcpus, None, None).unwrap();
+        let gm = GuestMemoryMmap::from_ranges(&ram_regions).unwrap();
+        configure_system(
+            &gm,
+            GuestAddress(0),
+            0,
+            &None,
+            no_vcpus,
+            None,
+            None,
+            BootProtocol::LinuxBoot,
+            None,
+        )
+        .unwrap();
+
+        configure_system(
+            &gm,
+            GuestAddress(0),
+            0,
+            &None,
+            no_vcpus,
+            None,
+            None,
+            BootProtocol::PvhBoot,
+            None,
+        )
+        .unwrap();
 
         // Now assigning some memory that falls after the 32bit memory hole.
         let mem_size = 3330 << 20;
@@ -266,8 +999,32 @@ mod tests {
             .filter(|r| r.2 == RegionType::Ram)
             .map(|r| (r.0, r.1))
             .collect();
-        let gm = GuestMemoryMmap::new(&ram_regions).unwrap();
-        configure_system(&gm, GuestAddress(0), 0, no_vcpus, None, None).unwrap();
+        let gm = GuestMemoryMmap::from_ranges(&ram_regions).unwrap();
+        configure_system(
+            &gm,
+            GuestAddress(0),
+            0,
+            &None,
+            no_vcpus,
+            None,
+            None,
+            BootProtocol::LinuxBoot,
+            None,
+        )
+        .unwrap();
+
+        configure_system(
+            &gm,
+            GuestAddress(0),
+            0,
+            &None,
+            no_vcpus,
+            None,
+            None,
+            BootProtocol::PvhBoot,
+            None,
+        )
+        .unwrap();
     }
 
     #[test]
@@ -309,4 +1066,29 @@ mod tests {
         )
         .is_err());
     }
+
+    #[test]
+    fn test_add_memmap_entry() {
+        let mut memmap: Vec<hvm_memmap_table_entry> = Vec::new();
+
+        let expected_memmap = vec![
+            hvm_memmap_table_entry {
+                addr: 0x0,
+                size: 0x1000,
+                type_: E820_RAM,
+                ..Default::default()
+            },
+            hvm_memmap_table_entry {
+                addr: 0x10000,
+                size: 0xa000,
+                type_: E820_RESERVED,
+                ..Default::default()
+            },
+        ];
+
+        add_memmap_entry(&mut memmap, 0, 0x1000, E820_RAM).unwrap();
+        add_memmap_entry(&mut memmap, 0x10000, 0xa000, E820_RESERVED).unwrap();
+
+        assert_eq!(format!("{:?}", memmap), format!("{:?}", expected_memmap));
+    }
 }

arch/src/x86_64/mptable.rs

@@ -14,7 +14,7 @@ use libc::c_char;
 
 use arch_gen::x86::mpspec;
 use layout::{APIC_START, IOAPIC_START, MPTABLE_START};
-use vm_memory::{Address, ByteValued, Bytes, GuestMemory, GuestMemoryMmap};
+use vm_memory::{Address, ByteValued, Bytes, GuestMemory, GuestMemoryError, GuestMemoryMmap};
 
 // This is a workaround to the Rust enforcement specifying that any implementation of a foreign
 // trait (in this case `ByteValued`) where:
@@ -45,30 +45,30 @@ unsafe impl ByteValued for MpcTableWrapper {}
 unsafe impl ByteValued for MpcLintsrcWrapper {}
 unsafe impl ByteValued for MpfIntelWrapper {}
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug)]
 pub enum Error {
     /// There was too little guest memory to store the entire MP table.
     NotEnoughMemory,
     /// The MP table has too little address space to be stored.
     AddressOverflow,
     /// Failure while zeroing out the memory for the MP table.
-    Clear,
+    Clear(GuestMemoryError),
     /// Number of CPUs exceeds the maximum supported CPUs
     TooManyCpus,
     /// Failure to write the MP floating pointer.
-    WriteMpfIntel,
+    WriteMpfIntel(GuestMemoryError),
     /// Failure to write MP CPU entry.
-    WriteMpcCpu,
+    WriteMpcCpu(GuestMemoryError),
     /// Failure to write MP ioapic entry.
-    WriteMpcIoapic,
+    WriteMpcIoapic(GuestMemoryError),
     /// Failure to write MP bus entry.
-    WriteMpcBus,
+    WriteMpcBus(GuestMemoryError),
     /// Failure to write MP interrupt source entry.
-    WriteMpcIntsrc,
+    WriteMpcIntsrc(GuestMemoryError),
     /// Failure to write MP local interrupt source entry.
-    WriteMpcLintsrc,
+    WriteMpcLintsrc(GuestMemoryError),
     /// Failure to write MP table header.
-    WriteMpcTable,
+    WriteMpcTable(GuestMemoryError),
 }
 
 pub type Result<T> = result::Result<T, Error>;
@@ -145,7 +145,7 @@ pub fn setup_mptable(mem: &GuestMemoryMmap, num_cpus: u8) -> Result<()> {
     }
 
     mem.read_exact_from(base_mp, &mut io::repeat(0), mp_size)
-        .map_err(|_| Error::Clear)?;
+        .map_err(Error::Clear)?;
 
     {
         let mut mpf_intel = MpfIntelWrapper(mpspec::mpf_intel::default());
@@ -156,7 +156,7 @@ pub fn setup_mptable(mem: &GuestMemoryMmap, num_cpus: u8) -> Result<()> {
         mpf_intel.0.physptr = (base_mp.raw_value() + size) as u32;
         mpf_intel.0.checksum = mpf_intel_compute_checksum(&mpf_intel.0);
         mem.write_obj(mpf_intel, base_mp)
-            .map_err(|_| Error::WriteMpfIntel)?;
+            .map_err(Error::WriteMpfIntel)?;
         base_mp = base_mp.unchecked_add(size);
     }
 
@@ -181,7 +181,7 @@ pub fn setup_mptable(mem: &GuestMemoryMmap, num_cpus: u8) -> Result<()> {
             mpc_cpu.0.cpufeature = CPU_STEPPING;
             mpc_cpu.0.featureflag = CPU_FEATURE_APIC | CPU_FEATURE_FPU;
             mem.write_obj(mpc_cpu, base_mp)
-                .map_err(|_| Error::WriteMpcCpu)?;
+                .map_err(Error::WriteMpcCpu)?;
             base_mp = base_mp.unchecked_add(size as u64);
             checksum = checksum.wrapping_add(compute_checksum(&mpc_cpu.0));
         }
@@ -193,7 +193,7 @@ pub fn setup_mptable(mem: &GuestMemoryMmap, num_cpus: u8) -> Result<()> {
         mpc_bus.0.busid = 0;
         mpc_bus.0.bustype = BUS_TYPE_ISA;
         mem.write_obj(mpc_bus, base_mp)
-            .map_err(|_| Error::WriteMpcBus)?;
+            .map_err(Error::WriteMpcBus)?;
         base_mp = base_mp.unchecked_add(size as u64);
         checksum = checksum.wrapping_add(compute_checksum(&mpc_bus.0));
     }
@@ -206,7 +206,7 @@ pub fn setup_mptable(mem: &GuestMemoryMmap, num_cpus: u8) -> Result<()> {
         mpc_ioapic.0.flags = mpspec::MPC_APIC_USABLE as u8;
         mpc_ioapic.0.apicaddr = IOAPIC_START.0 as u32;
         mem.write_obj(mpc_ioapic, base_mp)
-            .map_err(|_| Error::WriteMpcIoapic)?;
+            .map_err(Error::WriteMpcIoapic)?;
         base_mp = base_mp.unchecked_add(size as u64);
         checksum = checksum.wrapping_add(compute_checksum(&mpc_ioapic.0));
     }
@@ -222,7 +222,7 @@ pub fn setup_mptable(mem: &GuestMemoryMmap, num_cpus: u8) -> Result<()> {
         mpc_intsrc.0.dstapic = ioapicid;
         mpc_intsrc.0.dstirq = i;
         mem.write_obj(mpc_intsrc, base_mp)
-            .map_err(|_| Error::WriteMpcIntsrc)?;
+            .map_err(Error::WriteMpcIntsrc)?;
         base_mp = base_mp.unchecked_add(size as u64);
         checksum = checksum.wrapping_add(compute_checksum(&mpc_intsrc.0));
     }
@@ -237,7 +237,7 @@ pub fn setup_mptable(mem: &GuestMemoryMmap, num_cpus: u8) -> Result<()> {
         mpc_lintsrc.0.destapic = 0;
         mpc_lintsrc.0.destapiclint = 0;
         mem.write_obj(mpc_lintsrc, base_mp)
-            .map_err(|_| Error::WriteMpcLintsrc)?;
+            .map_err(Error::WriteMpcLintsrc)?;
         base_mp = base_mp.unchecked_add(size as u64);
         checksum = checksum.wrapping_add(compute_checksum(&mpc_lintsrc.0));
     }
@@ -252,7 +252,7 @@ pub fn setup_mptable(mem: &GuestMemoryMmap, num_cpus: u8) -> Result<()> {
         mpc_lintsrc.0.destapic = 0xFF; /* to all local APICs */
         mpc_lintsrc.0.destapiclint = 1;
         mem.write_obj(mpc_lintsrc, base_mp)
-            .map_err(|_| Error::WriteMpcLintsrc)?;
+            .map_err(Error::WriteMpcLintsrc)?;
         base_mp = base_mp.unchecked_add(size as u64);
         checksum = checksum.wrapping_add(compute_checksum(&mpc_lintsrc.0));
     }
@@ -271,7 +271,7 @@ pub fn setup_mptable(mem: &GuestMemoryMmap, num_cpus: u8) -> Result<()> {
         checksum = checksum.wrapping_add(compute_checksum(&mpc_table.0));
         mpc_table.0.checksum = (!checksum).wrapping_add(1) as i8;
         mem.write_obj(mpc_table, table_base)
-            .map_err(|_| Error::WriteMpcTable)?;
+            .map_err(Error::WriteMpcTable)?;
     }
 
     Ok(())
@@ -296,7 +296,8 @@ mod tests {
     #[test]
     fn bounds_check() {
         let num_cpus = 4;
-        let mem = GuestMemoryMmap::new(&[(MPTABLE_START, compute_mp_size(num_cpus))]).unwrap();
+        let mem =
+            GuestMemoryMmap::from_ranges(&[(MPTABLE_START, compute_mp_size(num_cpus))]).unwrap();
 
         setup_mptable(&mem, num_cpus).unwrap();
     }
@@ -304,7 +305,8 @@ mod tests {
     #[test]
     fn bounds_check_fails() {
         let num_cpus = 4;
-        let mem = GuestMemoryMmap::new(&[(MPTABLE_START, compute_mp_size(num_cpus) - 1)]).unwrap();
+        let mem = GuestMemoryMmap::from_ranges(&[(MPTABLE_START, compute_mp_size(num_cpus) - 1)])
+            .unwrap();
 
         assert!(setup_mptable(&mem, num_cpus).is_err());
     }
@@ -312,7 +314,8 @@ mod tests {
     #[test]
     fn mpf_intel_checksum() {
         let num_cpus = 1;
-        let mem = GuestMemoryMmap::new(&[(MPTABLE_START, compute_mp_size(num_cpus))]).unwrap();
+        let mem =
+            GuestMemoryMmap::from_ranges(&[(MPTABLE_START, compute_mp_size(num_cpus))]).unwrap();
 
         setup_mptable(&mem, num_cpus).unwrap();
 
@@ -327,7 +330,8 @@ mod tests {
     #[test]
     fn mpc_table_checksum() {
         let num_cpus = 4;
-        let mem = GuestMemoryMmap::new(&[(MPTABLE_START, compute_mp_size(num_cpus))]).unwrap();
+        let mem =
+            GuestMemoryMmap::from_ranges(&[(MPTABLE_START, compute_mp_size(num_cpus))]).unwrap();
 
         setup_mptable(&mem, num_cpus).unwrap();
 
@@ -356,9 +360,11 @@ mod tests {
 
     #[test]
     fn cpu_entry_count() {
-        let mem =
-            GuestMemoryMmap::new(&[(MPTABLE_START, compute_mp_size(MAX_SUPPORTED_CPUS as u8))])
-                .unwrap();
+        let mem = GuestMemoryMmap::from_ranges(&[(
+            MPTABLE_START,
+            compute_mp_size(MAX_SUPPORTED_CPUS as u8),
+        )])
+        .unwrap();
 
         for i in 0..MAX_SUPPORTED_CPUS as u8 {
             setup_mptable(&mem, i).unwrap();
@@ -391,9 +397,10 @@ mod tests {
     #[test]
     fn cpu_entry_count_max() {
         let cpus = MAX_SUPPORTED_CPUS + 1;
-        let mem = GuestMemoryMmap::new(&[(MPTABLE_START, compute_mp_size(cpus as u8))]).unwrap();
+        let mem =
+            GuestMemoryMmap::from_ranges(&[(MPTABLE_START, compute_mp_size(cpus as u8))]).unwrap();
 
-        let result = setup_mptable(&mem, cpus as u8).unwrap_err();
-        assert_eq!(result, Error::TooManyCpus);
+        let result = setup_mptable(&mem, cpus as u8);
+        assert!(result.is_err());
     }
 }

arch/src/x86_64/regs.rs

@@ -1,45 +1,48 @@
+// Copyright © 2020, Oracle and/or its affiliates.
+//
 // Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 // SPDX-License-Identifier: Apache-2.0
 //
 // Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE-BSD-3-Clause file.
-
+use std::sync::Arc;
 use std::{mem, result};
 
-use super::gdt::{gdt_entry, kvm_segment_from_gdt};
-use arch_gen::x86::msr_index;
-use kvm_bindings::{kvm_fpu, kvm_msr_entry, kvm_regs, kvm_sregs, Msrs};
-use kvm_ioctls::VcpuFd;
-use layout::{BOOT_GDT_START, BOOT_IDT_START, PDE_START, PDPTE_START, PML4_START};
-use vm_memory::{Address, Bytes, GuestMemory, GuestMemoryMmap};
-
-// MTRR constants
-const MTRR_ENABLE: u64 = 0x800; // IA32_MTRR_DEF_TYPE MSR: E (MTRRs enabled) flag, bit 11
-const MTRR_MEM_TYPE_WB: u64 = 0x6;
+use super::gdt::{gdt_entry, segment_from_gdt};
+use super::BootProtocol;
+use hypervisor::x86_64::{FpuState, SpecialRegisters, StandardRegisters};
+use layout::{
+    BOOT_GDT_START, BOOT_IDT_START, PDE_START, PDPTE_START, PML4_START, PML5_START, PVH_INFO_START,
+};
+use vm_memory::{Address, Bytes, GuestMemory, GuestMemoryError, GuestMemoryMmap};
 
 #[derive(Debug)]
 pub enum Error {
     /// Failed to get SREGs for this CPU.
-    GetStatusRegisters(kvm_ioctls::Error),
+    GetStatusRegisters(hypervisor::HypervisorCpuError),
     /// Failed to set base registers for this CPU.
-    SetBaseRegisters(kvm_ioctls::Error),
+    SetBaseRegisters(hypervisor::HypervisorCpuError),
     /// Failed to configure the FPU.
-    SetFPURegisters(kvm_ioctls::Error),
+    SetFPURegisters(hypervisor::HypervisorCpuError),
     /// Setting up MSRs failed.
-    SetModelSpecificRegisters(kvm_ioctls::Error),
+    SetModelSpecificRegisters(hypervisor::HypervisorCpuError),
     /// Failed to set SREGs for this CPU.
-    SetStatusRegisters(kvm_ioctls::Error),
+    SetStatusRegisters(hypervisor::HypervisorCpuError),
+    /// Checking the GDT address failed.
+    CheckGDTAddr,
     /// Writing the GDT to RAM failed.
-    WriteGDT,
+    WriteGDT(GuestMemoryError),
     /// Writing the IDT to RAM failed.
-    WriteIDT,
+    WriteIDT(GuestMemoryError),
     /// Writing PDPTE to RAM failed.
-    WritePDPTEAddress,
+    WritePDPTEAddress(GuestMemoryError),
     /// Writing PDE to RAM failed.
-    WritePDEAddress,
+    WritePDEAddress(GuestMemoryError),
     /// Writing PML4 to RAM failed.
-    WritePML4Address,
+    WritePML4Address(GuestMemoryError),
+    /// Writing PML5 to RAM failed.
+    WritePML5Address(GuestMemoryError),
 }
 
 pub type Result<T> = result::Result<T, Error>;
@@ -49,8 +52,8 @@ pub type Result<T> = result::Result<T, Error>;
 /// # Arguments
 ///
 /// * `vcpu` - Structure for the VCPU that holds the VCPU's fd.
-pub fn setup_fpu(vcpu: &VcpuFd) -> Result<()> {
-    let fpu: kvm_fpu = kvm_fpu {
+pub fn setup_fpu(vcpu: &Arc<dyn hypervisor::Vcpu>) -> Result<()> {
+    let fpu: FpuState = FpuState {
         fcw: 0x37f,
         mxcsr: 0x1f80,
         ..Default::default()
@@ -64,8 +67,8 @@ pub fn setup_fpu(vcpu: &VcpuFd) -> Result<()> {
 /// # Arguments
 ///
 /// * `vcpu` - Structure for the VCPU that holds the VCPU's fd.
-pub fn setup_msrs(vcpu: &VcpuFd) -> Result<()> {
-    vcpu.set_msrs(&create_msr_entries())
+pub fn setup_msrs(vcpu: &Arc<dyn hypervisor::Vcpu>) -> Result<()> {
+    vcpu.set_msrs(&hypervisor::x86_64::boot_msr_entries())
         .map_err(Error::SetModelSpecificRegisters)?;
 
     Ok(())
@@ -79,16 +82,31 @@ pub fn setup_msrs(vcpu: &VcpuFd) -> Result<()> {
 /// * `boot_ip` - Starting instruction pointer.
 /// * `boot_sp` - Starting stack pointer.
 /// * `boot_si` - Must point to zero page address per Linux ABI.
-pub fn setup_regs(vcpu: &VcpuFd, boot_ip: u64, boot_sp: u64, boot_si: u64) -> Result<()> {
-    let regs: kvm_regs = kvm_regs {
-        rflags: 0x0000000000000002u64,
-        rip: boot_ip,
-        rsp: boot_sp,
-        rbp: boot_sp,
-        rsi: boot_si,
-        ..Default::default()
+pub fn setup_regs(
+    vcpu: &Arc<dyn hypervisor::Vcpu>,
+    boot_ip: u64,
+    boot_sp: u64,
+    boot_si: u64,
+    boot_prot: BootProtocol,
+) -> Result<()> {
+    let regs: StandardRegisters = match boot_prot {
+        // Configure regs as required by PVH boot protocol.
+        BootProtocol::PvhBoot => StandardRegisters {
+            rflags: 0x0000000000000002u64,
+            rbx: PVH_INFO_START.raw_value(),
+            rip: boot_ip,
+            ..Default::default()
+        },
+        // Configure regs as required by Linux 64-bit boot protocol.
+        BootProtocol::LinuxBoot => StandardRegisters {
+            rflags: 0x0000000000000002u64,
+            rip: boot_ip,
+            rsp: boot_sp,
+            rbp: boot_sp,
+            rsi: boot_si,
+            ..Default::default()
+        },
     };
-
     vcpu.set_regs(&regs).map_err(Error::SetBaseRegisters)
 }
 
@@ -98,11 +116,18 @@ pub fn setup_regs(vcpu: &VcpuFd, boot_ip: u64, boot_sp: u64, boot_si: u64) -> Re
 ///
 /// * `mem` - The memory that will be passed to the guest.
 /// * `vcpu` - Structure for the VCPU that holds the VCPU's fd.
-pub fn setup_sregs(mem: &GuestMemoryMmap, vcpu: &VcpuFd) -> Result<()> {
-    let mut sregs: kvm_sregs = vcpu.get_sregs().map_err(Error::GetStatusRegisters)?;
+pub fn setup_sregs(
+    mem: &GuestMemoryMmap,
+    vcpu: &Arc<dyn hypervisor::Vcpu>,
+    boot_prot: BootProtocol,
+) -> Result<()> {
+    let mut sregs: SpecialRegisters = vcpu.get_sregs().map_err(Error::GetStatusRegisters)?;
 
-    configure_segments_and_sregs(mem, &mut sregs)?;
-    setup_page_tables(mem, &mut sregs)?; // TODO(dgreid) - Can this be done once per system instead?
+    configure_segments_and_sregs(mem, &mut sregs, boot_prot)?;
+
+    if let BootProtocol::LinuxBoot = boot_prot {
+        setup_page_tables(mem, &mut sregs)?; // TODO(dgreid) - Can this be done once per system instead?
+    }
 
     vcpu.set_sregs(&sregs).map_err(Error::SetStatusRegisters)
 }
@@ -115,16 +140,15 @@ const EFER_LME: u64 = 0x100;
 const X86_CR0_PE: u64 = 0x1;
 const X86_CR0_PG: u64 = 0x80000000;
 const X86_CR4_PAE: u64 = 0x20;
+const X86_CR4_LA57: u64 = 0x1000;
 
 fn write_gdt_table(table: &[u64], guest_mem: &GuestMemoryMmap) -> Result<()> {
     let boot_gdt_addr = BOOT_GDT_START;
     for (index, entry) in table.iter().enumerate() {
         let addr = guest_mem
             .checked_offset(boot_gdt_addr, index * mem::size_of::<u64>())
-            .ok_or(Error::WriteGDT)?;
-        guest_mem
-            .write_obj(*entry, addr)
-            .map_err(|_| Error::WriteGDT)?;
+            .ok_or(Error::CheckGDTAddr)?;
+        guest_mem.write_obj(*entry, addr).map_err(Error::WriteGDT)?;
     }
     Ok(())
 }
@@ -133,20 +157,38 @@ fn write_idt_value(val: u64, guest_mem: &GuestMemoryMmap) -> Result<()> {
     let boot_idt_addr = BOOT_IDT_START;
     guest_mem
         .write_obj(val, boot_idt_addr)
-        .map_err(|_| Error::WriteIDT)
+        .map_err(Error::WriteIDT)
 }
 
-fn configure_segments_and_sregs(mem: &GuestMemoryMmap, sregs: &mut kvm_sregs) -> Result<()> {
-    let gdt_table: [u64; BOOT_GDT_MAX as usize] = [
-        gdt_entry(0, 0, 0),            // NULL
-        gdt_entry(0xa09b, 0, 0xfffff), // CODE
-        gdt_entry(0xc093, 0, 0xfffff), // DATA
-        gdt_entry(0x808b, 0, 0xfffff), // TSS
-    ];
+pub fn configure_segments_and_sregs(
+    mem: &GuestMemoryMmap,
+    sregs: &mut SpecialRegisters,
+    boot_prot: BootProtocol,
+) -> Result<()> {
+    let gdt_table: [u64; BOOT_GDT_MAX as usize] = match boot_prot {
+        BootProtocol::PvhBoot => {
+            // Configure GDT entries as specified by PVH boot protocol
+            [
+                gdt_entry(0, 0, 0),               // NULL
+                gdt_entry(0xc09b, 0, 0xffffffff), // CODE
+                gdt_entry(0xc093, 0, 0xffffffff), // DATA
+                gdt_entry(0x008b, 0, 0x67),       // TSS
+            ]
+        }
+        BootProtocol::LinuxBoot => {
+            // Configure GDT entries as specified by Linux 64bit boot protocol
+            [
+                gdt_entry(0, 0, 0),            // NULL
+                gdt_entry(0xa09b, 0, 0xfffff), // CODE
+                gdt_entry(0xc093, 0, 0xfffff), // DATA
+                gdt_entry(0x808b, 0, 0xfffff), // TSS
+            ]
+        }
+    };
 
-    let code_seg = kvm_segment_from_gdt(gdt_table[1], 1);
-    let data_seg = kvm_segment_from_gdt(gdt_table[2], 2);
-    let tss_seg = kvm_segment_from_gdt(gdt_table[3], 3);
+    let code_seg = segment_from_gdt(gdt_table[1], 1);
+    let data_seg = segment_from_gdt(gdt_table[2], 2);
+    let tss_seg = segment_from_gdt(gdt_table[3], 3);
 
     // Write segments
     write_gdt_table(&gdt_table[..], mem)?;
@@ -165,111 +207,64 @@ fn configure_segments_and_sregs(mem: &GuestMemoryMmap, sregs: &mut kvm_sregs) ->
     sregs.ss = data_seg;
     sregs.tr = tss_seg;
 
-    /* 64-bit protected mode */
-    sregs.cr0 |= X86_CR0_PE;
-    sregs.efer |= EFER_LME | EFER_LMA;
+    match boot_prot {
+        BootProtocol::PvhBoot => {
+            sregs.cr0 = X86_CR0_PE;
+            sregs.cr4 = 0;
+        }
+        BootProtocol::LinuxBoot => {
+            /* 64-bit protected mode */
+            sregs.cr0 |= X86_CR0_PE;
+            sregs.efer |= EFER_LME | EFER_LMA;
+        }
+    }
 
     Ok(())
 }
 
-fn setup_page_tables(mem: &GuestMemoryMmap, sregs: &mut kvm_sregs) -> Result<()> {
-    // Puts PML4 right after zero page but aligned to 4k.
+pub fn setup_page_tables(mem: &GuestMemoryMmap, sregs: &mut SpecialRegisters) -> Result<()> {
+    // Puts PML5 or PML4 right after zero page but aligned to 4k.
+    if unsafe { std::arch::x86_64::__cpuid(7).ecx } & (1 << 16) != 0 {
+        // Entry covering VA [0..256TB)
+        mem.write_obj(PML4_START.raw_value() | 0x03, PML5_START)
+            .map_err(Error::WritePML5Address)?;
+
+        sregs.cr3 = PML5_START.raw_value();
+        sregs.cr4 |= X86_CR4_LA57;
+    } else {
+        sregs.cr3 = PML4_START.raw_value();
+    }
 
     // Entry covering VA [0..512GB)
     mem.write_obj(PDPTE_START.raw_value() | 0x03, PML4_START)
-        .map_err(|_| Error::WritePML4Address)?;
+        .map_err(Error::WritePML4Address)?;
 
     // Entry covering VA [0..1GB)
     mem.write_obj(PDE_START.raw_value() | 0x03, PDPTE_START)
-        .map_err(|_| Error::WritePDPTEAddress)?;
+        .map_err(Error::WritePDPTEAddress)?;
+
     // 512 2MB entries together covering VA [0..1GB). Note we are assuming
     // CPU supports 2MB pages (/proc/cpuinfo has 'pse'). All modern CPUs do.
     for i in 0..512 {
         mem.write_obj((i << 21) + 0x83u64, PDE_START.unchecked_add(i * 8))
-            .map_err(|_| Error::WritePDEAddress)?;
+            .map_err(Error::WritePDEAddress)?;
     }
 
-    sregs.cr3 = PML4_START.raw_value();
     sregs.cr4 |= X86_CR4_PAE;
     sregs.cr0 |= X86_CR0_PG;
+
     Ok(())
 }
 
-fn create_msr_entries() -> Msrs {
-    let mut entries = Vec::<kvm_msr_entry>::new();
-
-    entries.push(kvm_msr_entry {
-        index: msr_index::MSR_IA32_SYSENTER_CS,
-        data: 0x0,
-        ..Default::default()
-    });
-    entries.push(kvm_msr_entry {
-        index: msr_index::MSR_IA32_SYSENTER_ESP,
-        data: 0x0,
-        ..Default::default()
-    });
-    entries.push(kvm_msr_entry {
-        index: msr_index::MSR_IA32_SYSENTER_EIP,
-        data: 0x0,
-        ..Default::default()
-    });
-    // x86_64 specific msrs, we only run on x86_64 not x86.
-    entries.push(kvm_msr_entry {
-        index: msr_index::MSR_STAR,
-        data: 0x0,
-        ..Default::default()
-    });
-    entries.push(kvm_msr_entry {
-        index: msr_index::MSR_CSTAR,
-        data: 0x0,
-        ..Default::default()
-    });
-    entries.push(kvm_msr_entry {
-        index: msr_index::MSR_KERNEL_GS_BASE,
-        data: 0x0,
-        ..Default::default()
-    });
-    entries.push(kvm_msr_entry {
-        index: msr_index::MSR_SYSCALL_MASK,
-        data: 0x0,
-        ..Default::default()
-    });
-    entries.push(kvm_msr_entry {
-        index: msr_index::MSR_LSTAR,
-        data: 0x0,
-        ..Default::default()
-    });
-    // end of x86_64 specific code
-    entries.push(kvm_msr_entry {
-        index: msr_index::MSR_IA32_TSC,
-        data: 0x0,
-        ..Default::default()
-    });
-    entries.push(kvm_msr_entry {
-        index: msr_index::MSR_IA32_MISC_ENABLE,
-        data: msr_index::MSR_IA32_MISC_ENABLE_FAST_STRING as u64,
-        ..Default::default()
-    });
-    entries.push(kvm_msr_entry {
-        index: msr_index::MSR_MTRRdefType,
-        data: MTRR_ENABLE | MTRR_MEM_TYPE_WB,
-        ..Default::default()
-    });
-
-    Msrs::from_entries(&entries)
-}
-
 #[cfg(test)]
 mod tests {
-    extern crate kvm_ioctls;
     extern crate vm_memory;
 
     use super::*;
-    use kvm_ioctls::Kvm;
     use vm_memory::{GuestAddress, GuestMemoryMmap};
 
     fn create_guest_mem() -> GuestMemoryMmap {
-        GuestMemoryMmap::new(&vec![(GuestAddress(0), 0x10000)]).unwrap()
+        GuestMemoryMmap::from_ranges(&vec![(GuestAddress(0), 0x10000)]).unwrap()
     }
 
     fn read_u64(gm: &GuestMemoryMmap, offset: GuestAddress) -> u64 {
@@ -278,9 +273,9 @@ mod tests {
 
     #[test]
     fn segments_and_sregs() {
-        let mut sregs: kvm_sregs = Default::default();
+        let mut sregs: SpecialRegisters = Default::default();
         let gm = create_guest_mem();
-        configure_segments_and_sregs(&gm, &mut sregs).unwrap();
+        configure_segments_and_sregs(&gm, &mut sregs, BootProtocol::LinuxBoot).unwrap();
 
         assert_eq!(0x0, read_u64(&gm, BOOT_GDT_START));
         assert_eq!(
@@ -298,26 +293,59 @@ mod tests {
         assert_eq!(0x0, read_u64(&gm, BOOT_IDT_START));
 
         assert_eq!(0, sregs.cs.base);
-        assert_eq!(0xfffff, sregs.ds.limit);
+        assert_eq!(0xffffffff, sregs.ds.limit);
         assert_eq!(0x10, sregs.es.selector);
         assert_eq!(1, sregs.fs.present);
         assert_eq!(1, sregs.gs.g);
         assert_eq!(0, sregs.ss.avl);
         assert_eq!(0, sregs.tr.base);
-        assert_eq!(0xfffff, sregs.tr.limit);
+        assert_eq!(0xffffffff, sregs.tr.limit);
         assert_eq!(0, sregs.tr.avl);
         assert_eq!(X86_CR0_PE, sregs.cr0);
         assert_eq!(EFER_LME | EFER_LMA, sregs.efer);
+
+        configure_segments_and_sregs(&gm, &mut sregs, BootProtocol::PvhBoot).unwrap();
+        assert_eq!(0x0, read_u64(&gm, BOOT_GDT_START));
+        assert_eq!(
+            0xcf9b000000ffff,
+            read_u64(&gm, BOOT_GDT_START.unchecked_add(8))
+        );
+        assert_eq!(
+            0xcf93000000ffff,
+            read_u64(&gm, BOOT_GDT_START.unchecked_add(16))
+        );
+        assert_eq!(
+            0x8b0000000067,
+            read_u64(&gm, BOOT_GDT_START.unchecked_add(24))
+        );
+        assert_eq!(0x0, read_u64(&gm, BOOT_IDT_START));
+
+        assert_eq!(0, sregs.cs.base);
+        assert_eq!(0xffffffff, sregs.ds.limit);
+        assert_eq!(0x10, sregs.es.selector);
+        assert_eq!(1, sregs.fs.present);
+        assert_eq!(1, sregs.gs.g);
+        assert_eq!(0, sregs.ss.avl);
+        assert_eq!(0, sregs.tr.base);
+        assert_eq!(0, sregs.tr.g);
+        assert_eq!(0x67, sregs.tr.limit);
+        assert_eq!(0xb, sregs.tr.type_);
+        assert_eq!(0, sregs.tr.avl);
+        assert_eq!(X86_CR0_PE, sregs.cr0);
+        assert_eq!(0, sregs.cr4);
     }
 
     #[test]
     fn page_tables() {
-        let mut sregs: kvm_sregs = Default::default();
+        let mut sregs: SpecialRegisters = Default::default();
         let gm = create_guest_mem();
         setup_page_tables(&gm, &mut sregs).unwrap();
 
-        assert_eq!(0xa003, read_u64(&gm, PML4_START));
-        assert_eq!(0xb003, read_u64(&gm, PDPTE_START));
+        if unsafe { std::arch::x86_64::__cpuid(7).ecx } & (1 << 16) != 0 {
+            assert_eq!(0xa003, read_u64(&gm, PML5_START));
+        }
+        assert_eq!(0xb003, read_u64(&gm, PML4_START));
+        assert_eq!(0xc003, read_u64(&gm, PDPTE_START));
         for i in 0..512 {
             assert_eq!(
                 (i << 21) + 0x83u64,
@@ -325,99 +353,12 @@ mod tests {
             );
         }
 
-        assert_eq!(PML4_START.raw_value(), sregs.cr3);
+        if unsafe { std::arch::x86_64::__cpuid(7).ecx } & (1 << 16) != 0 {
+            assert_eq!(PML5_START.raw_value(), sregs.cr3);
+        } else {
+            assert_eq!(PML4_START.raw_value(), sregs.cr3);
+        }
         assert_eq!(X86_CR4_PAE, sregs.cr4);
         assert_eq!(X86_CR0_PG, sregs.cr0);
     }
-
-    #[test]
-    fn test_setup_fpu() {
-        let kvm = Kvm::new().unwrap();
-        let vm = kvm.create_vm().unwrap();
-        let vcpu = vm.create_vcpu(0).unwrap();
-        setup_fpu(&vcpu).unwrap();
-
-        let expected_fpu: kvm_fpu = kvm_fpu {
-            fcw: 0x37f,
-            mxcsr: 0x1f80,
-            ..Default::default()
-        };
-        let actual_fpu: kvm_fpu = vcpu.get_fpu().unwrap();
-        // TODO: auto-generate kvm related structures with PartialEq on.
-        assert_eq!(expected_fpu.fcw, actual_fpu.fcw);
-        // Setting the mxcsr register from kvm_fpu inside setup_fpu does not influence anything.
-        // See 'kvm_arch_vcpu_ioctl_set_fpu' from arch/x86/kvm/x86.c.
-        // The mxcsr will stay 0 and the assert below fails. Decide whether or not we should
-        // remove it at all.
-        // assert!(expected_fpu.mxcsr == actual_fpu.mxcsr);
-    }
-
-    #[test]
-    fn test_setup_msrs() {
-        let kvm = Kvm::new().unwrap();
-        let vm = kvm.create_vm().unwrap();
-        let vcpu = vm.create_vcpu(0).unwrap();
-        setup_msrs(&vcpu).unwrap();
-
-        // This test will check against the last MSR entry configured (the tenth one).
-        // See create_msr_entries for details.
-        let mut msrs = Msrs::from_entries(&[kvm_msr_entry {
-            index: msr_index::MSR_IA32_MISC_ENABLE,
-            ..Default::default()
-        }]);
-
-        // get_msrs returns the number of msrs that it succeed in reading. We only want to read 1
-        // in this test case scenario.
-        let read_msrs = vcpu.get_msrs(&mut msrs).unwrap();
-        assert_eq!(read_msrs, 1);
-
-        // Official entries that were setup when we did setup_msrs. We need to assert that the
-        // tenth one (i.e the one with index msr_index::MSR_IA32_MISC_ENABLE has the data we
-        // expect.
-        let entry_vec = create_msr_entries();
-        assert_eq!(entry_vec.as_slice()[9], msrs.as_slice()[0]);
-    }
-
-    #[test]
-    fn test_setup_regs() {
-        let kvm = Kvm::new().unwrap();
-        let vm = kvm.create_vm().unwrap();
-        let vcpu = vm.create_vcpu(0).unwrap();
-
-        let expected_regs: kvm_regs = kvm_regs {
-            rflags: 0x0000000000000002u64,
-            rip: 1,
-            rsp: 2,
-            rbp: 2,
-            rsi: 3,
-            ..Default::default()
-        };
-
-        setup_regs(
-            &vcpu,
-            expected_regs.rip,
-            expected_regs.rsp,
-            expected_regs.rsi,
-        )
-        .unwrap();
-
-        let actual_regs: kvm_regs = vcpu.get_regs().unwrap();
-        assert_eq!(actual_regs, expected_regs);
-    }
-
-    #[test]
-    fn test_setup_sregs() {
-        let kvm = Kvm::new().unwrap();
-        let vm = kvm.create_vm().unwrap();
-        let vcpu = vm.create_vcpu(0).unwrap();
-
-        let mut expected_sregs: kvm_sregs = vcpu.get_sregs().unwrap();
-        let gm = create_guest_mem();
-        configure_segments_and_sregs(&gm, &mut expected_sregs).unwrap();
-        setup_page_tables(&gm, &mut expected_sregs).unwrap();
-
-        setup_sregs(&gm, &vcpu).unwrap();
-        let actual_sregs: kvm_sregs = vcpu.get_sregs().unwrap();
-        assert_eq!(expected_sregs, actual_sregs);
-    }
 }

arch/src/x86_64/smbios.rs

@@ -0,0 +1,263 @@
+// Copyright © 2020 Intel Corporation
+//
+// Copyright 2019 The Chromium OS Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style license that can be
+// found in the LICENSE file.
+//
+// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
+
+use layout::SMBIOS_START;
+use std::fmt::{self, Display};
+use std::mem;
+use std::result;
+use std::slice;
+use vm_memory::ByteValued;
+use vm_memory::{Address, Bytes, GuestAddress, GuestMemoryMmap};
+
+#[allow(unused_variables)]
+#[derive(Debug)]
+pub enum Error {
+    /// There was too little guest memory to store the entire SMBIOS table.
+    NotEnoughMemory,
+    /// The SMBIOS table has too little address space to be stored.
+    AddressOverflow,
+    /// Failure while zeroing out the memory for the SMBIOS table.
+    Clear,
+    /// Failure to write SMBIOS entrypoint structure
+    WriteSmbiosEp,
+    /// Failure to write additional data to memory
+    WriteData,
+}
+
+impl std::error::Error for Error {}
+
+impl Display for Error {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        use self::Error::*;
+
+        let description = match self {
+            NotEnoughMemory => "There was too little guest memory to store the SMBIOS table",
+            AddressOverflow => "The SMBIOS table has too little address space to be stored",
+            Clear => "Failure while zeroing out the memory for the SMBIOS table",
+            WriteSmbiosEp => "Failure to write SMBIOS entrypoint structure",
+            WriteData => "Failure to write additional data to memory",
+        };
+
+        write!(f, "SMBIOS error: {}", description)
+    }
+}
+
+pub type Result<T> = result::Result<T, Error>;
+
+// Constants sourced from SMBIOS Spec 3.2.0.
+const SM3_MAGIC_IDENT: &[u8; 5usize] = b"_SM3_";
+const BIOS_INFORMATION: u8 = 0;
+const SYSTEM_INFORMATION: u8 = 1;
+const END_OF_TABLE: u8 = 127;
+const PCI_SUPPORTED: u64 = 1 << 7;
+const IS_VIRTUAL_MACHINE: u8 = 1 << 4;
+
+fn compute_checksum<T: Copy>(v: &T) -> u8 {
+    // Safe because we are only reading the bytes within the size of the `T` reference `v`.
+    let v_slice = unsafe { slice::from_raw_parts(v as *const T as *const u8, mem::size_of::<T>()) };
+    let mut checksum: u8 = 0;
+    for i in v_slice.iter() {
+        checksum = checksum.wrapping_add(*i);
+    }
+    (!checksum).wrapping_add(1)
+}
+
+#[repr(packed)]
+#[derive(Default, Copy)]
+pub struct Smbios30Entrypoint {
+    pub signature: [u8; 5usize],
+    pub checksum: u8,
+    pub length: u8,
+    pub majorver: u8,
+    pub minorver: u8,
+    pub docrev: u8,
+    pub revision: u8,
+    pub reserved: u8,
+    pub max_size: u32,
+    pub physptr: u64,
+}
+unsafe impl ByteValued for Smbios30Entrypoint {}
+
+impl Clone for Smbios30Entrypoint {
+    fn clone(&self) -> Self {
+        *self
+    }
+}
+
+#[repr(packed)]
+#[derive(Default, Copy)]
+pub struct SmbiosBiosInfo {
+    pub typ: u8,
+    pub length: u8,
+    pub handle: u16,
+    pub vendor: u8,
+    pub version: u8,
+    pub start_addr: u16,
+    pub release_date: u8,
+    pub rom_size: u8,
+    pub characteristics: u64,
+    pub characteristics_ext1: u8,
+    pub characteristics_ext2: u8,
+}
+
+impl Clone for SmbiosBiosInfo {
+    fn clone(&self) -> Self {
+        *self
+    }
+}
+
+unsafe impl ByteValued for SmbiosBiosInfo {}
+
+#[repr(packed)]
+#[derive(Default, Copy)]
+pub struct SmbiosSysInfo {
+    pub typ: u8,
+    pub length: u8,
+    pub handle: u16,
+    pub manufacturer: u8,
+    pub product_name: u8,
+    pub version: u8,
+    pub serial_number: u8,
+    pub uuid: [u8; 16usize],
+    pub wake_up_type: u8,
+    pub sku: u8,
+    pub family: u8,
+}
+
+impl Clone for SmbiosSysInfo {
+    fn clone(&self) -> Self {
+        *self
+    }
+}
+
+unsafe impl ByteValued for SmbiosSysInfo {}
+
+fn write_and_incr<T: ByteValued>(
+    mem: &GuestMemoryMmap,
+    val: T,
+    mut curptr: GuestAddress,
+) -> Result<GuestAddress> {
+    mem.write_obj(val, curptr).map_err(|_| Error::WriteData)?;
+    curptr = curptr
+        .checked_add(mem::size_of::<T>() as u64)
+        .ok_or(Error::NotEnoughMemory)?;
+    Ok(curptr)
+}
+
+fn write_string(
+    mem: &GuestMemoryMmap,
+    val: &str,
+    mut curptr: GuestAddress,
+) -> Result<GuestAddress> {
+    for c in val.as_bytes().iter() {
+        curptr = write_and_incr(mem, *c, curptr)?;
+    }
+    curptr = write_and_incr(mem, 0 as u8, curptr)?;
+    Ok(curptr)
+}
+
+pub fn setup_smbios(mem: &GuestMemoryMmap) -> Result<()> {
+    let physptr = GuestAddress(SMBIOS_START)
+        .checked_add(mem::size_of::<Smbios30Entrypoint>() as u64)
+        .ok_or(Error::NotEnoughMemory)?;
+    let mut curptr = physptr;
+    let mut handle = 0;
+
+    {
+        handle += 1;
+        let mut smbios_biosinfo = SmbiosBiosInfo::default();
+        smbios_biosinfo.typ = BIOS_INFORMATION;
+        smbios_biosinfo.length = mem::size_of::<SmbiosBiosInfo>() as u8;
+        smbios_biosinfo.handle = handle;
+        smbios_biosinfo.vendor = 1; // First string written in this section
+        smbios_biosinfo.version = 2; // Second string written in this section
+        smbios_biosinfo.characteristics = PCI_SUPPORTED;
+        smbios_biosinfo.characteristics_ext2 = IS_VIRTUAL_MACHINE;
+        curptr = write_and_incr(mem, smbios_biosinfo, curptr)?;
+        curptr = write_string(mem, "cloud-hypervisor", curptr)?;
+        curptr = write_string(mem, "0", curptr)?;
+        curptr = write_and_incr(mem, 0 as u8, curptr)?;
+    }
+
+    {
+        handle += 1;
+        let mut smbios_sysinfo = SmbiosSysInfo::default();
+        smbios_sysinfo.typ = SYSTEM_INFORMATION;
+        smbios_sysinfo.length = mem::size_of::<SmbiosSysInfo>() as u8;
+        smbios_sysinfo.handle = handle;
+        smbios_sysinfo.manufacturer = 1; // First string written in this section
+        smbios_sysinfo.product_name = 2; // Second string written in this section
+        curptr = write_and_incr(mem, smbios_sysinfo, curptr)?;
+        curptr = write_string(mem, "Cloud Hypervisor", curptr)?;
+        curptr = write_string(mem, "cloud-hypervisor", curptr)?;
+        curptr = write_and_incr(mem, 0 as u8, curptr)?;
+    }
+
+    {
+        handle += 1;
+        let mut smbios_sysinfo = SmbiosSysInfo::default();
+        smbios_sysinfo.typ = END_OF_TABLE;
+        smbios_sysinfo.length = mem::size_of::<SmbiosSysInfo>() as u8;
+        smbios_sysinfo.handle = handle;
+        curptr = write_and_incr(mem, smbios_sysinfo, curptr)?;
+        curptr = write_and_incr(mem, 0 as u8, curptr)?;
+    }
+
+    {
+        let mut smbios_ep = Smbios30Entrypoint::default();
+        smbios_ep.signature = *SM3_MAGIC_IDENT;
+        smbios_ep.length = mem::size_of::<Smbios30Entrypoint>() as u8;
+        // SMBIOS rev 3.2.0
+        smbios_ep.majorver = 0x03;
+        smbios_ep.minorver = 0x02;
+        smbios_ep.docrev = 0x00;
+        smbios_ep.revision = 0x01; // SMBIOS 3.0
+        smbios_ep.max_size = curptr.unchecked_offset_from(physptr) as u32;
+        smbios_ep.physptr = physptr.0;
+        smbios_ep.checksum = compute_checksum(&smbios_ep);
+        mem.write_obj(smbios_ep, GuestAddress(SMBIOS_START))
+            .map_err(|_| Error::WriteSmbiosEp)?;
+    }
+
+    Ok(())
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn struct_size() {
+        assert_eq!(
+            mem::size_of::<Smbios30Entrypoint>(),
+            0x18usize,
+            concat!("Size of: ", stringify!(Smbios30Entrypoint))
+        );
+        assert_eq!(
+            mem::size_of::<SmbiosBiosInfo>(),
+            0x14usize,
+            concat!("Size of: ", stringify!(SmbiosBiosInfo))
+        );
+        assert_eq!(
+            mem::size_of::<SmbiosSysInfo>(),
+            0x1busize,
+            concat!("Size of: ", stringify!(SmbiosSysInfo))
+        );
+    }
+
+    #[test]
+    fn entrypoint_checksum() {
+        let mem = GuestMemoryMmap::from_ranges(&[(GuestAddress(SMBIOS_START), 4096)]).unwrap();
+
+        setup_smbios(&mem).unwrap();
+
+        let smbios_ep: Smbios30Entrypoint = mem.read_obj(GuestAddress(SMBIOS_START)).unwrap();
+
+        assert_eq!(compute_checksum(&smbios_ep), 0);
+    }
+}

arch_gen/src/x86/mod.rs

@@ -16,11 +16,7 @@
     clippy::should_implement_trait,
     clippy::transmute_ptr_to_ptr
 )]
-pub mod bootparam;
 #[allow(non_camel_case_types)]
 #[allow(non_upper_case_globals)]
 #[allow(clippy::unreadable_literal, clippy::redundant_static_lifetimes)]
 pub mod mpspec;
-#[allow(non_upper_case_globals)]
-#[allow(clippy::unreadable_literal, clippy::redundant_static_lifetimes)]
-pub mod msr_index;

block_util/Cargo.toml

@@ -0,0 +1,21 @@
+[package]
+name = "block_util"
+version = "0.1.0"
+authors = ["The Cloud Hypervisor Authors"]
+edition = "2018"
+
+[features]
+default = []
+io_uring = []
+
+[dependencies]
+io-uring = { git = "https://github.com/tokio-rs/io-uring.git", branch = "0.4" }
+libc = "0.2.74"
+log = "0.4.11"
+serde = ">=1.0.27"
+serde_derive = ">=1.0.27"
+serde_json = ">=1.0.9"
+virtio-bindings = { version = "0.1", features = ["virtio-v5_0_0"]}
+vm-memory = { version = "0.2.1", features = ["backend-mmap", "backend-atomic"] }
+vm-virtio = { path = "../vm-virtio" }
+vmm-sys-util = ">=0.3.1"

block_util/src/lib.rs

@@ -0,0 +1,545 @@
+// Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style license that can be
+// found in the LICENSE-BSD-3-Clause file.
+//
+// Copyright © 2020 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
+
+#[macro_use]
+extern crate log;
+#[macro_use]
+extern crate serde_derive;
+
+#[cfg(feature = "io_uring")]
+use io_uring::{opcode, IoUring, Probe};
+use serde::ser::{Serialize, SerializeStruct, Serializer};
+use std::cmp;
+use std::io::{self, Read, Seek, SeekFrom, Write};
+use std::os::linux::fs::MetadataExt;
+#[cfg(feature = "io_uring")]
+use std::os::unix::io::{AsRawFd, RawFd};
+use std::path::PathBuf;
+use std::result;
+use virtio_bindings::bindings::virtio_blk::*;
+use vm_memory::{ByteValued, Bytes, GuestAddress, GuestMemory, GuestMemoryError, GuestMemoryMmap};
+use vm_virtio::DescriptorChain;
+#[cfg(feature = "io_uring")]
+use vmm_sys_util::eventfd::EventFd;
+
+const SECTOR_SHIFT: u8 = 9;
+pub const SECTOR_SIZE: u64 = (0x01 as u64) << SECTOR_SHIFT;
+
+#[derive(Debug)]
+pub enum Error {
+    /// Guest gave us bad memory addresses.
+    GuestMemory(GuestMemoryError),
+    /// Guest gave us offsets that would have overflowed a usize.
+    CheckedOffset(GuestAddress, usize),
+    /// Guest gave us a write only descriptor that protocol says to read from.
+    UnexpectedWriteOnlyDescriptor,
+    /// Guest gave us a read only descriptor that protocol says to write to.
+    UnexpectedReadOnlyDescriptor,
+    /// Guest gave us too few descriptors in a descriptor chain.
+    DescriptorChainTooShort,
+    /// Guest gave us a descriptor that was too short to use.
+    DescriptorLengthTooSmall,
+    /// Getting a block's metadata fails for any reason.
+    GetFileMetadata,
+    /// The requested operation would cause a seek beyond disk end.
+    InvalidOffset,
+}
+
+fn build_device_id(disk_path: &PathBuf) -> result::Result<String, Error> {
+    let blk_metadata = match disk_path.metadata() {
+        Err(_) => return Err(Error::GetFileMetadata),
+        Ok(m) => m,
+    };
+    // This is how kvmtool does it.
+    let device_id = format!(
+        "{}{}{}",
+        blk_metadata.st_dev(),
+        blk_metadata.st_rdev(),
+        blk_metadata.st_ino()
+    );
+    Ok(device_id)
+}
+
+pub fn build_disk_image_id(disk_path: &PathBuf) -> Vec<u8> {
+    let mut default_disk_image_id = vec![0; VIRTIO_BLK_ID_BYTES as usize];
+    match build_device_id(disk_path) {
+        Err(_) => {
+            warn!("Could not generate device id. We'll use a default.");
+        }
+        Ok(m) => {
+            // The kernel only knows to read a maximum of VIRTIO_BLK_ID_BYTES.
+            // This will also zero out any leftover bytes.
+            let disk_id = m.as_bytes();
+            let bytes_to_copy = cmp::min(disk_id.len(), VIRTIO_BLK_ID_BYTES as usize);
+            default_disk_image_id[..bytes_to_copy].clone_from_slice(&disk_id[..bytes_to_copy])
+        }
+    }
+    default_disk_image_id
+}
+
+#[derive(Debug)]
+pub enum ExecuteError {
+    BadRequest(Error),
+    Flush(io::Error),
+    Read(GuestMemoryError),
+    Seek(io::Error),
+    Write(GuestMemoryError),
+    Unsupported(u32),
+    SubmitIoUring(io::Error),
+    GetHostAddress(GuestMemoryError),
+}
+
+impl ExecuteError {
+    pub fn status(&self) -> u32 {
+        match *self {
+            ExecuteError::BadRequest(_) => VIRTIO_BLK_S_IOERR,
+            ExecuteError::Flush(_) => VIRTIO_BLK_S_IOERR,
+            ExecuteError::Read(_) => VIRTIO_BLK_S_IOERR,
+            ExecuteError::Seek(_) => VIRTIO_BLK_S_IOERR,
+            ExecuteError::Write(_) => VIRTIO_BLK_S_IOERR,
+            ExecuteError::Unsupported(_) => VIRTIO_BLK_S_UNSUPP,
+            ExecuteError::SubmitIoUring(_) => VIRTIO_BLK_S_IOERR,
+            ExecuteError::GetHostAddress(_) => VIRTIO_BLK_S_IOERR,
+        }
+    }
+}
+
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RequestType {
+    In,
+    Out,
+    Flush,
+    GetDeviceID,
+    Unsupported(u32),
+}
+
+pub fn request_type(
+    mem: &GuestMemoryMmap,
+    desc_addr: GuestAddress,
+) -> result::Result<RequestType, Error> {
+    let type_ = mem.read_obj(desc_addr).map_err(Error::GuestMemory)?;
+    match type_ {
+        VIRTIO_BLK_T_IN => Ok(RequestType::In),
+        VIRTIO_BLK_T_OUT => Ok(RequestType::Out),
+        VIRTIO_BLK_T_FLUSH => Ok(RequestType::Flush),
+        VIRTIO_BLK_T_GET_ID => Ok(RequestType::GetDeviceID),
+        t => Ok(RequestType::Unsupported(t)),
+    }
+}
+
+fn sector(mem: &GuestMemoryMmap, desc_addr: GuestAddress) -> result::Result<u64, Error> {
+    const SECTOR_OFFSET: usize = 8;
+    let addr = match mem.checked_offset(desc_addr, SECTOR_OFFSET) {
+        Some(v) => v,
+        None => return Err(Error::CheckedOffset(desc_addr, SECTOR_OFFSET)),
+    };
+
+    mem.read_obj(addr).map_err(Error::GuestMemory)
+}
+
+pub struct Request {
+    pub request_type: RequestType,
+    pub sector: u64,
+    pub data_addr: GuestAddress,
+    pub data_len: u32,
+    pub status_addr: GuestAddress,
+    pub writeback: bool,
+}
+
+impl Request {
+    pub fn parse(
+        avail_desc: &DescriptorChain,
+        mem: &GuestMemoryMmap,
+    ) -> result::Result<Request, Error> {
+        // The head contains the request type which MUST be readable.
+        if avail_desc.is_write_only() {
+            return Err(Error::UnexpectedWriteOnlyDescriptor);
+        }
+
+        let mut req = Request {
+            request_type: request_type(&mem, avail_desc.addr)?,
+            sector: sector(&mem, avail_desc.addr)?,
+            data_addr: GuestAddress(0),
+            data_len: 0,
+            status_addr: GuestAddress(0),
+            writeback: true,
+        };
+
+        let data_desc;
+        let status_desc;
+        let desc = avail_desc
+            .next_descriptor()
+            .ok_or(Error::DescriptorChainTooShort)?;
+
+        if !desc.has_next() {
+            status_desc = desc;
+            // Only flush requests are allowed to skip the data descriptor.
+            if req.request_type != RequestType::Flush {
+                return Err(Error::DescriptorChainTooShort);
+            }
+        } else {
+            data_desc = desc;
+            status_desc = data_desc
+                .next_descriptor()
+                .ok_or(Error::DescriptorChainTooShort)?;
+
+            if data_desc.is_write_only() && req.request_type == RequestType::Out {
+                return Err(Error::UnexpectedWriteOnlyDescriptor);
+            }
+            if !data_desc.is_write_only() && req.request_type == RequestType::In {
+                return Err(Error::UnexpectedReadOnlyDescriptor);
+            }
+            if !data_desc.is_write_only() && req.request_type == RequestType::GetDeviceID {
+                return Err(Error::UnexpectedReadOnlyDescriptor);
+            }
+
+            req.data_addr = data_desc.addr;
+            req.data_len = data_desc.len;
+        }
+
+        // The status MUST always be writable.
+        if !status_desc.is_write_only() {
+            return Err(Error::UnexpectedReadOnlyDescriptor);
+        }
+
+        if status_desc.len < 1 {
+            return Err(Error::DescriptorLengthTooSmall);
+        }
+
+        req.status_addr = status_desc.addr;
+
+        Ok(req)
+    }
+
+    #[allow(clippy::ptr_arg)]
+    pub fn execute<T: Seek + Read + Write>(
+        &self,
+        disk: &mut T,
+        disk_nsectors: u64,
+        mem: &GuestMemoryMmap,
+        disk_id: &Vec<u8>,
+    ) -> result::Result<u32, ExecuteError> {
+        let mut top: u64 = u64::from(self.data_len) / SECTOR_SIZE;
+        if u64::from(self.data_len) % SECTOR_SIZE != 0 {
+            top += 1;
+        }
+        top = top
+            .checked_add(self.sector)
+            .ok_or(ExecuteError::BadRequest(Error::InvalidOffset))?;
+        if top > disk_nsectors {
+            return Err(ExecuteError::BadRequest(Error::InvalidOffset));
+        }
+
+        disk.seek(SeekFrom::Start(self.sector << SECTOR_SHIFT))
+            .map_err(ExecuteError::Seek)?;
+
+        match self.request_type {
+            RequestType::In => {
+                mem.read_exact_from(self.data_addr, disk, self.data_len as usize)
+                    .map_err(ExecuteError::Read)?;
+                return Ok(self.data_len);
+            }
+            RequestType::Out => {
+                mem.write_all_to(self.data_addr, disk, self.data_len as usize)
+                    .map_err(ExecuteError::Write)?;
+                if !self.writeback {
+                    disk.flush().map_err(ExecuteError::Flush)?;
+                }
+            }
+            RequestType::Flush => disk.flush().map_err(ExecuteError::Flush)?,
+            RequestType::GetDeviceID => {
+                if (self.data_len as usize) < disk_id.len() {
+                    return Err(ExecuteError::BadRequest(Error::InvalidOffset));
+                }
+                mem.write_slice(&disk_id.as_slice(), self.data_addr)
+                    .map_err(ExecuteError::Write)?;
+            }
+            RequestType::Unsupported(t) => return Err(ExecuteError::Unsupported(t)),
+        };
+        Ok(0)
+    }
+
+    #[cfg(feature = "io_uring")]
+    pub fn execute_io_uring(
+        &self,
+        mem: &GuestMemoryMmap,
+        io_uring: &mut IoUring,
+        disk_nsectors: u64,
+        disk_image_fd: RawFd,
+        disk_id: &[u8],
+        user_data: u64,
+    ) -> result::Result<bool, ExecuteError> {
+        let data_len = self.data_len;
+        let sector = self.sector;
+        let data_addr = self.data_addr;
+        let request_type = self.request_type;
+
+        let mut top: u64 = u64::from(data_len) / SECTOR_SIZE;
+        if u64::from(data_len) % SECTOR_SIZE != 0 {
+            top += 1;
+        }
+        top = top
+            .checked_add(sector)
+            .ok_or(ExecuteError::BadRequest(Error::InvalidOffset))?;
+        if top > disk_nsectors {
+            return Err(ExecuteError::BadRequest(Error::InvalidOffset));
+        }
+
+        let buf = mem
+            .get_slice(data_addr, data_len as usize)
+            .map_err(ExecuteError::GetHostAddress)?
+            .as_ptr();
+        let offset = (sector as i64) << SECTOR_SHIFT;
+
+        let (submitter, sq, _) = io_uring.split();
+        let mut avail_sq = sq.available();
+
+        // Queue operations expected to be submitted.
+        match request_type {
+            RequestType::In => {
+                // Safe because we know the file descriptor is valid and we
+                // relied on vm-memory to provide the buffer address.
+                let _ = unsafe {
+                    avail_sq.push(
+                        opcode::Read::new(opcode::types::Fd(disk_image_fd), buf, data_len)
+                            .offset(offset)
+                            .build()
+                            .user_data(user_data),
+                    )
+                };
+            }
+            RequestType::Out => {
+                // Safe because we know the file descriptor is valid and we
+                // relied on vm-memory to provide the buffer address.
+                let _ = unsafe {
+                    avail_sq.push(
+                        opcode::Write::new(opcode::types::Fd(disk_image_fd), buf, data_len)
+                            .offset(offset)
+                            .build()
+                            .user_data(user_data),
+                    )
+                };
+            }
+            RequestType::Flush => {
+                // Safe because we know the file descriptor is valid.
+                let _ = unsafe {
+                    avail_sq.push(
+                        opcode::Fsync::new(opcode::types::Fd(disk_image_fd))
+                            .build()
+                            .user_data(user_data),
+                    )
+                };
+            }
+            RequestType::GetDeviceID => {
+                if (data_len as usize) < disk_id.len() {
+                    return Err(ExecuteError::BadRequest(Error::InvalidOffset));
+                }
+                mem.write_slice(disk_id, data_addr)
+                    .map_err(ExecuteError::Write)?;
+                return Ok(false);
+            }
+            RequestType::Unsupported(t) => return Err(ExecuteError::Unsupported(t)),
+        }
+
+        // Update the submission queue and submit new operations to the
+        // io_uring instance.
+        avail_sq.sync();
+        submitter.submit().map_err(ExecuteError::SubmitIoUring)?;
+
+        Ok(true)
+    }
+
+    pub fn set_writeback(&mut self, writeback: bool) {
+        self.writeback = writeback
+    }
+}
+
+#[derive(Copy, Clone, Debug, Default, Deserialize)]
+#[repr(C, packed)]
+pub struct VirtioBlockConfig {
+    pub capacity: u64,
+    pub size_max: u32,
+    pub seg_max: u32,
+    pub geometry: VirtioBlockGeometry,
+    pub blk_size: u32,
+    pub physical_block_exp: u8,
+    pub alignment_offset: u8,
+    pub min_io_size: u16,
+    pub opt_io_size: u32,
+    pub writeback: u8,
+    pub unused: u8,
+    pub num_queues: u16,
+    pub max_discard_sectors: u32,
+    pub max_discard_seg: u32,
+    pub discard_sector_alignment: u32,
+    pub max_write_zeroes_sectors: u32,
+    pub max_write_zeroes_seg: u32,
+    pub write_zeroes_may_unmap: u8,
+    pub unused1: [u8; 3],
+}
+
+// We must explicitly implement Serialize since the structure is packed and
+// it's unsafe to borrow from a packed structure. And by default, if we derive
+// Serialize from serde, it will borrow the values from the structure.
+// That's why this implementation copies each field separately before it
+// serializes the entire structure field by field.
+impl Serialize for VirtioBlockConfig {
+    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+    where
+        S: Serializer,
+    {
+        let capacity = self.capacity;
+        let size_max = self.size_max;
+        let seg_max = self.seg_max;
+        let geometry = self.geometry;
+        let blk_size = self.blk_size;
+        let physical_block_exp = self.physical_block_exp;
+        let alignment_offset = self.alignment_offset;
+        let min_io_size = self.min_io_size;
+        let opt_io_size = self.opt_io_size;
+        let writeback = self.writeback;
+        let unused = self.unused;
+        let num_queues = self.num_queues;
+        let max_discard_sectors = self.max_discard_sectors;
+        let max_discard_seg = self.max_discard_seg;
+        let discard_sector_alignment = self.discard_sector_alignment;
+        let max_write_zeroes_sectors = self.max_write_zeroes_sectors;
+        let max_write_zeroes_seg = self.max_write_zeroes_seg;
+        let write_zeroes_may_unmap = self.write_zeroes_may_unmap;
+        let unused1 = self.unused1;
+
+        let mut virtio_block_config = serializer.serialize_struct("VirtioBlockConfig", 60)?;
+        virtio_block_config.serialize_field("capacity", &capacity)?;
+        virtio_block_config.serialize_field("size_max", &size_max)?;
+        virtio_block_config.serialize_field("seg_max", &seg_max)?;
+        virtio_block_config.serialize_field("geometry", &geometry)?;
+        virtio_block_config.serialize_field("blk_size", &blk_size)?;
+        virtio_block_config.serialize_field("physical_block_exp", &physical_block_exp)?;
+        virtio_block_config.serialize_field("alignment_offset", &alignment_offset)?;
+        virtio_block_config.serialize_field("min_io_size", &min_io_size)?;
+        virtio_block_config.serialize_field("opt_io_size", &opt_io_size)?;
+        virtio_block_config.serialize_field("writeback", &writeback)?;
+        virtio_block_config.serialize_field("unused", &unused)?;
+        virtio_block_config.serialize_field("num_queues", &num_queues)?;
+        virtio_block_config.serialize_field("max_discard_sectors", &max_discard_sectors)?;
+        virtio_block_config.serialize_field("max_discard_seg", &max_discard_seg)?;
+        virtio_block_config
+            .serialize_field("discard_sector_alignment", &discard_sector_alignment)?;
+        virtio_block_config
+            .serialize_field("max_write_zeroes_sectors", &max_write_zeroes_sectors)?;
+        virtio_block_config.serialize_field("max_write_zeroes_seg", &max_write_zeroes_seg)?;
+        virtio_block_config.serialize_field("write_zeroes_may_unmap", &write_zeroes_may_unmap)?;
+        virtio_block_config.serialize_field("unused1", &unused1)?;
+        virtio_block_config.end()
+    }
+}
+
+unsafe impl ByteValued for VirtioBlockConfig {}
+
+#[derive(Copy, Clone, Debug, Default, Deserialize)]
+#[repr(C, packed)]
+pub struct VirtioBlockGeometry {
+    pub cylinders: u16,
+    pub heads: u8,
+    pub sectors: u8,
+}
+
+// We must explicitly implement Serialize since the structure is packed and
+// it's unsafe to borrow from a packed structure. And by default, if we derive
+// Serialize from serde, it will borrow the values from the structure.
+// That's why this implementation copies each field separately before it
+// serializes the entire structure field by field.
+impl Serialize for VirtioBlockGeometry {
+    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+    where
+        S: Serializer,
+    {
+        let cylinders = self.cylinders;
+        let heads = self.heads;
+        let sectors = self.sectors;
+
+        let mut virtio_block_geometry = serializer.serialize_struct("VirtioBlockGeometry", 4)?;
+        virtio_block_geometry.serialize_field("cylinders", &cylinders)?;
+        virtio_block_geometry.serialize_field("heads", &heads)?;
+        virtio_block_geometry.serialize_field("sectors", &sectors)?;
+        virtio_block_geometry.end()
+    }
+}
+
+unsafe impl ByteValued for VirtioBlockGeometry {}
+
+/// Check if io_uring for block device can be used on the current system, as
+/// it correctly supports the expected io_uring features.
+#[cfg(feature = "io_uring")]
+pub fn block_io_uring_is_supported() -> bool {
+    let error_msg = "io_uring not supported:";
+
+    // Check we can create an io_uring instance, which effectively verifies
+    // that io_uring_setup() syscall is supported.
+    let io_uring = match IoUring::new(1) {
+        Ok(io_uring) => io_uring,
+        Err(e) => {
+            info!("{} failed to create io_uring instance: {}", error_msg, e);
+            return false;
+        }
+    };
+
+    let submitter = io_uring.submitter();
+
+    let event_fd = match EventFd::new(libc::EFD_NONBLOCK) {
+        Ok(fd) => fd,
+        Err(e) => {
+            info!("{} failed to create eventfd: {}", error_msg, e);
+            return false;
+        }
+    };
+
+    // Check we can register an eventfd as this is going to be needed while
+    // using io_uring with the virtio block device. This also validates that
+    // io_uring_register() syscall is supported.
+    match submitter.register_eventfd(event_fd.as_raw_fd()) {
+        Ok(_) => {}
+        Err(e) => {
+            info!("{} failed to register eventfd: {}", error_msg, e);
+            return false;
+        }
+    }
+
+    let mut probe = Probe::new();
+
+    // Check we can register a probe to validate supported operations.
+    match submitter.register_probe(&mut probe) {
+        Ok(_) => {}
+        Err(e) => {
+            info!("{} failed to register a probe: {}", error_msg, e);
+            return false;
+        }
+    }
+
+    // Check IORING_OP_FSYNC is supported
+    if !probe.is_supported(opcode::Fsync::CODE) {
+        info!("{} IORING_OP_FSYNC operation not supported", error_msg);
+        return false;
+    }
+
+    // Check IORING_OP_READ is supported
+    if !probe.is_supported(opcode::Read::CODE) {
+        info!("{} IORING_OP_READ operation not supported", error_msg);
+        return false;
+    }
+
+    // Check IORING_OP_WRITE is supported
+    if !probe.is_supported(opcode::Write::CODE) {
+        info!("{} IORING_OP_WRITE operation not supported", error_msg);
+        return false;
+    }
+
+    true
+}

build.rs

@@ -0,0 +1,22 @@
+// Copyright © 2020 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+
+use std::process::Command;
+
+fn main() {
+    let git_out = Command::new("git")
+        .args(&["describe", "--dirty"])
+        .output()
+        .expect("Expect to get git describe output");
+
+    // This println!() has a special behavior, as it will set the environment
+    // variable BUILT_VERSION, so that it can be reused from the binary.
+    // Particularly, this is used from src/main.rs to display the exact
+    // version.
+    println!(
+        "cargo:rustc-env=BUILT_VERSION={}",
+        String::from_utf8(git_out.stdout).unwrap()
+    );
+}

devices/Cargo.toml

@@ -4,13 +4,19 @@ version = "0.1.0"
 authors = ["The Chromium OS Authors"]
 
 [dependencies]
-byteorder = "1.3.2"
+anyhow = "1.0"
+bitflags = ">=1.2.1"
+byteorder = "1.3.4"
 epoll = ">=4.0.1"
-kvm-bindings = "0.2.0"
-kvm-ioctls = "0.4.0"
-libc = "0.2.60"
-log = "0.4.8"
-vm-memory = { git = "https://github.com/rust-vmm/vm-memory" }
+libc = "0.2.74"
+log = "0.4.11"
+serde = {version = ">=1.0.27", features = ["rc"] }
+serde_derive = ">=1.0.27"
+serde_json = ">=1.0.9"
+vm-device = { path = "../vm-device" }
+acpi_tables = { path = "../acpi_tables", optional = true }
+vm-memory = "0.2.1"
+vm-migration = { path = "../vm-migration" }
 vmm-sys-util = ">=0.3.1"
 
 [dev-dependencies]
@@ -18,5 +24,6 @@ tempfile = "3.1.0"
 
 [features]
 default = []
-acpi = []
+acpi = ["acpi_tables"]
 cmos = []
+fwdebug = []

devices/src/acpi.rs

@@ -3,10 +3,13 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 
+use acpi_tables::{aml, aml::Aml};
+use std::sync::Arc;
+use std::time::Instant;
+use vm_device::interrupt::InterruptSourceGroup;
 use vmm_sys_util::eventfd::EventFd;
 use BusDevice;
-use HotPlugNotificationType;
-use Interrupt;
+use HotPlugNotificationFlags;
 
 /// A device for handling ACPI shutdown and reboot
 pub struct AcpiShutdownDevice {
@@ -46,6 +49,7 @@ impl BusDevice for AcpiShutdownDevice {
         const SLEEP_VALUE_BIT: u8 = 2;
         if data[0] == (S5_SLEEP_VALUE << SLEEP_VALUE_BIT) | (1 << SLEEP_STATUS_EN_BIT) {
             debug!("ACPI Shutdown signalled");
+            extern crate bitflags;
             if let Err(e) = self.exit_evt.write(1) {
                 error!("Error triggering ACPI shutdown event: {}", e);
             }
@@ -55,26 +59,26 @@ impl BusDevice for AcpiShutdownDevice {
 
 /// A device for handling ACPI GED event generation
 pub struct AcpiGEDDevice {
-    interrupt: Box<dyn Interrupt>,
-    notification_type: HotPlugNotificationType,
+    interrupt: Arc<Box<dyn InterruptSourceGroup>>,
+    notification_type: HotPlugNotificationFlags,
     ged_irq: u32,
 }
 
 impl AcpiGEDDevice {
-    pub fn new(interrupt: Box<dyn Interrupt>, ged_irq: u32) -> AcpiGEDDevice {
+    pub fn new(interrupt: Arc<Box<dyn InterruptSourceGroup>>, ged_irq: u32) -> AcpiGEDDevice {
         AcpiGEDDevice {
             interrupt,
-            notification_type: HotPlugNotificationType::NoDevicesChanged,
+            notification_type: HotPlugNotificationFlags::NO_DEVICES_CHANGED,
             ged_irq,
         }
     }
 
     pub fn notify(
         &mut self,
-        notification_type: HotPlugNotificationType,
+        notification_type: HotPlugNotificationFlags,
     ) -> Result<(), std::io::Error> {
-        self.notification_type = notification_type;
-        self.interrupt.deliver()
+        self.notification_type |= notification_type;
+        self.interrupt.trigger(0)
     }
 
     pub fn irq(&self) -> u32 {
@@ -86,8 +90,98 @@ impl AcpiGEDDevice {
 impl BusDevice for AcpiGEDDevice {
     // Spec has all fields as zero
     fn read(&mut self, _base: u64, _offset: u64, data: &mut [u8]) {
-        data[0] = self.notification_type as u8;
-        self.notification_type = HotPlugNotificationType::NoDevicesChanged;
+        data[0] = self.notification_type.bits();
+        self.notification_type = HotPlugNotificationFlags::NO_DEVICES_CHANGED;
+    }
+
+    fn write(&mut self, _base: u64, _offset: u64, _data: &[u8]) {}
+}
+
+#[cfg(feature = "acpi")]
+impl Aml for AcpiGEDDevice {
+    fn to_aml_bytes(&self) -> Vec<u8> {
+        aml::Device::new(
+            "_SB_.GED_".into(),
+            vec![
+                &aml::Name::new("_HID".into(), &"ACPI0013"),
+                &aml::Name::new("_UID".into(), &aml::ZERO),
+                &aml::Name::new(
+                    "_CRS".into(),
+                    &aml::ResourceTemplate::new(vec![&aml::Interrupt::new(
+                        true,
+                        true,
+                        false,
+                        false,
+                        self.ged_irq,
+                    )]),
+                ),
+                &aml::OpRegion::new("GDST".into(), aml::OpRegionSpace::SystemIO, 0xb000, 0x1),
+                &aml::Field::new(
+                    "GDST".into(),
+                    aml::FieldAccessType::Byte,
+                    aml::FieldUpdateRule::WriteAsZeroes,
+                    vec![aml::FieldEntry::Named(*b"GDAT", 8)],
+                ),
+                &aml::Method::new(
+                    "_EVT".into(),
+                    1,
+                    true,
+                    vec![
+                        &aml::Store::new(&aml::Local(0), &aml::Path::new("GDAT")),
+                        &aml::And::new(&aml::Local(1), &aml::Local(0), &aml::ONE),
+                        &aml::If::new(
+                            &aml::Equal::new(&aml::Local(1), &aml::ONE),
+                            vec![&aml::MethodCall::new("\\_SB_.CPUS.CSCN".into(), vec![])],
+                        ),
+                        &aml::And::new(&aml::Local(1), &aml::Local(0), &2usize),
+                        &aml::If::new(
+                            &aml::Equal::new(&aml::Local(1), &2usize),
+                            vec![&aml::MethodCall::new("\\_SB_.MHPC.MSCN".into(), vec![])],
+                        ),
+                        &aml::And::new(&aml::Local(1), &aml::Local(0), &4usize),
+                        &aml::If::new(
+                            &aml::Equal::new(&aml::Local(1), &4usize),
+                            vec![&aml::MethodCall::new("\\_SB_.PCI0.PCNT".into(), vec![])],
+                        ),
+                    ],
+                ),
+            ],
+        )
+        .to_aml_bytes()
+    }
+}
+
+pub struct AcpiPMTimerDevice {
+    start: Instant,
+}
+
+impl AcpiPMTimerDevice {
+    pub fn new() -> Self {
+        Self {
+            start: Instant::now(),
+        }
+    }
+}
+
+impl Default for AcpiPMTimerDevice {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+impl BusDevice for AcpiPMTimerDevice {
+    fn read(&mut self, _base: u64, _offset: u64, data: &mut [u8]) {
+        let now = Instant::now();
+        let since = now.duration_since(self.start);
+        let nanos = since.as_nanos();
+
+        const PM_TIMER_FREQUENCY_HZ: u128 = 3_579_545;
+        const NANOS_PER_SECOND: u128 = 1_000_000_000;
+
+        let counter = (nanos * PM_TIMER_FREQUENCY_HZ) / NANOS_PER_SECOND;
+        let counter: u32 = (counter & 0xffff_ffff) as u32;
+
+        data.copy_from_slice(&counter.to_le_bytes());
     }
 
     fn write(&mut self, _base: u64, _offset: u64, _data: &[u8]) {}

devices/src/bus.rs

@@ -9,7 +9,7 @@
 
 use std::cmp::{Ord, Ordering, PartialEq, PartialOrd};
 use std::collections::btree_map::BTreeMap;
-use std::sync::{Arc, Mutex, RwLock};
+use std::sync::{Arc, Mutex, RwLock, Weak};
 use std::{convert, error, fmt, io, result};
 
 /// Trait for devices that respond to reads or writes in an arbitrary address space.
@@ -95,7 +95,7 @@ impl PartialOrd for BusRange {
 /// only restriction is that no two devices can overlap in this address space.
 #[derive(Default)]
 pub struct Bus {
-    devices: RwLock<BTreeMap<BusRange, Arc<Mutex<dyn BusDevice>>>>,
+    devices: RwLock<BTreeMap<BusRange, Weak<Mutex<dyn BusDevice>>>>,
 }
 
 impl Bus {
@@ -112,7 +112,7 @@ impl Bus {
             .range(..=BusRange { base: addr, len: 1 })
             .rev()
             .next()?;
-        Some((*range, dev.clone()))
+        Some((*range, dev.upgrade().unwrap().clone()))
     }
 
     #[allow(clippy::type_complexity)]
@@ -147,7 +147,7 @@ impl Bus {
             .devices
             .write()
             .unwrap()
-            .insert(BusRange { base, len }, device)
+            .insert(BusRange { base, len }, Arc::downgrade(&device))
             .is_some()
         {
             return Err(Error::Overlap);
@@ -171,6 +171,24 @@ impl Bus {
         Ok(())
     }
 
+    /// Removes all entries referencing the given device.
+    pub fn remove_by_device(&self, device: &Arc<Mutex<dyn BusDevice>>) -> Result<()> {
+        let mut device_list = self.devices.write().unwrap();
+        let mut remove_key_list = Vec::new();
+
+        for (key, value) in device_list.iter() {
+            if Arc::ptr_eq(&value.upgrade().unwrap(), device) {
+                remove_key_list.push(*key);
+            }
+        }
+
+        for key in remove_key_list.iter() {
+            device_list.remove(key);
+        }
+
+        Ok(())
+    }
+
     /// Updates the address range for an existing device.
     pub fn update_range(
         &self,
@@ -312,9 +330,8 @@ mod tests {
 
         let bus = Bus::new();
         let mut data = [1, 2, 3, 4];
-        assert!(bus
-            .insert(Arc::new(Mutex::new(DummyDevice)), 0x10, 0x10)
-            .is_ok());
+        let device = Arc::new(Mutex::new(DummyDevice));
+        assert!(bus.insert(device.clone(), 0x10, 0x10).is_ok());
         assert!(bus.write(0x10, &mut data));
         assert!(bus.read(0x10, &mut data));
         assert_eq!(data, [1, 2, 3, 4]);

devices/src/gic.rs

@@ -0,0 +1,85 @@
+// Copyright 2020, ARM Limited.
+//
+// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
+
+use super::interrupt_controller::{Error, InterruptController};
+use std::result;
+use std::sync::Arc;
+use vm_device::interrupt::{
+    InterruptIndex, InterruptManager, InterruptSourceGroup, MsiIrqGroupConfig,
+};
+use vm_migration::{Migratable, MigratableError, Pausable, Snapshot, Snapshottable, Transportable};
+
+type Result<T> = result::Result<T, Error>;
+
+// Reserve 32 IRQs (GSI 32 ~ 64) for legacy device.
+// GsiAllocator should allocate beyond this: from 64 on
+pub const IRQ_LEGACY_COUNT: usize = 32;
+pub const IRQ_SPI_OFFSET: usize = 32;
+
+// This Gic struct implements InterruptController to provide interrupt delivery service.
+// The Gic source files in arch/ folder maintain the Aarch64 specific Gic device.
+// The 2 Gic instances could be merged together.
+// Leave this refactoring to future. Two options may be considered:
+//   1. Move Gic*.rs from arch/ folder here.
+//   2. Move this file and ioapic.rs to arch/, as they are architecture specific.
+pub struct Gic {
+    interrupt_source_group: Arc<Box<dyn InterruptSourceGroup>>,
+}
+
+impl Gic {
+    pub fn new(
+        _vcpu_count: u8,
+        interrupt_manager: Arc<dyn InterruptManager<GroupConfig = MsiIrqGroupConfig>>,
+    ) -> Result<Gic> {
+        let interrupt_source_group = interrupt_manager
+            .create_group(MsiIrqGroupConfig {
+                base: IRQ_SPI_OFFSET as InterruptIndex,
+                count: IRQ_LEGACY_COUNT as InterruptIndex,
+            })
+            .map_err(Error::CreateInterruptSourceGroup)?;
+
+        Ok(Gic {
+            interrupt_source_group,
+        })
+    }
+}
+
+impl InterruptController for Gic {
+    fn enable(&self) -> Result<()> {
+        &self
+            .interrupt_source_group
+            .enable()
+            .map_err(Error::EnableInterrupt)?;
+        Ok(())
+    }
+
+    // This should be called anytime an interrupt needs to be injected into the
+    // running guest.
+    fn service_irq(&mut self, irq: usize) -> Result<()> {
+        self.interrupt_source_group
+            .trigger(irq as InterruptIndex)
+            .map_err(Error::TriggerInterrupt)?;
+
+        Ok(())
+    }
+}
+
+const GIC_SNAPSHOT_ID: &str = "gic";
+impl Snapshottable for Gic {
+    fn id(&self) -> String {
+        GIC_SNAPSHOT_ID.to_string()
+    }
+
+    fn snapshot(&self) -> std::result::Result<Snapshot, MigratableError> {
+        unimplemented!();
+    }
+
+    fn restore(&mut self, _snapshot: Snapshot) -> std::result::Result<(), MigratableError> {
+        unimplemented!();
+    }
+}
+
+impl Pausable for Gic {}
+impl Transportable for Gic {}
+impl Migratable for Gic {}

devices/src/interrupt_controller.rs

@@ -0,0 +1,61 @@
+// Copyright 2020, ARM Limited.
+//
+// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
+
+use std::io;
+use std::result;
+
+#[derive(Debug)]
+pub enum Error {
+    /// Invalid destination mode.
+    InvalidDestinationMode,
+    /// Invalid trigger mode.
+    InvalidTriggerMode,
+    /// Invalid delivery mode.
+    InvalidDeliveryMode,
+    /// Failed creating the interrupt source group.
+    CreateInterruptSourceGroup(io::Error),
+    /// Failed triggering the interrupt.
+    TriggerInterrupt(io::Error),
+    /// Failed masking the interrupt.
+    MaskInterrupt(io::Error),
+    /// Failed unmasking the interrupt.
+    UnmaskInterrupt(io::Error),
+    /// Failed updating the interrupt.
+    UpdateInterrupt(io::Error),
+    /// Failed enabling the interrupt.
+    EnableInterrupt(io::Error),
+}
+
+type Result<T> = result::Result<T, Error>;
+
+pub struct MsiMessage {
+    // Message Address Register
+    //   31-20: Base address. Fixed value (0x0FEE)
+    //   19-12: Destination ID
+    //   11-4:  Reserved
+    //   3:     Redirection Hint indication
+    //   2:     Destination Mode
+    //   1-0:   Reserved
+    pub addr: u32,
+    // Message Data Register
+    //   32-16: Reserved
+    //   15:    Trigger Mode. 0 = Edge, 1 = Level
+    //   14:    Level. 0 = Deassert, 1 = Assert
+    //   13-11: Reserved
+    //   10-8:  Delivery Mode
+    //   7-0:   Vector
+    pub data: u32,
+}
+
+// Introduce trait InterruptController to uniform the interrupt
+// service provided for devices.
+// Device manager uses this trait without caring whether it is a
+// IOAPIC (X86) or GIC (Arm).
+pub trait InterruptController: Send {
+    fn service_irq(&mut self, irq: usize) -> Result<()>;
+    #[cfg(target_arch = "aarch64")]
+    fn enable(&self) -> Result<()>;
+    #[cfg(target_arch = "x86_64")]
+    fn end_of_interrupt(&mut self, vec: u8);
+}

devices/src/ioapic.rs

@@ -9,25 +9,25 @@
 // Implementation of an intel 82093AA Input/Output Advanced Programmable Interrupt Controller
 // See https://pdos.csail.mit.edu/6.828/2016/readings/ia32/ioapic.pdf for a specification.
 
+use super::interrupt_controller::{Error, InterruptController};
 use crate::BusDevice;
+use anyhow::anyhow;
 use byteorder::{ByteOrder, LittleEndian};
-use kvm_bindings::kvm_msi;
-use kvm_ioctls::VmFd;
 use std::result;
 use std::sync::Arc;
+use vm_device::interrupt::{
+    InterruptIndex, InterruptManager, InterruptSourceConfig, InterruptSourceGroup,
+    MsiIrqGroupConfig, MsiIrqSourceConfig,
+};
 use vm_memory::GuestAddress;
+use vm_migration::{
+    Migratable, MigratableError, Pausable, Snapshot, SnapshotDataSection, Snapshottable,
+    Transportable,
+};
 
-#[derive(Debug)]
-pub enum Error {
-    /// Failed to send an interrupt.
-    InterruptFailed(kvm_ioctls::Error),
-    /// Invalid destination mode.
-    InvalidDestinationMode,
-    /// Invalid trigger mode.
-    InvalidTriggerMode,
-    /// Invalid delivery mode.
-    InvalidDeliveryMode,
-}
+#[derive(Serialize, Deserialize)]
+#[serde(remote = "GuestAddress")]
+pub struct GuestAddressDef(pub u64);
 
 type Result<T> = result::Result<T, Error>;
 
@@ -86,25 +86,6 @@ fn set_remote_irr(entry: &mut RedirectionTableEntry, val: u8) {
     *entry |= u64::from(val & 0x1) << 14;
 }
 
-pub struct MsiMessage {
-    // Message Address Register
-    //   31-20: Base address. Fixed value (0x0FEE)
-    //   19-12: Destination ID
-    //   11-4:  Reserved
-    //   3:     Redirection Hint indication
-    //   2:     Destination Mode
-    //   1-0:   Reserved
-    pub addr: u32,
-    // Message Data Register
-    //   32-16: Reserved
-    //   15:    Trigger Mode. 0 = Edge, 1 = Level
-    //   14:    Level. 0 = Deassert, 1 = Assert
-    //   13-11: Reserved
-    //   10-8:  Delivery Mode
-    //   7-0:   Vector
-    pub data: u32,
-}
-
 pub const NUM_IOAPIC_PINS: usize = 24;
 const IOAPIC_VERSION_ID: u32 = 0x0017_0011;
 
@@ -153,10 +134,22 @@ fn decode_irq_from_selector(selector: u8) -> (usize, bool) {
 }
 
 pub struct Ioapic {
-    id: u32,
+    id: String,
+    id_reg: u32,
     reg_sel: u32,
     reg_entries: [RedirectionTableEntry; NUM_IOAPIC_PINS],
-    vm_fd: Arc<VmFd>,
+    used_entries: [bool; NUM_IOAPIC_PINS],
+    apic_address: GuestAddress,
+    interrupt_source_group: Arc<Box<dyn InterruptSourceGroup>>,
+}
+
+#[derive(Serialize, Deserialize)]
+pub struct IoapicState {
+    id_reg: u32,
+    reg_sel: u32,
+    reg_entries: [RedirectionTableEntry; NUM_IOAPIC_PINS],
+    used_entries: [bool; NUM_IOAPIC_PINS],
+    #[serde(with = "GuestAddressDef")]
     apic_address: GuestAddress,
 }
 
@@ -196,118 +189,38 @@ impl BusDevice for Ioapic {
 }
 
 impl Ioapic {
-    pub fn new(vm_fd: Arc<VmFd>, apic_address: GuestAddress) -> Ioapic {
-        Ioapic {
-            id: 0,
+    pub fn new(
+        id: String,
+        apic_address: GuestAddress,
+        interrupt_manager: Arc<dyn InterruptManager<GroupConfig = MsiIrqGroupConfig>>,
+    ) -> Result<Ioapic> {
+        let interrupt_source_group = interrupt_manager
+            .create_group(MsiIrqGroupConfig {
+                base: 0 as InterruptIndex,
+                count: NUM_IOAPIC_PINS as InterruptIndex,
+            })
+            .map_err(Error::CreateInterruptSourceGroup)?;
+
+        interrupt_source_group
+            .enable()
+            .map_err(Error::EnableInterrupt)?;
+
+        Ok(Ioapic {
+            id,
+            id_reg: 0,
             reg_sel: 0,
             reg_entries: [0; NUM_IOAPIC_PINS],
-            vm_fd,
+            used_entries: [false; NUM_IOAPIC_PINS],
             apic_address,
-        }
-    }
-
-    // The ioapic must be informed about EOIs in order to deassert interrupts
-    // already sent.
-    pub fn end_of_interrupt(&mut self, vec: u8) {
-        for i in 0..NUM_IOAPIC_PINS {
-            let entry = &mut self.reg_entries[i];
-            // Clear Remote IRR bit
-            if vector(*entry) == vec && trigger_mode(*entry) == 1 {
-                set_remote_irr(entry, 0);
-            }
-        }
-    }
-
-    // This should be called anytime an interrupt needs to be injected into the
-    // running guest.
-    pub fn service_irq(&mut self, irq: usize) -> Result<()> {
-        let entry = &mut self.reg_entries[irq];
-
-        // Don't inject the interrupt if the IRQ is masked
-        if interrupt_mask(*entry) == 1 {
-            return Ok(());
-        }
-
-        // Validate Destination Mode value, and retrieve Destination ID
-        let destination_mode = destination_mode(*entry);
-        let destination_id: u8 = match destination_mode {
-            x if x == DestinationMode::Physical as u8 => destination_field_physical(*entry),
-            x if x == DestinationMode::Logical as u8 => destination_field_logical(*entry),
-            _ => return Err(Error::InvalidDestinationMode),
-        };
-
-        // When this bit is set, the message is directed to the processor with
-        // the lowest interrupt priority among processors that can receive the
-        // interrupt.
-        let redirection_hint: u8 = 1;
-
-        // Generate MSI message address
-        let address_lo: u32 = self.apic_address.0 as u32
-            | u32::from(destination_id) << 12
-            | u32::from(redirection_hint) << 3
-            | u32::from(destination_mode) << 2;
-
-        // Validate Trigger Mode value
-        let trigger_mode = trigger_mode(*entry);
-        match trigger_mode {
-            x if (x == TriggerMode::Edge as u8) || (x == TriggerMode::Level as u8) => {}
-            _ => return Err(Error::InvalidTriggerMode),
-        }
-
-        // Validate Delivery Mode value
-        let delivery_mode = delivery_mode(*entry);
-        match delivery_mode {
-            x if (x == DeliveryMode::Fixed as u8)
-                || (x == DeliveryMode::Lowest as u8)
-                || (x == DeliveryMode::SMI as u8)
-                || (x == DeliveryMode::RemoteRead as u8)
-                || (x == DeliveryMode::NMI as u8)
-                || (x == DeliveryMode::Init as u8)
-                || (x == DeliveryMode::Startup as u8)
-                || (x == DeliveryMode::External as u8) => {}
-            _ => return Err(Error::InvalidDeliveryMode),
-        }
-
-        // Generate MSI message data
-        let data: u32 = u32::from(trigger_mode) << 15
-            | u32::from(remote_irr(*entry)) << 14
-            | u32::from(delivery_mode) << 8
-            | u32::from(vector(*entry));
-
-        let msi = kvm_msi {
-            address_lo,
-            address_hi: 0x0,
-            data,
-            flags: 0u32,
-            devid: 0u32,
-            pad: [0u8; 12],
-        };
-
-        match self.vm_fd.signal_msi(msi) {
-            Ok(ret) => {
-                if ret > 0 {
-                    debug!("MSI message successfully delivered");
-                    // If trigger mode is level sensitive, set the Remote IRR bit.
-                    // It will be cleared when the EOI is received.
-                    if trigger_mode == 1 {
-                        set_remote_irr(entry, 1);
-                    }
-                    // Clear the Delivery Status bit
-                    set_delivery_status(entry, 0);
-                } else {
-                    warn!("failed to deliver MSI message, blocked by guest");
-                }
-                Ok(())
-            }
-            Err(e) => Err(Error::InterruptFailed(e)),
-        }
+            interrupt_source_group,
+        })
     }
 
     fn ioapic_write(&mut self, val: u32) {
         debug!("IOAPIC_W reg 0x{:x}, val 0x{:x}", self.reg_sel, val);
 
         match self.reg_sel as u8 {
-            IOAPIC_REG_ID => self.id = (val >> 24) & 0xf,
+            IOAPIC_REG_ID => self.id_reg = (val >> 24) & 0xf,
             IOWIN_OFF..=REG_MAX_OFFSET => {
                 let (index, is_high_bits) = decode_irq_from_selector(self.reg_sel as u8);
                 if is_high_bits {
@@ -320,6 +233,13 @@ impl Ioapic {
                     self.reg_entries[index] &= 0xffff_ffff_0000_5000;
                     self.reg_entries[index] |= u64::from(val) & 0xffff_afff;
                 }
+                // The entry must be updated through the interrupt source
+                // group.
+                if let Err(e) = self.update_entry(index) {
+                    error!("Failed updating IOAPIC entry: {:?}", e);
+                }
+                // Store the information this IRQ is now being used.
+                self.used_entries[index] = true;
             }
             _ => error!("IOAPIC: invalid write to register offset"),
         }
@@ -330,7 +250,7 @@ impl Ioapic {
 
         match self.reg_sel as u8 {
             IOAPIC_REG_VERSION => IOAPIC_VERSION_ID,
-            IOAPIC_REG_ID | IOAPIC_REG_ARBITRATION_ID => (self.id & 0xf) << 24,
+            IOAPIC_REG_ID | IOAPIC_REG_ARBITRATION_ID => (self.id_reg & 0xf) << 24,
             IOWIN_OFF..=REG_MAX_OFFSET => {
                 let (index, is_high_bits) = decode_irq_from_selector(self.reg_sel as u8);
                 if is_high_bits {
@@ -345,4 +265,182 @@ impl Ioapic {
             }
         }
     }
+
+    fn state(&self) -> IoapicState {
+        IoapicState {
+            id_reg: self.id_reg,
+            reg_sel: self.reg_sel,
+            reg_entries: self.reg_entries,
+            used_entries: self.used_entries,
+            apic_address: self.apic_address,
+        }
+    }
+
+    fn set_state(&mut self, state: &IoapicState) -> Result<()> {
+        self.id_reg = state.id_reg;
+        self.reg_sel = state.reg_sel;
+        self.reg_entries = state.reg_entries;
+        self.used_entries = state.used_entries;
+        self.apic_address = state.apic_address;
+        for (irq, entry) in self.used_entries.iter().enumerate() {
+            if *entry {
+                self.update_entry(irq)?;
+            }
+        }
+
+        Ok(())
+    }
+
+    fn update_entry(&self, irq: usize) -> Result<()> {
+        let entry = self.reg_entries[irq];
+
+        // Validate Destination Mode value, and retrieve Destination ID
+        let destination_mode = destination_mode(entry);
+        let destination_id: u8 = match destination_mode {
+            x if x == DestinationMode::Physical as u8 => destination_field_physical(entry),
+            x if x == DestinationMode::Logical as u8 => destination_field_logical(entry),
+            _ => return Err(Error::InvalidDestinationMode),
+        };
+
+        // When this bit is set, the message is directed to the processor with
+        // the lowest interrupt priority among processors that can receive the
+        // interrupt.
+        let redirection_hint: u8 = 1;
+
+        // Generate MSI message address
+        let low_addr: u32 = self.apic_address.0 as u32
+            | u32::from(destination_id) << 12
+            | u32::from(redirection_hint) << 3
+            | u32::from(destination_mode) << 2;
+
+        // Validate Trigger Mode value
+        let trigger_mode = trigger_mode(entry);
+        match trigger_mode {
+            x if (x == TriggerMode::Edge as u8) || (x == TriggerMode::Level as u8) => {}
+            _ => return Err(Error::InvalidTriggerMode),
+        }
+
+        // Validate Delivery Mode value
+        let delivery_mode = delivery_mode(entry);
+        match delivery_mode {
+            x if (x == DeliveryMode::Fixed as u8)
+                || (x == DeliveryMode::Lowest as u8)
+                || (x == DeliveryMode::SMI as u8)
+                || (x == DeliveryMode::RemoteRead as u8)
+                || (x == DeliveryMode::NMI as u8)
+                || (x == DeliveryMode::Init as u8)
+                || (x == DeliveryMode::Startup as u8)
+                || (x == DeliveryMode::External as u8) => {}
+            _ => return Err(Error::InvalidDeliveryMode),
+        }
+
+        // Generate MSI message data
+        let data: u32 = u32::from(trigger_mode) << 15
+            | u32::from(remote_irr(entry)) << 14
+            | u32::from(delivery_mode) << 8
+            | u32::from(vector(entry));
+
+        let config = MsiIrqSourceConfig {
+            high_addr: 0x0,
+            low_addr,
+            data,
+            devid: 0,
+        };
+
+        self.interrupt_source_group
+            .update(irq as InterruptIndex, InterruptSourceConfig::MsiIrq(config))
+            .map_err(Error::UpdateInterrupt)?;
+
+        if interrupt_mask(entry) == 1 {
+            self.interrupt_source_group
+                .mask(irq as InterruptIndex)
+                .map_err(Error::MaskInterrupt)?;
+        } else {
+            self.interrupt_source_group
+                .unmask(irq as InterruptIndex)
+                .map_err(Error::UnmaskInterrupt)?;
+        }
+
+        Ok(())
+    }
 }
+
+impl InterruptController for Ioapic {
+    // The ioapic must be informed about EOIs in order to deassert interrupts
+    // already sent.
+    fn end_of_interrupt(&mut self, vec: u8) {
+        for i in 0..NUM_IOAPIC_PINS {
+            let entry = &mut self.reg_entries[i];
+            // Clear Remote IRR bit
+            if vector(*entry) == vec && trigger_mode(*entry) == 1 {
+                set_remote_irr(entry, 0);
+            }
+        }
+    }
+
+    // This should be called anytime an interrupt needs to be injected into the
+    // running guest.
+    fn service_irq(&mut self, irq: usize) -> Result<()> {
+        let entry = &mut self.reg_entries[irq];
+
+        self.interrupt_source_group
+            .trigger(irq as InterruptIndex)
+            .map_err(Error::TriggerInterrupt)?;
+        debug!("Interrupt successfully delivered");
+
+        // If trigger mode is level sensitive, set the Remote IRR bit.
+        // It will be cleared when the EOI is received.
+        if trigger_mode(*entry) == 1 {
+            set_remote_irr(entry, 1);
+        }
+        // Clear the Delivery Status bit
+        set_delivery_status(entry, 0);
+
+        Ok(())
+    }
+}
+
+impl Snapshottable for Ioapic {
+    fn id(&self) -> String {
+        self.id.clone()
+    }
+
+    fn snapshot(&self) -> std::result::Result<Snapshot, MigratableError> {
+        let snapshot =
+            serde_json::to_vec(&self.state()).map_err(|e| MigratableError::Snapshot(e.into()))?;
+
+        let mut ioapic_snapshot = Snapshot::new(self.id.as_str());
+        ioapic_snapshot.add_data_section(SnapshotDataSection {
+            id: format!("{}-section", self.id),
+            snapshot,
+        });
+
+        Ok(ioapic_snapshot)
+    }
+
+    fn restore(&mut self, snapshot: Snapshot) -> std::result::Result<(), MigratableError> {
+        if let Some(ioapic_section) = snapshot.snapshot_data.get(&format!("{}-section", self.id)) {
+            let ioapic_state = match serde_json::from_slice(&ioapic_section.snapshot) {
+                Ok(state) => state,
+                Err(error) => {
+                    return Err(MigratableError::Restore(anyhow!(
+                        "Could not deserialize IOAPIC {}",
+                        error
+                    )))
+                }
+            };
+
+            return self.set_state(&ioapic_state).map_err(|e| {
+                MigratableError::Restore(anyhow!("Could not restore IOAPIC state {:?}", e))
+            });
+        }
+
+        Err(MigratableError::Restore(anyhow!(
+            "Could not find IOAPIC snapshot section"
+        )))
+    }
+}
+
+impl Pausable for Ioapic {}
+impl Transportable for Ioapic {}
+impl Migratable for Ioapic {}

devices/src/legacy/cmos.rs

@@ -2,7 +2,7 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
-use libc::{gmtime_r, time, time_t, tm};
+use libc::{clock_gettime, gmtime_r, time_t, timespec, tm, CLOCK_REALTIME};
 use std::cmp::min;
 use std::mem;
 
@@ -77,14 +77,17 @@ impl BusDevice for Cmos {
                 let day;
                 let month;
                 let year;
-                // The time and gmtime_r calls are safe as long as the structs they are given are
-                // large enough, and neither of them fail. It is safe to zero initialize the tm
-                // struct because it contains only plain data.
-                unsafe {
+                // The clock_gettime and gmtime_r calls are safe as long as the structs they are
+                // given are large enough, and neither of them fail. It is safe to zero initialize
+                // the tm and timespec struct because it contains only plain data.
+                let update_in_progress = unsafe {
+                    let mut timespec: timespec = mem::zeroed();
+                    clock_gettime(CLOCK_REALTIME, &mut timespec as *mut _);
+
+                    let now: time_t = timespec.tv_sec;
                     let mut tm: tm = mem::zeroed();
-                    let mut now: time_t = 0;
-                    time(&mut now as *mut _);
                     gmtime_r(&now, &mut tm as *mut _);
+
                     // The following lines of code are safe but depend on tm being in scope.
                     seconds = tm.tm_sec;
                     minutes = tm.tm_min;
@@ -93,6 +96,11 @@ impl BusDevice for Cmos {
                     day = tm.tm_mday;
                     month = tm.tm_mon + 1;
                     year = tm.tm_year;
+
+                    // Update in Progress bit held for last 224us of each second
+                    const NANOSECONDS_PER_SECOND: i64 = 1_000_000_000;
+                    const UIP_HOLD_LENGTH: i64 = 8 * NANOSECONDS_PER_SECOND / 32768;
+                    timespec.tv_nsec >= (NANOSECONDS_PER_SECOND - UIP_HOLD_LENGTH)
                 };
                 match self.index {
                     0x00 => to_bcd(seconds as u8),
@@ -102,6 +110,8 @@ impl BusDevice for Cmos {
                     0x07 => to_bcd(day as u8),
                     0x08 => to_bcd(month as u8),
                     0x09 => to_bcd((year % 100) as u8),
+                    // Bit 5 for 32kHz clock. Bit 7 for Update in Progress
+                    0x0a => 1 << 5 | (update_in_progress as u8) << 7,
                     0x32 => to_bcd(((year + 1900) / 100) as u8),
                     _ => {
                         // self.index is always guaranteed to be in range via INDEX_MASK.

devices/src/legacy/fwdebug.rs

@@ -0,0 +1,40 @@
+// Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style license that can be
+// found in the LICENSE-BSD-3-Clause file.
+//
+// Copyright © 2020 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
+//
+
+use BusDevice;
+
+/// Provides firmware debug output via I/O port controls
+#[derive(Default)]
+pub struct FwDebugDevice {}
+
+impl FwDebugDevice {
+    pub fn new() -> Self {
+        Self {}
+    }
+}
+
+/// FwDebugDevice sits on the I/O bus as 0x402 and receives ASCII characters
+impl BusDevice for FwDebugDevice {
+    /// Upon read return the magic value to indicate that there is a debug port
+    fn read(&mut self, _base: u64, _offset: u64, data: &mut [u8]) {
+        if data.len() == 1 {
+            data[0] = 0xe9
+        } else {
+            error!("Invalid read size on debug port: {}", data.len())
+        }
+    }
+
+    fn write(&mut self, _base: u64, _offset: u64, data: &[u8]) {
+        if data.len() == 1 {
+            print!("{}", data[0] as char);
+        } else {
+            error!("Invalid write size on debug port: {}", data.len())
+        }
+    }
+}

devices/src/legacy/mod.rs

@@ -7,10 +7,19 @@
 
 #[cfg(feature = "cmos")]
 mod cmos;
+#[cfg(feature = "fwdebug")]
+mod fwdebug;
 mod i8042;
+#[cfg(target_arch = "aarch64")]
+mod rtc_pl031;
 mod serial;
 
 #[cfg(feature = "cmos")]
 pub use self::cmos::Cmos;
+#[cfg(feature = "fwdebug")]
+pub use self::fwdebug::FwDebugDevice;
 pub use self::i8042::I8042Device;
 pub use self::serial::Serial;
+
+#[cfg(target_arch = "aarch64")]
+pub use self::rtc_pl031::RTC;

devices/src/legacy/rtc_pl031.rs

@@ -0,0 +1,626 @@
+// Copyright 2020 Arm Limited (or its affiliates). All rights reserved.
+// Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+// SPDX-License-Identifier: Apache-2.0
+
+//! ARM PL031 Real Time Clock
+//!
+//! This module implements a PL031 Real Time Clock (RTC) that provides to provides long time base counter.
+//! This is achieved by generating an interrupt signal after counting for a programmed number of cycles of
+//! a real-time clock input.
+//!
+use std::fmt;
+use std::sync::Arc;
+use std::time::Instant;
+use std::{io, result};
+
+use crate::BusDevice;
+use vm_device::interrupt::InterruptSourceGroup;
+
+// As you can see in https://static.docs.arm.com/ddi0224/c/real_time_clock_pl031_r1p3_technical_reference_manual_DDI0224C.pdf
+// at section 3.2 Summary of RTC registers, the total size occupied by this device is 0x000 -> 0xFFC + 4 = 0x1000.
+// From 0x0 to 0x1C we have following registers:
+const RTCDR: u64 = 0x0; // Data Register.
+const RTCMR: u64 = 0x4; // Match Register.
+const RTCLR: u64 = 0x8; // Load Regiser.
+const RTCCR: u64 = 0xc; // Control Register.
+const RTCIMSC: u64 = 0x10; // Interrupt Mask Set or Clear Register.
+const RTCRIS: u64 = 0x14; // Raw Interrupt Status.
+const RTCMIS: u64 = 0x18; // Masked Interrupt Status.
+const RTCICR: u64 = 0x1c; // Interrupt Clear Register.
+                          // From 0x020 to 0xFDC => reserved space.
+                          // From 0xFE0 to 0x1000 => Peripheral and PrimeCell Identification Registers which are Read Only registers.
+                          // AMBA standard devices have CIDs (Cell IDs) and PIDs (Peripheral IDs). The linux kernel will look for these in order to assert the identity
+                          // of these devices (i.e look at the `amba_device_try_add` function).
+                          // We are putting the expected values (look at 'Reset value' column from above mentioned document) in an array.
+const PL031_ID: [u8; 8] = [0x31, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1];
+// We are only interested in the margins.
+const AMBA_ID_LOW: u64 = 0xFE0;
+const AMBA_ID_HIGH: u64 = 0x1000;
+/// Constant to convert seconds to nanoseconds.
+pub const NANOS_PER_SECOND: u64 = 1_000_000_000;
+
+#[allow(unused_macros)]
+macro_rules! generate_read_fn {
+    ($fn_name: ident, $data_type: ty, $byte_type: ty, $type_size: expr, $endian_type: ident) => {
+        #[allow(dead_code)]
+        pub fn $fn_name(input: &[$byte_type]) -> $data_type {
+            assert!($type_size == std::mem::size_of::<$data_type>());
+            let mut array = [0u8; $type_size];
+            for (byte, read) in array.iter_mut().zip(input.iter().cloned()) {
+                *byte = read as u8;
+            }
+            <$data_type>::$endian_type(array)
+        }
+    };
+}
+
+#[allow(unused_macros)]
+macro_rules! generate_write_fn {
+    ($fn_name: ident, $data_type: ty, $byte_type: ty, $endian_type: ident) => {
+        #[allow(dead_code)]
+        pub fn $fn_name(buf: &mut [$byte_type], n: $data_type) {
+            for (byte, read) in buf
+                .iter_mut()
+                .zip(<$data_type>::$endian_type(n).iter().cloned())
+            {
+                *byte = read as $byte_type;
+            }
+        }
+    };
+}
+
+generate_read_fn!(read_le_u16, u16, u8, 2, from_le_bytes);
+generate_read_fn!(read_le_u32, u32, u8, 4, from_le_bytes);
+generate_read_fn!(read_le_u64, u64, u8, 8, from_le_bytes);
+generate_read_fn!(read_le_i32, i32, i8, 4, from_le_bytes);
+
+generate_read_fn!(read_be_u16, u16, u8, 2, from_be_bytes);
+generate_read_fn!(read_be_u32, u32, u8, 4, from_be_bytes);
+
+generate_write_fn!(write_le_u16, u16, u8, to_le_bytes);
+generate_write_fn!(write_le_u32, u32, u8, to_le_bytes);
+generate_write_fn!(write_le_u64, u64, u8, to_le_bytes);
+generate_write_fn!(write_le_i32, i32, i8, to_le_bytes);
+
+generate_write_fn!(write_be_u16, u16, u8, to_be_bytes);
+generate_write_fn!(write_be_u32, u32, u8, to_be_bytes);
+
+#[derive(Debug)]
+pub enum Error {
+    BadWriteOffset(u64),
+    InterruptFailure(io::Error),
+}
+
+impl fmt::Display for Error {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        match self {
+            Error::BadWriteOffset(offset) => write!(f, "Bad Write Offset: {}", offset),
+            Error::InterruptFailure(e) => write!(f, "Failed to trigger interrupt: {}", e),
+        }
+    }
+}
+
+type Result<T> = result::Result<T, Error>;
+
+/// Wrapper over `libc::clockid_t` to specify Linux Kernel clock source.
+pub enum ClockType {
+    /// Equivalent to `libc::CLOCK_MONOTONIC`.
+    Monotonic,
+    /// Equivalent to `libc::CLOCK_REALTIME`.
+    #[allow(dead_code)]
+    Real,
+    /// Equivalent to `libc::CLOCK_PROCESS_CPUTIME_ID`.
+    ProcessCpu,
+    /// Equivalent to `libc::CLOCK_THREAD_CPUTIME_ID`.
+    #[allow(dead_code)]
+    ThreadCpu,
+}
+
+impl Into<libc::clockid_t> for ClockType {
+    fn into(self) -> libc::clockid_t {
+        match self {
+            ClockType::Monotonic => libc::CLOCK_MONOTONIC,
+            ClockType::Real => libc::CLOCK_REALTIME,
+            ClockType::ProcessCpu => libc::CLOCK_PROCESS_CPUTIME_ID,
+            ClockType::ThreadCpu => libc::CLOCK_THREAD_CPUTIME_ID,
+        }
+    }
+}
+
+/// Structure representing the date in local time with nanosecond precision.
+pub struct LocalTime {
+    /// Seconds in current minute.
+    sec: i32,
+    /// Minutes in current hour.
+    min: i32,
+    /// Hours in current day, 24H format.
+    hour: i32,
+    /// Days in current month.
+    mday: i32,
+    /// Months in current year.
+    mon: i32,
+    /// Years passed since 1900 BC.
+    year: i32,
+    /// Nanoseconds in current second.
+    nsec: i64,
+}
+
+impl LocalTime {
+    /// Returns the [LocalTime](struct.LocalTime.html) structure for the calling moment.
+    #[allow(dead_code)]
+    pub fn now() -> LocalTime {
+        let mut timespec = libc::timespec {
+            tv_sec: 0,
+            tv_nsec: 0,
+        };
+        let mut tm: libc::tm = libc::tm {
+            tm_sec: 0,
+            tm_min: 0,
+            tm_hour: 0,
+            tm_mday: 0,
+            tm_mon: 0,
+            tm_year: 0,
+            tm_wday: 0,
+            tm_yday: 0,
+            tm_isdst: 0,
+            tm_gmtoff: 0,
+            tm_zone: std::ptr::null(),
+        };
+
+        // Safe because the parameters are valid.
+        unsafe {
+            libc::clock_gettime(libc::CLOCK_REALTIME, &mut timespec);
+            libc::localtime_r(&timespec.tv_sec, &mut tm);
+        }
+
+        LocalTime {
+            sec: tm.tm_sec,
+            min: tm.tm_min,
+            hour: tm.tm_hour,
+            mday: tm.tm_mday,
+            mon: tm.tm_mon,
+            year: tm.tm_year,
+            nsec: timespec.tv_nsec,
+        }
+    }
+}
+
+impl fmt::Display for LocalTime {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(
+            f,
+            "{}-{:02}-{:02}T{:02}:{:02}:{:02}.{:09}",
+            self.year + 1900,
+            self.mon + 1,
+            self.mday,
+            self.hour,
+            self.min,
+            self.sec,
+            self.nsec
+        )
+    }
+}
+
+/// Holds a micro-second resolution timestamp with both the real time and cpu time.
+#[derive(Clone)]
+pub struct TimestampUs {
+    /// Real time in microseconds.
+    pub time_us: u64,
+    /// Cpu time in microseconds.
+    pub cputime_us: u64,
+}
+
+impl Default for TimestampUs {
+    fn default() -> TimestampUs {
+        TimestampUs {
+            time_us: get_time(ClockType::Monotonic) / 1000,
+            cputime_us: get_time(ClockType::ProcessCpu) / 1000,
+        }
+    }
+}
+
+/// Returns a timestamp in nanoseconds from a monotonic clock.
+///
+/// Uses `_rdstc` on `x86_64` and [`get_time`](fn.get_time.html) on other architectures.
+#[allow(dead_code)]
+pub fn timestamp_cycles() -> u64 {
+    #[cfg(target_arch = "x86_64")]
+    // Safe because there's nothing that can go wrong with this call.
+    unsafe {
+        std::arch::x86_64::_rdtsc() as u64
+    }
+    #[cfg(not(target_arch = "x86_64"))]
+    {
+        get_time(ClockType::Monotonic)
+    }
+}
+
+/// Returns a timestamp in nanoseconds based on the provided clock type.
+///
+/// # Arguments
+///
+/// * `clock_type` - Identifier of the Linux Kernel clock on which to act.
+pub fn get_time(clock_type: ClockType) -> u64 {
+    let mut time_struct = libc::timespec {
+        tv_sec: 0,
+        tv_nsec: 0,
+    };
+    // Safe because the parameters are valid.
+    unsafe { libc::clock_gettime(clock_type.into(), &mut time_struct) };
+    seconds_to_nanoseconds(time_struct.tv_sec).unwrap() as u64 + (time_struct.tv_nsec as u64)
+}
+
+/// Converts a timestamp in seconds to an equivalent one in nanoseconds.
+/// Returns `None` if the conversion overflows.
+///
+/// # Arguments
+///
+/// * `value` - Timestamp in seconds.
+pub fn seconds_to_nanoseconds(value: i64) -> Option<i64> {
+    value.checked_mul(NANOS_PER_SECOND as i64)
+}
+
+/// A RTC device following the PL031 specification..
+pub struct RTC {
+    previous_now: Instant,
+    tick_offset: i64,
+    // This is used for implementing the RTC alarm. However, in Firecracker we do not need it.
+    match_value: u32,
+    // Writes to this register load an update value into the RTC.
+    load: u32,
+    imsc: u32,
+    ris: u32,
+    interrupt: Arc<Box<dyn InterruptSourceGroup>>,
+}
+
+impl RTC {
+    /// Constructs an AMBA PL031 RTC device.
+    pub fn new(interrupt: Arc<Box<dyn InterruptSourceGroup>>) -> RTC {
+        RTC {
+            // This is used only for duration measuring purposes.
+            previous_now: Instant::now(),
+            tick_offset: get_time(ClockType::Real) as i64,
+            match_value: 0,
+            load: 0,
+            imsc: 0,
+            ris: 0,
+            interrupt,
+        }
+    }
+
+    fn trigger_interrupt(&mut self) -> Result<()> {
+        self.interrupt.trigger(0).map_err(Error::InterruptFailure)?;
+        Ok(())
+    }
+
+    fn get_time(&self) -> u32 {
+        let ts = (self.tick_offset as i128)
+            + (Instant::now().duration_since(self.previous_now).as_nanos() as i128);
+        (ts / NANOS_PER_SECOND as i128) as u32
+    }
+
+    fn handle_write(&mut self, offset: u64, val: u32) -> Result<()> {
+        match offset {
+            RTCMR => {
+                // The MR register is used for implementing the RTC alarm. A real time clock alarm is
+                // a feature that can be used to allow a computer to 'wake up' after shut down to execute
+                // tasks every day or on a certain day. It can sometimes be found in the 'Power Management'
+                // section of a motherboard's BIOS setup. This is functionality that extends beyond
+                // Firecracker intended use. However, we increment a metric just in case.
+                self.match_value = val;
+            }
+            RTCLR => {
+                self.load = val;
+                self.previous_now = Instant::now();
+                // If the unwrap fails, then the internal value of the clock has been corrupted and
+                // we want to terminate the execution of the process.
+                self.tick_offset = seconds_to_nanoseconds(i64::from(val)).unwrap();
+            }
+            RTCIMSC => {
+                self.imsc = val & 1;
+                self.trigger_interrupt()?;
+            }
+            RTCICR => {
+                // As per above mentioned doc, the interrupt is cleared by writing any data value to
+                // the Interrupt Clear Register.
+                self.ris = 0;
+                self.trigger_interrupt()?;
+            }
+            RTCCR => (), // ignore attempts to turn off the timer.
+            o => {
+                return Err(Error::BadWriteOffset(o));
+            }
+        }
+        Ok(())
+    }
+}
+
+impl BusDevice for RTC {
+    fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
+        let v;
+        let mut read_ok = true;
+
+        if offset < AMBA_ID_HIGH && offset >= AMBA_ID_LOW {
+            let index = ((offset - AMBA_ID_LOW) >> 2) as usize;
+            v = u32::from(PL031_ID[index]);
+        } else {
+            v = match offset {
+                RTCDR => self.get_time(),
+                RTCMR => {
+                    // Even though we are not implementing RTC alarm we return the last value
+                    self.match_value
+                }
+                RTCLR => self.load,
+                RTCCR => 1, // RTC is always enabled.
+                RTCIMSC => self.imsc,
+                RTCRIS => self.ris,
+                RTCMIS => self.ris & self.imsc,
+                _ => {
+                    read_ok = false;
+                    0
+                }
+            };
+        }
+        if read_ok && data.len() <= 4 {
+            write_le_u32(data, v);
+        } else {
+            warn!(
+                "Invalid RTC PL031 read: offset {}, data length {}",
+                offset,
+                data.len()
+            );
+        }
+    }
+
+    fn write(&mut self, _base: u64, offset: u64, data: &[u8]) {
+        if data.len() <= 4 {
+            let v = read_le_u32(&data[..]);
+            if let Err(e) = self.handle_write(offset, v) {
+                warn!("Failed to write to RTC PL031 device: {}", e);
+            }
+        } else {
+            warn!(
+                "Invalid RTC PL031 write: offset {}, data length {}",
+                offset,
+                data.len()
+            );
+        }
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+    use std::sync::Arc;
+    use vm_device::interrupt::{InterruptIndex, InterruptSourceConfig};
+    use vmm_sys_util::eventfd::EventFd;
+
+    const LEGACY_RTC_MAPPED_IO_START: u64 = 0x0901_0000;
+
+    #[test]
+    fn test_get_time() {
+        for _ in 0..1000 {
+            assert!(get_time(ClockType::Monotonic) <= get_time(ClockType::Monotonic));
+        }
+
+        for _ in 0..1000 {
+            assert!(get_time(ClockType::ProcessCpu) <= get_time(ClockType::ProcessCpu));
+        }
+
+        for _ in 0..1000 {
+            assert!(get_time(ClockType::ThreadCpu) <= get_time(ClockType::ThreadCpu));
+        }
+
+        assert_ne!(get_time(ClockType::Real), 0);
+    }
+
+    #[test]
+    fn test_local_time_display() {
+        let local_time = LocalTime {
+            sec: 30,
+            min: 15,
+            hour: 10,
+            mday: 4,
+            mon: 6,
+            year: 119,
+            nsec: 123_456_789,
+        };
+        assert_eq!(
+            String::from("2019-07-04T10:15:30.123456789"),
+            local_time.to_string()
+        );
+
+        let local_time = LocalTime {
+            sec: 5,
+            min: 5,
+            hour: 5,
+            mday: 23,
+            mon: 7,
+            year: 44,
+            nsec: 123,
+        };
+        assert_eq!(
+            String::from("1944-08-23T05:05:05.000000123"),
+            local_time.to_string()
+        );
+
+        let local_time = LocalTime::now();
+        assert!(local_time.mon >= 0 && local_time.mon <= 11);
+    }
+
+    #[test]
+    fn test_seconds_to_nanoseconds() {
+        assert_eq!(
+            seconds_to_nanoseconds(100).unwrap() as u64,
+            100 * NANOS_PER_SECOND
+        );
+
+        assert!(seconds_to_nanoseconds(9_223_372_037).is_none());
+    }
+
+    struct TestInterrupt {
+        event_fd: EventFd,
+    }
+
+    impl InterruptSourceGroup for TestInterrupt {
+        fn trigger(&self, _index: InterruptIndex) -> result::Result<(), std::io::Error> {
+            self.event_fd.write(1)
+        }
+
+        fn update(
+            &self,
+            _index: InterruptIndex,
+            _config: InterruptSourceConfig,
+        ) -> result::Result<(), std::io::Error> {
+            Ok(())
+        }
+
+        fn notifier(&self, _index: InterruptIndex) -> Option<&EventFd> {
+            Some(&self.event_fd)
+        }
+    }
+
+    impl TestInterrupt {
+        fn new(event_fd: EventFd) -> Self {
+            TestInterrupt { event_fd }
+        }
+    }
+
+    #[test]
+    fn test_rtc_read_write_and_event() {
+        let intr_evt = EventFd::new(libc::EFD_NONBLOCK).unwrap();
+
+        let mut rtc = RTC::new(Arc::new(Box::new(TestInterrupt::new(
+            intr_evt.try_clone().unwrap(),
+        ))));
+        let mut data = [0; 4];
+
+        // Read and write to the MR register.
+        write_le_u32(&mut data, 123);
+        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCMR, &mut data);
+        rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCMR, &mut data);
+        let v = read_le_u32(&data[..]);
+        assert_eq!(v, 123);
+
+        // Read and write to the LR register.
+        let v = get_time(ClockType::Real);
+        write_le_u32(&mut data, (v / NANOS_PER_SECOND) as u32);
+        let previous_now_before = rtc.previous_now;
+        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCLR, &mut data);
+
+        assert!(rtc.previous_now > previous_now_before);
+
+        rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCLR, &mut data);
+        let v_read = read_le_u32(&data[..]);
+        assert_eq!((v / NANOS_PER_SECOND) as u32, v_read);
+
+        // Read and write to IMSC register.
+        // Test with non zero value.
+        let non_zero = 1;
+        write_le_u32(&mut data, non_zero);
+        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &mut data);
+        // The interrupt line should be on.
+        assert!(rtc.interrupt.notifier(0).unwrap().read().unwrap() == 1);
+        rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &mut data);
+        let v = read_le_u32(&data[..]);
+        assert_eq!(non_zero & 1, v);
+
+        // Now test with 0.
+        write_le_u32(&mut data, 0);
+        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &mut data);
+        rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &mut data);
+        let v = read_le_u32(&data[..]);
+        assert_eq!(0, v);
+
+        // Read and write to the ICR register.
+        write_le_u32(&mut data, 1);
+        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCICR, &mut data);
+        // The interrupt line should be on.
+        assert!(rtc.interrupt.notifier(0).unwrap().read().unwrap() > 1);
+        let v_before = read_le_u32(&data[..]);
+
+        rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCICR, &mut data);
+        let v = read_le_u32(&data[..]);
+        // ICR is a  write only register. Data received should stay equal to data sent.
+        assert_eq!(v, v_before);
+
+        // Attempts to turn off the RTC should not go through.
+        write_le_u32(&mut data, 0);
+        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCCR, &mut data);
+        rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCCR, &mut data);
+        let v = read_le_u32(&data[..]);
+        assert_eq!(v, 1);
+
+        // Attempts to write beyond the writable space. Using here the space used to read
+        // the CID and PID from.
+        write_le_u32(&mut data, 0);
+        rtc.write(LEGACY_RTC_MAPPED_IO_START, AMBA_ID_LOW, &mut data);
+        // However, reading from the AMBA_ID_LOW should succeed upon read.
+
+        let mut data = [0; 4];
+        rtc.read(LEGACY_RTC_MAPPED_IO_START, AMBA_ID_LOW, &mut data);
+        let index = AMBA_ID_LOW + 3;
+        assert_eq!(data[0], PL031_ID[((index - AMBA_ID_LOW) >> 2) as usize]);
+    }
+
+    macro_rules! byte_order_test_read_write {
+        ($test_name: ident, $write_fn_name: ident, $read_fn_name: ident, $is_be: expr, $data_type: ty) => {
+            #[test]
+            fn $test_name() {
+                #[allow(overflowing_literals)]
+                let test_cases = [
+                    (
+                        0x0123_4567_89AB_CDEF as u64,
+                        [0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef],
+                    ),
+                    (
+                        0x0000_0000_0000_0000 as u64,
+                        [0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00],
+                    ),
+                    (
+                        0x1923_2345_ABF3_CCD4 as u64,
+                        [0x19, 0x23, 0x23, 0x45, 0xAB, 0xF3, 0xCC, 0xD4],
+                    ),
+                    (
+                        0x0FF0_0FF0_0FF0_0FF0 as u64,
+                        [0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0],
+                    ),
+                    (
+                        0xFFFF_FFFF_FFFF_FFFF as u64,
+                        [0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF],
+                    ),
+                    (
+                        0x89AB_12D4_C2D2_09BB as u64,
+                        [0x89, 0xAB, 0x12, 0xD4, 0xC2, 0xD2, 0x09, 0xBB],
+                    ),
+                ];
+
+                let type_size = std::mem::size_of::<$data_type>();
+                for (test_val, v_arr) in &test_cases {
+                    let v = *test_val as $data_type;
+                    let cmp_iter: Box<dyn Iterator<Item = _>> = if $is_be {
+                        Box::new(v_arr[(8 - type_size)..].iter())
+                    } else {
+                        Box::new(v_arr.iter().rev())
+                    };
+                    // test write
+                    let mut write_arr = vec![Default::default(); type_size];
+                    $write_fn_name(&mut write_arr, v);
+                    for (cmp, cur) in cmp_iter.zip(write_arr.iter()) {
+                        assert_eq!(*cmp, *cur as u8)
+                    }
+                    // test read
+                    let read_val = $read_fn_name(&write_arr);
+                    assert_eq!(v, read_val);
+                }
+            }
+        };
+    }
+
+    byte_order_test_read_write!(test_le_u16, write_le_u16, read_le_u16, false, u16);
+    byte_order_test_read_write!(test_le_u32, write_le_u32, read_le_u32, false, u32);
+    byte_order_test_read_write!(test_le_u64, write_le_u64, read_le_u64, false, u64);
+    byte_order_test_read_write!(test_le_i32, write_le_i32, read_le_i32, false, i32);
+    byte_order_test_read_write!(test_be_u16, write_be_u16, read_be_u16, true, u16);
+    byte_order_test_read_write!(test_be_u32, write_be_u32, read_be_u32, true, u32);
+}

devices/src/legacy/serial.rs

@@ -5,9 +5,16 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE-BSD-3-Clause file.
 
-use crate::{BusDevice, Interrupt};
+use crate::BusDevice;
+use anyhow::anyhow;
 use std::collections::VecDeque;
+use std::sync::Arc;
 use std::{io, result};
+use vm_device::interrupt::InterruptSourceGroup;
+use vm_migration::{
+    Migratable, MigratableError, Pausable, Snapshot, SnapshotDataSection, Snapshottable,
+    Transportable,
+};
 use vmm_sys_util::errno::Result;
 
 const LOOP_SIZE: usize = 0x40;
@@ -53,9 +60,10 @@ const DEFAULT_BAUD_DIVISOR: u16 = 12; // 9600 bps
 /// This can optionally write the guest's output to a Write trait object. To send input to the
 /// guest, use `queue_input_bytes`.
 pub struct Serial {
+    id: String,
     interrupt_enable: u8,
     interrupt_identification: u8,
-    interrupt: Box<dyn Interrupt>,
+    interrupt: Arc<Box<dyn InterruptSourceGroup>>,
     line_control: u8,
     line_status: u8,
     modem_control: u8,
@@ -66,9 +74,27 @@ pub struct Serial {
     out: Option<Box<dyn io::Write + Send>>,
 }
 
+#[derive(Serialize, Deserialize)]
+pub struct SerialState {
+    interrupt_enable: u8,
+    interrupt_identification: u8,
+    line_control: u8,
+    line_status: u8,
+    modem_control: u8,
+    modem_status: u8,
+    scratch: u8,
+    baud_divisor: u16,
+    in_buffer: VecDeque<u8>,
+}
+
 impl Serial {
-    pub fn new(interrupt: Box<dyn Interrupt>, out: Option<Box<dyn io::Write + Send>>) -> Serial {
+    pub fn new(
+        id: String,
+        interrupt: Arc<Box<dyn InterruptSourceGroup>>,
+        out: Option<Box<dyn io::Write + Send>>,
+    ) -> Serial {
         Serial {
+            id,
             interrupt_enable: 0,
             interrupt_identification: DEFAULT_INTERRUPT_IDENTIFICATION,
             interrupt,
@@ -84,13 +110,17 @@ impl Serial {
     }
 
     /// Constructs a Serial port ready for output.
-    pub fn new_out(interrupt: Box<dyn Interrupt>, out: Box<dyn io::Write + Send>) -> Serial {
-        Self::new(interrupt, Some(out))
+    pub fn new_out(
+        id: String,
+        interrupt: Arc<Box<dyn InterruptSourceGroup>>,
+        out: Box<dyn io::Write + Send>,
+    ) -> Serial {
+        Self::new(id, interrupt, Some(out))
     }
 
     /// Constructs a Serial port with no connected output.
-    pub fn new_sink(interrupt: Box<dyn Interrupt>) -> Serial {
-        Self::new(interrupt, None)
+    pub fn new_sink(id: String, interrupt: Arc<Box<dyn InterruptSourceGroup>>) -> Serial {
+        Self::new(id, interrupt, None)
     }
 
     /// Queues raw bytes for the guest to read and signals the interrupt if the line status would
@@ -149,7 +179,7 @@ impl Serial {
     }
 
     fn trigger_interrupt(&mut self) -> result::Result<(), io::Error> {
-        self.interrupt.deliver()
+        self.interrupt.trigger(0)
     }
 
     fn iir_reset(&mut self) {
@@ -186,6 +216,32 @@ impl Serial {
         }
         Ok(())
     }
+
+    fn state(&self) -> SerialState {
+        SerialState {
+            interrupt_enable: self.interrupt_enable,
+            interrupt_identification: self.interrupt_identification,
+            line_control: self.line_control,
+            line_status: self.line_status,
+            modem_control: self.modem_control,
+            modem_status: self.modem_status,
+            scratch: self.scratch,
+            baud_divisor: self.baud_divisor,
+            in_buffer: self.in_buffer.clone(),
+        }
+    }
+
+    fn set_state(&mut self, state: &SerialState) {
+        self.interrupt_enable = state.interrupt_enable;
+        self.interrupt_identification = state.interrupt_identification;
+        self.line_control = state.line_control;
+        self.line_status = state.line_status;
+        self.modem_control = state.modem_control;
+        self.modem_status = state.modem_status;
+        self.scratch = state.scratch;
+        self.baud_divisor = state.baud_divisor;
+        self.in_buffer = state.in_buffer.clone();
+    }
 }
 
 impl BusDevice for Serial {
@@ -228,21 +284,76 @@ impl BusDevice for Serial {
     }
 }
 
+impl Snapshottable for Serial {
+    fn id(&self) -> String {
+        self.id.clone()
+    }
+
+    fn snapshot(&self) -> std::result::Result<Snapshot, MigratableError> {
+        let snapshot =
+            serde_json::to_vec(&self.state()).map_err(|e| MigratableError::Snapshot(e.into()))?;
+
+        let mut serial_snapshot = Snapshot::new(self.id.as_str());
+        serial_snapshot.add_data_section(SnapshotDataSection {
+            id: format!("{}-section", self.id),
+            snapshot,
+        });
+
+        Ok(serial_snapshot)
+    }
+
+    fn restore(&mut self, snapshot: Snapshot) -> std::result::Result<(), MigratableError> {
+        if let Some(serial_section) = snapshot.snapshot_data.get(&format!("{}-section", self.id)) {
+            let serial_state = match serde_json::from_slice(&serial_section.snapshot) {
+                Ok(state) => state,
+                Err(error) => {
+                    return Err(MigratableError::Restore(anyhow!(
+                        "Could not deserialize SERIAL {}",
+                        error
+                    )))
+                }
+            };
+
+            self.set_state(&serial_state);
+
+            return Ok(());
+        }
+
+        Err(MigratableError::Restore(anyhow!(
+            "Could not find the serial snapshot section"
+        )))
+    }
+}
+
+impl Pausable for Serial {}
+impl Transportable for Serial {}
+impl Migratable for Serial {}
+
 #[cfg(test)]
 mod tests {
     use super::*;
     use std::io;
     use std::sync::{Arc, Mutex};
+    use vm_device::interrupt::{InterruptIndex, InterruptSourceConfig};
     use vmm_sys_util::eventfd::EventFd;
 
+    const SERIAL_NAME: &str = "serial";
+
     struct TestInterrupt {
         event_fd: EventFd,
     }
 
-    impl Interrupt for TestInterrupt {
-        fn deliver(&self) -> result::Result<(), std::io::Error> {
+    impl InterruptSourceGroup for TestInterrupt {
+        fn trigger(&self, _index: InterruptIndex) -> result::Result<(), std::io::Error> {
             self.event_fd.write(1)
         }
+        fn update(
+            &self,
+            _index: InterruptIndex,
+            _config: InterruptSourceConfig,
+        ) -> result::Result<(), std::io::Error> {
+            Ok(())
+        }
     }
 
     impl TestInterrupt {
@@ -278,7 +389,8 @@ mod tests {
         let intr_evt = EventFd::new(0).unwrap();
         let serial_out = SharedBuffer::new();
         let mut serial = Serial::new_out(
-            Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap())),
+            String::from(SERIAL_NAME),
+            Arc::new(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap()))),
             Box::new(serial_out.clone()),
         );
 
@@ -297,7 +409,8 @@ mod tests {
         let intr_evt = EventFd::new(0).unwrap();
         let serial_out = SharedBuffer::new();
         let mut serial = Serial::new_out(
-            Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap())),
+            String::from(SERIAL_NAME),
+            Arc::new(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap()))),
             Box::new(serial_out.clone()),
         );
 
@@ -334,8 +447,10 @@ mod tests {
     #[test]
     fn serial_thr() {
         let intr_evt = EventFd::new(0).unwrap();
-        let mut serial =
-            Serial::new_sink(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap())));
+        let mut serial = Serial::new_sink(
+            String::from(SERIAL_NAME),
+            Arc::new(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap()))),
+        );
 
         // write 1 to the interrupt event fd, so that read doesn't block in case the event fd
         // counter doesn't change (for 0 it blocks)
@@ -354,8 +469,10 @@ mod tests {
     #[test]
     fn serial_dlab() {
         let intr_evt = EventFd::new(0).unwrap();
-        let mut serial =
-            Serial::new_sink(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap())));
+        let mut serial = Serial::new_sink(
+            String::from(SERIAL_NAME),
+            Arc::new(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap()))),
+        );
 
         serial.write(0, LCR as u64, &[LCR_DLAB_BIT as u8]);
         serial.write(0, DLAB_LOW as u64, &[0x12 as u8]);
@@ -373,8 +490,10 @@ mod tests {
     #[test]
     fn serial_modem() {
         let intr_evt = EventFd::new(0).unwrap();
-        let mut serial =
-            Serial::new_sink(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap())));
+        let mut serial = Serial::new_sink(
+            String::from(SERIAL_NAME),
+            Arc::new(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap()))),
+        );
 
         serial.write(0, MCR as u64, &[MCR_LOOP_BIT as u8]);
         serial.write(0, DATA as u64, &['a' as u8]);
@@ -397,8 +516,10 @@ mod tests {
     #[test]
     fn serial_scratch() {
         let intr_evt = EventFd::new(0).unwrap();
-        let mut serial =
-            Serial::new_sink(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap())));
+        let mut serial = Serial::new_sink(
+            String::from(SERIAL_NAME),
+            Arc::new(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap()))),
+        );
 
         serial.write(0, SCR as u64, &[0x12 as u8]);
 

devices/src/lib.rs

@@ -6,27 +6,40 @@
 // found in the LICENSE-BSD-3-Clause file.
 
 //! Emulates virtual and hardware devices.
+extern crate anyhow;
+#[macro_use]
+extern crate bitflags;
 extern crate byteorder;
 extern crate epoll;
-extern crate kvm_bindings;
-extern crate kvm_ioctls;
 extern crate libc;
 #[macro_use]
 extern crate log;
+#[cfg(feature = "acpi")]
+extern crate acpi_tables;
+extern crate serde;
+extern crate vm_device;
 extern crate vm_memory;
+extern crate vm_migration;
 extern crate vmm_sys_util;
+#[macro_use]
+extern crate serde_derive;
+extern crate serde_json;
 
 use std::fs::File;
-use std::{io, result};
+use std::io;
 
 #[cfg(feature = "acpi")]
 mod acpi;
 mod bus;
+#[cfg(target_arch = "aarch64")]
+pub mod gic;
+pub mod interrupt_controller;
+#[cfg(target_arch = "x86_64")]
 pub mod ioapic;
 pub mod legacy;
 
 #[cfg(feature = "acpi")]
-pub use self::acpi::{AcpiGEDDevice, AcpiShutdownDevice};
+pub use self::acpi::{AcpiGEDDevice, AcpiPMTimerDevice, AcpiShutdownDevice};
 pub use self::bus::{Bus, BusDevice, Error as BusError};
 
 pub type DeviceEventT = u16;
@@ -67,12 +80,11 @@ pub enum Error {
     IoError(io::Error),
 }
 
-pub trait Interrupt: Send + Sync {
-    fn deliver(&self) -> result::Result<(), std::io::Error>;
-}
-
-#[derive(Clone, Copy)]
-pub enum HotPlugNotificationType {
-    NoDevicesChanged,
-    CPUDevicesChanged,
+bitflags! {
+    pub struct HotPlugNotificationFlags: u8 {
+        const NO_DEVICES_CHANGED = 0;
+        const CPU_DEVICES_CHANGED = 0b1;
+        const MEMORY_DEVICES_CHANGED = 0b10;
+        const PCI_DEVICES_CHANGED = 0b100;
+    }
 }

docs/api.md

@@ -0,0 +1,378 @@
+- [Cloud Hypervisor API](#cloud-hypervisor-api)
+  * [External API](#external-api)
+    + [REST API](#rest-api)
+      - [Location and availability](#location-and-availability)
+      - [Endpoints](#endpoints)
+		* [Virtual Machine Manager (VMM) Actions](#virtual-machine-manager-vmm-actions)
+		* [Virtual Machine (VM) Actions](#virtual-machine-vm-actions)
+      - [REST API Examples](#rest-api-examples)
+        * [Create a Virtual Machine](#create-a-virtual-machine)
+	    * [Boot a Virtual Machine](#boot-a-virtual-machine)
+        * [Dump a Virtual Machine Information](#dump-a-virtual-machine-information)
+        * [Reboot a Virtual Machine](#reboot-a-virtual-machine)
+        * [Shut a Virtual Machine Down](#shut-a-virtual-machine-down)
+    + [Command Line Interface](#command-line-interface)
+    + [REST API and CLI Architecural Relationship](#rest-api-and-cli-architectural-relationship)
+  * [Internal API](#internal-api)
+    + [Goals and Design](#goals-and-design)
+  * [End to End Example](#end-to-end-example)
+
+# Cloud Hypervisor API
+
+The Cloud Hypervisor API is made of 2 distinct interfaces:
+
+1. **The external API**. This is the user facing API. Users and operators can
+   control and manage Cloud Hypervisor through either a REST API or a Command
+   Line Interface (CLI).
+1. **The internal API**, based on [rust's Multi-Producer, Single-Consumer (MPSC)](https://doc.rust-lang.org/std/sync/mpsc/)
+   module. This API is used internally by the Cloud Hypervisor threads to
+   communicate between each others.
+
+The goal of this document is to describe the Cloud Hypervisor API as a whole,
+and to outline how the internal and external APIs are architecturally related.
+
+## External API
+
+### REST API
+
+The Cloud Hypervisor [REST](https://en.wikipedia.org/wiki/Representational_state_transfer)
+API triggers VM and VMM specific actions, and as such it is designed as a
+collection of RPC-style, static methods.
+
+The API is [OpenAPI 3.0](https://github.com/OAI/OpenAPI-Specification/blob/master/versions/3.0.0.md)
+compliant. Please consult the [Cloud Hypervisor API](https://raw.githubusercontent.com/cloud-hypervisor/cloud-hypervisor/master/vmm/src/api/openapi/cloud-hypervisor.yaml)
+document for more details about the API payloads and responses.
+
+### Location and availability
+
+The REST API is available as soon as the Cloud Hypervisor binary is started,
+through a local UNIX socket.
+By default, it is located at `/run/user/{user ID}/cloud-hypervisor.{Cloud Hypervisor PID}`.
+For example, if you launched Cloud Hypervisor as user ID 1000 and its PID is
+123456, the Cloud Hypervisor REST API will be available at `/run/user/1000/cloud-hypervisor.123456`.
+
+The REST API default URL can be overridden through the Cloud Hypervisor
+option `--api-socket`:
+
+```
+$ ./target/debug/cloud-hypervisor --api-socket /tmp/cloud-hypervisor.sock
+Cloud Hypervisor Guest
+    API server: /tmp/cloud-hypervisor.sock
+    vCPUs: 1
+    Memory: 512 MB
+    Kernel: None
+    Kernel cmdline:
+    Disk(s): None
+```
+
+### Endpoints
+
+The Cloud Hypervisor API exposes the following actions through its endpoints:
+
+#### Virtual Machine Manager (VMM) Actions
+
+Action                              | Endpoint        | Request Body | Response Body              | Prerequisites
+------------------------------------|-----------------|--------------|----------------------------|---------------------------
+Check for the REST API availability | `/vmm.ping`     | N/A          | `/schemas/VmmPingResponse` | N/A
+Shut the VMM down                   | `/vmm.shutdown` | N/A          | N/A                        | The VMM is running
+
+#### Virtual Machine (VM) Actions
+
+Action                             | Endpoint            | Request Body              | Response Body            | Prerequisites
+-----------------------------------|---------------------|---------------------------|--------------------------|---------------------------
+Create the VM                      | `/vm.create`        | `/schemas/VmConfig`       | N/A                      | The VM is not created yet
+Delete the VM                      | `/vm.delete`        | N/A                       | N/A                      | N/A
+Boot the VM                        | `/vm.boot`          | N/A                       | N/A                      | The VM is created but not booted
+Shut the VM down                   | `/vm.shutdown`      | N/A                       | N/A                      | The VM is booted
+Reboot the VM                      | `/vm.reboot`        | N/A                       | N/A                      | The VM is booted
+Pause the VM                       | `/vm.pause`         | N/A                       | N/A                      | The VM is booted
+Resume the VM                      | `/vm.resume`        | N/A                       | N/A                      | The VM is paused
+Add/remove CPUs to/from the VM     | `/vm.resize`        | `/schemas/VmResize`       | N/A                      | The VM is booted
+Remove memory from the VM          | `/vm.resize`        | `/schemas/VmResize`       | N/A                      | The VM is booted
+Dump the VM information            | `/vm.info`          | N/A                       | `/schemas/VmInfo`        | The VM is created
+Add VFIO PCI device to the VM      | `/vm.add-device`    | `/schemas/VmAddDevice`    | `/schemas/PciDeviceInfo` | The VM is booted
+Add disk device to the VM          | `/vm.add-disk`      | `/schemas/DiskConfig`     | `/schemas/PciDeviceInfo` | The VM is booted
+Add fs device to the VM            | `/vm.add-fs`        | `/schemas/FsConfig`       | `/schemas/PciDeviceInfo` | The VM is booted
+Add pmem device to the VM          | `/vm.add-pmem`      | `/schemas/PmemConfig`     | `/schemas/PciDeviceInfo` | The VM is booted
+Add network device to the VM       | `/vm.add-net`       | `/schemas/NetConfig`      | `/schemas/PciDeviceInfo` | The VM is booted
+Add vsock device to the VM         | `/vm.add-vsock`     | `/schemas/VsockConfig`    | `/schemas/PciDeviceInfo` | The VM is booted
+Remove device from the VM          | `/vm.remove-device` | `/schemas/VmRemoveDevice` | N/A                      | The VM is booted
+Dump the VM counters               | `/vm.counters`      | N/A                       | `/schemas/VmCounters`    | The VM is booted
+
+### REST API Examples
+
+For the following set of examples, we assume Cloud Hypervisor is started with
+the REST API available at `/tmp/cloud-hypervisor.sock`:
+
+```
+$ ./target/debug/cloud-hypervisor --api-socket /tmp/cloud-hypervisor.sock
+Cloud Hypervisor Guest
+    API server: /tmp/cloud-hypervisor.sock
+    vCPUs: 1
+    Memory: 512 MB
+    Kernel: None
+    Kernel cmdline:
+    Disk(s): None
+```
+
+#### Create a Virtual Machine
+
+We want to create a virtual machine with the following characteristics:
+
+* 4 vCPUs
+* 1 GB of RAM
+* 1 virtio based networking interface
+* Direct kernel boot from a custom 5.6.0-rc4 Linux kernel located at
+  `/opt/clh/kernel/vmlinux-virtio-fs-virtio-iommu`
+* Using a Ubuntu image as its root filesystem, located at
+  `/opt/clh/images/focal-server-cloudimg-amd64.raw`
+
+```shell
+#!/bin/bash
+
+curl --unix-socket /tmp/cloud-hypervisor.sock -i \
+     -X PUT 'http://localhost/api/v1/vm.create'  \
+     -H 'Accept: application/json'               \
+     -H 'Content-Type: application/json'         \
+     -d '{
+         "cpus":{"boot_vcpus": 4, "max_vcpus": 4},
+         "kernel":{"path":"/opt/clh/kernel/vmlinux-virtio-fs-virtio-iommu"},
+         "cmdline":{"args":"console=ttyS0 console=hvc0 root=/dev/vda1 rw"},
+         "disks":[{"path":"/opt/clh/images/focal-server-cloudimg-amd64.raw"}],
+         "rng":{"src":"/dev/urandom"},
+         "net":[{"ip":"192.168.10.10", "mask":"255.255.255.0", "mac":"12:34:56:78:90:01"}]
+         }'
+```
+
+#### Boot a Virtual Machine
+
+Once the VM is created, we can boot it:
+
+```shell
+#!/bin/bash
+
+curl --unix-socket /tmp/cloud-hypervisor.sock -i -X PUT 'http://localhost/api/v1/vm.boot'
+```
+
+#### Dump a Virtual Machine Information
+
+We can fetch information about any VM, as soon as it's created:
+
+```shell
+#!/bin/bash
+
+curl --unix-socket /tmp/cloud-hypervisor.sock -i \
+     -X GET 'http://localhost/api/v1/vm.info' \
+     -H 'Accept: application/json'
+```
+
+#### Reboot a Virtual Machine
+
+We can reboot a VM that's already booted:
+
+```shell
+#!/bin/bash
+
+curl --unix-socket /tmp/cloud-hypervisor.sock -i -X PUT 'http://localhost/api/v1/vm.reboot'
+```
+
+#### Shut a Virtual Machine Down
+
+Once booted, we can shut a VM down from the REST API:
+
+```shell
+#!/bin/bash
+
+curl --unix-socket /tmp/cloud-hypervisor.sock -i -X PUT 'http://localhost/api/v1/vm.shutdown'
+```
+
+### Command Line Interface
+
+The Cloud Hypervisor Command Line Interface (CLI) can only be used for launching
+the Cloud Hypervisor binary, i.e. it can not be used for controlling the VMM or
+the launched VM once they're up and running.
+
+If you want to inspect the VMM, or control the VM after launching Cloud
+Hypervisor from the CLI, you must use the [REST API](#rest-api).
+
+From the CLI, one can either:
+
+1. Create and boot a complete virtual machine by using the CLI options to build
+   the VM config. Run `cloud-hypervisor --help` for a complete list of CLI
+   options. As soon as the `cloud-hypervisor` binary is launched, the
+   [REST API](#rest-api) is available for controlling and managing the VM.
+1. Start the [REST API](#rest-api) server only, by not passing any VM
+   configuration options. The VM can then be asynchronously created and booted
+   by sending HTTP commands to the [REST API](#rest-api). Check the
+   [REST API examples](#rest-api-examples) section for more details.
+
+### REST API and CLI Architectural Relationship
+
+The REST API and the CLI both rely on a common, [internal API](#internal-api).
+
+The CLI options are parsed by the
+[clap crate](https://docs.rs/clap/2.33.0/clap/) and then translated into
+[internal API](#internal-api) commands.
+
+The REST API is processed by an HTTP thread using the
+[Firecracker's `micro_http`](https://github.com/firecracker-microvm/firecracker/tree/master/src/micro_http)
+crate. As with the CLI, the HTTP requests eventually get translated into
+[internal API](#internal-api) commands.
+
+As a summary, the REST API and the CLI are essentially frontends for the
+[internal API](#internal-api):
+
+```
+                                  +------------------+
+                        REST API  |                  |
+                       +--------->+    micro_http    +--------+
+                       |          |                  |        |
+                       |          +------------------+        |
+                       |                                      |      +------------------------+
+                       |                                      |      |                        |
++------------+         |                                      |      |                        |
+|            |         |                                      |      | +--------------+       |
+|    User    +---------+                                      +------> | Internal API |       |
+|            |         |                                      |      | +--------------+       |
++------------+         |                                      |      |                        |
+                       |                                      |      |                        |
+                       |                                      |      +------------------------+
+                       |            +----------+              |                 VMM
+                       |     CLI    |          |              |
+                       +----------->+   clap   +--------------+
+                                    |          |
+                                    +----------+
+
+
+```
+
+## Internal API
+
+The Cloud Hypervisor internal API, as its name suggests, is used internally
+by the different Cloud Hypervisor threads (VMM, HTTP, control loop, etc) to
+send commands and responses to each others.
+
+It is based on [rust's Multi-Producer, Single-Consumer (MPSC)](https://doc.rust-lang.org/std/sync/mpsc/),
+and the single consumer (a.k.a. the API receiver) is the Cloud Hypervisor
+control loop.
+
+API producers are the HTTP thread handling the [REST API](#rest-api) and the
+main thread that initially parses the [CLI](#command-line-interface).
+
+### Goals and Design
+
+The internal API is designed for controlling, managing and inspecting a Cloud
+Hypervisor VMM and its guest. It is a backend for handling external, user
+visible requests through either the [REST API](#rest-api) or the
+[CLI](#command-line-interface) interfaces.
+
+The API follows a command-response scheme that closely maps the [REST API](#rest-api).
+Any command must be replied to with a response.
+
+Commands are [MPSC](https://doc.rust-lang.org/std/sync/mpsc/) based messages and
+are received and processed by the VMM control loop.
+
+In order for the VMM control loop to respond to any internal API command, it
+must be able to send a response back to the MPSC sender. For that purpose, all
+internal API command payload carry the [Sender](https://doc.rust-lang.org/std/sync/mpsc/struct.Sender.html)
+end of an [MPSC](https://doc.rust-lang.org/std/sync/mpsc/) channel.
+
+The sender of any internal API command is therefore responsible for:
+
+1. Creating an [MPSC](https://doc.rust-lang.org/std/sync/mpsc/) response
+   channel.
+1. Passing the [Sender](https://doc.rust-lang.org/std/sync/mpsc/struct.Sender.html)
+   end of the response channel as part of the internal API command payload.
+1. Waiting for the internal API command's response on the [Receiver](https://doc.rust-lang.org/std/sync/mpsc/struct.Receiver.html)
+   end of the response channel.
+
+## End to End Example
+
+In order to further understand how the external and internal Cloud Hypervisor
+APIs work together, let's look at a complete VM creation flow, from the
+[REST API](#rest-api) call, to the reply the external user will receive:
+
+1. A user or operator sends an HTTP request to the Cloud Hypervisor
+   [REST API](#rest-api) in order to creates a virtual machine:
+   ```
+   shell
+   #!/bin/bash
+
+	curl --unix-socket /tmp/cloud-hypervisor.sock -i \
+		-X PUT 'http://localhost/api/v1/vm.create'  \
+		-H 'Accept: application/json'               \
+		-H 'Content-Type: application/json'         \
+		-d '{
+			"cpus":{"boot_vcpus": 4, "max_vcpus": 4},
+			"kernel":{"path":"/opt/clh/kernel/vmlinux-virtio-fs-virtio-iommu"},
+			"cmdline":{"args":"console=ttyS0 console=hvc0 root=/dev/vda1 rw"},
+			"disks":[{"path":"/opt/clh/images/focal-server-cloudimg-amd64.raw"}],
+			"rng":{"src":"/dev/urandom"},
+			"net":[{"ip":"192.168.10.10", "mask":"255.255.255.0", "mac":"12:34:56:78:90:01"}]
+			}'
+   ```
+1. The Cloud Hypervisor HTTP thread processes the request and de-serializes the
+   HTTP request JSON body into an internal `VmConfig` structure.
+1. The Cloud Hypervisor HTTP thread creates an
+   [MPSC](https://doc.rust-lang.org/std/sync/mpsc/) channel for the internal API
+   server to send its response back.
+1. The Cloud Hypervisor HTTP thread prepares an internal API command for creating a
+   virtual machine. The command's payload is made of the de-serialized
+   `VmConfig` structure and the response channel:
+   ```Rust
+   VmCreate(Arc<Mutex<VmConfig>>, Sender<ApiResponse>)
+   ```
+1. The Cloud Hypervisor HTTP thread sends the internal API command, and waits
+   for the response:
+   ```Rust
+   // Send the VM creation request.
+    api_sender
+        .send(ApiRequest::VmCreate(config, response_sender))
+        .map_err(ApiError::RequestSend)?;
+    api_evt.write(1).map_err(ApiError::EventFdWrite)?;
+
+    response_receiver.recv().map_err(ApiError::ResponseRecv)??;
+   ```
+1. The Cloud Hypervisor control loop receives the command, as it listens on the
+   internal API [MPSC](https://doc.rust-lang.org/std/sync/mpsc/) channel:
+   ```Rust
+   // Read from the API receiver channel
+   let api_request = api_receiver.recv().map_err(Error::ApiRequestRecv)?;
+   ```
+1. The Cloud Hypervisor control loop matches the received internal API against
+   the `VmCreate` payload, and extracts both the `VmConfig` structure and the
+   [Sender](https://doc.rust-lang.org/std/sync/mpsc/struct.Sender.html) from the
+   command payload. It stores the `VmConfig` structure and replies back to the
+   sender ((The HTTP thread):
+   ```Rust
+   match api_request {
+	   ApiRequest::VmCreate(config, sender) => {
+		   // We only store the passed VM config.
+		   // The VM will be created when being asked to boot it.
+		   let response = if self.vm_config.is_none() {
+			   self.vm_config = Some(config);
+			   Ok(ApiResponsePayload::Empty)
+		   } else {
+			   Err(ApiError::VmAlreadyCreated)
+		   };
+
+	       sender.send(response).map_err(Error::ApiResponseSend)?;
+	   }
+   ```
+1. The Cloud Hypervisor HTTP thread receives the internal API command response
+   as the return value from its `VmCreate` HTTP handler. Depending on the
+   control loop internal API response, it generates the appropriate HTTP
+   response:
+   ```Rust
+   // Call vm_create()
+   match vm_create(api_notifier, api_sender, Arc::new(Mutex::new(vm_config)))
+	   .map_err(HttpError::VmCreate)
+   {
+	   Ok(_) => Response::new(Version::Http11, StatusCode::NoContent),
+	   Err(e) => error_response(e, StatusCode::InternalServerError),
+   }
+   ```
+1. The Cloud Hypervisor HTTP thread sends the formed HTTP response back to the
+   user. This is abstracted by the
+   [micro_http](https://github.com/firecracker-microvm/firecracker/tree/master/src/micro_http)
+   crate.

docs/arm64.md

@@ -0,0 +1,68 @@
+# How to build and run Cloud-hypervisor on AArch64
+
+Cloud-hypervisor is partially enabled on AArch64 architecture.
+Although all features are not ready yet, you can begin to test Cloud-hypervisor on a AArch64 host by following this guide.
+
+## Prerequisites
+
+On AArch64 machines, Cloud-hypervisor depends on an external library `libfdt-dev` for generating Flattened Device Tree (FDT).
+
+The long-term plan is to replace `libfdt-dev` with some pure-Rust component to get rid of such dependency.
+
+```bash
+sudo apt-get update
+sudo apt-get install libfdt-dev
+```
+
+## Build
+
+For Virtio devices, you can choose MMIO or PCI as transport option.
+
+### MMIO
+
+```bash
+cargo build --no-default-features --features mmio,kvm
+```
+
+### PCI
+
+Using PCI devices requires GICv3-ITS for MSI messaging. GICv3-ITS is very common in modern servers, but your machine happen to be old ones with GICv2(M) (like Raspberry Pi 4) or GICv3 without ITS, MMIO can still work.
+
+```bash
+cargo build --no-default-features --features pci,kvm
+```
+
+## Image
+
+Download kernel binary and rootfs image from AWS.
+
+```bash
+wget https://s3.amazonaws.com/spec.ccfc.min/img/aarch64/ubuntu_with_ssh/fsfiles/xenial.rootfs.ext4 -O rootfs.ext4
+wget https://s3.amazonaws.com/spec.ccfc.min/img/aarch64/ubuntu_with_ssh/kernel/vmlinux.bin -O kernel.bin
+```
+
+## Containerized build
+
+If you want to build and test Cloud Hypervisor without having to install all the required dependencies, you can also turn to the development script: dev_cli.sh.
+
+To build the development container:
+
+```bash
+./scripts/dev_cli.sh build-container
+```
+
+To build Cloud-hypervisor in the container: (The default option for Virtio transport is MMIO.)
+
+```bash
+./scripts/dev_cli.sh build
+```
+
+## Run
+
+Assuming you have built Cloud-hypervisor with the development container, a VM can be started with command:
+
+```bash
+sudo build/cargo_target/aarch64-unknown-linux-gnu/debug/cloud-hypervisor --kernel kernel.bin --disk path=rootfs.ext4 --cmdline "keep_bootcon console=hvc0 reboot=k panic=1 pci=off root=/dev/vda rw" --cpus boot=4 --memory size=512M --serial file=serial.log --log-file log.log -vvv
+```
+
+If the build was done out of the container, replace the binary path with `target/debug/cloud-hypervisor`.

docs/custom-image.md

@@ -1,96 +1,136 @@
-# How to create a custom Clear Linux image
+# How to create a custom Ubuntu image
 
-In the context of adding more utility to the cloudguest image being used
-for integration testing, this is a quick guide on how to achieve the creation
-of your own Clear Linux image using the official Clear Linux tooling.
-
-## Prepare the environment
-
-From the host, the goal is run a Clear Linux VM that will allow us to build
-the custom image we want.
-
-```bash
-# Get latest CL version:
-IMG_VERSION=$(curl https://download.clearlinux.org/latest)
-# Get latest clear-kvm image:
-wget -P $HOME/workloads/ https://download.clearlinux.org/current/clear-${IMG_VERSION}-kvm.img.xz
-# Extract the image
-unxz $HOME/workloads/clear-${IMG_VERSION}-kvm.img.xz
-# Make sure cloud-hypervisor binary has CAP_NET_ADMIN capability set
-sudo setcap cap_net_admin+ep cloud-hypervisor
-# Boot cloud-hypervisor VM with the downloaded image
-./cloud-hypervisor -v --kernel $HOME/workloads/vmlinux --disk path=clear-${IMG_VERSION}-kvm.img --cmdline "console=ttyS0 console=hvc0 reboot=k panic=1 nomodules root=/dev/vda3 rw" --cpus 1 --memory size=4G --net tap=,mac=
-# Setup connectivity
-# First make sure to enable IP forwarding (disabled on Linux by default)
-sudo bash -c "echo 1 > /proc/sys/net/ipv4/ip_forward"
-# Retrieve the interface name and the gateway IP
-IFACE=$(ip route | grep default | awk -F 'dev' '{print $2}' | awk -F ' ' '{print $1}')
-GW=$(ip route | grep vmtap0 | awk -F ' ' '{print $1}')
-# Create a new masquerade rule to tag the packets going out
-sudo iptables -t nat -A POSTROUTING -s ${GW} -o ${IFACE} -j MASQUERADE
-```
+In the context of adding more utilities to the Ubuntu cloud image being used
+for integration testing, this quick guide details how to achieve the proper
+modification of an official Ubuntu cloud image.
 
 ## Create the image
 
-From the guest, we can now create the image.
+Let's go through the steps on how to extend an official Ubuntu image. These
+steps can be applied to other distributions (with a few changes regarding
+package management).
+
+### Get latest Ubuntu cloud image
 
 ```bash
-# Setup connectivity
-sudo ip addr add 192.168.249.2/24 dev enp0s3
-sudo ip route add default via 192.168.249.1
-# Install necessary bundles
-sudo swupd bundle-add clr-installer
-sudo swupd bundle-add os-installer
-# Download and update cloudguest image configuration
-wget https://download.clearlinux.org/current/config/image/cloudguest.yaml
-sed -i '/size: \"864M\"/d' cloudguest.yaml
-sed -i 's/\"800M\"/\"2G\"/g' cloudguest.yaml
-sed -i 's/bootloader,/bootloader,\n    iperf,/g' cloudguest.yaml
-sed -i 's/systemd-networkd-autostart/sysadmin-basic,\n    systemd-networkd-autostart/g' cloudguest.yaml
-# Create the custom cloudguest image
-clr-installer -c cloudguest.yaml
-# Make the guest accessible through ssh
-sudo mkdir -p /etc/ssh
-sudo bash -c "echo 'PermitRootLogin yes' >> /etc/ssh/sshd_config"
+wget https://cloud-images.ubuntu.com/focal/current/focal-server-cloudimg-amd64.img
 ```
 
-### Retrieve the image
-
-Once the new image has been created and the guest is accessible through
-`ssh`, it is time to retrieve the image from the host.
+### Check the file format is QCOW2
 
 ```bash
-# Retrieve new image (this is a raw image)
-scp root@192.168.249.2:cloudguest.img .
-mv cloudguest.img clear-cloudguest-raw.img
-# Create the QCOW image from the RAW image
-qemu-img convert -p -f raw -O qcow2 clear-cloudguest-raw.img clear-cloudguest.img
-# Compress the QCOW image
-xz -k -T $(nproc) clear-cloudguest.img
+file focal-server-cloudimg-amd64.img
+focal-server-cloudimg-amd64.img: QEMU QCOW2 Image (v2), 2361393152 bytes
+```
+
+### Convert QCOW2 into RAW
+
+```bash
+qemu-img convert -p -f qcow2 -O raw focal-server-cloudimg-amd64.img focal-server-cloudimg-amd64.raw
+```
+
+### Identify the Linux partition
+
+The goal is to mount the image rootfs so that it can be modified as needed.
+That's why we need to identify where the Linux filesystem partition is located
+in the image.
+
+```bash
+sudo fdisk -l focal-server-cloudimg-amd64.raw
+Disk focal-server-cloudimg-amd64.raw: 2.2 GiB, 2361393152 bytes, 4612096 sectors
+Units: sectors of 1 * 512 = 512 bytes
+Sector size (logical/physical): 512 bytes / 512 bytes
+I/O size (minimum/optimal): 512 bytes / 512 bytes
+Disklabel type: gpt
+Disk identifier: A1171ABA-2BEA-4218-A467-1B2B607E5953
+
+Device                             Start     End Sectors  Size Type
+focal-server-cloudimg-amd64.raw1  227328 4612062 4384735  2.1G Linux filesystem
+focal-server-cloudimg-amd64.raw14   2048   10239    8192    4M BIOS boot
+focal-server-cloudimg-amd64.raw15  10240  227327  217088  106M EFI System
+
+Partition table entries are not in disk order.
+```
+
+### Mount the Linux partition
+
+```bash
+mkdir -p /mnt
+sudo mount -o loop,offset=$((227328 * 512)) focal-server-cloudimg-amd64.raw /mnt
+```
+
+### Change root directory
+
+Changing the root directory will allow us to install new packages to the rootfs
+contained by the cloud image.
+
+```bash
+sudo chroot /mnt
+mount -t proc proc /proc
+mount -t devpts devpts /dev/pts
+```
+
+### Install needed packages
+
+In the context Cloud-Hypervisor's integration tests, we need several utilities.
+Here is the way to install them for a Ubuntu image. This step is specific to
+Ubuntu distributions.
+
+```bash
+apt update
+apt install fio iperf iperf3 socat
+```
+
+### Remove snapd
+
+This prevents snapd from trying to mount squashfs filesystem when the kernel
+might not support it. This might be the case when the image is used with direct
+kernel boot. This step is specific to Ubuntu distributions.
+
+```bash
+apt remove --purge snapd
+```
+
+### Cleanup the image
+
+Leave no trace in the image before unmounting its content.
+
+```bash
+umount /dev/pts
+umount /proc
+history -c
+exit
+umount /mnt
+```
+
+### Rename the image
+
+Renaming is important to identify this is a modified image.
+
+```bash
+mv focal-server-cloudimg-amd64.raw focal-server-cloudimg-amd64-custom.raw
+```
+
+### Create QCOW2 from RAW
+
+Last step is to create the QCOW2 image back from the modified image.
+
+```bash
+qemu-img convert -p -f raw -O qcow2 focal-server-cloudimg-amd64-custom.raw focal-server-cloudimg-amd64-custom.qcow2
 ```
 
 ## Switch CI to use the new image
 
 ### Upload to Azure storage
 
-The next step is to update the image stored as part of the Azure storage
-account, replacing it with the newly created image. This will make this
-new image available from the integration tests.
-This is usually achieved through the web interface.
+The next step is to update both images (QCOW2 and RAW) stored as part of the
+Azure storage account, replacing them with the newly created ones. This will
+make these new images available from the integration tests. This is usually
+achieved through the web interface.
 
 ### Update integration tests
 
 Last step is about updating the integration tests to work with this new image.
-The key point is to identify the UUID of this new image so that it can be used
-directly from the tests.
-
-Proceed as follow to determine this UUID:
-
-```bash
-# Mount the image
-sudo mount -o loop,offset=$((2048 * 512)) clear-cloudguest-raw.img /mnt/
-# Identify UUID
-sudo cat /mnt/loader/entries/Clear-linux-kvm-*.conf | grep "root=PARTUUID="
-# Unmount the image
-sudo umount /mnt
-```
+The key point is to identify where the Linux filesystem partition is located,
+as we might need to update the direct kernel boot command line, replacing
+`/dev/vda1` with the appropriate partition number.

docs/debug-port.md

@@ -43,7 +43,7 @@ to easily grep for the tracing logs (e.g.
 ```
 ./target/debug/cloud-hypervisor \
     --kernel ~/rust-hypervisor-firmware/target/target/release/hypervisor-fw \
-    --disk path=~/hypervisor/images/clear-30080-kvm.img \
+    --disk path=~/hypervisor/images/focal-server-cloudimg-amd64.raw \
     --cpus 4 \
     --memory size=1024M \
     --rng \

docs/device_model.md

@@ -166,8 +166,8 @@ processes, we added support for vhost-user-blk backends. This enables
 `cloud-hypervisor` users to plug a `vhost-user` based block device (e.g. SPDK)
 into the VMM as their virtio block backend.
 
-This device is always built-in, and it is enabled based on the presence of the
-flag `--vhost-user-blk`.
+This device is always built-in, and it is enabled when `vhost_user=true` and
+`socket` are provided to the `--disk` parameter.
 
 ### vhost-user-fs
 
@@ -188,8 +188,8 @@ processes, we added support for [vhost-user-net](https://access.redhat.com/solut
 backends. This enables `cloud-hypervisor` users to plug a `vhost-user` based
 networking device (e.g. DPDK) into the VMM as their virtio network backend.
 
-This device is always built-in, and it is enabled based on the presence of the
-flag `--vhost-user-net`.
+This device is always built-in, and it is enabled when `vhost_user=true` and
+`socket` are provided to the `--net` parameter.
 
 ## VFIO
 

docs/fs.md

@@ -26,14 +26,14 @@ _Run virtiofsd_
 ```bash
 ./virtiofsd \
     -d \
-    -o vhost_user_socket=/tmp/virtiofs \
+    --socket-path=/tmp/virtiofs \
     -o source=/tmp/shared_dir \
-    -o cache=always
+    -o cache=none
 ```
 
-The `cache=always` option should be the default when using `virtiofsd` with the __cloud-hypervisor__ VMM. This allows the daemon to memory map the shared files, which gives better I/O performance.
+The `cache=none` option should be the default when using `virtiofsd` with the __cloud-hypervisor__ VMM. This prevents from using the guest page cache, which reduces the memory footprint of the guest. When running multiple virtual machines on the same host, this will let the host deal with page cache, which will increase the density of virtual machines which can be launched.
 
-The `cache=none` option is another way to run the daemon but because the _virtqueues_ are used to convey the files content in this case, the I/O performance is impacted.
+The `cache=always` option will allow for the guest page cache to be used, which will increase the memory footprint of the guest. This option should be used only for specific use cases where a single VM is going to be running on a host.
 
 ### The kernel
 
@@ -52,39 +52,37 @@ Direct kernel boot option is preferred since we need to provide the custom kerne
 
 Because _vhost-user_ expects a dedicated process (__virtiofsd__ in this case) to be able to access the guest RAM to communicate through the _virtqueues_ with the driver running in the guest, `--memory` option needs to be slightly modified. It needs to specify a backing file for the memory so that an external process can access it.
 
-Assuming you have `clear-kvm.img` and `custom-vmlinux.bin` on your system, here is the __cloud-hypervisor__ command you need to run:
+Assuming you have `focal-server-cloudimg-amd64.raw` and `custom-vmlinux.bin` on your system, here is the __cloud-hypervisor__ command you need to run:
 ```bash
 ./cloud-hypervisor \
     --cpus 4 \
     --memory "size=512,file=/dev/shm" \
-    --disk path=clear-kvm.img \
+    --disk path=focal-server-cloudimg-amd64.raw \
     --kernel custom-vmlinux.bin \
-    --cmdline "console=ttyS0 reboot=k panic=1 nomodules root=/dev/vda3" \ 
-    --fs tag=virtiofs,sock=/tmp/virtiofs,num_queues=1,queue_size=512
+    --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
+    --fs tag=myfs,socket=/tmp/virtiofs,num_queues=1,queue_size=512
 ```
 
 By default, DAX is enabled with a cache window of 8GiB. You can specify a custom size (let's say 4GiB for this example) for the cache by explicitly setting DAX and the cache size:
 
 ```bash
---fs tag=virtiofs,sock=/tmp/virtiofs,num_queues=1,queue_size=512,dax=on,cache_size=4G
+--fs tag=virtiofs,socket=/tmp/virtiofs,num_queues=1,queue_size=512,dax=on,cache_size=4G
 
 ```
 
 In case you don't want to use a shared window of cache to pass the shared files content, this means you will have to explicitly disable DAX with `dax=off`. Note that in this case, the `cache_size` parameter will be ignored.
 
 ```bash
---fs tag=virtiofs,sock=/tmp/virtiofs,num_queues=1,queue_size=512,dax=off
+--fs tag=virtiofs,socket=/tmp/virtiofs,num_queues=1,queue_size=512,dax=off
 
 ```
 
 ### Mount the shared directory
-The last step is to mount the shared directory inside the guest, using the `virtio_fs` filesystem type.
+The last step is to mount the shared directory inside the guest, using the `virtiofs` filesystem type.
 ```bash
 mkdir mount_dir
-mount \
-    -t virtio_fs virtiofs mount_dir/ \
-    -o rootmode=040000,user_id=0,group_id=0,dax
+mount -t virtiofs -o dax myfs mount_dir/
 ```
-The `tag` needs to be consistent with what has been provided through the __cloud-hypervisor__ command line, which happens to be `virtiofs` in this example.
+The `tag` needs to be consistent with what has been provided through the __cloud-hypervisor__ command line, which happens to be `myfs` in this example.
 
-The `dax` option must be removed in case the shared cache region is not enabled from the VMM.
+The `-o dax` option must be removed in case the shared cache region is not enabled from the VMM.

docs/fuzzing.md

@@ -0,0 +1,35 @@
+# Fuzzing in Cloud Hypervisor
+
+Cloud Hypervisor uses [cargo-fuzz](https://github.com/rust-fuzz/cargo-fuzz) for fuzzing individual components.
+
+The fuzzers are are in the `fuzz/fuzz_targets` directory
+
+## Preparation
+
+Switch to nightly: 
+
+````
+rustup override set nightly
+````
+
+Install `cargo fuzz`: 
+
+```
+cargo install cargo-fuzz
+```
+
+## Running the fuzzers
+
+e.g. To run the `qcow` fuzzer using all available CPUs:
+
+```
+cargo fuzz run qcow -j `nproc`
+```
+
+## Adding a new fuzzer
+
+```
+cargo fuzz add <new_fuzzer>
+```
+
+Inspiration for fuzzers can be found in [crosvm](https://chromium.googlesource.com/chromiumos/platform/crosvm/+/refs/heads/master/fuzz/)

docs/hotplug.md

@@ -5,16 +5,14 @@ Currently Cloud Hypervisor only support hot plugging of CPU devices.
 ## Kernel support
 
 For hotplug on Cloud Hypervisor ACPI GED support is needed. This can either be achieved by turning on `CONFIG_ACPI_REDUCED_HARDWARE_ONLY` 
-or by using this kernel patch (available in 5.5rc1 and later): https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/patch/drivers/acpi/Makefile?id=ac36d37e943635fc072e9d4f47e40a48fbcdb3f0
-
-This patch is integrated into the Clear Linux KVM and cloudguest images.
+or by using this kernel patch (available in 5.5-rc1 and later): https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/patch/drivers/acpi/Makefile?id=ac36d37e943635fc072e9d4f47e40a48fbcdb3f0
 
 ## CPU Hot Plug
 
-Extra vCPUs can be added (but not removed [1]) from a running Cloud Hypervisor instance. This is controlled by two mechanisms:
+Extra vCPUs can be added and removed from a running Cloud Hypervisor instance. This is controlled by two mechanisms:
 
 1. Specifying a number of maximum potential vCPUs that is greater than the number of default (boot) vCPUs.
-2. Making a HTTP API request to the VM to ask for the additional vCPUs to be added.
+2. Making a HTTP API request to the VMM to ask for the additional vCPUs to be added.
 
 To use CPU hotplug start the VM with the number of max vCPUs greater than the number of boot vCPUs, e.g.
 
@@ -22,8 +20,9 @@ To use CPU hotplug start the VM with the number of max vCPUs greater than the nu
 $ pushd $CLOUDH
 $ sudo setcap cap_net_admin+ep ./cloud-hypervisor/target/release/cloud-hypervisor
 $ ./cloud-hypervisor/target/release/cloud-hypervisor \
-	--kernel ./hypervisor-fw \
-	--disk path=clear-31890-kvm.img \
+	--kernel custom-vmlinux.bin \
+	--cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
+	--disk path=focal-server-cloudimg-amd64.raw \
 	--cpus boot=4,max=8 \
 	--memory size=1024M \
 	--net "tap=,mac=,ip=,mask=" \
@@ -40,7 +39,7 @@ To ask the VMM to add additional vCPUs then use the resize API:
 curl -H "Accept: application/json" -H "Content-Type: application/json" -i -XPUT --unix-socket /tmp/ch-socket -d "{ \"desired_vcpus\":8}" http://localhost/api/v1/vm.resize
 ```
 
-The extra vCPU threads will be created and advertised to the running kernel. The kernel does not bring up the CPUs immediately and instead the user must "on-line" them from inside the VM:
+The extra vCPU threads will be created and advertised to the running kernel. The kernel does not bring up the CPUs immediately and instead the user must "online" them from inside the VM:
 
 ```shell
 root@ch-guest ~ # lscpu | grep list:
@@ -54,4 +53,61 @@ On-line CPU(s) list:             0-7
 
 After a reboot the added CPUs will remain.
 
-[1]: It is not currently possible to remove CPUs after they are added however CPU hot unplug is included in our roadmap for a future version.
+Removing CPUs works similarly by reducing the number in the "desired_vcpus" field of the reisze API. The CPUs will be automatically offlined inside the guest so there is no need to run any commands inside the guest:
+
+```shell
+curl -H "Accept: application/json" -H "Content-Type: application/json" -i -XPUT --unix-socket /tmp/ch-socket -d "{ \"desired_vcpus\":2}" http://localhost/api/v1/vm.resize
+```
+
+As per adding CPUs to the guest, after a reboot the VM will be running with the reduced number of vCPUs.
+
+## Memory Hot Plug
+
+Extra memory can be added from a runing Cloud Hypervisor instance. This is controlled by two mechanisms:
+
+1. Allocating some of the guest physical address space for hotplug memory.
+2. Making a HTTP API request to the VMM to ask for a new amount of RAM to be assigned to the VM. In the case of expanding the memory for the VM the new memory will be hotplugged into the running VM, if reducing the size of the memory then change will take effect after the next reboot.
+
+To use memory hotplug start the VM specifying some size RAM in the "hotplug_size" parameter to the memory configuration. Not all the memory specified in this parameter will be available to hotplug as there are spacing and alignment requirements so it is recommended to make it larger than the hotplug RAM needed.
+
+```shell
+$ pushd $CLOUDH
+$ sudo setcap cap_net_admin+ep ./cloud-hypervisor/target/release/cloud-hypervisor
+$ ./cloud-hypervisor/target/release/cloud-hypervisor \
+	--kernel custom-vmlinux.bin \
+	--cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
+	--disk path=focal-server-cloudimg-amd64.raw \
+	--cpus boot=4,max=8 \
+	--memory size=1024M,hotplug_size=8192M \
+	--net "tap=,mac=,ip=,mask=" \
+	--rng \
+    --api-socket=/tmp/ch-socket
+$ popd
+```
+
+Before issuing the API request it is necessary to run the following command inside the VM to make it automatically online the added memory:
+
+```shell
+root@ch-guest ~ # echo online | sudo tee /sys/devices/system/memory/auto_online_blocks
+```
+
+To ask the VMM to add expand the RAM for the VM  (request is in bytes):
+
+```shell
+curl -H "Accept: application/json" -H "Content-Type: application/json" -i -XPUT --unix-socket /tmp/ch-socket -d "{ \"desired_vcpus\": 4, \"desired_ram\" : 3221225472}" http://localhost/api/v1/vm.resize
+```
+
+The new memory is now available to use inside the VM:
+
+```shell
+free -h
+              total        used        free      shared  buff/cache   available
+Mem:          3.0Gi        71Mi       2.8Gi       0.0Ki        47Mi       2.8Gi
+Swap:          32Mi          0B        32Mi
+```
+
+Due to guest OS limitations is is necessary to ensure that amount of memory added (between currently assigned RAM and that which is desired) is a multiple of 128MiB.
+
+The same API can also be used to reduce the desired RAM for a VM but the change will not be applied until the VM is rebooted.
+
+Memory and CPU resizing can be combined together into the same HTTP API request.

docs/intel_sgx.md

@@ -0,0 +1,55 @@
+# Intel SGX
+
+Intel® Software Guard Extensions (Intel® SGX) is an Intel technology designed
+to increase the security of application code and data. Cloud-Hypervisor supports
+SGX virtualization through KVM. Because SGX is built on hardware features that
+cannot be emulated in software, virtualizing SGX requires support in KVM and in
+the host kernel. The required Linux and KVM changes can be found in the
+[KVM SGX Tree](https://github.com/intel/kvm-sgx).
+
+Utilizing SGX in the guest requires a kernel/OS with SGX support, e.g. a kernel
+buit using the [SGX Linux Development Tree](https://github.com/jsakkine-intel/linux-sgx.git)
+or the [KVM SGX Tree](https://github.com/intel/kvm-sgx). Running KVM SGX as the
+guest kernel allows nested virtualization of SGX.
+
+For more information about SGX, please refer to the [SGX Homepage](https://software.intel.com/sgx).
+
+For more information about SGX SDK and how to test SGX, please refer to the
+following [instructions](https://github.com/intel/linux-sgx).
+
+## Cloud-Hypervisor support
+
+Assuming the host exposes `/dev/sgx/virt_epc`, we can pass SGX enclaves through
+the guest.
+
+In order to use SGX enclaves within a Cloud-Hypervisor VM, we must define one
+or several Enclave Page Cache (EPC) sections. Here is an example of a VM being
+created with 2 EPC sections, the first one being 64MiB with pre-allocated
+memory, the second one being 32MiB with no pre-allocated memory.
+
+```bash
+./cloud-hypervisor \
+    --cpus boot=1 \
+    --memory size=1G \
+    --disk path=focal-server-cloudimg-amd64.raw \
+    --kernel bzImage \
+    --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
+    --sgx-epc size=64M,prefault=on size=32M,prefault=off
+```
+
+Once booted, and assuming your guest kernel contains the patches from the
+[KVM SGX Tree](https://github.com/intel/kvm-sgx), you can validate SGX devices
+have been correctly created under `/dev/sgx`:
+
+```bash
+ls /dev/sgx
+enclave provision virt_epc
+```
+
+From this point, it is possible to run any SGX application from the guest, as
+it will access `/dev/sgx/enclave` device to create dedicated SGX enclaves.
+
+Note: There is only one contiguous SGX EPC region, which contains all SGX EPC
+sections. This region is exposed through ACPI and marked as reserved through
+the e820 table. It is treated yet as another device, which means it should
+appear at the end of the guest address space.

docs/iommu.md

@@ -88,9 +88,9 @@ virtual IOMMU:
 ./cloud-hypervisor \
     --cpus 1 \
     --memory size=512M \
-    --disk path=clear-kvm.img,iommu=on \
+    --disk path=focal-server-cloudimg-amd64.raw,iommu=on \
     --kernel custom-bzImage \
-    --cmdline "console=ttyS0 root=/dev/vda3" \
+    --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
 ```
 
 From a guest perspective, it is easy to verify if the device is protected by
@@ -165,9 +165,9 @@ be consumed.
 ./cloud-hypervisor \
     --cpus 1 \
     --memory size=8G,file=/dev/hugepages \
-    --disk path=clear-kvm.img \
+    --disk path=focal-server-cloudimg-amd64.raw \
     --kernel custom-bzImage \
-    --cmdline "console=ttyS0 root=/dev/vda3 hugepagesz=2M hugepages=2048" \
+    --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw hugepagesz=2M hugepages=2048" \
     --net tap=,mac=,iommu=on
 ```
 
@@ -182,9 +182,9 @@ passing through is `0000:00:01.0`.
 ./cloud-hypervisor \
     --cpus 1 \
     --memory size=8G,file=/dev/hugepages \
-    --disk path=clear-kvm.img \
+    --disk path=focal-server-cloudimg-amd64.raw \
     --kernel custom-bzImage \
-    --cmdline "console=ttyS0 root=/dev/vda3 kvm-intel.nested=1 vfio_iommu_type1.allow_unsafe_interrupts rw hugepagesz=2M hugepages=2048" \
+    --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw kvm-intel.nested=1 vfio_iommu_type1.allow_unsafe_interrupts rw hugepagesz=2M hugepages=2048" \
     --device path=/sys/bus/pci/devices/0000:00:01.0,iommu=on
 ```
 
@@ -202,8 +202,8 @@ Last thing is to start the L2 guest with the huge pages memory backend.
 ./cloud-hypervisor \
     --cpus 1 \
     --memory size=4G,file=/dev/hugepages \
-    --disk path=clear-kvm.img \
+    --disk path=focal-server-cloudimg-amd64.raw \
     --kernel custom-bzImage \
-    --cmdline "console=ttyS0 root=/dev/vda3" \
+    --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
     --device path=/sys/bus/pci/devices/0000:00:04.0
 ```

docs/networking.md

@@ -2,6 +2,21 @@
 
 cloud-hypervisor can emulate one or more virtual network interfaces, represented at the hypervisor host by [tap devices](https://www.kernel.org/doc/Documentation/networking/tuntap.txt). This guide briefly describes, in a manual and distribution neutral way, how to setup and use networking with cloud-hypevisor.
 
+## Multiple queue support for net devices ##
+
+While multiple vcpus defined for guest, to gain the benefit of vcpu scalable to improve performance, it suggests to define multiple queue pairs for net devices, one Tx/Rx queue pair per one vcpu, that means the number of queue pairs at least is equal to the vcpu count. In that case, after virtnet driver set cpu affinity for virtqueues in guest kernel, vcpus could handle interrupt from different virtqueue pairs in parallel.
+
+It will gain better performance for guest that has multiple queues defined for net devices while it has multiple net sessions running in userspace.
+
+To enable multiple queue support in cloud-hypervisor, multiple queue pairs will be defined, while multiple tap fds will be opened for the same tap device, it will also have multiple threads started, each thread will monitor and handle the events from each virtqueue pairs and the associated tap fd.
+
+Note:
+
+- Currently, it does not support to use ethtool to change the combined queue numbers in guest.
+- Multiple queue is enabled for vhost-user-net backend in cloud-hypervisor, however, multiple thread is not added to handle mq, thus, the performance for vhost-user-net backend is not supposed to be improved. The multiple thread will be added for backend later.
+- Performance test for vhost-user-net will be covered once vhost-user-net backend has mulitple thread supported.
+- Performance test for virtio-net is done by comparing 2 queue pairs with 1 queue pairs, that to run 2 iperf3 sessions in the same test environments, throughput is improved about 37%.
+
 ## Start cloud-hypervisor with net devices
 
 Use one `--net` command-line argument from cloud-hypervisor to specify the emulation of one or more virtual NIC's. The example below instructs cloud-hypervisor to emulate for instance 2 virtual NIC's:
@@ -10,21 +25,37 @@ Use one `--net` command-line argument from cloud-hypervisor to specify the emula
 ./cloud-hypervisor \
     --cpus 4 \
     --memory "size=512M" \
-    --disk path=my-root-disk.img \
+    --disk path=focal-server-cloudimg-amd64.raw \
     --kernel my-vmlinux.bin \
-    --cmdline "console=ttyS0 reboot=k panic=1 nomodules root=/dev/vda3" \
-    --net tap=ich0,mac=a4:a1:c2:00:00:01,ip=192.168.4.2,mask=255.255.255.0 \
-          tap=ich1,mac=a4:a1:c2:00:00:02,ip=10.0.1.2,mask=255.255.255.0
+    --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
+    --net tap=ich0,mac=a4:a1:c2:00:00:01,ip=192.168.4.2,mask=255.255.255.0,num_queues=2,queue_size=256 \
+          tap=ich1,mac=a4:a1:c2:00:00:02,ip=10.0.1.2,mask=255.255.255.0,num_queues=2,queue_size=256
 ```
- 
+
 The `--net` argument takes 1 or more space-separated strings of key value pairs containing the following 4 keys or fields:
 
-| Name     | Purpose                    | Optional  |
-| -------- |----------------------------| ----------|
-| tap      | tap device name            | Yes       |
-| mac      | vNIC mac address           | Yes       |
-| ip       | tap IP IP address          | yes       |
-| mask     | tap IP netmask             | Yes       |
+| Name       | Purpose                    | Optional  |
+| -----------|----------------------------| ----------|
+| tap        | tap device name            | Yes       |
+| mac        | vNIC mac address           | Yes       |
+| ip         | tap IP IP address          | yes       |
+| mask       | tap IP netmask             | Yes       |
+| num_queues | the number of queues       | yes       |
+| queue_size | the size of each queue     | Yes       |
+
+num_queues is the total number of tx and rx queues, the default value is 2, and it could be increased by multiples of 2. Additionally, num_queues is suggested to be as 2 times of vcpu count. The default value for queue_size is 256.
+
+If the tap device is pre-created on host before guest boot up. To use multiple queue support for net device in guest, the tap device should be opened like this from host.
+
+```bash
+[root@localhost ~]# ip tuntap add name ich0 mode tap multi_queue
+```
+
+And the `--net` device should specify support for multiple queues. `num_queues` must be a multiple of 2 starting at least from 4 since multiple queues really means multiple queue pairs. We need at least 2 pairs for this configuration to be correct:
+
+```bash
+--net tap=ich0,mac=a4:a1:c2:00:00:01,ip=192.168.4.2,mask=255.255.255.0,num_queues=4,queue_size=256
+```
 
 ## Configure the tap devices
 

docs/snapshot_restore.md

@@ -0,0 +1,112 @@
+# Snapshot and Restore
+
+The goal for the snapshot/restore feature is to provide the user with the
+ability to take a snapshot of a previously paused virtual machine. This
+snapshot can be used as the base for creating new identical virtual machines,
+without the need to boot them from scratch. The restore codepath takes the
+snapshot and creates the exact same virtual machine, restoring the previously
+saved states. The new virtual machine is restored in a paused state, as it was
+before the snapshot was performed.
+
+This feature is important for the project as it establishes the first step
+towards the support for live migration.
+
+## Snapshot a Cloud-Hypervisor VM
+
+First thing, we must run a Cloud-Hypervisor VM:
+
+```bash
+./cloud-hypervisor \
+    --api-socket /tmp/cloud-hypervisor.sock \
+    --cpus boot=4 \
+    --memory size=4G \
+    --kernel bzImage \
+    --cmdline "root=/dev/vda1 console=hvc0 rw" \
+    --disk path=focal-server-cloudimg-amd64.raw
+```
+
+At any point in time when the VM is running, one might choose to pause it:
+
+```bash
+./ch-remote --api-socket=/tmp/cloud-hypervisor.sock pause
+```
+
+Once paused, the VM can be safely snapshot into the specified directory and
+using the following command:
+
+```bash
+./ch-remote --api-socket=/tmp/cloud-hypervisor.sock snapshot file:///home/foo/snapshot
+```
+
+Given the directory was present on the system, the snapshot will succeed and
+it should contain the following files:
+
+```bash
+ll /home/foo/snapshot/
+total 4194536
+drwxrwxr-x  2 foo bar       4096 Jul 22 11:50 ./
+drwxr-xr-x 47 foo bar       4096 Jul 22 11:47 ../
+-rw-------  1 foo bar 3221225472 Jul 22 11:19 memory-region-0
+-rw-------  1 foo bar 1073741824 Jul 22 11:19 memory-region-1
+-rw-------  1 foo bar     217853 Jul 22 11:19 vm.json
+```
+
+In this particular example, we can observe that 2 memory region files were
+created. That is explained by the size of the guest RAM, which is 4GiB in this
+case. Because it exceeds 3GiB (which is where we can find a ~1GiB memory hole),
+Cloud-Hypervisor needs 2 distincts memory regions to be created. Each memory
+region's content is stored through a dedicated file, which explains why we end
+up with 2 different files, the first one containing the guest RAM range 0-3GiB
+and the second one containing the guest RAM range 3-4GiB.
+
+`vm.json` gathers all information related to the virtual machine configuration
+and state. The configuration bits are used to create a similar virtual machine
+with the correct amount of CPUs, RAM, and other expected devices. The state
+bits are used to restore each component in the state it was left before the
+snapshot occured.
+
+## Restore a Cloud-Hypervisor VM
+
+Given that one has access to an existing snapshot in `/home/foo/snapshot`,
+it is possible to create a new VM based on this snapshot with the following 
+command:
+
+```bash
+./cloud-hypervisor \
+    --api-socket /tmp/cloud-hypervisor.sock \
+    --restore source_url=file:///home/foo/snapshot
+```
+
+Or using two different commands from two terminals:
+
+```bash
+# First terminal
+./cloud-hypervisor --api-socket /tmp/cloud-hypervisor.sock
+
+# Second terminal
+./ch-remote --api-socket=/tmp/cloud-hypervisor.sock restore source_url=file:///home/foo/snapshot
+```
+
+Remember the VM is restored in a `paused` state, which was the VM's state when
+it was snapshot. For this reason, one must explicitly `resume` the VM before to
+start using it.
+
+```bash
+./ch-remote --api-socket=/tmp/cloud-hypervisor.sock resume
+```
+
+At this point, the VM is fully restored and is identical to the VM which was
+snapshot earlier.
+
+## Limitations
+
+The support of snapshot/restore feature is still experimental, meaning one
+might still find some bugs associated with it.
+
+Additionally, some devices and features don't support to be snapshot and
+restored yet:
+- `vhost-user` devices
+- `virtio-mem`
+- Intel SGX
+
+VFIO devices are out of scope.

docs/vfio.md

@@ -66,10 +66,10 @@ takes the device's sysfs path as an argument. In our example it is
 ```
 ./target/debug/cloud-hypervisor \
     --kernel ~/vmlinux \
-    --disk path=~/clear-29160-kvm.img \
+    --disk path=~/focal-server-cloudimg-amd64.raw \
     --console off \
     --serial tty \
-    --cmdline "console=ttyS0 reboot=k panic=1 nomodules i8042.noaux i8042.nomux i8042.nopnp i8042.dumbkbd root=/dev/vda3" \
+    --cmdline "console=ttyS0 root=/dev/vda1 rw" \
     --cpus 4 \
     --memory size=512M \
     --device path=/sys/bus/pci/devices/0000:01:00.0/

docs/vhost-user-blk-testing.md

@@ -0,0 +1,104 @@
+# How to test vhost-user-blk with SPDK
+
+The purpose of this document is to illustrate how to test vhost-user-blk in Cloud Hypervisor with SPDK as the backend.
+
+## Framework
+
+It's a simple test to validate the block read/write between VM and block backend.
+```
+             +----+----------+          +-------------+-----------+
+             |    |          |          |             |           |
+             |    |vhost-user|----------| vhost-user  |    dpdk   |
+             |    |blk device|          | port 1      |           |
+             |    |          |          |             |           |
+             |    +----------+          +-------------+-----------+
+             |               |          |                         |
+             |      vm       |          |           spdk          |
+             |               |          |                         |
+          +--+----------------------------------------------------+--+
+          |  |                  hugepages                         |  |
+          |  +----------------------------------------------------+  |
+          |                                                          |
+          |                       host                               |
+          |                                                          |
+          +----------------------------------------------------------+
+```
+## Prerequisites
+
+Prior to running the test, the following steps need to be performed.
+- Enable hugepages
+- Install SPDK
+
+Here are some good references for detailing them.
+- spdk
+	* https://spdk.io/doc/
+
+## Test environment
+
+The below test environment is based on ubuntu release(16.04.1 LTS), as for other system, please check related document.
+The test runs with multiple queue (MQ) support enabled, using 4 queues defined for both SPDK and the virtual machine.
+Here are the details on how the test can be run.
+
+### The hugepages settings in host linux
+Add "default_hugepagesz=1G hugepagesz=1G hugepages=2" into host linux cmdline.
+As for how to change Ubuntu linux cmdline in grub file, please ref below link:
+https://www.ostechnix.com/configure-grub-2-boot-loader-settings-ubuntu-16-04/
+reboot Ubuntu
+sudo mount -t hugetlbfs -o pagesize=1G none /dev/hugepages
+
+### Download the SPDK code
+git clone https://github.com/spdk/spdk
+cd spdk
+git submodule update --init
+
+### Create the build dep
+./scripts/pkgdep.sh
+
+### Build spdk
+./configure
+make
+
+### Set the SPDk environment
+sudo HUGEMEM=2048 scripts/setup.sh
+sudo ./app/vhost/vhost -S /var/tmp -s 1024 -m 0x3 &
+
+### Create 512M block device
+sudo scripts/rpc.py bdev_malloc_create 512 512 -b Malloc0
+sudo scripts/rpc.py vhost_create_blk_controller --cpumask 0x1 vhost.1 Malloc0
+
+_Launch the VM_
+
+VMs run in client mode. They connect to the socket created by the `dpdkvhostuser` in the SPDK backend.
+```bash
+# From the test terminal. We need to create one vhost-user-blk device for the --disk.
+./cloud-hypervisor \
+        --cpus boot=4 \
+        --memory size=1024M,hugepages=on \
+        --kernel linux/arch/x86/boot/compressed/vmlinux.bin \
+        --cmdline "console=ttyS0 root=/dev/vda1 rw iommu=off" \
+        --disk path=images/focal-server-cloudimg-amd64.raw vhost_user=true,socket=/var/tmp/vhost.1,num_queues=4,queue_size=128 \
+        --console off \
+        --serial tty \
+        --rng
+```
+
+```bash
+# How to test the vhost-user-blk device with SPDK backend
+login in guest
+
+# Use lsblk command to find out vhost-user-blk device
+lsblk
+NAME    MAJ:MIN RM  SIZE RO TYPE MOUNTPOINT
+vda     252:0    0  2.2G  0 disk 
+├─vda1  252:1    0  2.1G  0 part /
+├─vda14 252:14   0    4M  0 part 
+└─vda15 252:15   0  106M  0 part /boot/efi
+vdb    253:16   0  512M  0 disk
+
+The vhost-user-blk device is /dev/vdb
+
+# How to do simple read/write test
+dd if=/dev/vdb of=/dev/null bs=2M iflag=direct
+dd of=/dev/vdb if=/dev/zero bs=2M oflag=direct count=256
+
+If you want to do fio test, please install fio binary into guest. The detailed info is not listed here.

docs/vhost-user-net-testing.md

@@ -0,0 +1,132 @@
+# How to test Vhost-user net with OpenVSwitch/DPDK
+
+The purpose of this document is to illustrate how to test vhost-user-net in cloud-hypervisor with OVS/DPDK as the backend.
+
+## Framework
+
+It's a simple test to validate the communication between two virtual machine, connecting them to vhost-user ports respectively provided by `OVS/DPDK`.
+```
+             +----+----------+          +-------------+-----------+-------------+          +----------+----+  
+             |    |          |          |             |           |             |          |          |    | 
+             |    |vhost-user|----------| vhost-user  |   ovs     | vhost-user  |----------|vhost-user|    |           
+             |    |net device|          | port 1      |           | port 2      |          |net device|    |           
+             |    |          |          |             |           |             |          |          |    |           
+             |    +----------+          +-------------+-----------+-------------+          +----------+    |           
+             |               |          |                                       |          |               |           
+             |vm1            |          |                  dpdk                 |          |           vm2 |           
+             |               |          |                                       |          |               |           
+          +--+---------------------------------------------------------------------------------------------+--+        
+          |  |                                       hugepages                                             |  |        
+          |  +---------------------------------------------------------------------------------------------+  |        
+          |                                                                                                   |        
+          |                                              host                                                 |        
+          |                                                                                                   |  
+          +---------------------------------------------------------------------------------------------------+        
+```
+## Prerequisites
+
+Prior to running the test, the following steps need to be performed.
+- Enable hugepages
+- Install DPDK
+- Install OVS
+
+Here are some good references for detailing them.
+- Red Hat
+	* https://wiki.qemu.org/Documentation/vhost-user-ovs-dpdk
+- Ubuntu server
+	* https://help.ubuntu.com/lts/serverguide/DPDK.html
+	* https://software.intel.com/en-us/articles/set-up-open-vswitch-with-dpdk-on-ubuntu-server
+
+## Test
+The test runs with multiple queue (MQ) support enabled, using 2 pairs of TX/RX queues defined for both OVS and the virtual machine. Here are the details on how the test can be run.
+
+_Setup OVS_
+
+`ovs_test.sh` is created to setup and start OVS. OVS will provide the `dpdkvhostuser` backend running in server mode.
+```bash
+mkdir -p /var/run/openvswitch
+modprobe openvswitch
+killall ovsdb-server ovs-vswitchd
+rm -f /var/run/openvswitch/vhost-user*
+rm -f /etc/openvswitch/conf.db
+export DB_SOCK=/var/run/openvswitch/db.sock
+ovsdb-tool create /etc/openvswitch/conf.db /usr/share/openvswitch/vswitch.ovsschema
+ovsdb-server --remote=punix:$DB_SOCK --remote=db:Open_vSwitch,Open_vSwitch,manager_options --pidfile --detach
+ovs-vsctl --no-wait init
+ovs-vsctl --no-wait set Open_vSwitch . other_config:dpdk-lcore-mask=0xf
+ovs-vsctl --no-wait set Open_vSwitch . other_config:dpdk-socket-mem=1024
+ovs-vsctl --no-wait set Open_vSwitch . other_config:dpdk-init=true
+ovs-vsctl --no-wait set Open_vSwitch . other_config:pmd-cpu-mask=0xf
+ovs-vswitchd unix:$DB_SOCK --pidfile --detach --log-file=/var/log/openvswitch/ovs-vswitchd.log
+ovs-vsctl add-br ovsbr0 -- set bridge ovsbr0 datapath_type=netdev
+ovs-vsctl add-port ovsbr0 vhost-user1 -- set Interface vhost-user1 type=dpdkvhostuser
+ovs-vsctl add-port ovsbr0 vhost-user2 -- set Interface vhost-user2 type=dpdkvhostuser
+ovs-vsctl set Interface vhost-user1 options:n_rxq=2
+ovs-vsctl set Interface vhost-user2 options:n_rxq=2
+```
+_Run ovs_test.sh_
+```bash
+./ovs_test.sh
+```
+
+_Launch the VMs_
+
+VMs run in client mode. They connect to the socket created by the `dpdkvhostuser` backend.
+```bash
+# From one terminal. We need to give the cloud-hypervisor binary the NET_ADMIN capabilities for it to set TAP interfaces up on the host.
+./cloud-hypervisor \
+        --cpus boot=2 \
+        --memory size=512M,hugepages=on   \
+        --kernel vmlinux \
+        --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
+        --disk path=focal-server-cloudimg-amd64.raw   \
+        --net mac=52:54:00:02:d9:01,vhost_user=true,socket=/var/run/openvswitch/vhost-user1,num_queues=4
+
+# From another terminal. We need to give the cloud-hypervisor binary the NET_ADMIN capabilities for it to set TAP interfaces up on the host.
+./cloud-hypervisor \
+        --cpus boot=2 \
+        --memory size=512M,hugepages=on   \
+        --kernel vmlinux \
+        --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
+        --disk path=focal-server-cloudimg-amd64.raw   \
+        --net "mac=52:54:20:11:C5:02,vhost_user=true,socket=/var/run/openvswitch/vhost-user2,num_queues=4"
+```
+
+_Setup VM1_
+```bash
+# From inside the guest
+sudo ip addr add 172.100.0.1/24 dev enp0s3
+```
+
+_Setup VM2_
+```bash
+# From inside the guest
+sudo ip addr add 172.100.0.2/24 dev enp0s3
+```
+
+_Ping VM1 from VM2_
+```bash
+# From inside the guest
+sudo ping 172.100.0.1
+```
+
+_Ping VM2 from VM1_
+```bash
+# From inside the guest
+sudo ping 172.100.0.2
+```
+
+__Result:__ At this point, VM1 and VM2 can ping each other successfully. We can now run `iperf3` test.
+
+_Run VM1 as server_
+```bash
+# From inside the guest
+iperf3 -s -p 4444
+```
+
+_Run VM2 as client_
+```bash
+# From inside the guest
+iperf3 -c 172.100.0.1 -t 30 -p 4444 &
+```
+

fuzz/.gitignore

@@ -0,0 +1,4 @@
+
+target
+corpus
+artifacts

fuzz/Cargo.toml

@@ -0,0 +1,41 @@
+
+[package]
+name = "cloud-hypervisor-fuzz"
+version = "0.0.0"
+authors = ["Automatically generated"]
+publish = false
+edition = "2018"
+
+[package.metadata]
+cargo-fuzz = true
+
+[dependencies]
+libc = "0.2.72"
+libfuzzer-sys = "0.3"
+qcow = { path = "../qcow" }
+virtio-devices = { path = "../virtio-devices" }
+vmm-sys-util = ">=0.3.1"
+vm-virtio = { path = "../vm-virtio" }
+vm-memory = "0.2.1"
+
+[dependencies.cloud-hypervisor]
+path = ".."
+
+[patch.crates-io]
+vm-memory = { git = "https://github.com/cloud-hypervisor/vm-memory", branch = "ch" }
+
+# Prevent this from interfering with workspaces
+[workspace]
+members = ["."]
+
+[[bin]]
+name = "qcow"
+path = "fuzz_targets/qcow.rs"
+test = false
+doc = false
+
+[[bin]]
+name = "block"
+path = "fuzz_targets/block.rs"
+test = false
+doc = false

fuzz/fuzz_targets/block.rs

@@ -0,0 +1,136 @@
+// Copyright 2018 The Chromium OS Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style license that can be
+// found in the LICENSE file.
+
+#![no_main]
+
+use libfuzzer_sys::fuzz_target;
+use std::ffi;
+use std::fs::File;
+use std::io::{self, Cursor, Read, Seek, SeekFrom};
+use std::mem::size_of;
+use std::os::unix::io::{AsRawFd, FromRawFd, RawFd};
+use std::path::PathBuf;
+use std::sync::Arc;
+use virtio_devices::{Block, VirtioDevice, VirtioInterrupt, VirtioInterruptType};
+use vm_memory::{Bytes, GuestAddress, GuestMemoryAtomic, GuestMemoryMmap};
+use vm_virtio::Queue;
+use vmm_sys_util::eventfd::EventFd;
+
+const MEM_SIZE: u64 = 256 * 1024 * 1024;
+const DESC_SIZE: u64 = 16; // Bytes in one virtio descriptor.
+const QUEUE_SIZE: u16 = 16; // Max entries in the queue.
+const CMD_SIZE: usize = 16; // Bytes in the command.
+
+fuzz_target!(|bytes| {
+    let size_u64 = size_of::<u64>();
+    let mem = GuestMemoryMmap::from_ranges(&[(GuestAddress(0), MEM_SIZE as usize)]).unwrap();
+
+    // The fuzz data is interpreted as:
+    // starting index 8 bytes
+    // command location 8 bytes
+    // command 16 bytes
+    // descriptors circular buffer 16 bytes * 3
+    if bytes.len() < 4 * size_u64 {
+        // Need an index to start.
+        return;
+    }
+
+    let mut data_image = Cursor::new(bytes);
+
+    let first_index = read_u64(&mut data_image);
+    if first_index > MEM_SIZE / DESC_SIZE {
+        return;
+    }
+    let first_offset = first_index * DESC_SIZE;
+    if first_offset as usize + size_u64 > bytes.len() {
+        return;
+    }
+
+    let command_addr = read_u64(&mut data_image);
+    if command_addr > MEM_SIZE - CMD_SIZE as u64 {
+        return;
+    }
+    if mem
+        .write_slice(
+            &bytes[2 * size_u64..(2 * size_u64) + CMD_SIZE],
+            GuestAddress(command_addr as u64),
+        )
+        .is_err()
+    {
+        return;
+    }
+
+    data_image.seek(SeekFrom::Start(first_offset)).unwrap();
+    let desc_table = read_u64(&mut data_image);
+
+    if mem
+        .write_slice(&bytes[32..], GuestAddress(desc_table as u64))
+        .is_err()
+    {
+        return;
+    }
+
+    let mut q = Queue::new(QUEUE_SIZE);
+    q.ready = true;
+    q.size = QUEUE_SIZE / 2;
+    q.max_size = QUEUE_SIZE;
+
+    let queue_evts: Vec<EventFd> = vec![EventFd::new(0).unwrap()];
+    let queue_fd = queue_evts[0].as_raw_fd();
+    let queue_evt = unsafe { EventFd::from_raw_fd(libc::dup(queue_fd)) };
+
+    let shm = memfd_create(&ffi::CString::new("fuzz").unwrap(), 0).unwrap();
+    let disk_file: File = unsafe { File::from_raw_fd(shm) };
+    let raw_img = qcow::RawFile::new(disk_file, false);
+
+    let mut block = Block::new(
+        "tmp".to_owned(),
+        raw_img,
+        PathBuf::from(""),
+        false,
+        false,
+        2,
+        256,
+    )
+    .unwrap();
+
+    block
+        .activate(
+            GuestMemoryAtomic::new(mem),
+            Arc::new(NoopVirtioInterrupt {}),
+            vec![q],
+            queue_evts,
+        )
+        .ok();
+
+    queue_evt.write(77).unwrap(); // Rings the doorbell, any byte will do.
+});
+
+fn read_u64<T: Read>(readable: &mut T) -> u64 {
+    let mut buf = [0u8; size_of::<u64>()];
+    readable.read_exact(&mut buf[..]).unwrap();
+    u64::from_le_bytes(buf)
+}
+
+fn memfd_create(name: &ffi::CStr, flags: u32) -> Result<RawFd, io::Error> {
+    let res = unsafe { libc::syscall(libc::SYS_memfd_create, name.as_ptr(), flags) };
+
+    if res < 0 {
+        Err(io::Error::last_os_error())
+    } else {
+        Ok(res as RawFd)
+    }
+}
+
+pub struct NoopVirtioInterrupt {}
+
+impl VirtioInterrupt for NoopVirtioInterrupt {
+    fn trigger(
+        &self,
+        _int_type: &VirtioInterruptType,
+        _queue: Option<&Queue>,
+    ) -> std::result::Result<(), std::io::Error> {
+        Ok(())
+    }
+}

fuzz/fuzz_targets/qcow.rs

@@ -0,0 +1,49 @@
+// Copyright 2018 The Chromium OS Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style license that can be
+// found in the LICENSE-BSD-3-Clause file.
+
+#![no_main]
+use libfuzzer_sys::fuzz_target;
+use qcow::{QcowFile, RawFile};
+use std::ffi;
+use std::fs::File;
+use std::io::{self, Cursor, Read, Seek, SeekFrom, Write};
+use std::mem::size_of;
+use std::os::unix::io::{FromRawFd, RawFd};
+
+// Take the first 64 bits of data as an address and the next 64 bits as data to
+// store there. The rest of the data is used as a qcow image.
+fuzz_target!(|bytes| {
+    if bytes.len() < 16 {
+        // Need an address and data, each are 8 bytes.
+        return;
+    }
+    let mut disk_image = Cursor::new(bytes);
+    let addr = read_u64(&mut disk_image);
+    let value = read_u64(&mut disk_image);
+    let shm = memfd_create(&ffi::CString::new("fuzz").unwrap(), 0).unwrap();
+    let mut disk_file: File = unsafe { File::from_raw_fd(shm) };
+    disk_file.write_all(&bytes[16..]).unwrap();
+    disk_file.seek(SeekFrom::Start(0)).unwrap();
+    if let Ok(mut qcow) = QcowFile::from(RawFile::new(disk_file, false)) {
+        if qcow.seek(SeekFrom::Start(addr)).is_ok() {
+            let _ = qcow.write_all(&value.to_le_bytes());
+        }
+    }
+});
+
+fn read_u64<T: Read>(readable: &mut T) -> u64 {
+    let mut buf = [0u8; size_of::<u64>()];
+    readable.read_exact(&mut buf[..]).unwrap();
+    u64::from_le_bytes(buf)
+}
+
+fn memfd_create(name: &ffi::CStr, flags: u32) -> Result<RawFd, io::Error> {
+    let res = unsafe { libc::syscall(libc::SYS_memfd_create, name.as_ptr(), flags) };
+
+    if res < 0 {
+        Err(io::Error::last_os_error())
+    } else {
+        Ok(res as RawFd)
+    }
+}

hypervisor/Cargo.toml

@@ -0,0 +1,25 @@
+[package]
+name = "hypervisor"
+version = "0.1.0"
+authors = ["Muminul Islam <muislam@microsoft.com>"]
+edition = "2018"
+
+[features]
+kvm = []
+
+[dependencies]
+anyhow = "1.0"
+thiserror = "1.0"
+libc = "0.2.74"
+log = "0.4.11"
+kvm-ioctls = { git = "https://github.com/cloud-hypervisor/kvm-ioctls", branch = "ch" }
+kvm-bindings = { git = "https://github.com/cloud-hypervisor/kvm-bindings", branch = "ch", features = ["with-serde", "fam-wrappers"] }
+serde = {version = ">=1.0.27", features = ["rc"] }
+serde_derive = ">=1.0.27"
+serde_json = ">=1.0.9"
+vm-memory = { version = "0.2.0", features = ["backend-mmap", "backend-atomic"] }
+vmm-sys-util = { version = ">=0.5.0", features = ["with-serde"] }
+
+[dependencies.linux-loader]
+git = "https://github.com/rust-vmm/linux-loader"
+features = ["elf", "bzimage"]

hypervisor/src/arch/mod.rs

@@ -0,0 +1,15 @@
+// Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style license that can be
+// found in the LICENSE-BSD-3-Clause file.
+//
+// Copyright © 2019 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause
+//
+// Copyright © 2020, Microsoft Corporation
+//
+
+#[cfg(target_arch = "x86_64")]
+pub mod x86;

hypervisor/src/arch/x86/mod.rs

@@ -0,0 +1,36 @@
+// Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style license that can be
+// found in the LICENSE-BSD-3-Clause file.
+//
+// Copyright © 2019 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause
+//
+// Copyright © 2020, Microsoft Corporation
+//
+
+#[allow(non_upper_case_globals)]
+#[allow(non_camel_case_types)]
+#[allow(non_snake_case)]
+#[allow(non_upper_case_globals)]
+#[allow(unused)]
+#[allow(
+    clippy::unreadable_literal,
+    clippy::redundant_static_lifetimes,
+    clippy::trivially_copy_pass_by_ref,
+    clippy::useless_transmute,
+    clippy::should_implement_trait,
+    clippy::transmute_ptr_to_ptr,
+    clippy::unreadable_literal,
+    clippy::redundant_static_lifetimes
+)]
+pub mod msr_index;
+
+// MTRR constants
+pub const MTRR_ENABLE: u64 = 0x800; // IA32_MTRR_DEF_TYPE MSR: E (MTRRs enabled) flag, bit 11
+pub const MTRR_MEM_TYPE_WB: u64 = 0x6;
+
+// IOAPIC pins
+pub const NUM_IOAPIC_PINS: usize = 24;

hypervisor/src/cpu.rs

@@ -0,0 +1,312 @@
+// Copyright © 2019 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause
+//
+// Copyright © 2020, Microsoft Corporation
+//
+// Copyright 2018-2019 CrowdStrike, Inc.
+//
+//
+
+#[cfg(target_arch = "aarch64")]
+use crate::aarch64::VcpuInit;
+use crate::{CpuState, MpState};
+
+#[cfg(target_arch = "x86_64")]
+use crate::x86_64::{
+    CpuId, ExtendedControlRegisters, FpuState, LapicState, MsrEntries, SpecialRegisters,
+    StandardRegisters, VcpuEvents, Xsave,
+};
+use thiserror::Error;
+
+#[derive(Error, Debug)]
+///
+/// Enum for CPU error
+pub enum HypervisorCpuError {
+    ///
+    /// Setting standard registers error
+    ///
+    #[error("Failed to set standard register: {0}")]
+    SetStandardRegs(#[source] anyhow::Error),
+    ///
+    /// Setting standard registers error
+    ///
+    #[error("Failed to get standard registers: {0}")]
+    GetStandardRegs(#[source] anyhow::Error),
+    ///
+    /// Setting special register error
+    ///
+    #[error("Failed to set special registers: {0}")]
+    SetSpecialRegs(#[source] anyhow::Error),
+    ///
+    /// Getting standard register error
+    ///
+    #[error("Failed to get special registers: {0}")]
+    GetSpecialRegs(#[source] anyhow::Error),
+    ///
+    /// Setting floating point registers error
+    ///
+    #[error("Failed to set special register: {0}")]
+    SetFloatingPointRegs(#[source] anyhow::Error),
+    ///
+    /// Getting floating point register error
+    ///
+    #[error("Failed to get special register: {0}")]
+    GetFloatingPointRegs(#[source] anyhow::Error),
+    ///
+    /// Setting Cpuid error
+    ///
+    #[error("Failed to set Cpuid: {0}")]
+    SetCpuid(#[source] anyhow::Error),
+    ///
+    /// Getting Cpuid error
+    ///
+    #[error("Failed to get Cpuid: {0}")]
+    GetCpuid(#[source] anyhow::Error),
+    ///
+    /// Setting lapic state error
+    ///
+    #[error("Failed to set Lapic state: {0}")]
+    SetLapicState(#[source] anyhow::Error),
+    ///
+    /// Getting Lapic state error
+    ///
+    #[error("Failed to get Lapic state: {0}")]
+    GetlapicState(#[source] anyhow::Error),
+    ///
+    /// Setting MSR entries error
+    ///
+    #[error("Failed to set Msr entries: {0}")]
+    SetMsrEntries(#[source] anyhow::Error),
+    ///
+    /// Getting Msr entries error
+    ///
+    #[error("Failed to get Msr entries: {0}")]
+    GetMsrEntries(#[source] anyhow::Error),
+    ///
+    /// Setting MSR entries error
+    ///
+    #[error("Failed to set MP state: {0}")]
+    SetMpState(#[source] anyhow::Error),
+    ///
+    /// Getting Msr entries error
+    ///
+    #[error("Failed to get MP state: {0}")]
+    GetMpState(#[source] anyhow::Error),
+    ///
+    /// Setting Saved Processor Extended States error
+    ///
+    #[error("Failed to set Saved Processor Extended States: {0}")]
+    SetXsaveState(#[source] anyhow::Error),
+    ///
+    /// Getting Saved Processor Extended States error
+    ///
+    #[error("Failed to get Saved Processor Extended States: {0}")]
+    GetXsaveState(#[source] anyhow::Error),
+    ///
+    /// Setting Extended Control Registers error
+    ///
+    #[error("Failed to set Extended Control Registers: {0}")]
+    SetXcsr(#[source] anyhow::Error),
+    ///
+    /// Getting Extended Control Registers error
+    ///
+    #[error("Failed to get Extended Control Registers: {0}")]
+    GetXcsr(#[source] anyhow::Error),
+    ///
+    /// Running Vcpu error
+    ///
+    #[error("Failed to run vcpu: {0}")]
+    RunVcpu(#[source] anyhow::Error),
+    ///
+    /// Getting Vcpu events error
+    ///
+    #[error("Failed to get Vcpu events: {0}")]
+    GetVcpuEvents(#[source] anyhow::Error),
+    ///
+    /// Setting Vcpu events error
+    ///
+    #[error("Failed to set Vcpu events: {0}")]
+    SetVcpuEvents(#[source] anyhow::Error),
+    ///
+    /// Vcpu Init error
+    ///
+    #[error("Failed to init vcpu: {0}")]
+    VcpuInit(#[source] anyhow::Error),
+    ///
+    /// Setting one reg error
+    ///
+    #[error("Failed to init vcpu: {0}")]
+    SetOneReg(#[source] anyhow::Error),
+    ///
+    /// Getting one reg error
+    ///
+    #[error("Failed to init vcpu: {0}")]
+    GetOneReg(#[source] anyhow::Error),
+    ///
+    /// Getting guest clock paused error
+    ///
+    #[error("Failed to notify guest its clock was paused: {0}")]
+    NotifyGuestClockPaused(#[source] anyhow::Error),
+}
+
+#[derive(Debug)]
+pub enum VmExit<'a> {
+    #[cfg(target_arch = "x86_64")]
+    IoOut(u16 /* port */, &'a [u8] /* data */),
+    #[cfg(target_arch = "x86_64")]
+    IoIn(u16 /* port */, &'a mut [u8] /* data */),
+    #[cfg(target_arch = "x86_64")]
+    IoapicEoi(u8 /* vector */),
+    MmioRead(u64 /* address */, &'a mut [u8]),
+    MmioWrite(u64 /* address */, &'a [u8]),
+    Ignore,
+    Reset,
+}
+
+///
+/// Result type for returning from a function
+///
+pub type Result<T> = anyhow::Result<T, HypervisorCpuError>;
+///
+/// Trait to represent a generic Vcpu
+///
+pub trait Vcpu: Send + Sync {
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Returns the vCPU general purpose registers.
+    ///
+    fn get_regs(&self) -> Result<StandardRegisters>;
+
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Sets the vCPU general purpose registers.
+    ///
+    fn set_regs(&self, regs: &StandardRegisters) -> Result<()>;
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Returns the vCPU special registers.
+    ///
+    fn get_sregs(&self) -> Result<SpecialRegisters>;
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Sets the vCPU special registers
+    ///
+    fn set_sregs(&self, sregs: &SpecialRegisters) -> Result<()>;
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Returns the floating point state (FPU) from the vCPU.
+    ///
+    fn get_fpu(&self) -> Result<FpuState>;
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Set the floating point state (FPU) of a vCPU
+    ///
+    fn set_fpu(&self, fpu: &FpuState) -> Result<()>;
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// X86 specific call to setup the CPUID registers.
+    ///
+    fn set_cpuid2(&self, cpuid: &CpuId) -> Result<()>;
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// X86 specific call to retrieve the CPUID registers.
+    ///
+    fn get_cpuid2(&self, num_entries: usize) -> Result<CpuId>;
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Returns the state of the LAPIC (Local Advanced Programmable Interrupt Controller).
+    ///
+    fn get_lapic(&self) -> Result<LapicState>;
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Sets the state of the LAPIC (Local Advanced Programmable Interrupt Controller).
+    ///
+    fn set_lapic(&self, lapic: &LapicState) -> Result<()>;
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Returns the model-specific registers (MSR) for this vCPU.
+    ///
+    fn get_msrs(&self, msrs: &mut MsrEntries) -> Result<usize>;
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Setup the model-specific registers (MSR) for this vCPU.
+    ///
+    fn set_msrs(&self, msrs: &MsrEntries) -> Result<usize>;
+    ///
+    /// Returns the vcpu's current "multiprocessing state".
+    ///
+    fn get_mp_state(&self) -> Result<MpState>;
+    ///
+    /// Sets the vcpu's current "multiprocessing state".
+    ///
+    fn set_mp_state(&self, mp_state: MpState) -> Result<()>;
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// X86 specific call that returns the vcpu's current "xsave struct".
+    ///
+    fn get_xsave(&self) -> Result<Xsave>;
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// X86 specific call that sets the vcpu's current "xsave struct".
+    ///
+    fn set_xsave(&self, xsave: &Xsave) -> Result<()>;
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// X86 specific call that returns the vcpu's current "xcrs".
+    ///
+    fn get_xcrs(&self) -> Result<ExtendedControlRegisters>;
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// X86 specific call that sets the vcpu's current "xcrs".
+    ///
+    fn set_xcrs(&self, xcrs: &ExtendedControlRegisters) -> Result<()>;
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Returns currently pending exceptions, interrupts, and NMIs as well as related
+    /// states of the vcpu.
+    ///
+    fn get_vcpu_events(&self) -> Result<VcpuEvents>;
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Sets pending exceptions, interrupts, and NMIs as well as related states
+    /// of the vcpu.
+    ///
+    fn set_vcpu_events(&self, events: &VcpuEvents) -> Result<()>;
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Let the guest know that it has been paused, which prevents from
+    /// potential soft lockups when being resumed.
+    ///
+    fn notify_guest_clock_paused(&self) -> Result<()>;
+    ///
+    /// Sets the type of CPU to be exposed to the guest and optional features.
+    ///
+    #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+    fn vcpu_init(&self, kvi: &VcpuInit) -> Result<()>;
+    ///
+    /// Sets the value of one register for this vCPU.
+    ///
+    #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+    fn set_one_reg(&self, reg_id: u64, data: u64) -> Result<()>;
+    ///
+    /// Sets the value of one register for this vCPU.
+    ///
+    #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+    fn get_one_reg(&self, reg_id: u64) -> Result<u64>;
+    ///
+    /// Retrieve the vCPU state.
+    /// This function is necessary to snapshot the VM
+    ///
+    fn state(&self) -> Result<CpuState>;
+    ///
+    /// Set the vCPU state.
+    /// This function is required when restoring the VM
+    ///
+    fn set_state(&self, state: &CpuState) -> Result<()>;
+
+    ///
+    /// Triggers the running of the current virtual CPU returning an exit reason.
+    ///
+    fn run(&self) -> std::result::Result<VmExit, HypervisorCpuError>;
+}

hypervisor/src/device.rs

@@ -0,0 +1,40 @@
+// Copyright © 2019 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause
+//
+// Copyright © 2020, Microsoft Corporation
+//
+// Copyright 2018-2019 CrowdStrike, Inc.
+//
+// Copyright 2020, ARM Limited
+//
+
+use crate::DeviceAttr;
+use std::os::unix::io::AsRawFd;
+use thiserror::Error;
+
+#[derive(Error, Debug)]
+///
+/// Enum for device error
+pub enum HypervisorDeviceError {
+    ///
+    /// Set device attribute error
+    ///
+    #[error("Failed to set device attribute: {0}")]
+    SetDeviceAttribute(#[source] anyhow::Error),
+}
+
+///
+/// Result type for returning from a function
+///
+pub type Result<T> = std::result::Result<T, HypervisorDeviceError>;
+
+///
+/// Trait to represent a device
+///
+/// This crate provides a hypervisor-agnostic interfaces for device
+///
+pub trait Device: Send + Sync + AsRawFd {
+    /// Set device attribute.
+    fn set_device_attr(&self, attr: &DeviceAttr) -> Result<()>;
+}

hypervisor/src/hypervisor.rs

@@ -0,0 +1,116 @@
+// Copyright © 2019 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause
+//
+// Copyright © 2020, Microsoft Corporation
+//
+// Copyright 2018-2019 CrowdStrike, Inc.
+//
+//
+use crate::vm::Vm;
+#[cfg(target_arch = "x86_64")]
+use crate::x86_64::{CpuId, MsrList};
+#[cfg(target_arch = "x86_64")]
+use kvm_ioctls::Cap;
+use std::sync::Arc;
+
+use thiserror::Error;
+
+#[derive(Error, Debug)]
+///
+///
+pub enum HypervisorError {
+    ///
+    /// Vm creation failure
+    ///
+    #[error("Failed to create Vm: {0}")]
+    VmCreate(#[source] anyhow::Error),
+    ///
+    /// Vm setup failure
+    ///
+    #[error("Failed to setup Vm: {0}")]
+    VmSetup(#[source] anyhow::Error),
+    ///
+    /// API version error
+    ///
+    #[error("Failed to get API Version: {0}")]
+    GetApiVersion(#[source] anyhow::Error),
+    ///
+    /// Vcpu mmap error
+    ///
+    #[error("Failed to get Vcpu Mmap: {0}")]
+    GetVcpuMmap(#[source] anyhow::Error),
+    ///
+    /// Max Vcpu error
+    ///
+    #[error("Failed to get number of max vcpus: {0}")]
+    GetMaxVcpu(#[source] anyhow::Error),
+    ///
+    /// Recommended Vcpu error
+    ///
+    #[error("Failed to get number of max vcpus: {0}")]
+    GetNrVcpus(#[source] anyhow::Error),
+    ///
+    /// CpuId error
+    ///
+    #[error("Failed to get number of max vcpus: {0}")]
+    GetCpuId(#[source] anyhow::Error),
+    ///
+    /// Failed to retrieve list of MSRs.
+    ///
+    #[error("Failed to get the list of supported MSRs: {0}")]
+    GetMsrList(#[source] anyhow::Error),
+}
+
+///
+/// Result type for returning from a function
+///
+pub type Result<T> = std::result::Result<T, HypervisorError>;
+
+///
+/// Trait to represent a Hypervisor
+///
+/// This crate provides a hypervisor-agnostic interfaces
+///
+pub trait Hypervisor: Send + Sync {
+    ///
+    /// Create a Vm using the underlying hypervisor
+    /// Return a hypervisor-agnostic Vm trait object
+    ///
+    fn create_vm(&self) -> Result<Arc<dyn Vm>>;
+    ///
+    /// Get the API version of the hypervisor
+    ///
+    fn get_api_version(&self) -> i32;
+    ///
+    /// Returns the size of the memory mapping required to use the vcpu's structures
+    ///
+    fn get_vcpu_mmap_size(&self) -> Result<usize>;
+    ///
+    /// Gets the recommended maximum number of VCPUs per VM.
+    ///
+    fn get_max_vcpus(&self) -> Result<usize>;
+    ///
+    /// Gets the recommended number of VCPUs per VM.
+    ///
+    fn get_nr_vcpus(&self) -> Result<usize>;
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Checks if a particular `Cap` is available.
+    ///
+    fn check_capability(&self, c: Cap) -> bool;
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Get the supported CpuID
+    ///
+    fn get_cpuid(&self) -> Result<CpuId>;
+    ///
+    /// Check particular extensions if any
+    ///
+    fn check_required_extensions(&self) -> Result<()>;
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Retrieve the list of MSRs supported by the hypervisor.
+    ///
+    fn get_msr_list(&self) -> Result<MsrList>;
+}

hypervisor/src/kvm/aarch64/mod.rs

@@ -0,0 +1,27 @@
+// Copyright © 2019 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause
+//
+// Copyright © 2020, Microsoft Corporation
+//
+// Copyright 2018-2019 CrowdStrike, Inc.
+//
+//
+
+///
+/// Export generically-named wrappers of kvm-bindings for Unix-based platforms
+///
+use crate::kvm::{KvmError, KvmResult};
+pub use kvm_bindings::kvm_vcpu_init as VcpuInit;
+use serde_derive::{Deserialize, Serialize};
+pub use {kvm_ioctls::Cap, kvm_ioctls::Kvm};
+
+pub fn check_required_kvm_extensions(kvm: &Kvm) -> KvmResult<()> {
+    if !kvm.check_extension(Cap::SignalMsi) {
+        return Err(KvmError::CapabilityMissing(Cap::SignalMsi));
+    }
+    Ok(())
+}
+
+#[derive(Clone, Serialize, Deserialize)]
+pub struct VcpuKvmState {}

hypervisor/src/kvm/mod.rs

@@ -0,0 +1,953 @@
+// Copyright © 2019 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause
+//
+// Copyright © 2020, Microsoft Corporation
+//
+// Copyright 2018-2019 CrowdStrike, Inc.
+//
+//
+
+use kvm_ioctls::{NoDatamatch, VcpuFd, VmFd};
+use std::os::unix::io::{AsRawFd, RawFd};
+use std::result;
+use std::sync::Arc;
+#[cfg(target_arch = "x86_64")]
+use vm_memory::Address;
+use vmm_sys_util::eventfd::EventFd;
+
+#[cfg(target_arch = "aarch64")]
+pub use crate::aarch64::{check_required_kvm_extensions, VcpuInit, VcpuKvmState as CpuState};
+use crate::cpu;
+use crate::device;
+use crate::hypervisor;
+use crate::vm;
+// x86_64 dependencies
+#[cfg(target_arch = "x86_64")]
+pub mod x86_64;
+
+#[cfg(target_arch = "x86_64")]
+use x86_64::{
+    check_required_kvm_extensions, FpuState, SpecialRegisters, StandardRegisters, KVM_TSS_ADDRESS,
+};
+
+#[cfg(target_arch = "x86_64")]
+pub use x86_64::{
+    CpuId, CpuIdEntry, ExtendedControlRegisters, LapicState, MsrEntries, VcpuKvmState as CpuState,
+    Xsave, CPUID_FLAG_VALID_INDEX,
+};
+
+#[cfg(target_arch = "x86_64")]
+use kvm_bindings::{kvm_enable_cap, MsrList, KVM_CAP_SPLIT_IRQCHIP};
+
+#[cfg(target_arch = "x86_64")]
+use crate::arch::x86::NUM_IOAPIC_PINS;
+
+// aarch64 dependencies
+#[cfg(target_arch = "aarch64")]
+pub mod aarch64;
+
+pub use kvm_bindings;
+pub use kvm_bindings::{
+    kvm_create_device, kvm_device_type_KVM_DEV_TYPE_VFIO, kvm_irq_routing, kvm_irq_routing_entry,
+    kvm_userspace_memory_region, KVM_IRQ_ROUTING_MSI, KVM_MEM_READONLY, KVM_MSI_VALID_DEVID,
+};
+pub use kvm_ioctls;
+pub use kvm_ioctls::{Cap, Kvm};
+
+///
+/// Export generically-named wrappers of kvm-bindings for Unix-based platforms
+///
+pub use {
+    kvm_bindings::kvm_clock_data as ClockData, kvm_bindings::kvm_create_device as CreateDevice,
+    kvm_bindings::kvm_device_attr as DeviceAttr,
+    kvm_bindings::kvm_irq_routing_entry as IrqRoutingEntry, kvm_bindings::kvm_mp_state as MpState,
+    kvm_bindings::kvm_userspace_memory_region as MemoryRegion,
+    kvm_bindings::kvm_vcpu_events as VcpuEvents, kvm_ioctls::DeviceFd, kvm_ioctls::IoEventAddress,
+    kvm_ioctls::VcpuExit,
+};
+
+/// Wrapper over KVM VM ioctls.
+pub struct KvmVm {
+    fd: Arc<VmFd>,
+    #[cfg(target_arch = "x86_64")]
+    msrs: MsrEntries,
+}
+
+// Returns a `Vec<T>` with a size in bytes at least as large as `size_in_bytes`.
+fn vec_with_size_in_bytes<T: Default>(size_in_bytes: usize) -> Vec<T> {
+    let rounded_size = (size_in_bytes + size_of::<T>() - 1) / size_of::<T>();
+    let mut v = Vec::with_capacity(rounded_size);
+    v.resize_with(rounded_size, T::default);
+    v
+}
+
+// The kvm API has many structs that resemble the following `Foo` structure:
+//
+// ```
+// #[repr(C)]
+// struct Foo {
+//    some_data: u32
+//    entries: __IncompleteArrayField<__u32>,
+// }
+// ```
+//
+// In order to allocate such a structure, `size_of::<Foo>()` would be too small because it would not
+// include any space for `entries`. To make the allocation large enough while still being aligned
+// for `Foo`, a `Vec<Foo>` is created. Only the first element of `Vec<Foo>` would actually be used
+// as a `Foo`. The remaining memory in the `Vec<Foo>` is for `entries`, which must be contiguous
+// with `Foo`. This function is used to make the `Vec<Foo>` with enough space for `count` entries.
+use std::mem::size_of;
+fn vec_with_array_field<T: Default, F>(count: usize) -> Vec<T> {
+    let element_space = count * size_of::<F>();
+    let vec_size_bytes = size_of::<T>() + element_space;
+    vec_with_size_in_bytes(vec_size_bytes)
+}
+
+///
+/// Implementation of Vm trait for KVM
+/// Example:
+/// #[cfg(feature = "kvm")]
+/// extern crate hypervisor
+/// let kvm = hypervisor::kvm::KvmHypervisor::new().unwrap();
+/// let hypervisor: Arc<dyn hypervisor::Hypervisor> = Arc::new(kvm);
+/// let vm = hypervisor.create_vm().expect("new VM fd creation failed");
+/// vm.set/get().unwrap()
+///
+impl vm::Vm for KvmVm {
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Sets the address of the three-page region in the VM's address space.
+    ///
+    fn set_tss_address(&self, offset: usize) -> vm::Result<()> {
+        self.fd
+            .set_tss_address(offset)
+            .map_err(|e| vm::HypervisorVmError::SetTssAddress(e.into()))
+    }
+    ///
+    /// Creates an in-kernel interrupt controller.
+    ///
+    fn create_irq_chip(&self) -> vm::Result<()> {
+        self.fd
+            .create_irq_chip()
+            .map_err(|e| vm::HypervisorVmError::CreateIrq(e.into()))
+    }
+    ///
+    /// Registers an event that will, when signaled, trigger the `gsi` IRQ.
+    ///
+    fn register_irqfd(&self, fd: &EventFd, gsi: u32) -> vm::Result<()> {
+        self.fd
+            .register_irqfd(fd, gsi)
+            .map_err(|e| vm::HypervisorVmError::RegisterIrqFd(e.into()))
+    }
+    ///
+    /// Unregisters an event that will, when signaled, trigger the `gsi` IRQ.
+    ///
+    fn unregister_irqfd(&self, fd: &EventFd, gsi: u32) -> vm::Result<()> {
+        self.fd
+            .unregister_irqfd(fd, gsi)
+            .map_err(|e| vm::HypervisorVmError::UnregisterIrqFd(e.into()))
+    }
+    ///
+    /// Creates a VcpuFd object from a vcpu RawFd.
+    ///
+    fn create_vcpu(&self, id: u8) -> vm::Result<Arc<dyn cpu::Vcpu>> {
+        let vc = self
+            .fd
+            .create_vcpu(id)
+            .map_err(|e| vm::HypervisorVmError::CreateVcpu(e.into()))?;
+        let vcpu = KvmVcpu {
+            fd: vc,
+            #[cfg(target_arch = "x86_64")]
+            msrs: self.msrs.clone(),
+        };
+        Ok(Arc::new(vcpu))
+    }
+    ///
+    /// Registers an event to be signaled whenever a certain address is written to.
+    ///
+    fn register_ioevent(
+        &self,
+        fd: &EventFd,
+        addr: &IoEventAddress,
+        datamatch: Option<vm::DataMatch>,
+    ) -> vm::Result<()> {
+        if let Some(dm) = datamatch {
+            match dm {
+                vm::DataMatch::DataMatch32(kvm_dm32) => self
+                    .fd
+                    .register_ioevent(fd, addr, kvm_dm32)
+                    .map_err(|e| vm::HypervisorVmError::RegisterIoEvent(e.into())),
+                vm::DataMatch::DataMatch64(kvm_dm64) => self
+                    .fd
+                    .register_ioevent(fd, addr, kvm_dm64)
+                    .map_err(|e| vm::HypervisorVmError::RegisterIoEvent(e.into())),
+            }
+        } else {
+            self.fd
+                .register_ioevent(fd, addr, NoDatamatch)
+                .map_err(|e| vm::HypervisorVmError::RegisterIoEvent(e.into()))
+        }
+    }
+    ///
+    /// Unregisters an event from a certain address it has been previously registered to.
+    ///
+    fn unregister_ioevent(&self, fd: &EventFd, addr: &IoEventAddress) -> vm::Result<()> {
+        self.fd
+            .unregister_ioevent(fd, addr, NoDatamatch)
+            .map_err(|e| vm::HypervisorVmError::UnregisterIoEvent(e.into()))
+    }
+    ///
+    /// Sets the GSI routing table entries, overwriting any previously set
+    /// entries, as per the `KVM_SET_GSI_ROUTING` ioctl.
+    ///
+    fn set_gsi_routing(&self, entries: &[IrqRoutingEntry]) -> vm::Result<()> {
+        let mut irq_routing =
+            vec_with_array_field::<kvm_irq_routing, kvm_irq_routing_entry>(entries.len());
+        irq_routing[0].nr = entries.len() as u32;
+        irq_routing[0].flags = 0;
+
+        unsafe {
+            let entries_slice: &mut [kvm_irq_routing_entry] =
+                irq_routing[0].entries.as_mut_slice(entries.len());
+            entries_slice.copy_from_slice(&entries);
+        }
+
+        self.fd
+            .set_gsi_routing(&irq_routing[0])
+            .map_err(|e| vm::HypervisorVmError::SetGsiRouting(e.into()))
+    }
+    ///
+    /// Creates a memory region structure that can be used with set_user_memory_region
+    ///
+    fn make_user_memory_region(
+        &self,
+        slot: u32,
+        guest_phys_addr: u64,
+        memory_size: u64,
+        userspace_addr: u64,
+        readonly: bool,
+    ) -> MemoryRegion {
+        MemoryRegion {
+            slot,
+            guest_phys_addr,
+            memory_size,
+            userspace_addr,
+            flags: if readonly { KVM_MEM_READONLY } else { 0 },
+        }
+    }
+    ///
+    /// Creates/modifies a guest physical memory slot.
+    ///
+    fn set_user_memory_region(&self, user_memory_region: MemoryRegion) -> vm::Result<()> {
+        // Safe because guest regions are guaranteed not to overlap.
+        unsafe {
+            self.fd
+                .set_user_memory_region(user_memory_region)
+                .map_err(|e| vm::HypervisorVmError::SetUserMemory(e.into()))
+        }
+    }
+    ///
+    /// Creates an emulated device in the kernel.
+    ///
+    /// See the documentation for `KVM_CREATE_DEVICE`.
+    fn create_device(&self, device: &mut CreateDevice) -> vm::Result<Arc<dyn device::Device>> {
+        let fd = self
+            .fd
+            .create_device(device)
+            .map_err(|e| vm::HypervisorVmError::CreateDevice(e.into()))?;
+        let device = KvmDevice { fd };
+        Ok(Arc::new(device))
+    }
+    ///
+    /// Returns the preferred CPU target type which can be emulated by KVM on underlying host.
+    ///
+    #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+    fn get_preferred_target(&self, kvi: &mut VcpuInit) -> vm::Result<()> {
+        self.fd
+            .get_preferred_target(kvi)
+            .map_err(|e| vm::HypervisorVmError::GetPreferredTarget(e.into()))
+    }
+    #[cfg(target_arch = "x86_64")]
+    fn enable_split_irq(&self) -> vm::Result<()> {
+        // Set TSS
+        self.fd
+            .set_tss_address(KVM_TSS_ADDRESS.raw_value() as usize)
+            .map_err(|e| vm::HypervisorVmError::EnableSplitIrq(e.into()))?;
+        // Create split irqchip
+        // Only the local APIC is emulated in kernel, both PICs and IOAPIC
+        // are not.
+        let mut cap: kvm_enable_cap = Default::default();
+        cap.cap = KVM_CAP_SPLIT_IRQCHIP;
+        cap.args[0] = NUM_IOAPIC_PINS as u64;
+        self.fd
+            .enable_cap(&cap)
+            .map_err(|e| vm::HypervisorVmError::EnableSplitIrq(e.into()))?;
+        Ok(())
+    }
+    /// Retrieve guest clock.
+    #[cfg(target_arch = "x86_64")]
+    fn get_clock(&self) -> vm::Result<ClockData> {
+        self.fd
+            .get_clock()
+            .map_err(|e| vm::HypervisorVmError::GetClock(e.into()))
+    }
+    /// Set guest clock.
+    #[cfg(target_arch = "x86_64")]
+    fn set_clock(&self, data: &ClockData) -> vm::Result<()> {
+        self.fd
+            .set_clock(data)
+            .map_err(|e| vm::HypervisorVmError::SetClock(e.into()))
+    }
+    /// Checks if a particular `Cap` is available.
+    fn check_extension(&self, c: Cap) -> bool {
+        self.fd.check_extension(c)
+    }
+    /// Create a device that is used for passthrough
+    fn create_passthrough_device(&self) -> vm::Result<Arc<dyn device::Device>> {
+        let mut vfio_dev = kvm_create_device {
+            type_: kvm_device_type_KVM_DEV_TYPE_VFIO,
+            fd: 0,
+            flags: 0,
+        };
+
+        self.create_device(&mut vfio_dev)
+            .map_err(|e| vm::HypervisorVmError::CreatePassthroughDevice(e.into()))
+    }
+}
+/// Wrapper over KVM system ioctls.
+pub struct KvmHypervisor {
+    kvm: Kvm,
+}
+/// Enum for KVM related error
+#[derive(Debug)]
+pub enum KvmError {
+    CapabilityMissing(Cap),
+}
+pub type KvmResult<T> = result::Result<T, KvmError>;
+impl KvmHypervisor {
+    /// Create a hypervisor based on Kvm
+    pub fn new() -> hypervisor::Result<KvmHypervisor> {
+        let kvm_obj = Kvm::new().map_err(|e| hypervisor::HypervisorError::VmCreate(e.into()))?;
+        Ok(KvmHypervisor { kvm: kvm_obj })
+    }
+}
+/// Implementation of Hypervisor trait for KVM
+/// Example:
+/// #[cfg(feature = "kvm")]
+/// extern crate hypervisor
+/// let kvm = hypervisor::kvm::KvmHypervisor::new().unwrap();
+/// let hypervisor: Arc<dyn hypervisor::Hypervisor> = Arc::new(kvm);
+/// let vm = hypervisor.create_vm().expect("new VM fd creation failed");
+///
+impl hypervisor::Hypervisor for KvmHypervisor {
+    /// Create a KVM vm object and return the object as Vm trait object
+    /// Example
+    /// # extern crate hypervisor;
+    /// # use hypervisor::KvmHypervisor;
+    /// use hypervisor::KvmVm;
+    /// let hypervisor = KvmHypervisor::new().unwrap();
+    /// let vm = hypervisor.create_vm().unwrap()
+    ///
+    fn create_vm(&self) -> hypervisor::Result<Arc<dyn vm::Vm>> {
+        let fd: VmFd;
+        loop {
+            match self.kvm.create_vm() {
+                Ok(res) => fd = res,
+                Err(e) => {
+                    if e.errno() == libc::EINTR {
+                        // If the error returned is EINTR, which means the
+                        // ioctl has been interrupted, we have to retry as
+                        // this can't be considered as a regular error.
+                        continue;
+                    } else {
+                        return Err(hypervisor::HypervisorError::VmCreate(e.into()));
+                    }
+                }
+            }
+            break;
+        }
+
+        let vm_fd = Arc::new(fd);
+
+        #[cfg(target_arch = "x86_64")]
+        {
+            let msr_list = self.get_msr_list()?;
+            let num_msrs = msr_list.as_fam_struct_ref().nmsrs as usize;
+            let mut msrs = MsrEntries::new(num_msrs);
+            let indices = msr_list.as_slice();
+            let msr_entries = msrs.as_mut_slice();
+            for (pos, index) in indices.iter().enumerate() {
+                msr_entries[pos].index = *index;
+            }
+
+            Ok(Arc::new(KvmVm { fd: vm_fd, msrs }))
+        }
+
+        #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+        {
+            Ok(Arc::new(KvmVm { fd: vm_fd }))
+        }
+    }
+
+    fn check_required_extensions(&self) -> hypervisor::Result<()> {
+        check_required_kvm_extensions(&self.kvm).expect("Missing KVM capabilities");
+        Ok(())
+    }
+
+    ///
+    /// Returns the KVM API version.
+    ///
+    fn get_api_version(&self) -> i32 {
+        self.kvm.get_api_version()
+    }
+    ///
+    ///  Returns the size of the memory mapping required to use the vcpu's `kvm_run` structure.
+    ///
+    fn get_vcpu_mmap_size(&self) -> hypervisor::Result<usize> {
+        self.kvm
+            .get_vcpu_mmap_size()
+            .map_err(|e| hypervisor::HypervisorError::GetVcpuMmap(e.into()))
+    }
+    ///
+    /// Gets the recommended maximum number of VCPUs per VM.
+    ///
+    fn get_max_vcpus(&self) -> hypervisor::Result<usize> {
+        Ok(self.kvm.get_max_vcpus())
+    }
+    ///
+    /// Gets the recommended number of VCPUs per VM.
+    ///
+    fn get_nr_vcpus(&self) -> hypervisor::Result<usize> {
+        Ok(self.kvm.get_nr_vcpus())
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Checks if a particular `Cap` is available.
+    ///
+    fn check_capability(&self, c: Cap) -> bool {
+        self.kvm.check_extension(c)
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// X86 specific call to get the system supported CPUID values.
+    ///
+    fn get_cpuid(&self) -> hypervisor::Result<CpuId> {
+        self.kvm
+            .get_supported_cpuid(kvm_bindings::KVM_MAX_CPUID_ENTRIES)
+            .map_err(|e| hypervisor::HypervisorError::GetCpuId(e.into()))
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Retrieve the list of MSRs supported by KVM.
+    ///
+    fn get_msr_list(&self) -> hypervisor::Result<MsrList> {
+        self.kvm
+            .get_msr_index_list()
+            .map_err(|e| hypervisor::HypervisorError::GetMsrList(e.into()))
+    }
+}
+/// Vcpu struct for KVM
+pub struct KvmVcpu {
+    fd: VcpuFd,
+    #[cfg(target_arch = "x86_64")]
+    msrs: MsrEntries,
+}
+/// Implementation of Vcpu trait for KVM
+/// Example:
+/// #[cfg(feature = "kvm")]
+/// extern crate hypervisor
+/// let kvm = hypervisor::kvm::KvmHypervisor::new().unwrap();
+/// let hypervisor: Arc<dyn hypervisor::Hypervisor> = Arc::new(kvm);
+/// let vm = hypervisor.create_vm().expect("new VM fd creation failed");
+/// let vcpu = vm.create_vcpu(0).unwrap();
+/// vcpu.get/set().unwrap()
+///
+impl cpu::Vcpu for KvmVcpu {
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Returns the vCPU general purpose registers.
+    ///
+    fn get_regs(&self) -> cpu::Result<StandardRegisters> {
+        self.fd
+            .get_regs()
+            .map_err(|e| cpu::HypervisorCpuError::GetStandardRegs(e.into()))
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Sets the vCPU general purpose registers using the `KVM_SET_REGS` ioctl.
+    ///
+    fn set_regs(&self, regs: &StandardRegisters) -> cpu::Result<()> {
+        self.fd
+            .set_regs(regs)
+            .map_err(|e| cpu::HypervisorCpuError::SetStandardRegs(e.into()))
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Returns the vCPU special registers.
+    ///
+    fn get_sregs(&self) -> cpu::Result<SpecialRegisters> {
+        self.fd
+            .get_sregs()
+            .map_err(|e| cpu::HypervisorCpuError::GetSpecialRegs(e.into()))
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Sets the vCPU special registers using the `KVM_SET_SREGS` ioctl.
+    ///
+    fn set_sregs(&self, sregs: &SpecialRegisters) -> cpu::Result<()> {
+        self.fd
+            .set_sregs(sregs)
+            .map_err(|e| cpu::HypervisorCpuError::SetSpecialRegs(e.into()))
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Returns the floating point state (FPU) from the vCPU.
+    ///
+    fn get_fpu(&self) -> cpu::Result<FpuState> {
+        self.fd
+            .get_fpu()
+            .map_err(|e| cpu::HypervisorCpuError::GetFloatingPointRegs(e.into()))
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Set the floating point state (FPU) of a vCPU using the `KVM_SET_FPU` ioct.
+    ///
+    fn set_fpu(&self, fpu: &FpuState) -> cpu::Result<()> {
+        self.fd
+            .set_fpu(fpu)
+            .map_err(|e| cpu::HypervisorCpuError::SetFloatingPointRegs(e.into()))
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// X86 specific call to setup the CPUID registers.
+    ///
+    fn set_cpuid2(&self, cpuid: &CpuId) -> cpu::Result<()> {
+        self.fd
+            .set_cpuid2(cpuid)
+            .map_err(|e| cpu::HypervisorCpuError::SetCpuid(e.into()))
+    }
+    ///
+    /// X86 specific call to retrieve the CPUID registers.
+    ///
+    #[cfg(target_arch = "x86_64")]
+    fn get_cpuid2(&self, num_entries: usize) -> cpu::Result<CpuId> {
+        self.fd
+            .get_cpuid2(num_entries)
+            .map_err(|e| cpu::HypervisorCpuError::GetCpuid(e.into()))
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Returns the state of the LAPIC (Local Advanced Programmable Interrupt Controller).
+    ///
+    fn get_lapic(&self) -> cpu::Result<LapicState> {
+        self.fd
+            .get_lapic()
+            .map_err(|e| cpu::HypervisorCpuError::GetlapicState(e.into()))
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Sets the state of the LAPIC (Local Advanced Programmable Interrupt Controller).
+    ///
+    fn set_lapic(&self, klapic: &LapicState) -> cpu::Result<()> {
+        self.fd
+            .set_lapic(klapic)
+            .map_err(|e| cpu::HypervisorCpuError::SetLapicState(e.into()))
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Returns the model-specific registers (MSR) for this vCPU.
+    ///
+    fn get_msrs(&self, msrs: &mut MsrEntries) -> cpu::Result<usize> {
+        self.fd
+            .get_msrs(msrs)
+            .map_err(|e| cpu::HypervisorCpuError::GetMsrEntries(e.into()))
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Setup the model-specific registers (MSR) for this vCPU.
+    /// Returns the number of MSR entries actually written.
+    ///
+    fn set_msrs(&self, msrs: &MsrEntries) -> cpu::Result<usize> {
+        self.fd
+            .set_msrs(msrs)
+            .map_err(|e| cpu::HypervisorCpuError::SetMsrEntries(e.into()))
+    }
+    ///
+    /// Returns the vcpu's current "multiprocessing state".
+    ///
+    fn get_mp_state(&self) -> cpu::Result<MpState> {
+        self.fd
+            .get_mp_state()
+            .map_err(|e| cpu::HypervisorCpuError::GetMpState(e.into()))
+    }
+    ///
+    /// Sets the vcpu's current "multiprocessing state".
+    ///
+    fn set_mp_state(&self, mp_state: MpState) -> cpu::Result<()> {
+        self.fd
+            .set_mp_state(mp_state)
+            .map_err(|e| cpu::HypervisorCpuError::SetMpState(e.into()))
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// X86 specific call that returns the vcpu's current "xsave struct".
+    ///
+    fn get_xsave(&self) -> cpu::Result<Xsave> {
+        self.fd
+            .get_xsave()
+            .map_err(|e| cpu::HypervisorCpuError::GetXsaveState(e.into()))
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// X86 specific call that sets the vcpu's current "xsave struct".
+    ///
+    fn set_xsave(&self, xsave: &Xsave) -> cpu::Result<()> {
+        self.fd
+            .set_xsave(xsave)
+            .map_err(|e| cpu::HypervisorCpuError::SetXsaveState(e.into()))
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// X86 specific call that returns the vcpu's current "xcrs".
+    ///
+    fn get_xcrs(&self) -> cpu::Result<ExtendedControlRegisters> {
+        self.fd
+            .get_xcrs()
+            .map_err(|e| cpu::HypervisorCpuError::GetXcsr(e.into()))
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// X86 specific call that sets the vcpu's current "xcrs".
+    ///
+    fn set_xcrs(&self, xcrs: &ExtendedControlRegisters) -> cpu::Result<()> {
+        self.fd
+            .set_xcrs(&xcrs)
+            .map_err(|e| cpu::HypervisorCpuError::SetXcsr(e.into()))
+    }
+    ///
+    /// Triggers the running of the current virtual CPU returning an exit reason.
+    ///
+    fn run(&self) -> std::result::Result<cpu::VmExit, cpu::HypervisorCpuError> {
+        match self.fd.run() {
+            Ok(run) => match run {
+                #[cfg(target_arch = "x86_64")]
+                VcpuExit::IoIn(addr, data) => Ok(cpu::VmExit::IoIn(addr, data)),
+                #[cfg(target_arch = "x86_64")]
+                VcpuExit::IoOut(addr, data) => Ok(cpu::VmExit::IoOut(addr, data)),
+                #[cfg(target_arch = "x86_64")]
+                VcpuExit::IoapicEoi(vector) => Ok(cpu::VmExit::IoapicEoi(vector)),
+                #[cfg(target_arch = "x86_64")]
+                VcpuExit::Shutdown | VcpuExit::Hlt => Ok(cpu::VmExit::Reset),
+
+                #[cfg(target_arch = "aarch64")]
+                VcpuExit::SystemEvent(event_type, flags) => {
+                    use kvm_bindings::KVM_SYSTEM_EVENT_SHUTDOWN;
+                    // On Aarch64, when the VM is shutdown, run() returns
+                    // VcpuExit::SystemEvent with reason KVM_SYSTEM_EVENT_SHUTDOWN
+                    if event_type == KVM_SYSTEM_EVENT_SHUTDOWN {
+                        Ok(cpu::VmExit::Reset)
+                    } else {
+                        Err(cpu::HypervisorCpuError::RunVcpu(anyhow!(
+                            "Unexpected system event with type 0x{:x}, flags 0x{:x}",
+                            event_type,
+                            flags
+                        )))
+                    }
+                }
+
+                VcpuExit::MmioRead(addr, data) => Ok(cpu::VmExit::MmioRead(addr, data)),
+                VcpuExit::MmioWrite(addr, data) => Ok(cpu::VmExit::MmioWrite(addr, data)),
+
+                r => Err(cpu::HypervisorCpuError::RunVcpu(anyhow!(
+                    "Unexpected exit reason on vcpu run: {:?}",
+                    r
+                ))),
+            },
+
+            Err(ref e) => match e.errno() {
+                libc::EAGAIN | libc::EINTR => Ok(cpu::VmExit::Ignore),
+                _ => Err(cpu::HypervisorCpuError::RunVcpu(anyhow!(
+                    "VCPU error {:?}",
+                    e
+                ))),
+            },
+        }
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Returns currently pending exceptions, interrupts, and NMIs as well as related
+    /// states of the vcpu.
+    ///
+    fn get_vcpu_events(&self) -> cpu::Result<VcpuEvents> {
+        self.fd
+            .get_vcpu_events()
+            .map_err(|e| cpu::HypervisorCpuError::GetVcpuEvents(e.into()))
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Sets pending exceptions, interrupts, and NMIs as well as related states
+    /// of the vcpu.
+    ///
+    fn set_vcpu_events(&self, events: &VcpuEvents) -> cpu::Result<()> {
+        self.fd
+            .set_vcpu_events(events)
+            .map_err(|e| cpu::HypervisorCpuError::SetVcpuEvents(e.into()))
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Let the guest know that it has been paused, which prevents from
+    /// potential soft lockups when being resumed.
+    ///
+    fn notify_guest_clock_paused(&self) -> cpu::Result<()> {
+        self.fd
+            .kvmclock_ctrl()
+            .map_err(|e| cpu::HypervisorCpuError::NotifyGuestClockPaused(e.into()))
+    }
+    #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+    fn vcpu_init(&self, kvi: &VcpuInit) -> cpu::Result<()> {
+        self.fd
+            .vcpu_init(kvi)
+            .map_err(|e| cpu::HypervisorCpuError::VcpuInit(e.into()))
+    }
+    ///
+    /// Sets the value of one register for this vCPU.
+    ///
+    #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+    fn set_one_reg(&self, reg_id: u64, data: u64) -> cpu::Result<()> {
+        self.fd
+            .set_one_reg(reg_id, data)
+            .map_err(|e| cpu::HypervisorCpuError::SetOneReg(e.into()))
+    }
+    ///
+    /// Gets the value of one register for this vCPU.
+    ///
+    #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+    fn get_one_reg(&self, reg_id: u64) -> cpu::Result<u64> {
+        self.fd
+            .get_one_reg(reg_id)
+            .map_err(|e| cpu::HypervisorCpuError::GetOneReg(e.into()))
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Get the current CPU state
+    ///
+    /// Ordering requirements:
+    ///
+    /// KVM_GET_MP_STATE calls kvm_apic_accept_events(), which might modify
+    /// vCPU/LAPIC state. As such, it must be done before most everything
+    /// else, otherwise we cannot restore everything and expect it to work.
+    ///
+    /// KVM_GET_VCPU_EVENTS/KVM_SET_VCPU_EVENTS is unsafe if other vCPUs are
+    /// still running.
+    ///
+    /// KVM_GET_LAPIC may change state of LAPIC before returning it.
+    ///
+    /// GET_VCPU_EVENTS should probably be last to save. The code looks as
+    /// it might as well be affected by internal state modifications of the
+    /// GET ioctls.
+    ///
+    /// SREGS saves/restores a pending interrupt, similar to what
+    /// VCPU_EVENTS also does.
+    ///
+    /// GET_MSRS requires a pre-populated data structure to do something
+    /// meaningful. For SET_MSRS it will then contain good data.
+    ///
+    /// # Example
+    ///
+    /// ```rust
+    /// # extern crate hypervisor;
+    /// # use hypervisor::KvmHypervisor;
+    /// # use std::sync::Arc;
+    /// let kvm = hypervisor::kvm::KvmHypervisor::new().unwrap();
+    /// let hv: Arc<dyn hypervisor::Hypervisor> = Arc::new(kvm);
+    /// let vm = hv.create_vm().expect("new VM fd creation failed");
+    /// vm.enable_split_irq().unwrap();
+    /// let vcpu = vm.create_vcpu(0).unwrap();
+    /// let state = vcpu.state().unwrap();
+    /// ```
+    fn state(&self) -> cpu::Result<CpuState> {
+        let mp_state = self.get_mp_state()?;
+        let regs = self.get_regs()?;
+        let sregs = self.get_sregs()?;
+        let xsave = self.get_xsave()?;
+        let xcrs = self.get_xcrs()?;
+        let lapic_state = self.get_lapic()?;
+        let fpu = self.get_fpu()?;
+
+        // Try to get all MSRs based on the list previously retrieved from KVM.
+        // If the number of MSRs obtained from GET_MSRS is different from the
+        // expected amount, we fallback onto a slower method by getting MSRs
+        // by chunks. This is the only way to make sure we try to get as many
+        // MSRs as possible, even if some MSRs are not supported.
+        let mut msr_entries = self.msrs.clone();
+        let expected_num_msrs = msr_entries.as_fam_struct_ref().nmsrs as usize;
+        let num_msrs = self.get_msrs(&mut msr_entries)?;
+        let msrs = if num_msrs != expected_num_msrs {
+            let mut faulty_msr_index = num_msrs;
+            let mut msr_entries_tmp =
+                MsrEntries::from_entries(&msr_entries.as_slice()[..faulty_msr_index]);
+
+            loop {
+                warn!(
+                    "Detected faulty MSR 0x{:x} while getting MSRs",
+                    msr_entries.as_slice()[faulty_msr_index].index
+                );
+
+                let start_pos = faulty_msr_index + 1;
+                let mut sub_msr_entries =
+                    MsrEntries::from_entries(&msr_entries.as_slice()[start_pos..]);
+                let expected_num_msrs = sub_msr_entries.as_fam_struct_ref().nmsrs as usize;
+                let num_msrs = self.get_msrs(&mut sub_msr_entries)?;
+
+                for i in 0..num_msrs {
+                    msr_entries_tmp
+                        .push(sub_msr_entries.as_slice()[i])
+                        .map_err(|e| {
+                            cpu::HypervisorCpuError::GetMsrEntries(anyhow!(
+                                "Failed adding MSR entries: {:?}",
+                                e
+                            ))
+                        })?;
+                }
+
+                if num_msrs == expected_num_msrs {
+                    break;
+                }
+
+                faulty_msr_index = start_pos + num_msrs;
+            }
+
+            msr_entries_tmp
+        } else {
+            msr_entries
+        };
+
+        let vcpu_events = self.get_vcpu_events()?;
+
+        Ok(CpuState {
+            msrs,
+            vcpu_events,
+            regs,
+            sregs,
+            fpu,
+            lapic_state,
+            xsave,
+            xcrs,
+            mp_state,
+        })
+    }
+    #[cfg(target_arch = "aarch64")]
+    fn state(&self) -> cpu::Result<CpuState> {
+        unimplemented!();
+    }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// Restore the previously saved CPU state
+    ///
+    /// Ordering requirements:
+    ///
+    /// KVM_GET_VCPU_EVENTS/KVM_SET_VCPU_EVENTS is unsafe if other vCPUs are
+    /// still running.
+    ///
+    /// Some SET ioctls (like set_mp_state) depend on kvm_vcpu_is_bsp(), so
+    /// if we ever change the BSP, we have to do that before restoring anything.
+    /// The same seems to be true for CPUID stuff.
+    ///
+    /// SREGS saves/restores a pending interrupt, similar to what
+    /// VCPU_EVENTS also does.
+    ///
+    /// SET_REGS clears pending exceptions unconditionally, thus, it must be
+    /// done before SET_VCPU_EVENTS, which restores it.
+    ///
+    /// SET_LAPIC must come after SET_SREGS, because the latter restores
+    /// the apic base msr.
+    ///
+    /// SET_LAPIC must come before SET_MSRS, because the TSC deadline MSR
+    /// only restores successfully, when the LAPIC is correctly configured.
+    ///
+    /// Arguments: CpuState
+    /// # Example
+    ///
+    /// ```rust
+    /// # extern crate hypervisor;
+    /// # use hypervisor::KvmHypervisor;
+    /// # use std::sync::Arc;
+    /// let kvm = hypervisor::kvm::KvmHypervisor::new().unwrap();
+    /// let hv: Arc<dyn hypervisor::Hypervisor> = Arc::new(kvm);
+    /// let vm = hv.create_vm().expect("new VM fd creation failed");
+    /// vm.enable_split_irq().unwrap();
+    /// let vcpu = vm.create_vcpu(0).unwrap();
+    /// let state = vcpu.state().unwrap();
+    /// vcpu.set_state(&state).unwrap();
+    /// ```
+    fn set_state(&self, state: &CpuState) -> cpu::Result<()> {
+        self.set_mp_state(state.mp_state)?;
+        self.set_regs(&state.regs)?;
+        self.set_sregs(&state.sregs)?;
+        self.set_xsave(&state.xsave)?;
+        self.set_xcrs(&state.xcrs)?;
+        self.set_lapic(&state.lapic_state)?;
+        self.set_fpu(&state.fpu)?;
+
+        // Try to set all MSRs previously stored.
+        // If the number of MSRs set from SET_MSRS is different from the
+        // expected amount, we fallback onto a slower method by setting MSRs
+        // by chunks. This is the only way to make sure we try to set as many
+        // MSRs as possible, even if some MSRs are not supported.
+        let expected_num_msrs = state.msrs.as_fam_struct_ref().nmsrs as usize;
+        let num_msrs = self.set_msrs(&state.msrs)?;
+        if num_msrs != expected_num_msrs {
+            let mut faulty_msr_index = num_msrs;
+
+            loop {
+                warn!(
+                    "Detected faulty MSR 0x{:x} while setting MSRs",
+                    state.msrs.as_slice()[faulty_msr_index].index
+                );
+
+                let start_pos = faulty_msr_index + 1;
+                let sub_msr_entries = MsrEntries::from_entries(&state.msrs.as_slice()[start_pos..]);
+                let expected_num_msrs = sub_msr_entries.as_fam_struct_ref().nmsrs as usize;
+                let num_msrs = self.set_msrs(&sub_msr_entries)?;
+
+                if num_msrs == expected_num_msrs {
+                    break;
+                }
+
+                faulty_msr_index = start_pos + num_msrs;
+            }
+        }
+
+        self.set_vcpu_events(&state.vcpu_events)?;
+
+        Ok(())
+    }
+    #[allow(unused_variables)]
+    #[cfg(target_arch = "aarch64")]
+    fn set_state(&self, state: &CpuState) -> cpu::Result<()> {
+        Ok(())
+    }
+}
+
+/// Device struct for KVM
+pub struct KvmDevice {
+    fd: DeviceFd,
+}
+
+impl device::Device for KvmDevice {
+    ///
+    /// Set device attribute
+    ///
+    fn set_device_attr(&self, attr: &DeviceAttr) -> device::Result<()> {
+        self.fd
+            .set_device_attr(attr)
+            .map_err(|e| device::HypervisorDeviceError::SetDeviceAttribute(e.into()))
+    }
+}
+
+impl AsRawFd for KvmDevice {
+    fn as_raw_fd(&self) -> RawFd {
+        self.fd.as_raw_fd()
+    }
+}

hypervisor/src/kvm/x86_64/mod.rs

@@ -0,0 +1,97 @@
+// Copyright © 2019 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause
+//
+// Copyright © 2020, Microsoft Corporation
+//
+// Copyright 2018-2019 CrowdStrike, Inc.
+//
+//
+
+use vm_memory::GuestAddress;
+
+use crate::arch::x86::{msr_index, MTRR_ENABLE, MTRR_MEM_TYPE_WB};
+use crate::kvm::{Cap, Kvm, KvmError, KvmResult};
+use serde_derive::{Deserialize, Serialize};
+
+///
+/// Export generically-named wrappers of kvm-bindings for Unix-based platforms
+///
+pub use {
+    kvm_bindings::kvm_cpuid_entry2 as CpuIdEntry, kvm_bindings::kvm_dtable as DescriptorTable,
+    kvm_bindings::kvm_fpu as FpuState, kvm_bindings::kvm_lapic_state as LapicState,
+    kvm_bindings::kvm_mp_state as MpState, kvm_bindings::kvm_msr_entry as MsrEntry,
+    kvm_bindings::kvm_regs as StandardRegisters, kvm_bindings::kvm_segment as SegmentRegister,
+    kvm_bindings::kvm_sregs as SpecialRegisters, kvm_bindings::kvm_vcpu_events as VcpuEvents,
+    kvm_bindings::kvm_xcrs as ExtendedControlRegisters, kvm_bindings::kvm_xsave as Xsave,
+    kvm_bindings::CpuId, kvm_bindings::MsrList, kvm_bindings::Msrs as MsrEntries,
+    kvm_bindings::KVM_CPUID_FLAG_SIGNIFCANT_INDEX as CPUID_FLAG_VALID_INDEX,
+};
+
+pub const KVM_TSS_ADDRESS: GuestAddress = GuestAddress(0xfffb_d000);
+
+macro_rules! msr {
+    ($msr:expr) => {
+        MsrEntry {
+            index: $msr,
+            data: 0x0,
+            ..Default::default()
+        }
+    };
+}
+macro_rules! msr_data {
+    ($msr:expr, $data:expr) => {
+        MsrEntry {
+            index: $msr,
+            data: $data,
+            ..Default::default()
+        }
+    };
+}
+
+pub fn boot_msr_entries() -> MsrEntries {
+    MsrEntries::from_entries(&[
+        msr!(msr_index::MSR_IA32_SYSENTER_CS),
+        msr!(msr_index::MSR_IA32_SYSENTER_ESP),
+        msr!(msr_index::MSR_IA32_SYSENTER_EIP),
+        msr!(msr_index::MSR_STAR),
+        msr!(msr_index::MSR_CSTAR),
+        msr!(msr_index::MSR_LSTAR),
+        msr!(msr_index::MSR_KERNEL_GS_BASE),
+        msr!(msr_index::MSR_SYSCALL_MASK),
+        msr!(msr_index::MSR_IA32_TSC),
+        msr_data!(
+            msr_index::MSR_IA32_MISC_ENABLE,
+            msr_index::MSR_IA32_MISC_ENABLE_FAST_STRING as u64
+        ),
+        msr_data!(msr_index::MSR_MTRRdefType, MTRR_ENABLE | MTRR_MEM_TYPE_WB),
+    ])
+}
+
+///
+/// Check KVM extension for Linux
+///
+pub fn check_required_kvm_extensions(kvm: &Kvm) -> KvmResult<()> {
+    if !kvm.check_extension(Cap::SignalMsi) {
+        return Err(KvmError::CapabilityMissing(Cap::SignalMsi));
+    }
+    if !kvm.check_extension(Cap::TscDeadlineTimer) {
+        return Err(KvmError::CapabilityMissing(Cap::TscDeadlineTimer));
+    }
+    if !kvm.check_extension(Cap::SplitIrqchip) {
+        return Err(KvmError::CapabilityMissing(Cap::SplitIrqchip));
+    }
+    Ok(())
+}
+#[derive(Clone, Serialize, Deserialize)]
+pub struct VcpuKvmState {
+    pub msrs: MsrEntries,
+    pub vcpu_events: VcpuEvents,
+    pub regs: StandardRegisters,
+    pub sregs: SpecialRegisters,
+    pub fpu: FpuState,
+    pub lapic_state: LapicState,
+    pub xsave: Xsave,
+    pub xcrs: ExtendedControlRegisters,
+    pub mp_state: MpState,
+}

hypervisor/src/lib.rs

@@ -0,0 +1,60 @@
+// Copyright © 2019 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause
+//
+// Copyright © 2020, Microsoft Corporation
+//
+// Copyright 2018-2019 CrowdStrike, Inc.
+//
+//
+
+//! A generic abstraction around hypervisor functionality
+//!
+//! This crate offers a trait abstraction for underlying hypervisors
+//!
+//! # Platform support
+//!
+//! - x86_64
+//! - arm64
+//!
+
+#[macro_use]
+extern crate anyhow;
+#[macro_use]
+extern crate log;
+extern crate serde;
+extern crate serde_derive;
+extern crate serde_json;
+extern crate thiserror;
+
+/// KVM implementation module
+pub mod kvm;
+
+/// Hypevisor related module
+pub mod hypervisor;
+
+/// Vm related module
+pub mod vm;
+
+/// Architecture specific definitions
+pub mod arch;
+
+/// CPU related module
+mod cpu;
+
+/// Device related module
+mod device;
+
+pub use crate::hypervisor::{Hypervisor, HypervisorError};
+pub use cpu::{HypervisorCpuError, Vcpu, VmExit};
+pub use device::{Device, HypervisorDeviceError};
+pub use kvm::*;
+pub use vm::{DataMatch, HypervisorVmError, Vm};
+
+use std::sync::Arc;
+pub fn new() -> std::result::Result<Arc<dyn Hypervisor>, HypervisorError> {
+    #[cfg(feature = "kvm")]
+    let hv = kvm::KvmHypervisor::new()?;
+
+    Ok(Arc::new(hv))
+}

hypervisor/src/vm.rs

@@ -0,0 +1,182 @@
+// Copyright © 2019 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause
+//
+// Copyright © 2020, Microsoft Corporation
+//
+// Copyright 2018-2019 CrowdStrike, Inc.
+//
+//
+
+#[cfg(target_arch = "aarch64")]
+use crate::aarch64::VcpuInit;
+use crate::cpu::Vcpu;
+use crate::device::Device;
+#[cfg(target_arch = "x86_64")]
+use crate::ClockData;
+use crate::{CreateDevice, IoEventAddress, IrqRoutingEntry, MemoryRegion};
+use kvm_ioctls::Cap;
+use std::sync::Arc;
+use thiserror::Error;
+use vmm_sys_util::eventfd::EventFd;
+
+///
+/// I/O events data matches (32 or 64 bits).
+///
+pub enum DataMatch {
+    DataMatch32(u32),
+    DataMatch64(u64),
+}
+
+impl Into<u64> for DataMatch {
+    fn into(self) -> u64 {
+        match self {
+            DataMatch::DataMatch32(dm) => dm.into(),
+            DataMatch::DataMatch64(dm) => dm,
+        }
+    }
+}
+
+#[derive(Error, Debug)]
+///
+/// Enum for VM error
+pub enum HypervisorVmError {
+    ///
+    /// Create Vcpu error
+    ///
+    #[error("Failed to create Vcpu: {0}")]
+    CreateVcpu(#[source] anyhow::Error),
+    ///
+    /// TSS address error
+    ///
+    #[error("Failed to set TSS address: {0}")]
+    SetTssAddress(#[source] anyhow::Error),
+    ///
+    /// Create interrupt controller error
+    ///
+    #[error("Failed to create interrupt controller: {0}")]
+    CreateIrq(#[source] anyhow::Error),
+    ///
+    /// Register interrupt event error
+    ///
+    #[error("Failed to register interrupt event: {0}")]
+    RegisterIrqFd(#[source] anyhow::Error),
+    ///
+    /// Un register interrupt event error
+    ///
+    #[error("Failed to unregister interrupt event: {0}")]
+    UnregisterIrqFd(#[source] anyhow::Error),
+    ///
+    /// Register IO event error
+    ///
+    #[error("Failed to register IO event: {0}")]
+    RegisterIoEvent(#[source] anyhow::Error),
+    ///
+    /// Unregister IO event error
+    ///
+    #[error("Failed to unregister IO event: {0}")]
+    UnregisterIoEvent(#[source] anyhow::Error),
+    ///
+    /// Set GSI routing error
+    ///
+    #[error("Failed to set GSI routing: {0}")]
+    SetGsiRouting(#[source] anyhow::Error),
+    ///
+    /// Set user memory error
+    ///
+    #[error("Failed to set user memory: {0}")]
+    SetUserMemory(#[source] anyhow::Error),
+    ///
+    /// Create device error
+    ///
+    #[error("Failed to set GSI routing: {0}")]
+    CreateDevice(#[source] anyhow::Error),
+    ///
+    /// Get preferred target error
+    ///
+    #[error("Failed to get preferred target: {0}")]
+    GetPreferredTarget(#[source] anyhow::Error),
+    ///
+    /// Enable split Irq error
+    ///
+    #[error("Failed to enable split Irq: {0}")]
+    EnableSplitIrq(#[source] anyhow::Error),
+    ///
+    /// Get clock error
+    ///
+    #[error("Failed to get clock: {0}")]
+    GetClock(#[source] anyhow::Error),
+    ///
+    /// Set clock error
+    ///
+    #[error("Failed to set clock: {0}")]
+    SetClock(#[source] anyhow::Error),
+    ///
+    /// Create passthrough device
+    ///
+    #[error("Failed to create passthrough device: {0}")]
+    CreatePassthroughDevice(#[source] anyhow::Error),
+}
+///
+/// Result type for returning from a function
+///
+pub type Result<T> = std::result::Result<T, HypervisorVmError>;
+
+///
+/// Trait to represent a Vm
+///
+/// This crate provides a hypervisor-agnostic interfaces for Vm
+///
+pub trait Vm: Send + Sync {
+    #[cfg(target_arch = "x86_64")]
+    /// Sets the address of the three-page region in the VM's address space.
+    fn set_tss_address(&self, offset: usize) -> Result<()>;
+    /// Creates an in-kernel interrupt controller.
+    fn create_irq_chip(&self) -> Result<()>;
+    /// Registers an event that will, when signaled, trigger the `gsi` IRQ.
+    fn register_irqfd(&self, fd: &EventFd, gsi: u32) -> Result<()>;
+    /// Unregister an event that will, when signaled, trigger the `gsi` IRQ.
+    fn unregister_irqfd(&self, fd: &EventFd, gsi: u32) -> Result<()>;
+    /// Creates a new KVM vCPU file descriptor and maps the memory corresponding
+    fn create_vcpu(&self, id: u8) -> Result<Arc<dyn Vcpu>>;
+    /// Registers an event to be signaled whenever a certain address is written to.
+    fn register_ioevent(
+        &self,
+        fd: &EventFd,
+        addr: &IoEventAddress,
+        datamatch: Option<DataMatch>,
+    ) -> Result<()>;
+    /// Unregister an event from a certain address it has been previously registered to.
+    fn unregister_ioevent(&self, fd: &EventFd, addr: &IoEventAddress) -> Result<()>;
+    /// Sets the GSI routing table entries, overwriting any previously set
+    fn set_gsi_routing(&self, entries: &[IrqRoutingEntry]) -> Result<()>;
+    /// Creates a memory region structure that can be used with set_user_memory_region
+    fn make_user_memory_region(
+        &self,
+        slot: u32,
+        guest_phys_addr: u64,
+        memory_size: u64,
+        userspace_addr: u64,
+        readonly: bool,
+    ) -> MemoryRegion;
+    /// Creates/modifies a guest physical memory slot.
+    fn set_user_memory_region(&self, user_memory_region: MemoryRegion) -> Result<()>;
+    /// Creates an emulated device in the kernel.
+    fn create_device(&self, device: &mut CreateDevice) -> Result<Arc<dyn Device>>;
+    /// Returns the preferred CPU target type which can be emulated by KVM on underlying host.
+    #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+    fn get_preferred_target(&self, kvi: &mut VcpuInit) -> Result<()>;
+    /// Enable split Irq capability
+    #[cfg(target_arch = "x86_64")]
+    fn enable_split_irq(&self) -> Result<()>;
+    /// Retrieve guest clock.
+    #[cfg(target_arch = "x86_64")]
+    fn get_clock(&self) -> Result<ClockData>;
+    /// Set guest clock.
+    #[cfg(target_arch = "x86_64")]
+    fn set_clock(&self, data: &ClockData) -> Result<()>;
+    /// Checks if a particular `Cap` is available.
+    fn check_extension(&self, c: Cap) -> bool;
+    /// Create a device that is used for passthrough
+    fn create_passthrough_device(&self) -> Result<Arc<dyn Device>>;
+}

net_util/Cargo.toml

@@ -4,14 +4,18 @@ version = "0.1.0"
 authors = ["The Chromium OS Authors"]
 
 [dependencies]
-libc = "0.2.60"
-rand = "0.7.0"
-serde = "1.0.98"
-vmm-sys-util = ">=0.3.1"
-
+epoll = ">=4.0.1"
+libc = "0.2.74"
+log = "0.4.11"
 net_gen = { path = "../net_gen" }
+rand = "0.7.3"
+serde = "1.0.114"
+virtio-bindings = "0.1.0"
+vm-memory = { version = "0.2.1", features = ["backend-mmap", "backend-atomic"] }
+vm-virtio = { path = "../vm-virtio" }
+vmm-sys-util = ">=0.3.1"
 
 [dev-dependencies]
 lazy_static = "1.3.0"
-pnet = "0.22.0"
-serde_json = "1.0.40"
+pnet = "0.26.0"
+serde_json = "1.0.57"

net_util/src/lib.rs

@@ -11,21 +11,28 @@
 #[macro_use]
 extern crate lazy_static;
 extern crate libc;
+#[macro_use]
+extern crate log;
+extern crate net_gen;
 extern crate rand;
 extern crate serde;
-
-extern crate net_gen;
+extern crate virtio_bindings;
+extern crate vm_memory;
+extern crate vm_virtio;
 extern crate vmm_sys_util;
 
 mod mac;
+mod open_tap;
+mod queue_pair;
 mod tap;
 
 use std::io::Error as IoError;
-use std::mem;
-use std::net;
-use std::os::unix::io::FromRawFd;
+use std::os::unix::io::{FromRawFd, RawFd};
+use std::{io, mem, net};
 
 pub use mac::{MacAddr, MAC_ADDR_LEN};
+pub use open_tap::{open_tap, Error as OpenTapError};
+pub use queue_pair::{NetCounters, NetQueuePair, NetQueuePairError, RxVirtio, TxVirtio};
 pub use tap::{Error as TapError, Tap};
 
 #[derive(Debug)]
@@ -62,6 +69,39 @@ fn create_socket() -> Result<net::UdpSocket> {
     Ok(unsafe { net::UdpSocket::from_raw_fd(sock) })
 }
 
+fn vnet_hdr_len() -> usize {
+    use virtio_bindings::bindings::virtio_net::virtio_net_hdr_v1;
+    std::mem::size_of::<virtio_net_hdr_v1>()
+}
+
+pub fn register_listener(
+    epoll_fd: RawFd,
+    fd: RawFd,
+    ev_type: epoll::Events,
+    data: u64,
+) -> std::result::Result<(), io::Error> {
+    epoll::ctl(
+        epoll_fd,
+        epoll::ControlOptions::EPOLL_CTL_ADD,
+        fd,
+        epoll::Event::new(ev_type, data),
+    )
+}
+
+pub fn unregister_listener(
+    epoll_fd: RawFd,
+    fd: RawFd,
+    ev_type: epoll::Events,
+    data: u64,
+) -> std::result::Result<(), io::Error> {
+    epoll::ctl(
+        epoll_fd,
+        epoll::ControlOptions::EPOLL_CTL_DEL,
+        fd,
+        epoll::Event::new(ev_type, data),
+    )
+}
+
 #[cfg(test)]
 mod tests {
     use super::*;

net_util/src/mac.rs

@@ -7,7 +7,9 @@
 
 use rand::Rng;
 use std::fmt;
+use std::io;
 use std::result::Result;
+use std::str::FromStr;
 
 use serde::de::{Deserialize, Deserializer, Error};
 use serde::ser::{Serialize, Serializer};
@@ -20,23 +22,31 @@ pub struct MacAddr {
 }
 
 impl MacAddr {
-    // The error contains the str that failed to be parsed, for nicer error message generation.
-    pub fn parse_str<S>(s: &S) -> Result<MacAddr, &str>
+    pub fn parse_str<S>(s: &S) -> Result<MacAddr, io::Error>
     where
         S: AsRef<str> + ?Sized,
     {
         let v: Vec<&str> = s.as_ref().split(':').collect();
         let mut bytes = [0u8; MAC_ADDR_LEN];
+        let common_err = Err(io::Error::new(
+            io::ErrorKind::Other,
+            format!("parsing of {} into a MAC address failed", s.as_ref()),
+        ));
 
         if v.len() != MAC_ADDR_LEN {
-            return Err(s.as_ref());
+            return common_err;
         }
 
         for i in 0..MAC_ADDR_LEN {
             if v[i].len() != 2 {
-                return Err(s.as_ref());
+                return common_err;
             }
-            bytes[i] = u8::from_str_radix(v[i], 16).map_err(|_| s.as_ref())?;
+            bytes[i] = u8::from_str_radix(v[i], 16).map_err(|e| {
+                io::Error::new(
+                    io::ErrorKind::Other,
+                    format!("parsing of {} into a MAC address failed: {}", s.as_ref(), e),
+                )
+            })?;
         }
 
         Ok(MacAddr { bytes })
@@ -106,7 +116,20 @@ impl<'de> Deserialize<'de> for MacAddr {
         D: Deserializer<'de>,
     {
         let s = String::deserialize(deserializer)?;
-        MacAddr::parse_str(&s).map_err(|_| D::Error::custom("The provided MAC address is invalid."))
+        MacAddr::parse_str(&s)
+            .map_err(|e| D::Error::custom(format!("The provided MAC address is invalid: {}", e)))
+    }
+}
+
+pub enum MacAddrParseError {
+    InvalidValue(String),
+}
+
+impl FromStr for MacAddr {
+    type Err = MacAddrParseError;
+
+    fn from_str(s: &str) -> std::result::Result<Self, Self::Err> {
+        MacAddr::parse_str(s).map_err(|_| MacAddrParseError::InvalidValue(s.to_owned()))
     }
 }
 

net_util/src/open_tap.rs

@@ -0,0 +1,116 @@
+// Copyright (c) 2020 Intel Corporation. All rights reserved.
+//
+// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
+
+use super::{vnet_hdr_len, MacAddr, Tap, TapError};
+use std::net::Ipv4Addr;
+use std::path::Path;
+use std::{fs, io};
+
+#[derive(Debug)]
+pub enum Error {
+    /// Failed to convert an hexadecimal string into an integer.
+    ConvertHexStringToInt(std::num::ParseIntError),
+    /// Error related to the multiqueue support (no support TAP side).
+    MultiQueueNoTapSupport,
+    /// Error related to the multiqueue support (no support device side).
+    MultiQueueNoDeviceSupport,
+    /// Failed to read the TAP flags from sysfs.
+    ReadSysfsTunFlags(io::Error),
+    /// Open tap device failed.
+    TapOpen(TapError),
+    /// Setting tap IP failed.
+    TapSetIp(TapError),
+    /// Setting tap netmask failed.
+    TapSetNetmask(TapError),
+    /// Setting MAC address failed
+    TapSetMac(TapError),
+    /// Getting MAC address failed
+    TapGetMac(TapError),
+    /// Setting tap interface offload flags failed.
+    TapSetOffload(TapError),
+    /// Setting vnet header size failed.
+    TapSetVnetHdrSize(TapError),
+    /// Enabling tap interface failed.
+    TapEnable(TapError),
+}
+
+type Result<T> = std::result::Result<T, Error>;
+
+fn check_mq_support(if_name: &Option<&str>, queue_pairs: usize) -> Result<()> {
+    if let Some(tap_name) = if_name {
+        let mq = queue_pairs > 1;
+        let path = format!("/sys/class/net/{}/tun_flags", tap_name);
+        // interface does not exist, check is not required
+        if !Path::new(&path).exists() {
+            return Ok(());
+        }
+        let tun_flags_str = fs::read_to_string(path).map_err(Error::ReadSysfsTunFlags)?;
+        let tun_flags = u32::from_str_radix(tun_flags_str.trim().trim_start_matches("0x"), 16)
+            .map_err(Error::ConvertHexStringToInt)?;
+        if (tun_flags & net_gen::IFF_MULTI_QUEUE != 0) && !mq {
+            return Err(Error::MultiQueueNoDeviceSupport);
+        } else if (tun_flags & net_gen::IFF_MULTI_QUEUE == 0) && mq {
+            return Err(Error::MultiQueueNoTapSupport);
+        }
+    }
+    Ok(())
+}
+
+/// Create a new virtio network device with the given IP address and
+/// netmask.
+pub fn open_tap(
+    if_name: Option<&str>,
+    ip_addr: Option<Ipv4Addr>,
+    netmask: Option<Ipv4Addr>,
+    host_mac: &mut Option<MacAddr>,
+    num_rx_q: usize,
+) -> Result<Vec<Tap>> {
+    let mut taps: Vec<Tap> = Vec::new();
+    let mut ifname: String = String::new();
+    let vnet_hdr_size = vnet_hdr_len() as i32;
+    let flag = net_gen::TUN_F_CSUM | net_gen::TUN_F_UFO | net_gen::TUN_F_TSO4 | net_gen::TUN_F_TSO6;
+
+    // In case the tap interface already exists, check if the number of
+    // queues is appropriate. The tap might not support multiqueue while
+    // the number of queues indicates the user expects multiple queues, or
+    // on the contrary, the tap might support multiqueue while the number
+    // of queues indicates the user doesn't expect multiple queues.
+    check_mq_support(&if_name, num_rx_q)?;
+
+    for i in 0..num_rx_q {
+        let tap: Tap;
+        if i == 0 {
+            tap = match if_name {
+                Some(name) => Tap::open_named(name, num_rx_q).map_err(Error::TapOpen)?,
+                None => Tap::new(num_rx_q).map_err(Error::TapOpen)?,
+            };
+            if let Some(ip) = ip_addr {
+                tap.set_ip_addr(ip).map_err(Error::TapSetIp)?;
+            }
+            if let Some(mask) = netmask {
+                tap.set_netmask(mask).map_err(Error::TapSetNetmask)?;
+            }
+            if let Some(mac) = host_mac {
+                tap.set_mac_addr(*mac).map_err(Error::TapSetMac)?
+            } else {
+                *host_mac = Some(tap.get_mac_addr().map_err(Error::TapGetMac)?)
+            }
+            tap.enable().map_err(Error::TapEnable)?;
+            tap.set_offload(flag).map_err(Error::TapSetOffload)?;
+
+            tap.set_vnet_hdr_size(vnet_hdr_size)
+                .map_err(Error::TapSetVnetHdrSize)?;
+
+            ifname = String::from_utf8(tap.get_if_name()).unwrap();
+        } else {
+            tap = Tap::open_named(ifname.as_str(), num_rx_q).map_err(Error::TapOpen)?;
+            tap.set_offload(flag).map_err(Error::TapSetOffload)?;
+
+            tap.set_vnet_hdr_size(vnet_hdr_size)
+                .map_err(Error::TapSetVnetHdrSize)?;
+        }
+        taps.push(tap);
+    }
+    Ok(taps)
+}

net_util/src/queue_pair.rs

@@ -0,0 +1,380 @@
+// Copyright (c) 2020 Intel Corporation. All rights reserved.
+//
+// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
+
+use super::{register_listener, unregister_listener, vnet_hdr_len, Tap};
+use libc::EAGAIN;
+use std::cmp;
+use std::io;
+use std::io::{Read, Write};
+use std::num::Wrapping;
+use std::os::unix::io::{AsRawFd, RawFd};
+use std::sync::atomic::{AtomicU64, Ordering};
+use std::sync::Arc;
+use vm_memory::{Bytes, GuestAddress, GuestAddressSpace, GuestMemoryAtomic, GuestMemoryMmap};
+use vm_virtio::{DescriptorChain, Queue};
+
+/// The maximum buffer size when segmentation offload is enabled. This
+/// includes the 12-byte virtio net header.
+/// http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.html#x1-1740003
+const MAX_BUFFER_SIZE: usize = 65562;
+
+#[derive(Clone)]
+pub struct TxVirtio {
+    pub iovec: Vec<(GuestAddress, usize)>,
+    pub frame_buf: [u8; MAX_BUFFER_SIZE],
+    pub counter_bytes: Wrapping<u64>,
+    pub counter_frames: Wrapping<u64>,
+}
+
+impl Default for TxVirtio {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+impl TxVirtio {
+    pub fn new() -> Self {
+        TxVirtio {
+            iovec: Vec::new(),
+            frame_buf: [0u8; MAX_BUFFER_SIZE],
+            counter_bytes: Wrapping(0),
+            counter_frames: Wrapping(0),
+        }
+    }
+
+    pub fn process_desc_chain(&mut self, mem: &GuestMemoryMmap, tap: &mut Tap, queue: &mut Queue) {
+        while let Some(avail_desc) = queue.iter(&mem).next() {
+            let head_index = avail_desc.index;
+            let mut read_count = 0;
+            let mut next_desc = Some(avail_desc);
+
+            self.iovec.clear();
+            while let Some(desc) = next_desc {
+                if desc.is_write_only() {
+                    break;
+                }
+                self.iovec.push((desc.addr, desc.len as usize));
+                read_count += desc.len as usize;
+                next_desc = desc.next_descriptor();
+            }
+
+            read_count = 0;
+            // Copy buffer from across multiple descriptors.
+            // TODO(performance - Issue #420): change this to use `writev()` instead of `write()`
+            // and get rid of the intermediate buffer.
+            for (desc_addr, desc_len) in self.iovec.drain(..) {
+                let limit = cmp::min((read_count + desc_len) as usize, self.frame_buf.len());
+
+                let read_result =
+                    mem.read_slice(&mut self.frame_buf[read_count..limit as usize], desc_addr);
+                match read_result {
+                    Ok(_) => {
+                        // Increment by number of bytes actually read
+                        read_count += limit - read_count;
+                    }
+                    Err(e) => {
+                        println!("Failed to read slice: {:?}", e);
+                        break;
+                    }
+                }
+            }
+
+            let write_result = tap.write(&self.frame_buf[..read_count]);
+            match write_result {
+                Ok(_) => {}
+                Err(e) => {
+                    println!("net: tx: error failed to write to tap: {}", e);
+                }
+            };
+
+            self.counter_bytes += Wrapping((read_count - vnet_hdr_len()) as u64);
+            self.counter_frames += Wrapping(1);
+
+            queue.add_used(&mem, head_index, 0);
+            queue.update_avail_event(&mem);
+        }
+    }
+}
+
+#[derive(Clone)]
+pub struct RxVirtio {
+    pub deferred_frame: bool,
+    pub deferred_irqs: bool,
+    pub bytes_read: usize,
+    pub frame_buf: [u8; MAX_BUFFER_SIZE],
+    pub counter_bytes: Wrapping<u64>,
+    pub counter_frames: Wrapping<u64>,
+}
+
+impl Default for RxVirtio {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+impl RxVirtio {
+    pub fn new() -> Self {
+        RxVirtio {
+            deferred_frame: false,
+            deferred_irqs: false,
+            bytes_read: 0,
+            frame_buf: [0u8; MAX_BUFFER_SIZE],
+            counter_bytes: Wrapping(0),
+            counter_frames: Wrapping(0),
+        }
+    }
+
+    pub fn process_desc_chain(
+        &mut self,
+        mem: &GuestMemoryMmap,
+        mut next_desc: Option<DescriptorChain>,
+        queue: &mut Queue,
+    ) -> bool {
+        let head_index = next_desc.as_ref().unwrap().index;
+        let mut write_count = 0;
+
+        // Copy from frame into buffer, which may span multiple descriptors.
+        loop {
+            match next_desc {
+                Some(desc) => {
+                    if !desc.is_write_only() {
+                        break;
+                    }
+                    let limit = cmp::min(write_count + desc.len as usize, self.bytes_read);
+                    let source_slice = &self.frame_buf[write_count..limit];
+                    let write_result = mem.write_slice(source_slice, desc.addr);
+
+                    match write_result {
+                        Ok(_) => {
+                            write_count = limit;
+                        }
+                        Err(e) => {
+                            error!("Failed to write slice: {:?}", e);
+                            break;
+                        }
+                    };
+
+                    if write_count >= self.bytes_read {
+                        break;
+                    }
+                    next_desc = desc.next_descriptor();
+                }
+                None => {
+                    warn!("Receiving buffer is too small to hold frame of current size");
+                    break;
+                }
+            }
+        }
+
+        self.counter_bytes += Wrapping((write_count - vnet_hdr_len()) as u64);
+        self.counter_frames += Wrapping(1);
+
+        queue.add_used(&mem, head_index, write_count as u32);
+        queue.update_avail_event(&mem);
+
+        // Mark that we have at least one pending packet and we need to interrupt the guest.
+        self.deferred_irqs = true;
+
+        // Update the frame_buf buffer.
+        if write_count < self.bytes_read {
+            self.frame_buf.copy_within(write_count..self.bytes_read, 0);
+            self.bytes_read -= write_count;
+            false
+        } else {
+            self.bytes_read = 0;
+            true
+        }
+    }
+}
+
+#[derive(Default, Clone)]
+pub struct NetCounters {
+    pub tx_bytes: Arc<AtomicU64>,
+    pub tx_frames: Arc<AtomicU64>,
+    pub rx_bytes: Arc<AtomicU64>,
+    pub rx_frames: Arc<AtomicU64>,
+}
+
+#[derive(Debug)]
+pub enum NetQueuePairError {
+    /// No memory configured
+    NoMemoryConfigured,
+    /// Error registering listener
+    RegisterListener(io::Error),
+    /// Error unregistering listener
+    UnregisterListener(io::Error),
+    /// Error reading from the TAP device
+    FailedReadTap,
+}
+
+pub struct NetQueuePair {
+    pub mem: Option<GuestMemoryAtomic<GuestMemoryMmap>>,
+    pub tap: Tap,
+    pub rx: RxVirtio,
+    pub tx: TxVirtio,
+    pub epoll_fd: Option<RawFd>,
+    pub rx_tap_listening: bool,
+    pub counters: NetCounters,
+    pub tap_event_id: u16,
+}
+
+impl NetQueuePair {
+    // Copies a single frame from `self.rx.frame_buf` into the guest. Returns true
+    // if a buffer was used, and false if the frame must be deferred until a buffer
+    // is made available by the driver.
+    fn rx_single_frame(&mut self, mut queue: &mut Queue) -> Result<bool, NetQueuePairError> {
+        let mem = self
+            .mem
+            .as_ref()
+            .ok_or(NetQueuePairError::NoMemoryConfigured)
+            .map(|m| m.memory())?;
+        let next_desc = queue.iter(&mem).next();
+
+        if next_desc.is_none() {
+            // Queue has no available descriptors
+            if self.rx_tap_listening {
+                unregister_listener(
+                    self.epoll_fd.unwrap(),
+                    self.tap.as_raw_fd(),
+                    epoll::Events::EPOLLIN,
+                    u64::from(self.tap_event_id),
+                )
+                .map_err(NetQueuePairError::UnregisterListener)?;
+                self.rx_tap_listening = false;
+                info!("Listener unregistered");
+            }
+            return Ok(false);
+        }
+
+        Ok(self.rx.process_desc_chain(&mem, next_desc, &mut queue))
+    }
+
+    fn process_rx(&mut self, queue: &mut Queue) -> Result<bool, NetQueuePairError> {
+        // Read as many frames as possible.
+        loop {
+            match self.read_tap() {
+                Ok(count) => {
+                    self.rx.bytes_read = count;
+                    if !self.rx_single_frame(queue)? {
+                        self.rx.deferred_frame = true;
+                        break;
+                    }
+                }
+                Err(e) => {
+                    // The tap device is non-blocking, so any error aside from EAGAIN is
+                    // unexpected.
+                    match e.raw_os_error() {
+                        Some(err) if err == EAGAIN => (),
+                        _ => {
+                            error!("Failed to read tap: {:?}", e);
+                            return Err(NetQueuePairError::FailedReadTap);
+                        }
+                    };
+                    break;
+                }
+            }
+        }
+
+        // Consume the counters from the Rx/Tx queues and accumulate into
+        // the counters for the device as whole. This consumption is needed
+        // to handle MQ.
+        self.counters
+            .rx_bytes
+            .fetch_add(self.rx.counter_bytes.0, Ordering::AcqRel);
+        self.counters
+            .rx_frames
+            .fetch_add(self.rx.counter_frames.0, Ordering::AcqRel);
+        self.rx.counter_bytes = Wrapping(0);
+        self.rx.counter_frames = Wrapping(0);
+
+        if self.rx.deferred_irqs {
+            self.rx.deferred_irqs = false;
+            let mem = self
+                .mem
+                .as_ref()
+                .ok_or(NetQueuePairError::NoMemoryConfigured)
+                .map(|m| m.memory())?;
+            Ok(queue.needs_notification(&mem, queue.next_used))
+        } else {
+            Ok(false)
+        }
+    }
+
+    pub fn resume_rx(&mut self, queue: &mut Queue) -> Result<bool, NetQueuePairError> {
+        if !self.rx_tap_listening {
+            register_listener(
+                self.epoll_fd.unwrap(),
+                self.tap.as_raw_fd(),
+                epoll::Events::EPOLLIN,
+                u64::from(self.tap_event_id),
+            )
+            .map_err(NetQueuePairError::RegisterListener)?;
+            self.rx_tap_listening = true;
+            info!("Listener registered");
+        }
+        if self.rx.deferred_frame {
+            if self.rx_single_frame(queue)? {
+                self.rx.deferred_frame = false;
+                // process_rx() was interrupted possibly before consuming all
+                // packets in the tap; try continuing now.
+                self.process_rx(queue)
+            } else if self.rx.deferred_irqs {
+                self.rx.deferred_irqs = false;
+                let mem = self
+                    .mem
+                    .as_ref()
+                    .ok_or(NetQueuePairError::NoMemoryConfigured)
+                    .map(|m| m.memory())?;
+                Ok(queue.needs_notification(&mem, queue.next_used))
+            } else {
+                Ok(false)
+            }
+        } else {
+            Ok(false)
+        }
+    }
+
+    pub fn process_tx(&mut self, mut queue: &mut Queue) -> Result<bool, NetQueuePairError> {
+        let mem = self
+            .mem
+            .as_ref()
+            .ok_or(NetQueuePairError::NoMemoryConfigured)
+            .map(|m| m.memory())?;
+        self.tx.process_desc_chain(&mem, &mut self.tap, &mut queue);
+
+        self.counters
+            .tx_bytes
+            .fetch_add(self.tx.counter_bytes.0, Ordering::AcqRel);
+        self.counters
+            .tx_frames
+            .fetch_add(self.tx.counter_frames.0, Ordering::AcqRel);
+        self.tx.counter_bytes = Wrapping(0);
+        self.tx.counter_frames = Wrapping(0);
+
+        Ok(queue.needs_notification(&mem, queue.next_used))
+    }
+
+    pub fn process_rx_tap(&mut self, mut queue: &mut Queue) -> Result<bool, NetQueuePairError> {
+        if self.rx.deferred_frame
+        // Process a deferred frame first if available. Don't read from tap again
+        // until we manage to receive this deferred frame.
+        {
+            if self.rx_single_frame(&mut queue)? {
+                self.rx.deferred_frame = false;
+                self.process_rx(&mut queue)
+            } else if self.rx.deferred_irqs {
+                self.rx.deferred_irqs = false;
+                Ok(true)
+            } else {
+                Ok(false)
+            }
+        } else {
+            self.process_rx(&mut queue)
+        }
+    }
+
+    fn read_tap(&mut self) -> io::Result<usize> {
+        self.tap.read(&mut self.rx.frame_buf)
+    }
+}

net_util/src/tap.rs

@@ -5,28 +5,33 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the THIRD-PARTY file.
 
+use super::{create_sockaddr, create_socket, Error as NetUtilError, MacAddr};
+use mac::MAC_ADDR_LEN;
+use net_gen;
 use std::fs::File;
 use std::io::{Error as IoError, Read, Result as IoResult, Write};
 use std::net;
 use std::os::raw::*;
 use std::os::unix::io::{AsRawFd, FromRawFd, RawFd};
-
-use super::{create_sockaddr, create_socket, Error as NetUtilError};
-use libc;
-use net_gen;
 use vmm_sys_util::ioctl::{ioctl_with_mut_ref, ioctl_with_ref, ioctl_with_val};
 
 #[derive(Debug)]
 pub enum Error {
     /// Couldn't open /dev/net/tun.
     OpenTun(IoError),
-    /// Unable to create tap interface.
-    CreateTap(IoError),
+    /// Unable to configure tap interface.
+    ConfigureTap(IoError),
+    /// Unable to retrieve features.
+    GetFeatures(IoError),
+    /// Missing multiqueue support in the kernel.
+    MultiQueueKernelSupport,
     /// ioctl failed.
     IoctlError(IoError),
     /// Failed to create a socket.
     NetUtil(NetUtilError),
     InvalidIfname,
+    /// Error parsing MAC data
+    MacParsing(()),
 }
 
 pub type Result<T> = ::std::result::Result<T, Error>;
@@ -40,7 +45,7 @@ pub type Result<T> = ::std::result::Result<T, Error>;
 #[derive(Debug)]
 pub struct Tap {
     tap_file: File,
-    if_name: [u8; 16usize],
+    if_name: Vec<u8>,
 }
 
 impl PartialEq for Tap {
@@ -53,7 +58,7 @@ impl std::clone::Clone for Tap {
     fn clone(&self) -> Self {
         Tap {
             tap_file: self.tap_file.try_clone().unwrap(),
-            if_name: self.if_name,
+            if_name: self.if_name.clone(),
         }
     }
 }
@@ -78,7 +83,7 @@ fn build_terminated_if_name(if_name: &str) -> Result<Vec<u8>> {
 }
 
 impl Tap {
-    pub fn open_named(if_name: &str) -> Result<Tap> {
+    pub fn open_named(if_name: &str, num_queue_pairs: usize) -> Result<Tap> {
         let terminated_if_name = build_terminated_if_name(if_name)?;
 
         let fd = unsafe {
@@ -96,6 +101,20 @@ impl Tap {
         // We just checked that the fd is valid.
         let tuntap = unsafe { File::from_raw_fd(fd) };
 
+        // Let's validate some features before going any further.
+        // ioctl is safe since we call it with a valid tap fd and check the return
+        // value.
+        let mut features = 0;
+        let ret = unsafe { ioctl_with_mut_ref(&tuntap, net_gen::TUNGETFEATURES(), &mut features) };
+        if ret < 0 {
+            return Err(Error::GetFeatures(IoError::last_os_error()));
+        }
+
+        // Check if the user parameters match the kernel support for MQ
+        if (features & net_gen::IFF_MULTI_QUEUE == 0) && num_queue_pairs > 1 {
+            return Err(Error::MultiQueueKernelSupport);
+        }
+
         // This is pretty messy because of the unions used by ifreq. Since we
         // don't call as_mut on the same union field more than once, this block
         // is safe.
@@ -107,26 +126,31 @@ impl Tap {
             name_slice.copy_from_slice(terminated_if_name.as_slice());
             *ifru_flags =
                 (net_gen::IFF_TAP | net_gen::IFF_NO_PI | net_gen::IFF_VNET_HDR) as c_short;
+            if num_queue_pairs > 1 {
+                *ifru_flags |= net_gen::IFF_MULTI_QUEUE as c_short;
+            }
         }
 
         // ioctl is safe since we call it with a valid tap fd and check the return
         // value.
         let ret = unsafe { ioctl_with_mut_ref(&tuntap, net_gen::TUNSETIFF(), &mut ifreq) };
-
         if ret < 0 {
-            return Err(Error::CreateTap(IoError::last_os_error()));
+            return Err(Error::ConfigureTap(IoError::last_os_error()));
         }
 
+        let if_name_temp = unsafe { *ifreq.ifr_ifrn.ifrn_name.as_ref() };
+        let mut if_name = if_name_temp.to_vec();
+        if_name.truncate(terminated_if_name.len() - 1);
         // Safe since only the name is accessed, and it's cloned out.
         Ok(Tap {
             tap_file: tuntap,
-            if_name: unsafe { *ifreq.ifr_ifrn.ifrn_name.as_ref() },
+            if_name,
         })
     }
 
     /// Create a new tap interface.
-    pub fn new() -> Result<Tap> {
-        Self::open_named("vmtap%d")
+    pub fn new(num_queue_pairs: usize) -> Result<Tap> {
+        Self::open_named("vmtap%d", num_queue_pairs)
     }
 
     /// Set the host-side IP address for the tap interface.
@@ -153,6 +177,72 @@ impl Tap {
         Ok(())
     }
 
+    /// Set mac addr for tap interface.
+    pub fn set_mac_addr(&self, addr: MacAddr) -> Result<()> {
+        // Checking if the mac address already matches the desired one
+        // is useful to avoid making the "set ioctl" in the case where
+        // the VMM is running without the privilege to do that.
+        // In practice this comes from a reboot after the configuration
+        // has been update with the kernel generated address.
+        if self.get_mac_addr()? == addr {
+            return Ok(());
+        }
+
+        let sock = create_socket().map_err(Error::NetUtil)?;
+
+        let mut ifreq = self.get_ifreq();
+
+        // ioctl is safe. Called with a valid sock fd, and we check the return.
+        #[allow(clippy::cast_lossless)]
+        let ret =
+            unsafe { ioctl_with_ref(&sock, net_gen::sockios::SIOCGIFHWADDR as c_ulong, &ifreq) };
+        if ret < 0 {
+            return Err(Error::IoctlError(IoError::last_os_error()));
+        }
+        // We only access one field of the ifru union, hence this is safe.
+        unsafe {
+            let ifru_hwaddr = ifreq.ifr_ifru.ifru_hwaddr.as_mut();
+            for (i, v) in addr.get_bytes().iter().enumerate() {
+                ifru_hwaddr.sa_data[i] = *v as c_char;
+            }
+        }
+
+        // ioctl is safe. Called with a valid sock fd, and we check the return.
+        #[allow(clippy::cast_lossless)]
+        let ret =
+            unsafe { ioctl_with_ref(&sock, net_gen::sockios::SIOCSIFHWADDR as c_ulong, &ifreq) };
+        if ret < 0 {
+            return Err(Error::IoctlError(IoError::last_os_error()));
+        }
+
+        Ok(())
+    }
+
+    /// Get mac addr for tap interface.
+    pub fn get_mac_addr(&self) -> Result<MacAddr> {
+        let sock = create_socket().map_err(Error::NetUtil)?;
+
+        let ifreq = self.get_ifreq();
+
+        // ioctl is safe. Called with a valid sock fd, and we check the return.
+        #[allow(clippy::cast_lossless)]
+        let ret =
+            unsafe { ioctl_with_ref(&sock, net_gen::sockios::SIOCGIFHWADDR as c_ulong, &ifreq) };
+        if ret < 0 {
+            return Err(Error::IoctlError(IoError::last_os_error()));
+        }
+
+        // We only access one field of the ifru union, hence this is safe.
+        let addr = unsafe {
+            let ifru_hwaddr = ifreq.ifr_ifru.ifru_hwaddr.as_ref();
+            MacAddr::from_bytes(
+                &*(&ifru_hwaddr.sa_data[0..MAC_ADDR_LEN] as *const _ as *const [u8]),
+            )
+            .map_err(Error::MacParsing)?
+        };
+        Ok(addr)
+    }
+
     /// Set the netmask for the subnet that the tap interface will exist on.
     pub fn set_netmask(&self, netmask: net::Ipv4Addr) -> Result<()> {
         let sock = create_socket().map_err(Error::NetUtil)?;
@@ -196,9 +286,26 @@ impl Tap {
 
         let mut ifreq = self.get_ifreq();
 
+        #[allow(clippy::cast_lossless)]
+        let ret =
+            unsafe { ioctl_with_ref(&sock, net_gen::sockios::SIOCGIFFLAGS as c_ulong, &ifreq) };
+        if ret < 0 {
+            return Err(Error::IoctlError(IoError::last_os_error()));
+        }
+
+        // If TAP device is already up don't try and enable it
+        let ifru_flags = unsafe { ifreq.ifr_ifru.ifru_flags.as_ref() };
+        if ifru_flags
+            & (net_gen::net_device_flags_IFF_UP | net_gen::net_device_flags_IFF_RUNNING) as i16
+            == (net_gen::net_device_flags_IFF_UP | net_gen::net_device_flags_IFF_RUNNING) as i16
+        {
+            return Ok(());
+        }
+
         // We only access one field of the ifru union, hence this is safe.
         unsafe {
             let ifru_flags = ifreq.ifr_ifru.ifru_flags.as_mut();
+
             *ifru_flags =
                 (net_gen::net_device_flags_IFF_UP | net_gen::net_device_flags_IFF_RUNNING) as i16;
         }
@@ -232,11 +339,16 @@ impl Tap {
         // in a single-field union.
         unsafe {
             let ifrn_name = ifreq.ifr_ifrn.ifrn_name.as_mut();
-            ifrn_name.clone_from_slice(&self.if_name);
+            let name_slice = &mut ifrn_name[..self.if_name.len()];
+            name_slice.copy_from_slice(&self.if_name);
         }
 
         ifreq
     }
+
+    pub fn get_if_name(&self) -> Vec<u8> {
+        self.if_name.clone()
+    }
 }
 
 impl Read for Tap {
@@ -415,7 +527,7 @@ mod tests {
         let interface = interfaces.into_iter().find(interface_name_matches).unwrap();
 
         if let Ok(Ethernet(tx, rx)) = datalink::channel(&interface, Default::default()) {
-            (interface.mac_address(), tx, rx)
+            (interface.mac.unwrap(), tx, rx)
         } else {
             panic!("datalink channel error or unhandled channel type");
         }
@@ -423,7 +535,7 @@ mod tests {
 
     #[test]
     fn test_tap_create() {
-        let t = Tap::new().unwrap();
+        let t = Tap::new(1).unwrap();
         println!("created tap: {:?}", t);
     }
 
@@ -435,7 +547,7 @@ mod tests {
         // the end of the function.
         let tap_ip_guard = TAP_IP_LOCK.lock().unwrap();
 
-        let tap = Tap::new().unwrap();
+        let tap = Tap::new(1).unwrap();
         let ip_addr: net::Ipv4Addr = (*tap_ip_guard).parse().unwrap();
         let netmask: net::Ipv4Addr = SUBNET_MASK.parse().unwrap();
 
@@ -448,21 +560,21 @@ mod tests {
     #[test]
     fn test_set_options() {
         // This line will fail to provide an initialized FD if the test is not run as root.
-        let tap = Tap::new().unwrap();
+        let tap = Tap::new(1).unwrap();
         tap.set_vnet_hdr_size(16).unwrap();
         tap.set_offload(0).unwrap();
     }
 
     #[test]
     fn test_tap_enable() {
-        let tap = Tap::new().unwrap();
+        let tap = Tap::new(1).unwrap();
         let ret = tap.enable();
         assert!(ret.is_ok());
     }
 
     #[test]
     fn test_tap_get_ifreq() {
-        let tap = Tap::new().unwrap();
+        let tap = Tap::new(1).unwrap();
         let ret = tap.get_ifreq();
         assert_eq!(
             "__BindgenUnionField",
@@ -472,7 +584,7 @@ mod tests {
 
     #[test]
     fn test_raw_fd() {
-        let tap = Tap::new().unwrap();
+        let tap = Tap::new(1).unwrap();
         assert_eq!(tap.as_raw_fd(), tap.tap_file.as_raw_fd());
     }
 
@@ -480,7 +592,7 @@ mod tests {
     fn test_read() {
         let tap_ip_guard = TAP_IP_LOCK.lock().unwrap();
 
-        let mut tap = Tap::new().unwrap();
+        let mut tap = Tap::new(1).unwrap();
         tap.set_ip_addr((*tap_ip_guard).parse().unwrap()).unwrap();
         tap.set_netmask(SUBNET_MASK.parse().unwrap()).unwrap();
         tap.enable().unwrap();
@@ -541,7 +653,7 @@ mod tests {
     fn test_write() {
         let tap_ip_guard = TAP_IP_LOCK.lock().unwrap();
 
-        let mut tap = Tap::new().unwrap();
+        let mut tap = Tap::new(1).unwrap();
         tap.set_ip_addr((*tap_ip_guard).parse().unwrap()).unwrap();
         tap.set_netmask(SUBNET_MASK.parse().unwrap()).unwrap();
         tap.enable().unwrap();

option_parser/Cargo.toml

@@ -0,0 +1,5 @@
+[package]
+name = "option_parser"
+version = "0.1.0"
+authors = ["The Cloud Hypervisor Authors"]
+edition = "2018"

option_parser/src/lib.rs

@@ -0,0 +1,172 @@
+// Copyright © 2020 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+
+use std::collections::HashMap;
+use std::fmt;
+use std::str::FromStr;
+
+#[derive(Default)]
+pub struct OptionParser {
+    options: HashMap<String, OptionParserValue>,
+}
+
+struct OptionParserValue {
+    value: Option<String>,
+    requires_value: bool,
+}
+
+#[derive(Debug)]
+pub enum OptionParserError {
+    UnknownOption(String),
+    InvalidSyntax(String),
+    Conversion(String, String),
+}
+
+impl fmt::Display for OptionParserError {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        match self {
+            OptionParserError::UnknownOption(s) => write!(f, "unknown option: {}", s),
+            OptionParserError::InvalidSyntax(s) => write!(f, "invalid syntax:{}", s),
+            OptionParserError::Conversion(field, value) => {
+                write!(f, "unable to parse {} for {}", value, field)
+            }
+        }
+    }
+}
+type OptionParserResult<T> = std::result::Result<T, OptionParserError>;
+
+impl OptionParser {
+    pub fn new() -> Self {
+        Self {
+            options: HashMap::new(),
+        }
+    }
+
+    pub fn parse(&mut self, input: &str) -> OptionParserResult<()> {
+        if input.trim().is_empty() {
+            return Ok(());
+        }
+
+        let options_list: Vec<&str> = input.trim().split(',').collect();
+
+        for option in options_list.iter() {
+            let parts: Vec<&str> = option.split('=').collect();
+
+            match self.options.get_mut(parts[0]) {
+                None => return Err(OptionParserError::UnknownOption(parts[0].to_owned())),
+                Some(value) => {
+                    if value.requires_value {
+                        if parts.len() != 2 {
+                            return Err(OptionParserError::InvalidSyntax((*option).to_owned()));
+                        }
+                        value.value = Some(parts[1].trim().to_owned());
+                    } else {
+                        value.value = Some(String::new());
+                    }
+                }
+            }
+        }
+
+        Ok(())
+    }
+
+    pub fn add(&mut self, option: &str) -> &mut Self {
+        self.options.insert(
+            option.to_owned(),
+            OptionParserValue {
+                value: None,
+                requires_value: true,
+            },
+        );
+
+        self
+    }
+
+    pub fn add_valueless(&mut self, option: &str) -> &mut Self {
+        self.options.insert(
+            option.to_owned(),
+            OptionParserValue {
+                value: None,
+                requires_value: false,
+            },
+        );
+
+        self
+    }
+
+    pub fn get(&self, option: &str) -> Option<String> {
+        self.options
+            .get(option)
+            .and_then(|v| v.value.clone())
+            .and_then(|s| if s.is_empty() { None } else { Some(s) })
+    }
+
+    pub fn is_set(&self, option: &str) -> bool {
+        self.options
+            .get(option)
+            .and_then(|v| v.value.as_ref())
+            .is_some()
+    }
+
+    pub fn convert<T: FromStr>(&self, option: &str) -> OptionParserResult<Option<T>> {
+        match self.get(option) {
+            None => Ok(None),
+            Some(v) => Ok(Some(v.parse().map_err(|_| {
+                OptionParserError::Conversion(option.to_owned(), v.to_owned())
+            })?)),
+        }
+    }
+}
+
+pub struct Toggle(pub bool);
+
+pub enum ToggleParseError {
+    InvalidValue(String),
+}
+
+impl FromStr for Toggle {
+    type Err = ToggleParseError;
+
+    fn from_str(s: &str) -> std::result::Result<Self, Self::Err> {
+        match s.to_lowercase().as_str() {
+            "" => Ok(Toggle(false)),
+            "on" => Ok(Toggle(true)),
+            "off" => Ok(Toggle(false)),
+            "true" => Ok(Toggle(true)),
+            "false" => Ok(Toggle(false)),
+            _ => Err(ToggleParseError::InvalidValue(s.to_owned())),
+        }
+    }
+}
+
+pub struct ByteSized(pub u64);
+
+pub enum ByteSizedParseError {
+    InvalidValue(String),
+}
+
+impl FromStr for ByteSized {
+    type Err = ByteSizedParseError;
+
+    fn from_str(s: &str) -> std::result::Result<Self, Self::Err> {
+        Ok(ByteSized({
+            let s = s.trim();
+            let shift = if s.ends_with('K') {
+                10
+            } else if s.ends_with('M') {
+                20
+            } else if s.ends_with('G') {
+                30
+            } else {
+                0
+            };
+
+            let s = s.trim_end_matches(|c| c == 'K' || c == 'M' || c == 'G');
+            s.parse::<u64>()
+                .map_err(|_| ByteSizedParseError::InvalidValue(s.to_owned()))?
+                << shift
+        }))
+    }
+}

pci/Cargo.toml

@@ -5,10 +5,22 @@ authors = ["Samuel Ortiz <sameo@linux.intel.com>"]
 edition = "2018"
 
 [dependencies]
-vm-allocator = { path = "../vm-allocator" }
-byteorder = "1.3.2"
+anyhow = "1.0"
+byteorder = "1.3.4"
 devices = { path = "../devices" }
-libc = "0.2.60"
-log = "0.4.8"
-vm-memory = { git = "https://github.com/rust-vmm/vm-memory" }
+hypervisor = { path = "../hypervisor" }
+vfio-ioctls = { git = "https://github.com/cloud-hypervisor/vfio-ioctls", branch = "ch" }
 vmm-sys-util = ">=0.3.1"
+libc = "0.2.74"
+log = "0.4.11"
+serde = {version = ">=1.0.27", features = ["rc"] }
+serde_derive = ">=1.0.27"
+serde_json = ">=1.0.9"
+vm-allocator = { path = "../vm-allocator" }
+vm-device = { path = "../vm-device" }
+vm-memory = "0.2.1"
+vm-migration = { path = "../vm-migration" }
+
+[dependencies.vfio-bindings]
+version = "0.2.0"
+features = ["fam-wrappers"]

pci/src/bus.rs

@@ -8,14 +8,15 @@ use crate::configuration::{
 use crate::device::{DeviceRelocation, Error as PciDeviceError, PciDevice};
 use byteorder::{ByteOrder, LittleEndian};
 use devices::BusDevice;
-use std;
 use std::any::Any;
+use std::collections::HashMap;
 use std::ops::DerefMut;
-use std::sync::{Arc, Mutex, Weak};
+use std::sync::{Arc, Mutex};
 use vm_memory::{Address, GuestAddress, GuestUsize};
 
 const VENDOR_ID_INTEL: u16 = 0x8086;
 const DEVICE_ID_INTEL_VIRT_PCIE_HOST: u16 = 0x0d57;
+const NUM_DEVICE_IDS: usize = 32;
 
 /// Errors for device manager.
 #[derive(Debug)]
@@ -28,6 +29,12 @@ pub enum PciRootError {
     PioInsert(devices::BusError),
     /// Could not add a device to the mmio bus.
     MmioInsert(devices::BusError),
+    /// Could not find an available device slot on the PCI bus.
+    NoPciDeviceSlotAvailable,
+    /// Invalid PCI device identifier provided.
+    InvalidPciDeviceSlot(usize),
+    /// Valid PCI device identifier but already used.
+    AlreadyInUsePciDeviceSlot(usize),
 }
 pub type Result<T> = std::result::Result<T, PciRootError>;
 
@@ -47,6 +54,7 @@ impl PciRoot {
                 config: PciConfiguration::new(
                     VENDOR_ID_INTEL,
                     DEVICE_ID_INTEL_VIRT_PCIE_HOST,
+                    0,
                     PciClassCode::BridgeDevice,
                     &PciBridgeSubclass::HostBridge,
                     None,
@@ -67,7 +75,7 @@ impl PciDevice for PciRoot {
         self.config.write_config_register(reg_idx, offset, data);
     }
 
-    fn read_config_register(&self, reg_idx: usize) -> u32 {
+    fn read_config_register(&mut self, reg_idx: usize) -> u32 {
         self.config.read_reg(reg_idx)
     }
 
@@ -79,35 +87,42 @@ impl PciDevice for PciRoot {
 pub struct PciBus {
     /// Devices attached to this bus.
     /// Device 0 is host bridge.
-    devices: Vec<Arc<Mutex<dyn PciDevice>>>,
-    device_reloc: Weak<dyn DeviceRelocation>,
+    devices: HashMap<u32, Arc<Mutex<dyn PciDevice>>>,
+    device_reloc: Arc<dyn DeviceRelocation>,
+    device_ids: Vec<bool>,
 }
 
 impl PciBus {
-    pub fn new(pci_root: PciRoot, device_reloc: Weak<dyn DeviceRelocation>) -> Self {
-        let mut devices: Vec<Arc<Mutex<dyn PciDevice>>> = Vec::new();
+    pub fn new(pci_root: PciRoot, device_reloc: Arc<dyn DeviceRelocation>) -> Self {
+        let mut devices: HashMap<u32, Arc<Mutex<dyn PciDevice>>> = HashMap::new();
+        let mut device_ids: Vec<bool> = vec![false; NUM_DEVICE_IDS];
 
-        devices.push(Arc::new(Mutex::new(pci_root)));
+        devices.insert(0, Arc::new(Mutex::new(pci_root)));
+        device_ids[0] = true;
 
         PciBus {
             devices,
             device_reloc,
+            device_ids,
         }
     }
 
     pub fn register_mapping(
         &self,
         dev: Arc<Mutex<dyn BusDevice>>,
-        io_bus: &devices::Bus,
+        #[cfg(target_arch = "x86_64")] io_bus: &devices::Bus,
         mmio_bus: &devices::Bus,
         bars: Vec<(GuestAddress, GuestUsize, PciBarRegionType)>,
     ) -> Result<()> {
         for (address, size, type_) in bars {
             match type_ {
                 PciBarRegionType::IORegion => {
+                    #[cfg(target_arch = "x86_64")]
                     io_bus
                         .insert(dev.clone(), address.raw_value(), size)
                         .map_err(PciRootError::PioInsert)?;
+                    #[cfg(target_arch = "aarch64")]
+                    error!("I/O region is not supported");
                 }
                 PciBarRegionType::Memory32BitRegion | PciBarRegionType::Memory64BitRegion => {
                     mmio_bus
@@ -119,13 +134,51 @@ impl PciBus {
         Ok(())
     }
 
-    pub fn add_device(&mut self, device: Arc<Mutex<dyn PciDevice>>) -> Result<()> {
-        self.devices.push(device);
+    pub fn add_device(
+        &mut self,
+        pci_device_bdf: u32,
+        device: Arc<Mutex<dyn PciDevice>>,
+    ) -> Result<()> {
+        self.devices.insert(pci_device_bdf >> 3, device);
         Ok(())
     }
 
-    pub fn next_device_id(&self) -> u32 {
-        self.devices.len() as u32
+    pub fn remove_by_device(&mut self, device: &Arc<Mutex<dyn PciDevice>>) -> Result<()> {
+        self.devices.retain(|_, dev| !Arc::ptr_eq(dev, device));
+        Ok(())
+    }
+
+    pub fn next_device_id(&mut self) -> Result<u32> {
+        for (idx, device_id) in self.device_ids.iter_mut().enumerate() {
+            if !(*device_id) {
+                *device_id = true;
+                return Ok(idx as u32);
+            }
+        }
+
+        Err(PciRootError::NoPciDeviceSlotAvailable)
+    }
+
+    pub fn get_device_id(&mut self, id: usize) -> Result<()> {
+        if id < NUM_DEVICE_IDS {
+            if !self.device_ids[id] {
+                self.device_ids[id] = true;
+                Ok(())
+            } else {
+                Err(PciRootError::AlreadyInUsePciDeviceSlot(id))
+            }
+        } else {
+            Err(PciRootError::InvalidPciDeviceSlot(id))
+        }
+    }
+
+    pub fn put_device_id(&mut self, id: usize) -> Result<()> {
+        if id < NUM_DEVICE_IDS {
+            self.device_ids[id] = false;
+            Ok(())
+        } else {
+            Err(PciRootError::InvalidPciDeviceSlot(id))
+        }
     }
 }
 
@@ -150,7 +203,7 @@ impl PciConfigIo {
         }
 
         let (bus, device, function, register) =
-            parse_config_address(self.config_address & !0x8000_0000);
+            parse_io_config_address(self.config_address & !0x8000_0000);
 
         // Only support one bus.
         if bus != 0 {
@@ -166,7 +219,7 @@ impl PciConfigIo {
             .lock()
             .unwrap()
             .devices
-            .get(device)
+            .get(&(device as u32))
             .map_or(0xffff_ffff, |d| {
                 d.lock().unwrap().read_config_register(register)
             })
@@ -183,7 +236,7 @@ impl PciConfigIo {
         }
 
         let (bus, device, _function, register) =
-            parse_config_address(self.config_address & !0x8000_0000);
+            parse_io_config_address(self.config_address & !0x8000_0000);
 
         // Only support one bus.
         if bus != 0 {
@@ -191,20 +244,23 @@ impl PciConfigIo {
         }
 
         let pci_bus = self.pci_bus.lock().unwrap();
-        if let Some(d) = pci_bus.devices.get(device) {
+        if let Some(d) = pci_bus.devices.get(&(device as u32)) {
             let mut device = d.lock().unwrap();
 
             // Find out if one of the device's BAR is being reprogrammed, and
             // reprogram it if needed.
             if let Some(params) = device.detect_bar_reprogramming(register, data) {
-                if let Err(e) = pci_bus.device_reloc.upgrade().unwrap().move_bar(
+                if let Err(e) = pci_bus.device_reloc.move_bar(
                     params.old_base,
                     params.new_base,
                     params.len,
                     device.deref_mut(),
                     params.region_type,
                 ) {
-                    error!("Failed moving device BAR: {}", e);
+                    error!(
+                        "Failed moving device BAR: {}: 0x{:x}->0x{:x}(0x{:x})",
+                        e, params.old_base, params.new_base, params.len
+                    );
                 }
             }
 
@@ -277,7 +333,7 @@ impl PciConfigMmio {
     }
 
     fn config_space_read(&self, config_address: u32) -> u32 {
-        let (bus, device, _function, register) = parse_config_address(config_address);
+        let (bus, device, _function, register) = parse_mmio_config_address(config_address);
 
         // Only support one bus.
         if bus != 0 {
@@ -288,7 +344,7 @@ impl PciConfigMmio {
             .lock()
             .unwrap()
             .devices
-            .get(device)
+            .get(&(device as u32))
             .map_or(0xffff_ffff, |d| {
                 d.lock().unwrap().read_config_register(register)
             })
@@ -299,7 +355,7 @@ impl PciConfigMmio {
             return;
         }
 
-        let (bus, device, _function, register) = parse_config_address(config_address);
+        let (bus, device, _function, register) = parse_mmio_config_address(config_address);
 
         // Only support one bus.
         if bus != 0 {
@@ -307,20 +363,23 @@ impl PciConfigMmio {
         }
 
         let pci_bus = self.pci_bus.lock().unwrap();
-        if let Some(d) = pci_bus.devices.get(device) {
+        if let Some(d) = pci_bus.devices.get(&(device as u32)) {
             let mut device = d.lock().unwrap();
 
             // Find out if one of the device's BAR is being reprogrammed, and
             // reprogram it if needed.
             if let Some(params) = device.detect_bar_reprogramming(register, data) {
-                if let Err(e) = pci_bus.device_reloc.upgrade().unwrap().move_bar(
+                if let Err(e) = pci_bus.device_reloc.move_bar(
                     params.old_base,
                     params.new_base,
                     params.len,
                     device.deref_mut(),
                     params.region_type,
                 ) {
-                    error!("Failed moving device BAR: {}", e);
+                    error!(
+                        "Failed moving device BAR: {}: 0x{:x}->0x{:x}(0x{:x})",
+                        e, params.old_base, params.new_base, params.len
+                    );
                 }
             }
 
@@ -356,8 +415,33 @@ impl BusDevice for PciConfigMmio {
     }
 }
 
+fn shift_and_mask(value: u32, offset: usize, mask: u32) -> usize {
+    ((value >> offset) & mask) as usize
+}
+
+// Parse the MMIO address offset to a (bus, device, function, register) tuple.
+// See section 7.2.2 PCI Express Enhanced Configuration Access Mechanism (ECAM)
+// from the Pci Express Base Specification Revision 5.0 Version 1.0.
+fn parse_mmio_config_address(config_address: u32) -> (usize, usize, usize, usize) {
+    const BUS_NUMBER_OFFSET: usize = 20;
+    const BUS_NUMBER_MASK: u32 = 0x00ff;
+    const DEVICE_NUMBER_OFFSET: usize = 15;
+    const DEVICE_NUMBER_MASK: u32 = 0x1f;
+    const FUNCTION_NUMBER_OFFSET: usize = 12;
+    const FUNCTION_NUMBER_MASK: u32 = 0x07;
+    const REGISTER_NUMBER_OFFSET: usize = 2;
+    const REGISTER_NUMBER_MASK: u32 = 0x3ff;
+
+    (
+        shift_and_mask(config_address, BUS_NUMBER_OFFSET, BUS_NUMBER_MASK),
+        shift_and_mask(config_address, DEVICE_NUMBER_OFFSET, DEVICE_NUMBER_MASK),
+        shift_and_mask(config_address, FUNCTION_NUMBER_OFFSET, FUNCTION_NUMBER_MASK),
+        shift_and_mask(config_address, REGISTER_NUMBER_OFFSET, REGISTER_NUMBER_MASK),
+    )
+}
+
 // Parse the CONFIG_ADDRESS register to a (bus, device, function, register) tuple.
-fn parse_config_address(config_address: u32) -> (usize, usize, usize, usize) {
+fn parse_io_config_address(config_address: u32) -> (usize, usize, usize, usize) {
     const BUS_NUMBER_OFFSET: usize = 16;
     const BUS_NUMBER_MASK: u32 = 0x00ff;
     const DEVICE_NUMBER_OFFSET: usize = 11;
@@ -367,12 +451,10 @@ fn parse_config_address(config_address: u32) -> (usize, usize, usize, usize) {
     const REGISTER_NUMBER_OFFSET: usize = 2;
     const REGISTER_NUMBER_MASK: u32 = 0x3f;
 
-    let bus_number = ((config_address >> BUS_NUMBER_OFFSET) & BUS_NUMBER_MASK) as usize;
-    let device_number = ((config_address >> DEVICE_NUMBER_OFFSET) & DEVICE_NUMBER_MASK) as usize;
-    let function_number =
-        ((config_address >> FUNCTION_NUMBER_OFFSET) & FUNCTION_NUMBER_MASK) as usize;
-    let register_number =
-        ((config_address >> REGISTER_NUMBER_OFFSET) & REGISTER_NUMBER_MASK) as usize;
-
-    (bus_number, device_number, function_number, register_number)
+    (
+        shift_and_mask(config_address, BUS_NUMBER_OFFSET, BUS_NUMBER_MASK),
+        shift_and_mask(config_address, DEVICE_NUMBER_OFFSET, DEVICE_NUMBER_MASK),
+        shift_and_mask(config_address, FUNCTION_NUMBER_OFFSET, FUNCTION_NUMBER_MASK),
+        shift_and_mask(config_address, REGISTER_NUMBER_OFFSET, REGISTER_NUMBER_MASK),
+    )
 }

pci/src/configuration.rs

@@ -2,15 +2,16 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE-BSD-3-Clause file.
 
-use std::sync::{Arc, Mutex};
-
 use crate::device::BarReprogrammingParams;
 use crate::{MsixConfig, PciInterruptPin};
+use anyhow::anyhow;
 use byteorder::{ByteOrder, LittleEndian};
 use std::fmt::{self, Display};
+use std::sync::{Arc, Mutex};
+use vm_migration::{MigratableError, Pausable, Snapshot, SnapshotDataSection, Snapshottable};
 
-// The number of 32bit registers in the config space, 256 bytes.
-const NUM_CONFIGURATION_REGISTERS: usize = 64;
+// The number of 32bit registers in the config space, 4096 bytes.
+const NUM_CONFIGURATION_REGISTERS: usize = 1024;
 
 const STATUS_REG: usize = 1;
 const STATUS_REG_CAPABILITIES_USED_MASK: u32 = 0x0010_0000;
@@ -244,16 +245,65 @@ pub trait PciCapability {
     fn id(&self) -> PciCapabilityID;
 }
 
+fn encode_32_bits_bar_size(bar_size: u32) -> Option<u32> {
+    if bar_size > 0 {
+        return Some(!(bar_size - 1));
+    }
+    None
+}
+
+fn decode_32_bits_bar_size(bar_size: u32) -> Option<u32> {
+    if bar_size > 0 {
+        return Some(!bar_size + 1);
+    }
+    None
+}
+
+fn encode_64_bits_bar_size(bar_size: u64) -> Option<(u32, u32)> {
+    if bar_size > 0 {
+        let result = !(bar_size - 1);
+        let result_hi = (result >> 32) as u32;
+        let result_lo = (result & 0xffff_ffff) as u32;
+        return Some((result_hi, result_lo));
+    }
+    None
+}
+
+fn decode_64_bits_bar_size(bar_size_hi: u32, bar_size_lo: u32) -> Option<u64> {
+    let bar_size: u64 = ((bar_size_hi as u64) << 32) | (bar_size_lo as u64);
+    if bar_size > 0 {
+        return Some(!bar_size + 1);
+    }
+    None
+}
+
+#[derive(Serialize, Deserialize, Default, Clone, Copy)]
+struct PciBar {
+    addr: u32,
+    size: u32,
+    used: bool,
+    r#type: Option<PciBarRegionType>,
+}
+
+#[derive(Serialize, Deserialize)]
+struct PciConfigurationState {
+    registers: Vec<u32>,
+    writable_bits: Vec<u32>,
+    bars: Vec<PciBar>,
+    rom_bar_addr: u32,
+    rom_bar_size: u32,
+    rom_bar_used: bool,
+    last_capability: Option<(usize, usize)>,
+    msix_cap_reg_idx: Option<usize>,
+}
+
 /// Contains the configuration space of a PCI node.
 /// See the [specification](https://en.wikipedia.org/wiki/PCI_configuration_space).
 /// The configuration space is accessed with DWORD reads and writes from the guest.
 pub struct PciConfiguration {
     registers: [u32; NUM_CONFIGURATION_REGISTERS],
     writable_bits: [u32; NUM_CONFIGURATION_REGISTERS], // writable bits for each register.
-    bar_addr: [u32; NUM_BAR_REGS],
-    bar_size: [u32; NUM_BAR_REGS],
-    bar_used: [bool; NUM_BAR_REGS],
-    bar_type: [Option<PciBarRegionType>; NUM_BAR_REGS],
+    bars: [PciBar; NUM_BAR_REGS],
     rom_bar_addr: u32,
     rom_bar_size: u32,
     rom_bar_used: bool,
@@ -264,7 +314,7 @@ pub struct PciConfiguration {
 }
 
 /// See pci_regs.h in kernel
-#[derive(Copy, Clone, PartialEq)]
+#[derive(Copy, Clone, PartialEq, Serialize, Deserialize)]
 pub enum PciBarRegionType {
     Memory32BitRegion = 0,
     IORegion = 0x01,
@@ -297,6 +347,10 @@ pub enum Error {
     CapabilityEmpty,
     CapabilityLengthInvalid(usize),
     CapabilitySpaceFull(usize),
+    Decode32BarSize,
+    Decode64BarSize,
+    Encode32BarSize,
+    Encode64BarSize,
     RomBarAddressInvalid(u64, u64),
     RomBarInUse(usize),
     RomBarInvalid(usize),
@@ -324,6 +378,10 @@ impl Display for Error {
             CapabilityEmpty => write!(f, "empty capabilities are invalid"),
             CapabilityLengthInvalid(l) => write!(f, "Invalid capability length {}", l),
             CapabilitySpaceFull(s) => write!(f, "capability of size {} doesn't fit", s),
+            Decode32BarSize => write!(f, "failed to decode 32 bits BAR size"),
+            Decode64BarSize => write!(f, "failed to decode 64 bits BAR size"),
+            Encode32BarSize => write!(f, "failed to encode 32 bits BAR size"),
+            Encode64BarSize => write!(f, "failed to encode 64 bits BAR size"),
             RomBarAddressInvalid(a, s) => write!(f, "address {} size {} too big", a, s),
             RomBarInUse(b) => write!(f, "rom bar {} already used", b),
             RomBarInvalid(b) => write!(f, "rom bar {} invalid, max {}", b, NUM_BAR_REGS - 1),
@@ -337,6 +395,7 @@ impl PciConfiguration {
     pub fn new(
         vendor_id: u16,
         device_id: u16,
+        revision_id: u8,
         class_code: PciClassCode,
         subclass: &dyn PciSubclass,
         programming_interface: Option<&dyn PciProgrammingInterface>,
@@ -347,8 +406,6 @@ impl PciConfiguration {
     ) -> Self {
         let mut registers = [0u32; NUM_CONFIGURATION_REGISTERS];
         let mut writable_bits = [0u32; NUM_CONFIGURATION_REGISTERS];
-        let bar_addr = [0u32; NUM_BAR_REGS];
-        let bar_size = [0u32; NUM_BAR_REGS];
         registers[0] = u32::from(device_id) << 16 | u32::from(vendor_id);
         // TODO(dverkamp): Status should be write-1-to-clear
         writable_bits[1] = 0x0000_ffff; // Status (r/o), command (r/w)
@@ -359,7 +416,8 @@ impl PciConfiguration {
         };
         registers[2] = u32::from(class_code.get_register_value()) << 24
             | u32::from(subclass.get_register_value()) << 16
-            | u32::from(pi) << 8;
+            | u32::from(pi) << 8
+            | u32::from(revision_id);
         writable_bits[3] = 0x0000_00ff; // Cacheline size (r/w)
         match header_type {
             PciHeaderType::Device => {
@@ -374,13 +432,12 @@ impl PciConfiguration {
         };
         registers[11] = u32::from(subsystem_id) << 16 | u32::from(subsystem_vendor_id);
 
+        let bars = [PciBar::default(); NUM_BAR_REGS];
+
         PciConfiguration {
             registers,
             writable_bits,
-            bar_addr,
-            bar_size,
-            bar_used: [false; NUM_BAR_REGS],
-            bar_type: [None; NUM_BAR_REGS],
+            bars,
             rom_bar_addr: 0,
             rom_bar_size: 0,
             rom_bar_used: false,
@@ -390,6 +447,31 @@ impl PciConfiguration {
         }
     }
 
+    fn state(&self) -> PciConfigurationState {
+        PciConfigurationState {
+            registers: self.registers.to_vec(),
+            writable_bits: self.writable_bits.to_vec(),
+            bars: self.bars.to_vec(),
+            rom_bar_addr: self.rom_bar_addr,
+            rom_bar_size: self.rom_bar_size,
+            rom_bar_used: self.rom_bar_used,
+            last_capability: self.last_capability,
+            msix_cap_reg_idx: self.msix_cap_reg_idx,
+        }
+    }
+
+    fn set_state(&mut self, state: &PciConfigurationState) {
+        self.registers.clone_from_slice(state.registers.as_slice());
+        self.writable_bits
+            .clone_from_slice(state.writable_bits.as_slice());
+        self.bars.clone_from_slice(state.bars.as_slice());
+        self.rom_bar_addr = state.rom_bar_addr;
+        self.rom_bar_size = state.rom_bar_size;
+        self.rom_bar_used = state.rom_bar_used;
+        self.last_capability = state.last_capability;
+        self.msix_cap_reg_idx = state.msix_cap_reg_idx;
+    }
+
     /// Reads a 32bit register from `reg_idx` in the register map.
     pub fn read_reg(&self, reg_idx: usize) -> u32 {
         *(self.registers.get(reg_idx).unwrap_or(&0xffff_ffff))
@@ -399,13 +481,18 @@ impl PciConfiguration {
     pub fn write_reg(&mut self, reg_idx: usize, value: u32) {
         let mut mask = self.writable_bits[reg_idx];
 
-        if value == 0xffff_ffff {
-            if reg_idx >= BAR0_REG && reg_idx < BAR0_REG + NUM_BAR_REGS {
-                // Handle very specific case where the BAR is being written with
-                // all 1's to retrieve the BAR size on next BAR reading.
-                mask = self.bar_size[reg_idx - 4];
-            } else if reg_idx == ROM_BAR_REG {
-                mask = self.rom_bar_size;
+        if reg_idx >= BAR0_REG && reg_idx < BAR0_REG + NUM_BAR_REGS {
+            // Handle very specific case where the BAR is being written with
+            // all 1's to retrieve the BAR size during next BAR reading.
+            if value == 0xffff_ffff {
+                mask &= self.bars[reg_idx - 4].size;
+            }
+        } else if reg_idx == ROM_BAR_REG {
+            // Handle very specific case where the BAR is being written with
+            // all 1's on bits 31-11 to retrieve the BAR size during next BAR
+            // reading.
+            if value & ROM_BAR_ADDR_MASK == ROM_BAR_ADDR_MASK {
+                mask &= self.rom_bar_size;
             }
         }
 
@@ -467,7 +554,7 @@ impl PciConfiguration {
     /// (i.e, region size must be power of two, register not already used). Returns 'None' on
     /// failure all, `Some(BarIndex)` on success.
     pub fn add_pci_bar(&mut self, config: &PciBarConfiguration) -> Result<usize> {
-        if self.bar_used[config.reg_idx] {
+        if self.bars[config.reg_idx].used {
             return Err(Error::BarInUse(config.reg_idx));
         }
 
@@ -489,6 +576,11 @@ impl PciConfiguration {
                 if end_addr > u64::from(u32::max_value()) {
                     return Err(Error::BarAddressInvalid(config.addr, config.size));
                 }
+
+                // Encode the BAR size as expected by the software running in
+                // the guest.
+                self.bars[config.reg_idx].size =
+                    encode_32_bits_bar_size(config.size as u32).ok_or(Error::Encode32BarSize)?;
             }
             PciBarRegionType::Memory64BitRegion => {
                 if config.reg_idx + 1 >= NUM_BAR_REGS {
@@ -499,15 +591,21 @@ impl PciConfiguration {
                     return Err(Error::BarAddressInvalid(config.addr, config.size));
                 }
 
-                if self.bar_used[config.reg_idx + 1] {
+                if self.bars[config.reg_idx + 1].used {
                     return Err(Error::BarInUse64(config.reg_idx));
                 }
 
+                // Encode the BAR size as expected by the software running in
+                // the guest.
+                let (bar_size_hi, bar_size_lo) =
+                    encode_64_bits_bar_size(config.size).ok_or(Error::Encode64BarSize)?;
+
                 self.registers[bar_idx + 1] = (config.addr >> 32) as u32;
                 self.writable_bits[bar_idx + 1] = 0xffff_ffff;
-                self.bar_addr[config.reg_idx + 1] = self.registers[bar_idx + 1];
-                self.bar_size[config.reg_idx + 1] = (config.size >> 32) as u32;
-                self.bar_used[config.reg_idx + 1] = true;
+                self.bars[config.reg_idx + 1].addr = self.registers[bar_idx + 1];
+                self.bars[config.reg_idx].size = bar_size_lo;
+                self.bars[config.reg_idx + 1].size = bar_size_hi;
+                self.bars[config.reg_idx + 1].used = true;
             }
         }
 
@@ -521,10 +619,9 @@ impl PciConfiguration {
 
         self.registers[bar_idx] = ((config.addr as u32) & mask) | lower_bits;
         self.writable_bits[bar_idx] = mask;
-        self.bar_addr[config.reg_idx] = self.registers[bar_idx];
-        self.bar_size[config.reg_idx] = config.size as u32;
-        self.bar_used[config.reg_idx] = true;
-        self.bar_type[config.reg_idx] = Some(config.region_type);
+        self.bars[config.reg_idx].addr = self.registers[bar_idx];
+        self.bars[config.reg_idx].used = true;
+        self.bars[config.reg_idx].r#type = Some(config.region_type);
         Ok(config.reg_idx)
     }
 
@@ -554,7 +651,8 @@ impl PciConfiguration {
         self.registers[config.reg_idx] = (config.addr as u32) | active;
         self.writable_bits[config.reg_idx] = ROM_BAR_ADDR_MASK;
         self.rom_bar_addr = self.registers[config.reg_idx];
-        self.rom_bar_size = config.size as u32;
+        self.rom_bar_size =
+            encode_32_bits_bar_size(config.size as u32).ok_or(Error::Encode32BarSize)?;
         self.rom_bar_used = true;
         Ok(config.reg_idx)
     }
@@ -563,11 +661,11 @@ impl PciConfiguration {
     pub fn get_bar_addr(&self, bar_num: usize) -> u64 {
         let bar_idx = BAR0_REG + bar_num;
 
-        let mut addr = u64::from(self.bar_addr[bar_num] & self.writable_bits[bar_idx]);
+        let mut addr = u64::from(self.bars[bar_num].addr & self.writable_bits[bar_idx]);
 
-        if let Some(bar_type) = self.bar_type[bar_num] {
+        if let Some(bar_type) = self.bars[bar_num].r#type {
             if bar_type == PciBarRegionType::Memory64BitRegion {
-                addr |= u64::from(self.bar_addr[bar_num + 1]) << 32;
+                addr |= u64::from(self.bars[bar_num + 1].addr) << 32;
             }
         }
 
@@ -669,31 +767,37 @@ impl PciConfiguration {
 
         let value = LittleEndian::read_u32(data);
 
-        if value == 0xffff_ffff {
-            return None;
-        }
-
         let mask = self.writable_bits[reg_idx];
         if reg_idx >= BAR0_REG && reg_idx < BAR0_REG + NUM_BAR_REGS {
             let bar_idx = reg_idx - 4;
-            if (value & mask) != (self.bar_addr[bar_idx] & mask) {
+            if (value & mask) != (self.bars[bar_idx].addr & mask) {
                 // Handle special case where the address being written is
                 // different from the address initially provided. This is a
                 // BAR reprogramming case which needs to be properly caught.
-                if let Some(bar_type) = self.bar_type[bar_idx] {
+                if let Some(bar_type) = self.bars[bar_idx].r#type {
                     match bar_type {
                         PciBarRegionType::Memory64BitRegion => {}
                         _ => {
+                            // Ignore the case where the BAR size is being
+                            // asked for.
+                            if value == 0xffff_ffff {
+                                return None;
+                            }
+
                             debug!(
                                 "DETECT BAR REPROG: current 0x{:x}, new 0x{:x}",
                                 self.registers[reg_idx], value
                             );
-                            let old_base = u64::from(self.bar_addr[bar_idx] & mask);
+                            let old_base = u64::from(self.bars[bar_idx].addr & mask);
                             let new_base = u64::from(value & mask);
-                            let len = u64::from(self.bar_size[bar_idx]);
+                            let len = u64::from(
+                                decode_32_bits_bar_size(self.bars[bar_idx].size)
+                                    .ok_or(Error::Decode32BarSize)
+                                    .unwrap(),
+                            );
                             let region_type = bar_type;
 
-                            self.bar_addr[bar_idx] = value;
+                            self.bars[bar_idx].addr = value;
 
                             return Some(BarReprogrammingParams {
                                 old_base,
@@ -705,22 +809,37 @@ impl PciConfiguration {
                     }
                 } else if (reg_idx > BAR0_REG)
                     && (self.registers[reg_idx - 1] & self.writable_bits[reg_idx - 1])
-                        != (self.bar_addr[bar_idx - 1] & self.writable_bits[reg_idx - 1])
+                        != (self.bars[bar_idx - 1].addr & self.writable_bits[reg_idx - 1])
                 {
+                    // Ignore the case where the BAR size is being asked for.
+                    // Because we are in the 64bits case here, we have to check
+                    // if the lower 32bits of the current BAR have already been
+                    // asked for the BAR size too.
+                    if value == 0xffff_ffff
+                        && self.registers[reg_idx - 1] & self.writable_bits[reg_idx - 1]
+                            == self.bars[bar_idx - 1].size & self.writable_bits[reg_idx - 1]
+                    {
+                        return None;
+                    }
+
                     debug!(
                         "DETECT BAR REPROG: current 0x{:x}, new 0x{:x}",
                         self.registers[reg_idx], value
                     );
-                    let old_base = u64::from(self.bar_addr[bar_idx] & mask) << 32
-                        | u64::from(self.bar_addr[bar_idx - 1] & self.writable_bits[reg_idx - 1]);
+                    let old_base = u64::from(self.bars[bar_idx].addr & mask) << 32
+                        | u64::from(self.bars[bar_idx - 1].addr & self.writable_bits[reg_idx - 1]);
                     let new_base = u64::from(value & mask) << 32
                         | u64::from(self.registers[reg_idx - 1] & self.writable_bits[reg_idx - 1]);
-                    let len = u64::from(self.bar_size[bar_idx]) << 32
-                        | u64::from(self.bar_size[bar_idx - 1]);
+                    let len = decode_64_bits_bar_size(
+                        self.bars[bar_idx].size,
+                        self.bars[bar_idx - 1].size,
+                    )
+                    .ok_or(Error::Decode64BarSize)
+                    .unwrap();
                     let region_type = PciBarRegionType::Memory64BitRegion;
 
-                    self.bar_addr[bar_idx] = value;
-                    self.bar_addr[bar_idx - 1] = self.registers[reg_idx - 1];
+                    self.bars[bar_idx].addr = value;
+                    self.bars[bar_idx - 1].addr = self.registers[reg_idx - 1];
 
                     return Some(BarReprogrammingParams {
                         old_base,
@@ -731,13 +850,22 @@ impl PciConfiguration {
                 }
             }
         } else if reg_idx == ROM_BAR_REG && (value & mask) != (self.rom_bar_addr & mask) {
+            // Ignore the case where the BAR size is being asked for.
+            if value & ROM_BAR_ADDR_MASK == ROM_BAR_ADDR_MASK {
+                return None;
+            }
+
             debug!(
                 "DETECT ROM BAR REPROG: current 0x{:x}, new 0x{:x}",
                 self.registers[reg_idx], value
             );
             let old_base = u64::from(self.rom_bar_addr & mask);
             let new_base = u64::from(value & mask);
-            let len = u64::from(self.rom_bar_size);
+            let len = u64::from(
+                decode_32_bits_bar_size(self.rom_bar_size)
+                    .ok_or(Error::Decode32BarSize)
+                    .unwrap(),
+            );
             let region_type = PciBarRegionType::Memory32BitRegion;
 
             self.rom_bar_addr = value;
@@ -754,6 +882,54 @@ impl PciConfiguration {
     }
 }
 
+impl Pausable for PciConfiguration {}
+
+impl Snapshottable for PciConfiguration {
+    fn id(&self) -> String {
+        String::from("pci_configuration")
+    }
+
+    fn snapshot(&self) -> std::result::Result<Snapshot, MigratableError> {
+        let snapshot =
+            serde_json::to_vec(&self.state()).map_err(|e| MigratableError::Snapshot(e.into()))?;
+
+        let mut config_snapshot = Snapshot::new(self.id().as_str());
+        config_snapshot.add_data_section(SnapshotDataSection {
+            id: format!("{}-section", self.id()),
+            snapshot,
+        });
+
+        Ok(config_snapshot)
+    }
+
+    fn restore(&mut self, snapshot: Snapshot) -> std::result::Result<(), MigratableError> {
+        if let Some(config_section) = snapshot
+            .snapshot_data
+            .get(&format!("{}-section", self.id()))
+        {
+            let config_state = match serde_json::from_slice(&config_section.snapshot) {
+                Ok(state) => state,
+                Err(error) => {
+                    return Err(MigratableError::Restore(anyhow!(
+                        "Could not deserialize {}: {}",
+                        self.id(),
+                        error
+                    )))
+                }
+            };
+
+            self.set_state(&config_state);
+
+            return Ok(());
+        }
+
+        Err(MigratableError::Restore(anyhow!(
+            "Could not find {} snapshot section",
+            self.id()
+        )))
+    }
+}
+
 impl Default for PciBarConfiguration {
     fn default() -> Self {
         PciBarConfiguration {
@@ -839,6 +1015,7 @@ mod tests {
         let mut cfg = PciConfiguration::new(
             0x1234,
             0x5678,
+            0x1,
             PciClassCode::MultimediaController,
             &PciMultimediaSubclass::AudioController,
             None,
@@ -894,6 +1071,7 @@ mod tests {
         let cfg = PciConfiguration::new(
             0x1234,
             0x5678,
+            0x1,
             PciClassCode::MultimediaController,
             &PciMultimediaSubclass::AudioController,
             Some(&TestPI::Test),

pci/src/device.rs

@@ -3,23 +3,13 @@
 // found in the LICENSE-BSD-3-Clause file.
 
 use crate::configuration::{self, PciBarRegionType};
-use crate::msix::MsixTableEntry;
-use crate::PciInterruptPin;
 use devices::BusDevice;
 use std::any::Any;
 use std::fmt::{self, Display};
-use std::sync::Arc;
 use std::{self, io, result};
 use vm_allocator::SystemAllocator;
 use vm_memory::{GuestAddress, GuestUsize};
 
-pub struct InterruptParameters<'a> {
-    pub msix: Option<&'a MsixTableEntry>,
-}
-
-pub type InterruptDelivery =
-    Box<dyn Fn(InterruptParameters) -> result::Result<(), io::Error> + Send + Sync>;
-
 #[derive(Debug)]
 pub enum Error {
     /// Setup of the device capabilities failed.
@@ -56,19 +46,6 @@ pub struct BarReprogrammingParams {
 }
 
 pub trait PciDevice: BusDevice {
-    /// Assign a legacy PCI IRQ to this device.
-    /// The device may write to `irq_evt` to trigger an interrupt.
-    fn assign_pin_irq(
-        &mut self,
-        _irq_cb: Arc<InterruptDelivery>,
-        _irq_num: u32,
-        _irq_pin: PciInterruptPin,
-    ) {
-    }
-
-    /// Assign MSI-X to this device.
-    fn assign_msix(&mut self, _msi_cb: Arc<InterruptDelivery>) {}
-
     /// Allocates the needed PCI BARs space using the `allocate` function which takes a size and
     /// returns an address. Returns a Vec of (GuestAddress, GuestUsize) tuples.
     fn allocate_bars(
@@ -78,13 +55,18 @@ pub trait PciDevice: BusDevice {
         Ok(Vec::new())
     }
 
+    /// Frees the PCI BARs previously allocated with a call to allocate_bars().
+    fn free_bars(&mut self, _allocator: &mut SystemAllocator) -> Result<()> {
+        Ok(())
+    }
+
     /// Sets a register in the configuration space.
     /// * `reg_idx` - The index of the config register to modify.
     /// * `offset` - Offset in to the register.
     fn write_config_register(&mut self, reg_idx: usize, offset: u64, data: &[u8]);
     /// Gets a register from the configuration space.
     /// * `reg_idx` - The index of the config register to read.
-    fn read_config_register(&self, reg_idx: usize) -> u32;
+    fn read_config_register(&mut self, reg_idx: usize) -> u32;
     /// Detects if a BAR is being reprogrammed.
     fn detect_bar_reprogramming(
         &mut self,

pci/src/lib.rs

@@ -6,14 +6,19 @@
 #[macro_use]
 extern crate log;
 extern crate devices;
+extern crate hypervisor;
+extern crate serde;
+#[macro_use]
+extern crate serde_derive;
+extern crate serde_json;
 extern crate vm_memory;
-extern crate vmm_sys_util;
 
 mod bus;
 mod configuration;
 mod device;
 mod msi;
 mod msix;
+mod vfio;
 
 pub use self::bus::{PciBus, PciConfigIo, PciConfigMmio, PciRoot, PciRootError};
 pub use self::configuration::{
@@ -22,11 +27,11 @@ pub use self::configuration::{
     PciNetworkControllerSubclass, PciProgrammingInterface, PciSerialBusSubClass, PciSubclass,
 };
 pub use self::device::{
-    BarReprogrammingParams, DeviceRelocation, Error as PciDeviceError, InterruptDelivery,
-    InterruptParameters, PciDevice,
+    BarReprogrammingParams, DeviceRelocation, Error as PciDeviceError, PciDevice,
 };
-pub use self::msi::MsiCap;
+pub use self::msi::{msi_num_enabled_vectors, MsiCap, MsiConfig};
 pub use self::msix::{MsixCap, MsixConfig, MsixTableEntry, MSIX_TABLE_ENTRY_SIZE};
+pub use self::vfio::{VfioPciDevice, VfioPciError};
 
 /// PCI has four interrupt pins A->D.
 #[derive(Copy, Clone)]

pci/src/msi.rs

@@ -7,6 +7,10 @@ extern crate byteorder;
 extern crate vm_memory;
 
 use byteorder::{ByteOrder, LittleEndian};
+use std::sync::Arc;
+use vm_device::interrupt::{
+    InterruptIndex, InterruptSourceConfig, InterruptSourceGroup, MsiIrqSourceConfig,
+};
 
 // MSI control masks
 const MSI_CTL_ENABLE: u16 = 0x1;
@@ -21,6 +25,16 @@ const MSI_MSG_ADDR_LO_OFFSET: u64 = 0x4;
 // MSI message masks
 const MSI_MSG_ADDR_LO_MASK: u32 = 0xffff_fffc;
 
+pub fn msi_num_enabled_vectors(msg_ctl: u16) -> usize {
+    let field = (msg_ctl >> 4) & 0x7;
+
+    if field > 5 {
+        return 0;
+    }
+
+    1 << field
+}
+
 #[derive(Clone, Copy, Default)]
 pub struct MsiCap {
     // Message Control Register
@@ -58,21 +72,15 @@ impl MsiCap {
         self.msg_ctl & MSI_CTL_PER_VECTOR == MSI_CTL_PER_VECTOR
     }
 
-    pub fn enabled(&self) -> bool {
+    fn enabled(&self) -> bool {
         self.msg_ctl & MSI_CTL_ENABLE == MSI_CTL_ENABLE
     }
 
-    pub fn num_enabled_vectors(&self) -> usize {
-        let field = (self.msg_ctl >> 4) & 0x7;
-
-        if field > 5 {
-            return 0;
-        }
-
-        1 << field
+    fn num_enabled_vectors(&self) -> usize {
+        msi_num_enabled_vectors(self.msg_ctl)
     }
 
-    pub fn vector_masked(&self, vector: usize) -> bool {
+    fn vector_masked(&self, vector: usize) -> bool {
         if !self.per_vector_mask() {
             return false;
         }
@@ -80,7 +88,7 @@ impl MsiCap {
         (self.mask_bits >> vector) & 0x1 == 0x1
     }
 
-    pub fn size(&self) -> u64 {
+    fn size(&self) -> u64 {
         let mut size: u64 = 0xa;
 
         if self.addr_64_bits() {
@@ -93,7 +101,7 @@ impl MsiCap {
         size
     }
 
-    pub fn update(&mut self, offset: u64, data: &[u8]) {
+    fn update(&mut self, offset: u64, data: &[u8]) {
         // Calculate message data offset depending on the address being 32 or
         // 64 bits.
         // Calculate upper address offset if the address is 64 bits.
@@ -151,3 +159,76 @@ impl MsiCap {
         }
     }
 }
+
+pub struct MsiConfig {
+    cap: MsiCap,
+    interrupt_source_group: Arc<Box<dyn InterruptSourceGroup>>,
+}
+
+impl MsiConfig {
+    pub fn new(msg_ctl: u16, interrupt_source_group: Arc<Box<dyn InterruptSourceGroup>>) -> Self {
+        let cap = MsiCap {
+            msg_ctl,
+            ..Default::default()
+        };
+
+        MsiConfig {
+            cap,
+            interrupt_source_group,
+        }
+    }
+
+    pub fn enabled(&self) -> bool {
+        self.cap.enabled()
+    }
+
+    pub fn size(&self) -> u64 {
+        self.cap.size()
+    }
+
+    pub fn num_enabled_vectors(&self) -> usize {
+        self.cap.num_enabled_vectors()
+    }
+
+    pub fn update(&mut self, offset: u64, data: &[u8]) {
+        let old_enabled = self.cap.enabled();
+
+        self.cap.update(offset, data);
+
+        if self.cap.enabled() {
+            for idx in 0..self.num_enabled_vectors() {
+                let config = MsiIrqSourceConfig {
+                    high_addr: self.cap.msg_addr_hi,
+                    low_addr: self.cap.msg_addr_lo,
+                    data: self.cap.msg_data as u32,
+                    devid: 0,
+                };
+
+                if let Err(e) = self
+                    .interrupt_source_group
+                    .update(idx as InterruptIndex, InterruptSourceConfig::MsiIrq(config))
+                {
+                    error!("Failed updating vector: {:?}", e);
+                }
+
+                if self.cap.vector_masked(idx) {
+                    if let Err(e) = self.interrupt_source_group.mask(idx as InterruptIndex) {
+                        error!("Failed masking vector: {:?}", e);
+                    }
+                } else if let Err(e) = self.interrupt_source_group.unmask(idx as InterruptIndex) {
+                    error!("Failed unmasking vector: {:?}", e);
+                }
+            }
+
+            if !old_enabled {
+                if let Err(e) = self.interrupt_source_group.enable() {
+                    error!("Failed enabling irq_fd: {:?}", e);
+                }
+            }
+        } else if old_enabled {
+            if let Err(e) = self.interrupt_source_group.disable() {
+                error!("Failed disabling irq_fd: {:?}", e);
+            }
+        }
+    }
+}

pci/src/msix.rs

@@ -6,12 +6,17 @@
 extern crate byteorder;
 extern crate vm_memory;
 
-use std::sync::Arc;
-
-use crate::device::InterruptParameters;
-use crate::{InterruptDelivery, PciCapability, PciCapabilityID};
+use crate::{PciCapability, PciCapabilityID};
+use anyhow::anyhow;
 use byteorder::{ByteOrder, LittleEndian};
+use std::io;
+use std::result;
+use std::sync::Arc;
+use vm_device::interrupt::{
+    InterruptIndex, InterruptSourceConfig, InterruptSourceGroup, MsiIrqSourceConfig,
+};
 use vm_memory::ByteValued;
+use vm_migration::{MigratableError, Pausable, Snapshot, SnapshotDataSection, Snapshottable};
 
 const MAX_MSIX_VECTORS_PER_DEVICE: u16 = 2048;
 const MSIX_TABLE_ENTRIES_MODULO: u64 = 16;
@@ -23,7 +28,15 @@ const FUNCTION_MASK_MASK: u16 = (1 << FUNCTION_MASK_BIT) as u16;
 const MSIX_ENABLE_MASK: u16 = (1 << MSIX_ENABLE_BIT) as u16;
 pub const MSIX_TABLE_ENTRY_SIZE: usize = 16;
 
-#[derive(Debug, Clone)]
+#[derive(Debug)]
+enum Error {
+    /// Failed enabling the interrupt route.
+    EnableInterruptRoute(io::Error),
+    /// Failed updating the interrupt route.
+    UpdateInterruptRoute(io::Error),
+}
+
+#[derive(Debug, Clone, Serialize, Deserialize)]
 pub struct MsixTableEntry {
     pub msg_addr_lo: u32,
     pub msg_addr_hi: u32,
@@ -48,16 +61,29 @@ impl Default for MsixTableEntry {
     }
 }
 
+#[derive(Serialize, Deserialize)]
+struct MsixConfigState {
+    table_entries: Vec<MsixTableEntry>,
+    pba_entries: Vec<u64>,
+    masked: bool,
+    enabled: bool,
+}
+
 pub struct MsixConfig {
     pub table_entries: Vec<MsixTableEntry>,
     pub pba_entries: Vec<u64>,
-    interrupt_cb: Option<Arc<InterruptDelivery>>,
+    pub devid: u32,
+    interrupt_source_group: Arc<Box<dyn InterruptSourceGroup>>,
     masked: bool,
     enabled: bool,
 }
 
 impl MsixConfig {
-    pub fn new(msix_vectors: u16) -> Self {
+    pub fn new(
+        msix_vectors: u16,
+        interrupt_source_group: Arc<Box<dyn InterruptSourceGroup>>,
+        devid: u32,
+    ) -> Self {
         assert!(msix_vectors <= MAX_MSIX_VECTORS_PER_DEVICE);
 
         let mut table_entries: Vec<MsixTableEntry> = Vec::new();
@@ -69,14 +95,52 @@ impl MsixConfig {
         MsixConfig {
             table_entries,
             pba_entries,
-            interrupt_cb: None,
+            devid,
+            interrupt_source_group,
             masked: false,
             enabled: false,
         }
     }
 
-    pub fn register_interrupt_cb(&mut self, cb: Arc<InterruptDelivery>) {
-        self.interrupt_cb = Some(cb);
+    fn state(&self) -> MsixConfigState {
+        MsixConfigState {
+            table_entries: self.table_entries.clone(),
+            pba_entries: self.pba_entries.clone(),
+            masked: self.masked,
+            enabled: self.enabled,
+        }
+    }
+
+    fn set_state(&mut self, state: &MsixConfigState) -> result::Result<(), Error> {
+        self.table_entries = state.table_entries.clone();
+        self.pba_entries = state.pba_entries.clone();
+        self.masked = state.masked;
+        self.enabled = state.enabled;
+
+        if self.enabled && !self.masked {
+            for (idx, table_entry) in self.table_entries.iter().enumerate() {
+                if table_entry.masked() {
+                    continue;
+                }
+
+                let config = MsiIrqSourceConfig {
+                    high_addr: table_entry.msg_addr_hi,
+                    low_addr: table_entry.msg_addr_lo,
+                    data: table_entry.msg_data,
+                    devid: self.devid,
+                };
+
+                self.interrupt_source_group
+                    .update(idx as InterruptIndex, InterruptSourceConfig::MsiIrq(config))
+                    .map_err(Error::UpdateInterruptRoute)?;
+
+                self.interrupt_source_group
+                    .enable()
+                    .map_err(Error::EnableInterruptRoute)?;
+            }
+        }
+
+        Ok(())
     }
 
     pub fn masked(&self) -> bool {
@@ -89,10 +153,51 @@ impl MsixConfig {
 
     pub fn set_msg_ctl(&mut self, reg: u16) {
         let old_masked = self.masked;
+        let old_enabled = self.enabled;
 
         self.masked = ((reg >> FUNCTION_MASK_BIT) & 1u16) == 1u16;
         self.enabled = ((reg >> MSIX_ENABLE_BIT) & 1u16) == 1u16;
 
+        // Update KVM routes
+        if old_masked != self.masked || old_enabled != self.enabled {
+            if self.enabled && !self.masked {
+                for (idx, table_entry) in self.table_entries.iter().enumerate() {
+                    let config = MsiIrqSourceConfig {
+                        high_addr: table_entry.msg_addr_hi,
+                        low_addr: table_entry.msg_addr_lo,
+                        data: table_entry.msg_data,
+                        devid: self.devid,
+                    };
+
+                    if let Err(e) = self
+                        .interrupt_source_group
+                        .update(idx as InterruptIndex, InterruptSourceConfig::MsiIrq(config))
+                    {
+                        error!("Failed updating vector: {:?}", e);
+                    }
+
+                    if table_entry.masked() {
+                        if let Err(e) = self.interrupt_source_group.mask(idx as InterruptIndex) {
+                            error!("Failed masking vector: {:?}", e);
+                        }
+                    } else if let Err(e) = self.interrupt_source_group.unmask(idx as InterruptIndex)
+                    {
+                        error!("Failed unmasking vector: {:?}", e);
+                    }
+                }
+
+                if !old_enabled || old_masked {
+                    if let Err(e) = self.interrupt_source_group.enable() {
+                        error!("Failed enabling irq_fd: {:?}", e);
+                    }
+                }
+            } else if old_enabled || !old_masked {
+                if let Err(e) = self.interrupt_source_group.disable() {
+                    error!("Failed disabling irq_fd: {:?}", e);
+                }
+            }
+        }
+
         // If the Function Mask bit was set, and has just been cleared, it's
         // important to go through the entire PBA to check if there was any
         // pending MSI-X message to inject, given that the vector is not
@@ -198,6 +303,33 @@ impl MsixConfig {
             _ => error!("invalid data length"),
         };
 
+        // Update interrupt routes
+        if self.enabled && !self.masked {
+            let table_entry = &self.table_entries[index];
+
+            let config = MsiIrqSourceConfig {
+                high_addr: table_entry.msg_addr_hi,
+                low_addr: table_entry.msg_addr_lo,
+                data: table_entry.msg_data,
+                devid: self.devid,
+            };
+
+            if let Err(e) = self.interrupt_source_group.update(
+                index as InterruptIndex,
+                InterruptSourceConfig::MsiIrq(config),
+            ) {
+                error!("Failed updating vector: {:?}", e);
+            }
+
+            if table_entry.masked() {
+                if let Err(e) = self.interrupt_source_group.mask(index as InterruptIndex) {
+                    error!("Failed masking vector: {:?}", e);
+                }
+            } else if let Err(e) = self.interrupt_source_group.unmask(index as InterruptIndex) {
+                error!("Failed unmasking vector: {:?}", e);
+            }
+        }
+
         // After the MSI-X table entry has been updated, it is necessary to
         // check if the vector control masking bit has changed. In case the
         // bit has been flipped from 1 to 0, we need to inject a MSI message
@@ -285,13 +417,12 @@ impl MsixConfig {
 
     fn inject_msix_and_clear_pba(&mut self, vector: usize) {
         // Inject the MSI message
-        if let Some(cb) = &self.interrupt_cb {
-            match (cb)(InterruptParameters {
-                msix: Some(&self.table_entries[vector]),
-            }) {
-                Ok(_) => debug!("MSI-X injected on vector control flip"),
-                Err(e) => error!("failed to inject MSI-X: {}", e),
-            };
+        match self
+            .interrupt_source_group
+            .trigger(vector as InterruptIndex)
+        {
+            Ok(_) => debug!("MSI-X injected on vector control flip"),
+            Err(e) => error!("failed to inject MSI-X: {}", e),
         }
 
         // Clear the bit from PBA
@@ -299,6 +430,52 @@ impl MsixConfig {
     }
 }
 
+impl Pausable for MsixConfig {}
+
+impl Snapshottable for MsixConfig {
+    fn id(&self) -> String {
+        String::from("msix_config")
+    }
+
+    fn snapshot(&self) -> std::result::Result<Snapshot, MigratableError> {
+        let snapshot =
+            serde_json::to_vec(&self.state()).map_err(|e| MigratableError::Snapshot(e.into()))?;
+
+        let mut msix_snapshot = Snapshot::new(self.id().as_str());
+        msix_snapshot.add_data_section(SnapshotDataSection {
+            id: format!("{}-section", self.id()),
+            snapshot,
+        });
+
+        Ok(msix_snapshot)
+    }
+
+    fn restore(&mut self, snapshot: Snapshot) -> std::result::Result<(), MigratableError> {
+        if let Some(msix_section) = snapshot
+            .snapshot_data
+            .get(&format!("{}-section", self.id()))
+        {
+            let msix_state = match serde_json::from_slice(&msix_section.snapshot) {
+                Ok(state) => state,
+                Err(error) => {
+                    return Err(MigratableError::Restore(anyhow!(
+                        "Could not deserialize MSI-X {}",
+                        error
+                    )))
+                }
+            };
+
+            return self.set_state(&msix_state).map_err(|e| {
+                MigratableError::Restore(anyhow!("Could not restore MSI-X state {:?}", e))
+            });
+        }
+
+        Err(MigratableError::Restore(anyhow!(
+            "Could not find MSI-X snapshot section"
+        )))
+    }
+}
+
 #[allow(dead_code)]
 #[repr(packed)]
 #[derive(Clone, Copy, Default)]

pci/src/vfio.rs

@@ -4,43 +4,47 @@
 //
 
 extern crate devices;
-extern crate pci;
 extern crate vm_allocator;
 
-use crate::vec_with_array_field;
-use crate::vfio_device::VfioDevice;
+use crate::{
+    msi_num_enabled_vectors, BarReprogrammingParams, MsiConfig, MsixCap, MsixConfig,
+    PciBarConfiguration, PciBarRegionType, PciCapabilityID, PciClassCode, PciConfiguration,
+    PciDevice, PciDeviceError, PciHeaderType, PciSubclass, MSIX_TABLE_ENTRY_SIZE,
+};
 use byteorder::{ByteOrder, LittleEndian};
 use devices::BusDevice;
-use kvm_bindings::{
-    kvm_irq_routing, kvm_irq_routing_entry, kvm_userspace_memory_region, KVM_IRQ_ROUTING_MSI,
-};
-use kvm_ioctls::*;
-use pci::{
-    BarReprogrammingParams, MsiCap, MsixCap, MsixConfig, PciBarConfiguration, PciBarRegionType,
-    PciCapabilityID, PciClassCode, PciConfiguration, PciDevice, PciDeviceError, PciHeaderType,
-    PciSubclass, MSIX_TABLE_ENTRY_SIZE,
-};
 use std::any::Any;
-use std::collections::HashMap;
+use std::ops::Deref;
 use std::os::unix::io::AsRawFd;
 use std::ptr::null_mut;
-use std::sync::{Arc, Mutex};
+use std::sync::Arc;
 use std::{fmt, io, result};
 use vfio_bindings::bindings::vfio::*;
+use vfio_ioctls::{VfioDevice, VfioError};
 use vm_allocator::SystemAllocator;
-use vm_memory::{Address, GuestAddress, GuestUsize};
+use vm_device::interrupt::{
+    InterruptIndex, InterruptManager, InterruptSourceGroup, MsiIrqGroupConfig,
+};
+use vm_memory::{
+    Address, GuestAddress, GuestAddressSpace, GuestMemoryAtomic, GuestMemoryMmap, GuestRegionMmap,
+    GuestUsize,
+};
 use vmm_sys_util::eventfd::EventFd;
 
 #[derive(Debug)]
 pub enum VfioPciError {
     AllocateGsi,
     EventFd(io::Error),
-    IrqFd(kvm_ioctls::Error),
+    InterruptSourceGroupCreate(io::Error),
+    IrqFd(hypervisor::HypervisorVmError),
     NewVfioPciDevice,
-    MapRegionGuest(kvm_ioctls::Error),
-    SetGsiRouting(kvm_ioctls::Error),
+    MapRegionGuest(anyhow::Error),
+    SetGsiRouting(hypervisor::HypervisorVmError),
     MsiNotConfigured,
     MsixNotConfigured,
+    UpdateMemory(VfioError),
+    UpdateMsiEventFd,
+    UpdateMsixEventFd,
 }
 pub type Result<T> = std::result::Result<T, VfioPciError>;
 
@@ -49,6 +53,9 @@ impl fmt::Display for VfioPciError {
         match self {
             VfioPciError::AllocateGsi => write!(f, "failed to allocate GSI"),
             VfioPciError::EventFd(e) => write!(f, "failed to create eventfd: {}", e),
+            VfioPciError::InterruptSourceGroupCreate(e) => {
+                write!(f, "failed to create interrupt source group: {}", e)
+            }
             VfioPciError::IrqFd(e) => write!(f, "failed to register irqfd: {}", e),
             VfioPciError::NewVfioPciDevice => write!(f, "failed to create VFIO PCI device"),
             VfioPciError::MapRegionGuest(e) => {
@@ -57,6 +64,9 @@ impl fmt::Display for VfioPciError {
             VfioPciError::SetGsiRouting(e) => write!(f, "failed to set GSI routes for KVM: {}", e),
             VfioPciError::MsiNotConfigured => write!(f, "MSI interrupt not yet configured"),
             VfioPciError::MsixNotConfigured => write!(f, "MSI-X interrupt not yet configured"),
+            VfioPciError::UpdateMemory(e) => write!(f, "failed to update memory: {}", e),
+            VfioPciError::UpdateMsiEventFd => write!(f, "failed to update MSI eventfd"),
+            VfioPciError::UpdateMsixEventFd => write!(f, "failed to update MSI-X eventfd"),
         }
     }
 }
@@ -79,19 +89,19 @@ enum InterruptUpdateAction {
     DisableMsix,
 }
 
-#[derive(Copy, Clone)]
 struct VfioMsi {
-    cap: MsiCap,
+    cfg: MsiConfig,
     cap_offset: u32,
+    interrupt_source_group: Arc<Box<dyn InterruptSourceGroup>>,
 }
 
 impl VfioMsi {
     fn update(&mut self, offset: u64, data: &[u8]) -> Option<InterruptUpdateAction> {
-        let old_enabled = self.cap.enabled();
+        let old_enabled = self.cfg.enabled();
 
-        self.cap.update(offset, data);
+        self.cfg.update(offset, data);
 
-        let new_enabled = self.cap.enabled();
+        let new_enabled = self.cfg.enabled();
 
         if !old_enabled && new_enabled {
             return Some(InterruptUpdateAction::EnableMsi);
@@ -109,18 +119,19 @@ struct VfioMsix {
     bar: MsixConfig,
     cap: MsixCap,
     cap_offset: u32,
+    interrupt_source_group: Arc<Box<dyn InterruptSourceGroup>>,
 }
 
 impl VfioMsix {
     fn update(&mut self, offset: u64, data: &[u8]) -> Option<InterruptUpdateAction> {
-        let old_enabled = self.cap.enabled();
+        let old_enabled = self.bar.enabled();
 
         // Update "Message Control" word
         if offset == 2 && data.len() == 2 {
-            self.cap.set_msg_ctl(LittleEndian::read_u16(data));
+            self.bar.set_msg_ctl(LittleEndian::read_u16(data));
         }
 
-        let new_enabled = self.cap.enabled();
+        let new_enabled = self.bar.enabled();
 
         if !old_enabled && new_enabled {
             return Some(InterruptUpdateAction::EnableMsix);
@@ -169,7 +180,7 @@ impl Interrupt {
     fn accessed(&self, offset: u64) -> Option<(PciCapabilityID, u64)> {
         if let Some(msi) = &self.msi {
             if offset >= u64::from(msi.cap_offset)
-                && offset < u64::from(msi.cap_offset) + msi.cap.size()
+                && offset < u64::from(msi.cap_offset) + msi.cfg.size()
             {
                 return Some((
                     PciCapabilityID::MessageSignalledInterrupts,
@@ -210,34 +221,11 @@ impl Interrupt {
     }
 }
 
-struct InterruptRoute {
-    gsi: u32,
-    irq_fd: EventFd,
-}
-
-impl InterruptRoute {
-    fn new(allocator: &mut SystemAllocator) -> Result<Self> {
-        let irq_fd = EventFd::new(libc::EFD_NONBLOCK).map_err(VfioPciError::EventFd)?;
-        let gsi = allocator.allocate_gsi().ok_or(VfioPciError::AllocateGsi)?;
-
-        Ok(InterruptRoute { gsi, irq_fd })
-    }
-
-    fn enable(&self, vm: &Arc<VmFd>) -> Result<()> {
-        vm.register_irqfd(&self.irq_fd, self.gsi)
-            .map_err(VfioPciError::IrqFd)
-    }
-
-    fn disable(&self, vm: &Arc<VmFd>) -> Result<()> {
-        vm.unregister_irqfd(&self.irq_fd, self.gsi)
-            .map_err(VfioPciError::IrqFd)
-    }
-}
-
 #[derive(Copy, Clone)]
 struct MmioRegion {
     start: GuestAddress,
     length: GuestUsize,
+    type_: PciBarRegionType,
     index: u32,
     mem_slot: Option<u32>,
     host_addr: Option<u64>,
@@ -291,28 +279,28 @@ impl VfioPciConfig {
 /// The VMM creates a VfioDevice, then assigns it to a VfioPciDevice,
 /// which then gets added to the PCI bus.
 pub struct VfioPciDevice {
-    vm_fd: Arc<VmFd>,
+    vm: Arc<dyn hypervisor::Vm>,
     device: Arc<VfioDevice>,
     vfio_pci_configuration: VfioPciConfig,
     configuration: PciConfiguration,
     mmio_regions: Vec<MmioRegion>,
     interrupt: Interrupt,
-    interrupt_routes: Vec<InterruptRoute>,
-    gsi_msi_routes: Arc<Mutex<HashMap<u32, kvm_irq_routing_entry>>>,
+    mem: GuestMemoryAtomic<GuestMemoryMmap>,
 }
 
 impl VfioPciDevice {
     /// Constructs a new Vfio Pci device for the given Vfio device
     pub fn new(
-        vm_fd: &Arc<VmFd>,
-        allocator: &mut SystemAllocator,
+        vm: &Arc<dyn hypervisor::Vm>,
         device: VfioDevice,
-        gsi_msi_routes: Arc<Mutex<HashMap<u32, kvm_irq_routing_entry>>>,
+        interrupt_manager: &Arc<dyn InterruptManager<GroupConfig = MsiIrqGroupConfig>>,
+        mem: GuestMemoryAtomic<GuestMemoryMmap>,
     ) -> Result<Self> {
         let device = Arc::new(device);
         device.reset();
 
         let configuration = PciConfiguration::new(
+            0,
             0,
             0,
             PciClassCode::Other,
@@ -327,7 +315,7 @@ impl VfioPciDevice {
         let vfio_pci_configuration = VfioPciConfig::new(Arc::clone(&device));
 
         let mut vfio_pci_device = VfioPciDevice {
-            vm_fd: vm_fd.clone(),
+            vm: vm.clone(),
             device,
             configuration,
             vfio_pci_configuration,
@@ -336,65 +324,19 @@ impl VfioPciDevice {
                 msi: None,
                 msix: None,
             },
-            interrupt_routes: Vec::new(),
-            gsi_msi_routes,
+            mem,
         };
 
-        vfio_pci_device.parse_capabilities();
-
-        // Allocate temporary interrupt routes for now.
-        // The MSI vectors will be filled when the guest driver programs the device.
-        let max_interrupts = vfio_pci_device.device.max_interrupts();
-        for _ in 0..max_interrupts {
-            let route = InterruptRoute::new(allocator)?;
-            vfio_pci_device.interrupt_routes.push(route);
-        }
+        vfio_pci_device.parse_capabilities(interrupt_manager);
 
         Ok(vfio_pci_device)
     }
 
-    fn enable_irq_fds(&self) -> Result<Vec<&EventFd>> {
-        let mut irq_fds: Vec<&EventFd> = Vec::new();
-
-        for r in &self.interrupt_routes {
-            r.enable(&self.vm_fd)?;
-            irq_fds.push(&r.irq_fd);
-        }
-
-        Ok(irq_fds)
-    }
-
-    fn disable_irq_fds(&self) -> Result<()> {
-        for r in &self.interrupt_routes {
-            r.disable(&self.vm_fd)?;
-        }
-
-        Ok(())
-    }
-
-    fn set_kvm_routes(&self) -> Result<()> {
-        let mut entry_vec: Vec<kvm_irq_routing_entry> = Vec::new();
-        for (_, entry) in self.gsi_msi_routes.lock().unwrap().iter() {
-            entry_vec.push(*entry);
-        }
-
-        let mut irq_routing =
-            vec_with_array_field::<kvm_irq_routing, kvm_irq_routing_entry>(entry_vec.len());
-        irq_routing[0].nr = entry_vec.len() as u32;
-        irq_routing[0].flags = 0;
-
-        unsafe {
-            let entries: &mut [kvm_irq_routing_entry] =
-                irq_routing[0].entries.as_mut_slice(entry_vec.len());
-            entries.copy_from_slice(&entry_vec);
-        }
-
-        self.vm_fd
-            .set_gsi_routing(&irq_routing[0])
-            .map_err(VfioPciError::SetGsiRouting)
-    }
-
-    fn parse_msix_capabilities(&mut self, cap: u8) {
+    fn parse_msix_capabilities(
+        &mut self,
+        cap: u8,
+        interrupt_manager: &Arc<dyn InterruptManager<GroupConfig = MsiIrqGroupConfig>>,
+    ) {
         let msg_ctl = self
             .vfio_pci_configuration
             .read_config_word((cap + 2).into());
@@ -412,30 +354,53 @@ impl VfioPciDevice {
             table,
             pba,
         };
-        let msix_config = MsixConfig::new(msix_cap.table_size());
+
+        let interrupt_source_group = interrupt_manager
+            .create_group(MsiIrqGroupConfig {
+                base: 0,
+                count: msix_cap.table_size() as InterruptIndex,
+            })
+            .unwrap();
+
+        let msix_config = MsixConfig::new(msix_cap.table_size(), interrupt_source_group.clone(), 0);
 
         self.interrupt.msix = Some(VfioMsix {
             bar: msix_config,
             cap: msix_cap,
             cap_offset: cap.into(),
+            interrupt_source_group,
         });
     }
 
-    fn parse_msi_capabilities(&mut self, cap: u8) {
+    fn parse_msi_capabilities(
+        &mut self,
+        cap: u8,
+        interrupt_manager: &Arc<dyn InterruptManager<GroupConfig = MsiIrqGroupConfig>>,
+    ) {
         let msg_ctl = self
             .vfio_pci_configuration
             .read_config_word((cap + 2).into());
 
+        let interrupt_source_group = interrupt_manager
+            .create_group(MsiIrqGroupConfig {
+                base: 0,
+                count: msi_num_enabled_vectors(msg_ctl) as InterruptIndex,
+            })
+            .unwrap();
+
+        let msi_config = MsiConfig::new(msg_ctl, interrupt_source_group.clone());
+
         self.interrupt.msi = Some(VfioMsi {
-            cap: MsiCap {
-                msg_ctl,
-                ..Default::default()
-            },
+            cfg: msi_config,
             cap_offset: cap.into(),
+            interrupt_source_group,
         });
     }
 
-    fn parse_capabilities(&mut self) {
+    fn parse_capabilities(
+        &mut self,
+        interrupt_manager: &Arc<dyn InterruptManager<GroupConfig = MsiIrqGroupConfig>>,
+    ) {
         let mut cap_next = self
             .vfio_pci_configuration
             .read_config_byte(PCI_CONFIG_CAPABILITY_OFFSET);
@@ -447,10 +412,10 @@ impl VfioPciDevice {
 
             match PciCapabilityID::from(cap_id) {
                 PciCapabilityID::MessageSignalledInterrupts => {
-                    self.parse_msi_capabilities(cap_next);
+                    self.parse_msi_capabilities(cap_next, interrupt_manager);
                 }
                 PciCapabilityID::MSIX => {
-                    self.parse_msix_capabilities(cap_next);
+                    self.parse_msix_capabilities(cap_next, interrupt_manager);
                 }
                 _ => {}
             };
@@ -461,158 +426,66 @@ impl VfioPciDevice {
         }
     }
 
-    fn update_msi_interrupt_routes(&self, msi: &VfioMsi) -> Result<()> {
-        if msi.cap.enabled() {
-            let mut gsi_msi_routes = self.gsi_msi_routes.lock().unwrap();
-
-            for (idx, route) in self.interrupt_routes.iter().enumerate() {
-                // Ignore MSI vector if the amount of vectors supported by the
-                // guest OS does not match the expected amount. This is related
-                // to "Multiple Message Capable" and "Multiple Message Enable"
-                // fields from the "Message Control" register.
-                if idx >= msi.cap.num_enabled_vectors() {
-                    continue;
-                }
-
-                // Ignore MSI vector if masked.
-                if msi.cap.vector_masked(idx) {
-                    continue;
-                }
-
-                let mut entry = kvm_irq_routing_entry {
-                    gsi: route.gsi,
-                    type_: KVM_IRQ_ROUTING_MSI,
-                    ..Default::default()
-                };
-
-                entry.u.msi.address_lo = msi.cap.msg_addr_lo;
-                entry.u.msi.address_hi = msi.cap.msg_addr_hi;
-                entry.u.msi.data = u32::from(msi.cap.msg_data) | (idx as u32);
-
-                gsi_msi_routes.insert(route.gsi, entry);
-            }
-        } else {
-            let mut gsi_msi_routes = self.gsi_msi_routes.lock().unwrap();
-
-            for route in self.interrupt_routes.iter() {
-                gsi_msi_routes.remove(&route.gsi);
-            }
-        }
-
-        self.set_kvm_routes()
-    }
-
-    fn update_msix_interrupt_routes(&self, msix: &VfioMsix) -> Result<()> {
-        if msix.cap.enabled() && !msix.cap.masked() {
-            let mut gsi_msi_routes = self.gsi_msi_routes.lock().unwrap();
-
-            for (idx, table_entry) in msix.bar.table_entries.iter().enumerate() {
-                // Ignore MSI-X vector if masked.
-                if table_entry.masked() {
-                    continue;
-                }
-
-                let gsi = self.interrupt_routes[idx].gsi;
-
-                let mut entry = kvm_irq_routing_entry {
-                    gsi,
-                    type_: KVM_IRQ_ROUTING_MSI,
-                    ..Default::default()
-                };
-
-                entry.u.msi.address_lo = table_entry.msg_addr_lo;
-                entry.u.msi.address_hi = table_entry.msg_addr_hi;
-                entry.u.msi.data = table_entry.msg_data;
-
-                gsi_msi_routes.insert(gsi, entry);
-            }
-        } else {
-            let mut gsi_msi_routes = self.gsi_msi_routes.lock().unwrap();
-
-            for route in self.interrupt_routes.iter() {
-                gsi_msi_routes.remove(&route.gsi);
-            }
-        }
-
-        self.set_kvm_routes()
-    }
-
-    fn read_msix_table(&mut self, offset: u64, data: &mut [u8]) {
-        self.interrupt.msix_read_table(offset, data);
-    }
-
-    fn write_msix_table(&mut self, offset: u64, data: &[u8]) {
-        self.interrupt.msix_write_table(offset, data);
-
-        if let Some(msix) = &self.interrupt.msix {
-            if let Err(e) = self.update_msix_interrupt_routes(&msix) {
-                error!("Could not update MSI-X interrupt routes: {}", e);
-            }
-        }
-    }
-
     fn update_msi_capabilities(&mut self, offset: u64, data: &[u8]) -> Result<()> {
         match self.interrupt.update_msi(offset, data) {
-            Some(InterruptUpdateAction::EnableMsi) => match self.enable_irq_fds() {
-                Ok(fds) => {
-                    if let Err(e) = self.device.enable_msi(fds) {
+            Some(InterruptUpdateAction::EnableMsi) => {
+                if let Some(msi) = &self.interrupt.msi {
+                    let mut irq_fds: Vec<&EventFd> = Vec::new();
+                    for i in 0..msi.cfg.num_enabled_vectors() {
+                        if let Some(eventfd) =
+                            msi.interrupt_source_group.notifier(i as InterruptIndex)
+                        {
+                            irq_fds.push(eventfd);
+                        } else {
+                            return Err(VfioPciError::UpdateMsiEventFd);
+                        }
+                    }
+
+                    if let Err(e) = self.device.enable_msi(irq_fds) {
                         warn!("Could not enable MSI: {}", e);
                     }
                 }
-                Err(e) => warn!("Could not get IRQ fds: {}", e),
-            },
+            }
             Some(InterruptUpdateAction::DisableMsi) => {
                 if let Err(e) = self.device.disable_msi() {
                     warn!("Could not disable MSI: {}", e);
                 }
-                if let Err(e) = self.disable_irq_fds() {
-                    warn!("Could not disable MSI: {}", e);
-                }
             }
             _ => {}
         }
 
-        // Update the gsi_msi_routes table now that the MSI cache has been
-        // updated. The point is to always update the table based on latest
-        // changes to the cache, and based on the state of masking flags, the
-        // KVM GSI routes should be configured.
-        if let Some(msi) = &self.interrupt.msi {
-            return self.update_msi_interrupt_routes(&msi);
-        }
-
-        // If the code reach this point, something went wrong.
-        Err(VfioPciError::MsiNotConfigured)
+        Ok(())
     }
 
     fn update_msix_capabilities(&mut self, offset: u64, data: &[u8]) -> Result<()> {
         match self.interrupt.update_msix(offset, data) {
-            Some(InterruptUpdateAction::EnableMsix) => match self.enable_irq_fds() {
-                Ok(fds) => {
-                    if let Err(e) = self.device.enable_msix(fds) {
+            Some(InterruptUpdateAction::EnableMsix) => {
+                if let Some(msix) = &self.interrupt.msix {
+                    let mut irq_fds: Vec<&EventFd> = Vec::new();
+                    for i in 0..msix.bar.table_entries.len() {
+                        if let Some(eventfd) =
+                            msix.interrupt_source_group.notifier(i as InterruptIndex)
+                        {
+                            irq_fds.push(eventfd);
+                        } else {
+                            return Err(VfioPciError::UpdateMsiEventFd);
+                        }
+                    }
+
+                    if let Err(e) = self.device.enable_msix(irq_fds) {
                         warn!("Could not enable MSI-X: {}", e);
                     }
                 }
-                Err(e) => warn!("Could not get IRQ fds: {}", e),
-            },
+            }
             Some(InterruptUpdateAction::DisableMsix) => {
                 if let Err(e) = self.device.disable_msix() {
                     warn!("Could not disable MSI-X: {}", e);
                 }
-                if let Err(e) = self.disable_irq_fds() {
-                    warn!("Could not disable MSI: {}", e);
-                }
             }
             _ => {}
         }
 
-        // Update the gsi_msi_routes table because the state of the enable bit
-        // changed.
-        if let Some(msix) = &self.interrupt.msix {
-            return self.update_msix_interrupt_routes(&msix);
-        }
-
-        // If the code reach this point, something went wrong.
-        Err(VfioPciError::MsixNotConfigured)
+        Ok(())
     }
 
     fn find_region(&self, addr: u64) -> Option<MmioRegion> {
@@ -637,9 +510,11 @@ impl VfioPciDevice {
     /// # Return value
     ///
     /// This function returns the updated KVM memory slot id.
-    pub fn map_mmio_regions(&mut self, vm: &Arc<VmFd>, mem_slot: u32) -> Result<u32> {
+    pub fn map_mmio_regions<F>(&mut self, vm: &Arc<dyn hypervisor::Vm>, mem_slot: F) -> Result<()>
+    where
+        F: Fn() -> u32,
+    {
         let fd = self.device.as_raw_fd();
-        let mut new_mem_slot = mem_slot;
 
         for region in self.mmio_regions.iter_mut() {
             // We want to skip the mapping of the BAR containing the MSI-X
@@ -683,45 +558,68 @@ impl VfioPciDevice {
                     continue;
                 }
 
-                let mem_region = kvm_userspace_memory_region {
-                    slot: new_mem_slot as u32,
-                    guest_phys_addr: region.start.raw_value() + mmap_offset,
-                    memory_size: mmap_size as u64,
-                    userspace_addr: host_addr as u64,
-                    flags: 0,
-                };
+                let slot = mem_slot();
+                let mem_region = vm.make_user_memory_region(
+                    slot,
+                    region.start.raw_value() + mmap_offset,
+                    mmap_size as u64,
+                    host_addr as u64,
+                    false,
+                );
 
-                // Safe because the guest regions are guaranteed not to overlap.
-                unsafe {
-                    vm.set_user_memory_region(mem_region)
-                        .map_err(VfioPciError::MapRegionGuest)?;
-                }
+                vm.set_user_memory_region(mem_region)
+                    .map_err(|e| VfioPciError::MapRegionGuest(e.into()))?;
 
                 // Update the region with memory mapped info.
-                region.mem_slot = Some(new_mem_slot);
+                region.mem_slot = Some(slot);
                 region.host_addr = Some(host_addr as u64);
                 region.mmap_size = Some(mmap_size as usize);
-
-                new_mem_slot += 1;
             }
         }
 
-        Ok(new_mem_slot)
+        Ok(())
     }
 
     pub fn unmap_mmio_regions(&mut self) {
         for region in self.mmio_regions.iter() {
-            if let (Some(addr), Some(size)) = (region.host_addr, region.mmap_size) {
-                let ret = unsafe { libc::munmap(addr as *mut libc::c_void, size) };
+            if let (Some(host_addr), Some(mmap_size), Some(mem_slot)) =
+                (region.host_addr, region.mmap_size, region.mem_slot)
+            {
+                let (mmap_offset, _) = self.device.get_region_mmap(region.index);
+
+                // Remove region from KVM
+                let kvm_region = self.vm.make_user_memory_region(
+                    mem_slot,
+                    region.start.raw_value() + mmap_offset,
+                    0,
+                    host_addr as u64,
+                    false,
+                );
+
+                if let Err(e) = self.vm.set_user_memory_region(kvm_region) {
+                    error!(
+                        "Could not remove the userspace memory region from KVM: {}",
+                        e
+                    );
+                }
+
+                let ret = unsafe { libc::munmap(host_addr as *mut libc::c_void, mmap_size) };
                 if ret != 0 {
                     error!(
-                        "Could not unmap regions, error:{}",
+                        "Could not unmap region {}, error:{}",
+                        region.index,
                         io::Error::last_os_error()
                     );
                 }
             }
         }
     }
+
+    pub fn update_memory(&self, new_region: &Arc<GuestRegionMmap>) -> Result<()> {
+        self.device
+            .extend_dma_map(new_region)
+            .map_err(VfioPciError::UpdateMemory)
+    }
 }
 
 impl Drop for VfioPciDevice {
@@ -729,18 +627,22 @@ impl Drop for VfioPciDevice {
         self.unmap_mmio_regions();
 
         if let Some(msix) = &self.interrupt.msix {
-            if msix.cap.enabled() && self.device.disable_msix().is_err() {
+            if msix.bar.enabled() && self.device.disable_msix().is_err() {
                 error!("Could not disable MSI-X");
             }
         }
 
         if let Some(msi) = &self.interrupt.msi {
-            if msi.cap.enabled() && self.device.disable_msi().is_err() {
+            if msi.cfg.enabled() && self.device.disable_msi().is_err() {
                 error!("Could not disable MSI");
             }
         }
 
-        if self.device.unset_dma_map().is_err() {
+        if self
+            .device
+            .unset_dma_map(self.mem.memory().deref())
+            .is_err()
+        {
             error!("failed to remove all guest memory regions from iommu table");
         }
     }
@@ -841,20 +743,25 @@ impl PciDevice for VfioPciDevice {
             let mut region_type = PciBarRegionType::Memory32BitRegion;
 
             if io_bar {
-                // IO BAR
-                region_type = PciBarRegionType::IORegion;
+                #[cfg(target_arch = "x86_64")]
+                {
+                    // IO BAR
+                    region_type = PciBarRegionType::IORegion;
 
-                // Clear first bit.
-                lsb_size &= 0xffff_fffc;
+                    // Clear first bit.
+                    lsb_size &= 0xffff_fffc;
 
-                // Find the first bit that's set to 1.
-                let first_bit = lsb_size.trailing_zeros();
-                region_size = 2u64.pow(first_bit);
-                // We need to allocate a guest PIO address range for that BAR.
-                // The address needs to be 4 bytes aligned.
-                bar_addr = allocator
-                    .allocate_io_addresses(None, region_size, Some(0x4))
-                    .ok_or_else(|| PciDeviceError::IoAllocationFailed(region_size))?;
+                    // Find the first bit that's set to 1.
+                    let first_bit = lsb_size.trailing_zeros();
+                    region_size = 2u64.pow(first_bit);
+                    // We need to allocate a guest PIO address range for that BAR.
+                    // The address needs to be 4 bytes aligned.
+                    bar_addr = allocator
+                        .allocate_io_addresses(None, region_size, Some(0x4))
+                        .ok_or_else(|| PciDeviceError::IoAllocationFailed(region_size))?;
+                }
+                #[cfg(target_arch = "aarch64")]
+                unimplemented!()
             } else {
                 if is_64bit_bar {
                     // 64 bits Memory BAR
@@ -864,7 +771,7 @@ impl PciDevice for VfioPciDevice {
                     let msb_bar_offset: u32 = PCI_CONFIG_BAR_OFFSET + (bar_id + 1) * 4;
 
                     self.vfio_pci_configuration
-                        .write_config_dword(msb_bar_offset, msb_size);
+                        .write_config_dword(msb_size, msb_bar_offset);
 
                     msb_size = self
                         .vfio_pci_configuration
@@ -933,6 +840,7 @@ impl PciDevice for VfioPciDevice {
             self.mmio_regions.push(MmioRegion {
                 start: bar_addr,
                 length: region_size,
+                type_: region_type,
                 index: bar_id as u32,
                 mem_slot: None,
                 host_addr: None,
@@ -945,13 +853,40 @@ impl PciDevice for VfioPciDevice {
             }
         }
 
-        if self.device.setup_dma_map().is_err() {
+        if self
+            .device
+            .setup_dma_map(self.mem.memory().deref())
+            .is_err()
+        {
             error!("failed to add all guest memory regions into iommu table");
         }
 
         Ok(ranges)
     }
 
+    fn free_bars(
+        &mut self,
+        allocator: &mut SystemAllocator,
+    ) -> std::result::Result<(), PciDeviceError> {
+        for region in self.mmio_regions.iter() {
+            match region.type_ {
+                PciBarRegionType::IORegion => {
+                    #[cfg(target_arch = "x86_64")]
+                    allocator.free_io_addresses(region.start, region.length);
+                    #[cfg(target_arch = "aarch64")]
+                    error!("I/O region is not supported");
+                }
+                PciBarRegionType::Memory32BitRegion => {
+                    allocator.free_mmio_hole_addresses(region.start, region.length);
+                }
+                PciBarRegionType::Memory64BitRegion => {
+                    allocator.free_mmio_addresses(region.start, region.length);
+                }
+            }
+        }
+        Ok(())
+    }
+
     fn write_config_register(&mut self, reg_idx: usize, offset: u64, data: &[u8]) {
         // When the guest wants to write to a BAR, we trap it into
         // our local configuration space. We're not reprogramming
@@ -1002,7 +937,7 @@ impl PciDevice for VfioPciDevice {
             .region_write(VFIO_PCI_CONFIG_REGION_INDEX, data, reg + offset);
     }
 
-    fn read_config_register(&self, reg_idx: usize) -> u32 {
+    fn read_config_register(&mut self, reg_idx: usize) -> u32 {
         // When reading the BARs, we trap it and return what comes
         // from our local configuration space. We want the guest to
         // use that and not the VFIO device BARs as it does not map
@@ -1050,7 +985,7 @@ impl PciDevice for VfioPciDevice {
             let offset = addr - region.start.raw_value();
 
             if self.interrupt.msix_table_accessed(region.index, offset) {
-                self.read_msix_table(offset, data);
+                self.interrupt.msix_read_table(offset, data);
             } else {
                 self.device.region_read(region.index, data, offset);
             }
@@ -1064,7 +999,7 @@ impl PciDevice for VfioPciDevice {
 
             // If the MSI-X table is written to, we need to update our cache.
             if self.interrupt.msix_table_accessed(region.index, offset) {
-                self.write_msix_table(offset, data);
+                self.interrupt.msix_write_table(offset, data);
             } else {
                 self.device.region_write(region.index, data, offset);
             }
@@ -1081,34 +1016,30 @@ impl PciDevice for VfioPciDevice {
                         let (mmap_offset, mmap_size) = self.device.get_region_mmap(region.index);
 
                         // Remove old region from KVM
-                        let old_mem_region = kvm_userspace_memory_region {
-                            slot: mem_slot,
-                            guest_phys_addr: old_base + mmap_offset,
-                            memory_size: 0,
-                            userspace_addr: host_addr,
-                            flags: 0,
-                        };
-                        // Safe because the guest regions are guaranteed not to overlap.
-                        unsafe {
-                            self.vm_fd
-                                .set_user_memory_region(old_mem_region)
-                                .map_err(|e| io::Error::from_raw_os_error(e.errno()))?;
-                        }
+                        let old_mem_region = self.vm.make_user_memory_region(
+                            mem_slot,
+                            old_base + mmap_offset,
+                            0,
+                            host_addr as u64,
+                            false,
+                        );
+
+                        self.vm
+                            .set_user_memory_region(old_mem_region)
+                            .map_err(|e| io::Error::new(io::ErrorKind::Other, e))?;
 
                         // Insert new region to KVM
-                        let new_mem_region = kvm_userspace_memory_region {
-                            slot: mem_slot,
-                            guest_phys_addr: new_base + mmap_offset,
-                            memory_size: mmap_size as u64,
-                            userspace_addr: host_addr,
-                            flags: 0,
-                        };
-                        // Safe because the guest regions are guaranteed not to overlap.
-                        unsafe {
-                            self.vm_fd
-                                .set_user_memory_region(new_mem_region)
-                                .map_err(|e| io::Error::from_raw_os_error(e.errno()))?;
-                        }
+                        let new_mem_region = self.vm.make_user_memory_region(
+                            mem_slot,
+                            new_base + mmap_offset,
+                            mmap_size as u64,
+                            host_addr as u64,
+                            false,
+                        );
+
+                        self.vm
+                            .set_user_memory_region(new_mem_region)
+                            .map_err(|e| io::Error::new(io::ErrorKind::Other, e))?;
                     }
                 }
             }

qcow/Cargo.toml

@@ -9,10 +9,10 @@ license = "BSD-3-Clause"
 path = "src/qcow.rs"
 
 [dependencies]
-byteorder = "1.3.2"
-libc = "0.2.60"
-log = "0.4.8"
-remain = "0.1.3"
+byteorder = "1.3.4"
+libc = "0.2.74"
+log = "0.4.11"
+remain = "0.2.2"
 vmm-sys-util = ">=0.3.1"
 
 [dev-dependencies]

qcow/src/qcow.rs

@@ -6,27 +6,26 @@
 extern crate log;
 
 mod qcow_raw_file;
+mod raw_file;
 mod refcount;
 mod vec_cache;
 
+use crate::qcow_raw_file::QcowRawFile;
+use crate::refcount::RefCount;
+use crate::vec_cache::{CacheMap, Cacheable, VecCache};
 use byteorder::{BigEndian, ReadBytesExt, WriteBytesExt};
 use libc::{EINVAL, ENOSPC, ENOTSUP};
 use remain::sorted;
+use std::cmp::{max, min};
+use std::fmt::{self, Display};
+use std::io::{self, Read, Seek, SeekFrom, Write};
+use std::mem::size_of;
 use vmm_sys_util::{
     file_traits::FileSetLen, file_traits::FileSync, seek_hole::SeekHole, write_zeroes::PunchHole,
     write_zeroes::WriteZeroes,
 };
 
-use std::cmp::{max, min};
-use std::fmt::{self, Display};
-use std::fs::File;
-use std::io::{self, Read, Seek, SeekFrom, Write};
-use std::mem::size_of;
-use std::os::unix::io::{AsRawFd, RawFd};
-
-use crate::qcow_raw_file::QcowRawFile;
-use crate::refcount::RefCount;
-use crate::vec_cache::{CacheMap, Cacheable, VecCache};
+pub use crate::raw_file::RawFile;
 
 #[sorted]
 #[derive(Debug)]
@@ -190,7 +189,7 @@ pub struct QcowHeader {
 
 impl QcowHeader {
     /// Creates a QcowHeader from a reference to a file.
-    pub fn new(f: &mut File) -> Result<QcowHeader> {
+    pub fn new(f: &mut RawFile) -> Result<QcowHeader> {
         f.seek(SeekFrom::Start(0)).map_err(Error::ReadingHeader)?;
         let magic = f.read_u32::<BigEndian>().map_err(Error::ReadingHeader)?;
         if magic != QCOW_MAGIC {
@@ -198,12 +197,12 @@ impl QcowHeader {
         }
 
         // Reads the next u32 from the file.
-        fn read_u32_from_file(f: &mut File) -> Result<u32> {
+        fn read_u32_from_file(f: &mut RawFile) -> Result<u32> {
             f.read_u32::<BigEndian>().map_err(Error::ReadingHeader)
         }
 
         // Reads the next u64 from the file.
-        fn read_u64_from_file(f: &mut File) -> Result<u64> {
+        fn read_u64_from_file(f: &mut RawFile) -> Result<u64> {
             f.read_u64::<BigEndian>().map_err(Error::ReadingHeader)
         }
 
@@ -368,9 +367,10 @@ fn max_refcount_clusters(refcount_order: u32, cluster_size: u32, num_clusters: u
 ///
 /// ```
 /// # use std::io::{Read, Seek, SeekFrom};
-/// # use qcow::{self, QcowFile};
+/// # use qcow::{self, QcowFile, RawFile};
 /// # fn test(file: std::fs::File) -> std::io::Result<()> {
-///     let mut q = QcowFile::from(file).expect("Can't open qcow file");
+///     let mut raw_img = RawFile::new(file, false);
+///     let mut q = QcowFile::from(raw_img).expect("Can't open qcow file");
 ///     let mut buf = [0u8; 12];
 ///     q.seek(SeekFrom::Start(10 as u64))?;
 ///     q.read(&mut buf[..])?;
@@ -395,7 +395,7 @@ pub struct QcowFile {
 
 impl QcowFile {
     /// Creates a QcowFile from `file`. File must be a valid qcow2 image.
-    pub fn from(mut file: File) -> Result<QcowFile> {
+    pub fn from(mut file: RawFile) -> Result<QcowFile> {
         let header = QcowHeader::new(&mut file)?;
 
         // Only v2 and v3 files are supported.
@@ -544,7 +544,7 @@ impl QcowFile {
     }
 
     /// Creates a new QcowFile at the given path.
-    pub fn new(mut file: File, version: u32, virtual_size: u64) -> Result<QcowFile> {
+    pub fn new(mut file: RawFile, version: u32, virtual_size: u64) -> Result<QcowFile> {
         let header = QcowHeader::create_for_size(version, virtual_size);
         file.seek(SeekFrom::Start(0)).map_err(Error::SeekingFile)?;
         header.write_to(&mut file)?;
@@ -1220,7 +1220,12 @@ impl QcowFile {
         let refcount = self
             .refcounts
             .get_cluster_refcount(&mut self.raw_file, cluster_addr)
-            .map_err(|_| std::io::Error::from_raw_os_error(EINVAL))?;
+            .map_err(|e| {
+                io::Error::new(
+                    io::ErrorKind::InvalidData,
+                    format!("failed to get cluster refcount: {}", e),
+                )
+            })?;
         if refcount == 0 {
             return Err(std::io::Error::from_raw_os_error(EINVAL));
         }
@@ -1394,12 +1399,6 @@ impl Drop for QcowFile {
     }
 }
 
-impl AsRawFd for QcowFile {
-    fn as_raw_fd(&self) -> RawFd {
-        self.raw_file.file().as_raw_fd()
-    }
-}
-
 impl Read for QcowFile {
     fn read(&mut self, buf: &mut [u8]) -> std::io::Result<usize> {
         let address: u64 = self.current_offset as u64;
@@ -1634,7 +1633,7 @@ where
     Ok(())
 }
 
-fn convert_reader<R>(reader: &mut R, dst_file: File, dst_type: ImageType) -> Result<()>
+fn convert_reader<R>(reader: &mut R, dst_file: RawFile, dst_type: ImageType) -> Result<()>
 where
     R: Read + Seek + SeekHole,
 {
@@ -1666,8 +1665,8 @@ where
 /// Copy the contents of a disk image in `src_file` into `dst_file`.
 /// The type of `src_file` is automatically detected, and the output file type is
 /// determined by `dst_type`.
-pub fn convert(src_file: File, dst_file: File, dst_type: ImageType) -> Result<()> {
-    let src_type = detect_image_type(&src_file)?;
+pub fn convert(mut src_file: RawFile, dst_file: RawFile, dst_type: ImageType) -> Result<()> {
+    let src_type = detect_image_type(&mut src_file)?;
     match src_type {
         ImageType::Qcow2 => {
             let mut src_reader = QcowFile::from(src_file)?;
@@ -1682,17 +1681,18 @@ pub fn convert(src_file: File, dst_file: File, dst_type: ImageType) -> Result<()
 }
 
 /// Detect the type of an image file by checking for a valid qcow2 header.
-pub fn detect_image_type(file: &File) -> Result<ImageType> {
-    let mut f = file;
-    let orig_seek = f.seek(SeekFrom::Current(0)).map_err(Error::SeekingFile)?;
-    f.seek(SeekFrom::Start(0)).map_err(Error::SeekingFile)?;
-    let magic = f.read_u32::<BigEndian>().map_err(Error::ReadingHeader)?;
+pub fn detect_image_type(file: &mut RawFile) -> Result<ImageType> {
+    let orig_seek = file
+        .seek(SeekFrom::Current(0))
+        .map_err(Error::SeekingFile)?;
+    file.seek(SeekFrom::Start(0)).map_err(Error::SeekingFile)?;
+    let magic = file.read_u32::<BigEndian>().map_err(Error::ReadingHeader)?;
     let image_type = if magic == QCOW_MAGIC {
         ImageType::Qcow2
     } else {
         ImageType::Raw
     };
-    f.seek(SeekFrom::Start(orig_seek))
+    file.seek(SeekFrom::Start(orig_seek))
         .map_err(Error::SeekingFile)?;
     Ok(image_type)
 }
@@ -1700,7 +1700,6 @@ pub fn detect_image_type(file: &File) -> Result<ImageType> {
 #[cfg(test)]
 mod tests {
     use super::*;
-    use std::fs::File;
     use std::io::{Read, Seek, SeekFrom, Write};
     use tempfile::tempfile;
 
@@ -1771,9 +1770,9 @@ mod tests {
 
     fn with_basic_file<F>(header: &[u8], mut testfn: F)
     where
-        F: FnMut(File),
+        F: FnMut(RawFile),
     {
-        let mut disk_file: File = tempfile().unwrap();
+        let mut disk_file: RawFile = RawFile::new(tempfile().unwrap(), false);
         disk_file.write_all(&header).unwrap();
         disk_file.set_len(0x1_0000_0000).unwrap();
         disk_file.seek(SeekFrom::Start(0)).unwrap();
@@ -1781,11 +1780,11 @@ mod tests {
         testfn(disk_file); // File closed when the function exits.
     }
 
-    fn with_default_file<F>(file_size: u64, mut testfn: F)
+    fn with_default_file<F>(file_size: u64, direct: bool, mut testfn: F)
     where
         F: FnMut(QcowFile),
     {
-        let tmp = tempfile().unwrap();
+        let tmp: RawFile = RawFile::new(tempfile().unwrap(), direct);
         let qcow_file = QcowFile::new(tmp, 3, file_size).unwrap();
 
         testfn(qcow_file); // File closed when the function exits.
@@ -1794,7 +1793,7 @@ mod tests {
     #[test]
     fn default_header_v2() {
         let header = QcowHeader::create_for_size(2, 0x10_0000);
-        let mut disk_file: File = tempfile().unwrap();
+        let mut disk_file: RawFile = RawFile::new(tempfile().unwrap(), false);
         header
             .write_to(&mut disk_file)
             .expect("Failed to write header to temporary file.");
@@ -1805,7 +1804,7 @@ mod tests {
     #[test]
     fn default_header_v3() {
         let header = QcowHeader::create_for_size(3, 0x10_0000);
-        let mut disk_file: File = tempfile().unwrap();
+        let mut disk_file: RawFile = RawFile::new(tempfile().unwrap(), false);
         header
             .write_to(&mut disk_file)
             .expect("Failed to write header to temporary file.");
@@ -1815,13 +1814,13 @@ mod tests {
 
     #[test]
     fn header_read() {
-        with_basic_file(&valid_header_v2(), |mut disk_file: File| {
+        with_basic_file(&valid_header_v2(), |mut disk_file: RawFile| {
             let header = QcowHeader::new(&mut disk_file).expect("Failed to create Header.");
             assert_eq!(header.version, 2);
             assert_eq!(header.refcount_order, DEFAULT_REFCOUNT_ORDER);
             assert_eq!(header.header_size, V2_BARE_HEADER_SIZE);
         });
-        with_basic_file(&valid_header_v3(), |mut disk_file: File| {
+        with_basic_file(&valid_header_v3(), |mut disk_file: RawFile| {
             let header = QcowHeader::new(&mut disk_file).expect("Failed to create Header.");
             assert_eq!(header.version, 3);
             assert_eq!(header.refcount_order, DEFAULT_REFCOUNT_ORDER);
@@ -1832,7 +1831,7 @@ mod tests {
     #[test]
     fn invalid_magic() {
         let invalid_header = vec![0x51u8, 0x46, 0x4a, 0xfb];
-        with_basic_file(&invalid_header, |mut disk_file: File| {
+        with_basic_file(&invalid_header, |mut disk_file: RawFile| {
             QcowHeader::new(&mut disk_file).expect_err("Invalid header worked.");
         });
     }
@@ -1841,7 +1840,7 @@ mod tests {
     fn invalid_refcount_order() {
         let mut header = valid_header_v3();
         header[99] = 2;
-        with_basic_file(&header, |disk_file: File| {
+        with_basic_file(&header, |disk_file: RawFile| {
             QcowFile::from(disk_file).expect_err("Invalid refcount order worked.");
         });
     }
@@ -1850,7 +1849,7 @@ mod tests {
     fn invalid_cluster_bits() {
         let mut header = valid_header_v3();
         header[23] = 3;
-        with_basic_file(&header, |disk_file: File| {
+        with_basic_file(&header, |disk_file: RawFile| {
             QcowFile::from(disk_file).expect_err("Failed to create file.");
         });
     }
@@ -1858,7 +1857,7 @@ mod tests {
     #[test]
     fn test_header_huge_file() {
         let header = test_huge_header();
-        with_basic_file(&header, |disk_file: File| {
+        with_basic_file(&header, |disk_file: RawFile| {
             QcowFile::from(disk_file).expect_err("Failed to create file.");
         });
     }
@@ -1867,7 +1866,7 @@ mod tests {
     fn test_header_crazy_file_size_rejected() {
         let mut header = valid_header_v3();
         &mut header[24..32].copy_from_slice(&[0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1e]);
-        with_basic_file(&header, |disk_file: File| {
+        with_basic_file(&header, |disk_file: RawFile| {
             QcowFile::from(disk_file).expect_err("Failed to create file.");
         });
     }
@@ -1876,7 +1875,7 @@ mod tests {
     fn test_huge_l1_table() {
         let mut header = valid_header_v3();
         header[36] = 0x12;
-        with_basic_file(&header, |disk_file: File| {
+        with_basic_file(&header, |disk_file: RawFile| {
             QcowFile::from(disk_file).expect_err("Failed to create file.");
         });
     }
@@ -1888,7 +1887,7 @@ mod tests {
         header[26] = 1;
         header[31] = 0;
         // 1 TB with the min cluster size makes the arrays too big, it should fail.
-        with_basic_file(&header, |disk_file: File| {
+        with_basic_file(&header, |disk_file: RawFile| {
             QcowFile::from(disk_file).expect_err("Failed to create file.");
         });
     }
@@ -1902,7 +1901,7 @@ mod tests {
         header[31] = 0;
         // set cluster_bits
         header[23] = 16;
-        with_basic_file(&header, |disk_file: File| {
+        with_basic_file(&header, |disk_file: RawFile| {
             let mut qcow = QcowFile::from(disk_file).expect("Failed to create file.");
             qcow.seek(SeekFrom::Start(0x100_0000_0000 - 8))
                 .expect("Failed to seek.");
@@ -1916,7 +1915,7 @@ mod tests {
     fn test_header_huge_num_refcounts() {
         let mut header = valid_header_v3();
         &mut header[56..60].copy_from_slice(&[0x02, 0x00, 0xe8, 0xff]);
-        with_basic_file(&header, |disk_file: File| {
+        with_basic_file(&header, |disk_file: RawFile| {
             QcowFile::from(disk_file).expect_err("Created disk with crazy refcount clusters");
         });
     }
@@ -1925,14 +1924,14 @@ mod tests {
     fn test_header_huge_refcount_offset() {
         let mut header = valid_header_v3();
         &mut header[48..56].copy_from_slice(&[0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02, 0x00]);
-        with_basic_file(&header, |disk_file: File| {
+        with_basic_file(&header, |disk_file: RawFile| {
             QcowFile::from(disk_file).expect_err("Created disk with crazy refcount offset");
         });
     }
 
     #[test]
     fn write_read_start() {
-        with_basic_file(&valid_header_v3(), |disk_file: File| {
+        with_basic_file(&valid_header_v3(), |disk_file: RawFile| {
             let mut q = QcowFile::from(disk_file).unwrap();
             q.write(b"test first bytes")
                 .expect("Failed to write test string.");
@@ -1945,7 +1944,7 @@ mod tests {
 
     #[test]
     fn offset_write_read() {
-        with_basic_file(&valid_header_v3(), |disk_file: File| {
+        with_basic_file(&valid_header_v3(), |disk_file: RawFile| {
             let mut q = QcowFile::from(disk_file).unwrap();
             let b = [0x55u8; 0x1000];
             q.seek(SeekFrom::Start(0xfff2000)).expect("Failed to seek.");
@@ -1959,7 +1958,7 @@ mod tests {
 
     #[test]
     fn write_zeroes_read() {
-        with_basic_file(&valid_header_v3(), |disk_file: File| {
+        with_basic_file(&valid_header_v3(), |disk_file: RawFile| {
             let mut q = QcowFile::from(disk_file).unwrap();
             // Write some test data.
             let b = [0x55u8; 0x1000];
@@ -1985,7 +1984,7 @@ mod tests {
         // Choose a size that is larger than a cluster.
         // valid_header uses cluster_bits = 12, which corresponds to a cluster size of 4096.
         const CHUNK_SIZE: usize = 4096 * 2 + 512;
-        with_basic_file(&valid_header_v3(), |disk_file: File| {
+        with_basic_file(&valid_header_v3(), |disk_file: RawFile| {
             let mut q = QcowFile::from(disk_file).unwrap();
             // Write some test data.
             let b = [0x55u8; CHUNK_SIZE];
@@ -2006,11 +2005,11 @@ mod tests {
 
     #[test]
     fn test_header() {
-        with_basic_file(&valid_header_v2(), |disk_file: File| {
+        with_basic_file(&valid_header_v2(), |disk_file: RawFile| {
             let q = QcowFile::from(disk_file).unwrap();
             assert_eq!(q.virtual_size(), 0x20_0000_0000);
         });
-        with_basic_file(&valid_header_v3(), |disk_file: File| {
+        with_basic_file(&valid_header_v3(), |disk_file: RawFile| {
             let q = QcowFile::from(disk_file).unwrap();
             assert_eq!(q.virtual_size(), 0x20_0000_0000);
         });
@@ -2018,7 +2017,7 @@ mod tests {
 
     #[test]
     fn read_small_buffer() {
-        with_basic_file(&valid_header_v3(), |disk_file: File| {
+        with_basic_file(&valid_header_v3(), |disk_file: RawFile| {
             let mut q = QcowFile::from(disk_file).unwrap();
             let mut b = [5u8; 16];
             q.seek(SeekFrom::Start(1000)).expect("Failed to seek.");
@@ -2030,7 +2029,7 @@ mod tests {
 
     #[test]
     fn replay_ext4() {
-        with_basic_file(&valid_header_v3(), |disk_file: File| {
+        with_basic_file(&valid_header_v3(), |disk_file: RawFile| {
             let mut q = QcowFile::from(disk_file).unwrap();
             const BUF_SIZE: usize = 0x1000;
             let mut b = [0u8; BUF_SIZE];
@@ -2406,7 +2405,16 @@ mod tests {
 
     #[test]
     fn combo_write_read() {
-        with_default_file(1024 * 1024 * 1024 * 256, |mut qcow_file| {
+        combo_write_read_common(false);
+    }
+
+    #[test]
+    fn combo_write_read_direct() {
+        combo_write_read_common(true);
+    }
+
+    fn combo_write_read_common(direct: bool) {
+        with_default_file(1024 * 1024 * 1024 * 256, direct, |mut qcow_file| {
             const NUM_BLOCKS: usize = 555;
             const BLOCK_SIZE: usize = 0x1_0000;
             const OFFSET: usize = 0x1_0000_0020;
@@ -2459,7 +2467,16 @@ mod tests {
 
     #[test]
     fn seek_data() {
-        with_default_file(0x30000, |mut file| {
+        seek_data_common(false);
+    }
+
+    #[test]
+    fn seek_data_direct() {
+        seek_data_common(true);
+    }
+
+    fn seek_data_common(direct: bool) {
+        with_default_file(0x30000, direct, |mut file| {
             // seek_data at or after the end of the file should return None
             assert_eq!(file.seek_data(0x10000).unwrap(), None);
             assert_eq!(seek_cur(&mut file), 0);
@@ -2492,7 +2509,16 @@ mod tests {
 
     #[test]
     fn seek_hole() {
-        with_default_file(0x30000, |mut file| {
+        seek_hole_common(false);
+    }
+
+    #[test]
+    fn seek_hole_direct() {
+        seek_hole_common(true);
+    }
+
+    fn seek_hole_common(direct: bool) {
+        with_default_file(0x30000, direct, |mut file| {
             // File consisting entirely of a hole
             assert_eq!(file.seek_hole(0).unwrap(), Some(0));
             assert_eq!(seek_cur(&mut file), 0);
@@ -2566,7 +2592,7 @@ mod tests {
 
     #[test]
     fn rebuild_refcounts() {
-        with_basic_file(&valid_header_v3(), |mut disk_file: File| {
+        with_basic_file(&valid_header_v3(), |mut disk_file: RawFile| {
             let header = QcowHeader::new(&mut disk_file).expect("Failed to create Header.");
             let cluster_size = 65536;
             let mut raw_file =

qcow/src/qcow_raw_file.rs

@@ -2,17 +2,16 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE-BSD-3-Clause file.
 
-use std::fs::File;
+use super::RawFile;
+use byteorder::{BigEndian, ReadBytesExt, WriteBytesExt};
 use std::io::{self, BufWriter, Seek, SeekFrom};
 use std::mem::size_of;
-
-use byteorder::{BigEndian, ReadBytesExt, WriteBytesExt};
 use vmm_sys_util::write_zeroes::WriteZeroes;
 
 /// A qcow file. Allows reading/writing clusters and appending clusters.
 #[derive(Debug)]
 pub struct QcowRawFile {
-    file: File,
+    file: RawFile,
     cluster_size: u64,
     cluster_mask: u64,
 }
@@ -20,7 +19,7 @@ pub struct QcowRawFile {
 impl QcowRawFile {
     /// Creates a `QcowRawFile` from the given `File`, `None` is returned if `cluster_size` is not
     /// a power of two.
-    pub fn from(file: File, cluster_size: u64) -> Option<Self> {
+    pub fn from(file: RawFile, cluster_size: u64) -> Option<Self> {
         if cluster_size.count_ones() != 1 {
             return None;
         }
@@ -67,7 +66,7 @@ impl QcowRawFile {
         non_zero_flags: u64,
     ) -> io::Result<()> {
         self.file.seek(SeekFrom::Start(offset))?;
-        let mut buffer = BufWriter::with_capacity(table.len() * size_of::<u64>(), &self.file);
+        let mut buffer = BufWriter::with_capacity(table.len() * size_of::<u64>(), &mut self.file);
         for addr in table {
             let val = if *addr == 0 {
                 0
@@ -92,7 +91,7 @@ impl QcowRawFile {
     /// Writes a refcount block to the file.
     pub fn write_refcount_block(&mut self, offset: u64, table: &[u16]) -> io::Result<()> {
         self.file.seek(SeekFrom::Start(offset))?;
-        let mut buffer = BufWriter::with_capacity(table.len() * size_of::<u16>(), &self.file);
+        let mut buffer = BufWriter::with_capacity(table.len() * size_of::<u16>(), &mut self.file);
         for count in table {
             buffer.write_u16::<BigEndian>(*count)?;
         }
@@ -115,13 +114,8 @@ impl QcowRawFile {
         Ok(Some(new_cluster_address))
     }
 
-    /// Returns a reference to the underlying file.
-    pub fn file(&self) -> &File {
-        &self.file
-    }
-
     /// Returns a mutable reference to the underlying file.
-    pub fn file_mut(&mut self) -> &mut File {
+    pub fn file_mut(&mut self) -> &mut RawFile {
         &mut self.file
     }
 

qcow/src/raw_file.rs

@@ -0,0 +1,324 @@
+// Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style license that can be
+// found in the LICENSE-BSD-3-Clause file.
+//
+// Copyright © 2020 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
+
+use libc::c_void;
+use std::alloc::{alloc_zeroed, dealloc, Layout};
+use std::convert::TryInto;
+use std::fs::{File, Metadata};
+use std::io::{self, Read, Seek, SeekFrom, Write};
+use std::os::unix::io::{AsRawFd, RawFd};
+use std::slice;
+use vmm_sys_util::{seek_hole::SeekHole, write_zeroes::PunchHole};
+
+#[derive(Debug)]
+pub struct RawFile {
+    file: File,
+    alignment: usize,
+    position: u64,
+}
+
+const BLK_ALIGNMENTS: [usize; 2] = [512, 4096];
+
+fn is_valid_alignment(fd: RawFd, alignment: usize) -> bool {
+    let layout = Layout::from_size_align(alignment, alignment).unwrap();
+    let ptr = unsafe { alloc_zeroed(layout) };
+
+    let ret = unsafe {
+        ::libc::pread(
+            fd,
+            ptr as *mut c_void,
+            alignment,
+            alignment.try_into().unwrap(),
+        )
+    };
+
+    unsafe { dealloc(ptr, layout) };
+
+    ret >= 0
+}
+
+impl RawFile {
+    pub fn new(file: File, direct_io: bool) -> Self {
+        // Assume no alignment restrictions if we aren't using O_DIRECT.
+        let mut alignment = 0;
+        if direct_io {
+            for align in &BLK_ALIGNMENTS {
+                if is_valid_alignment(file.as_raw_fd(), *align) {
+                    alignment = *align;
+                    break;
+                }
+            }
+        }
+        RawFile {
+            file,
+            alignment: alignment.try_into().unwrap(),
+            position: 0,
+        }
+    }
+
+    fn round_up(&self, offset: u64) -> u64 {
+        let align: u64 = self.alignment.try_into().unwrap();
+        ((offset / (align + 1)) + 1) * align
+    }
+
+    fn round_down(&self, offset: u64) -> u64 {
+        let align: u64 = self.alignment.try_into().unwrap();
+        (offset / align) * align
+    }
+
+    fn is_aligned(&self, buf: &[u8]) -> bool {
+        if self.alignment == 0 {
+            return true;
+        }
+
+        let align64: u64 = self.alignment.try_into().unwrap();
+
+        (self.position % align64 == 0)
+            && ((buf.as_ptr() as usize) % self.alignment == 0)
+            && (buf.len() % self.alignment == 0)
+    }
+
+    pub fn set_len(&self, size: u64) -> std::io::Result<()> {
+        self.file.set_len(size)
+    }
+
+    pub fn metadata(&self) -> std::io::Result<Metadata> {
+        self.file.metadata()
+    }
+
+    pub fn try_clone(&self) -> std::io::Result<RawFile> {
+        Ok(RawFile {
+            file: self.file.try_clone().expect("RawFile cloning failed"),
+            alignment: self.alignment,
+            position: self.position,
+        })
+    }
+
+    pub fn sync_all(&self) -> std::io::Result<()> {
+        self.file.sync_all()
+    }
+
+    pub fn sync_data(&self) -> std::io::Result<()> {
+        self.file.sync_data()
+    }
+}
+
+impl Read for RawFile {
+    fn read(&mut self, buf: &mut [u8]) -> std::io::Result<usize> {
+        if self.is_aligned(buf) {
+            match self.file.read(buf) {
+                Ok(r) => {
+                    self.position = self.position.checked_add(r.try_into().unwrap()).unwrap();
+                    Ok(r)
+                }
+                Err(e) => Err(e),
+            }
+        } else {
+            let rounded_pos: u64 = self.round_down(self.position);
+            let file_offset: usize = self
+                .position
+                .checked_sub(rounded_pos)
+                .unwrap()
+                .try_into()
+                .unwrap();
+            let buf_len: usize = buf.len();
+            let rounded_len: usize = self
+                .round_up(
+                    file_offset
+                        .checked_add(buf_len)
+                        .unwrap()
+                        .try_into()
+                        .unwrap(),
+                )
+                .try_into()
+                .unwrap();
+
+            let layout = Layout::from_size_align(rounded_len, self.alignment).unwrap();
+            let tmp_ptr = unsafe { alloc_zeroed(layout) };
+            let tmp_buf = unsafe { slice::from_raw_parts_mut(tmp_ptr, rounded_len) };
+
+            // This can eventually replaced with read_at once its interface
+            // has been stabilized.
+            let ret = unsafe {
+                ::libc::pread64(
+                    self.file.as_raw_fd(),
+                    tmp_buf.as_mut_ptr() as *mut c_void,
+                    tmp_buf.len(),
+                    rounded_pos.try_into().unwrap(),
+                )
+            };
+            if ret < 0 {
+                unsafe { dealloc(tmp_ptr, layout) };
+                return Err(io::Error::last_os_error());
+            }
+
+            let read: usize = ret.try_into().unwrap();
+            if read < file_offset {
+                unsafe { dealloc(tmp_ptr, layout) };
+                return Ok(0);
+            }
+
+            let mut to_copy = read - file_offset;
+            if to_copy > buf_len {
+                to_copy = buf_len;
+            }
+
+            buf.copy_from_slice(&tmp_buf[file_offset..(file_offset + buf_len)]);
+            unsafe { dealloc(tmp_ptr, layout) };
+
+            self.seek(SeekFrom::Current(to_copy.try_into().unwrap()))
+                .unwrap();
+            Ok(to_copy.try_into().unwrap())
+        }
+    }
+}
+
+impl Write for RawFile {
+    fn write(&mut self, buf: &[u8]) -> std::io::Result<usize> {
+        if self.is_aligned(buf) {
+            match self.file.write(buf) {
+                Ok(r) => {
+                    self.position = self.position.checked_add(r.try_into().unwrap()).unwrap();
+                    Ok(r)
+                }
+                Err(e) => Err(e),
+            }
+        } else {
+            let rounded_pos: u64 = self.round_down(self.position);
+            let file_offset: usize = self
+                .position
+                .checked_sub(rounded_pos)
+                .unwrap()
+                .try_into()
+                .unwrap();
+            let buf_len: usize = buf.len();
+            let rounded_len: usize = self
+                .round_up(
+                    file_offset
+                        .checked_add(buf_len)
+                        .unwrap()
+                        .try_into()
+                        .unwrap(),
+                )
+                .try_into()
+                .unwrap();
+
+            let layout = Layout::from_size_align(rounded_len, self.alignment).unwrap();
+            let tmp_ptr = unsafe { alloc_zeroed(layout) };
+            let tmp_buf = unsafe { slice::from_raw_parts_mut(tmp_ptr, rounded_len) };
+
+            // This can eventually replaced with read_at once its interface
+            // has been stabilized.
+            let ret = unsafe {
+                ::libc::pread64(
+                    self.file.as_raw_fd(),
+                    tmp_buf.as_mut_ptr() as *mut c_void,
+                    tmp_buf.len(),
+                    rounded_pos.try_into().unwrap(),
+                )
+            };
+            if ret < 0 {
+                unsafe { dealloc(tmp_ptr, layout) };
+                return Err(io::Error::last_os_error());
+            };
+
+            tmp_buf[file_offset..(file_offset + buf_len)].copy_from_slice(buf);
+
+            // This can eventually replaced with write_at once its interface
+            // has been stabilized.
+            let ret = unsafe {
+                ::libc::pwrite64(
+                    self.file.as_raw_fd(),
+                    tmp_buf.as_ptr() as *const c_void,
+                    tmp_buf.len(),
+                    rounded_pos.try_into().unwrap(),
+                )
+            };
+
+            unsafe { dealloc(tmp_ptr, layout) };
+
+            if ret < 0 {
+                return Err(io::Error::last_os_error());
+            }
+
+            let written: usize = ret.try_into().unwrap();
+            if written < file_offset {
+                Ok(0)
+            } else {
+                let mut to_seek = written - file_offset;
+                if to_seek > buf_len {
+                    to_seek = buf_len;
+                }
+
+                self.seek(SeekFrom::Current(to_seek.try_into().unwrap()))
+                    .unwrap();
+                Ok(to_seek.try_into().unwrap())
+            }
+        }
+    }
+
+    fn flush(&mut self) -> std::io::Result<()> {
+        self.file.sync_all()
+    }
+}
+
+impl Seek for RawFile {
+    fn seek(&mut self, newpos: SeekFrom) -> std::io::Result<u64> {
+        match self.file.seek(newpos) {
+            Ok(pos) => {
+                self.position = pos;
+                Ok(pos)
+            }
+            Err(e) => Err(e),
+        }
+    }
+}
+
+impl PunchHole for RawFile {
+    fn punch_hole(&mut self, offset: u64, length: u64) -> std::io::Result<()> {
+        self.file.punch_hole(offset, length)
+    }
+}
+
+impl SeekHole for RawFile {
+    fn seek_hole(&mut self, offset: u64) -> std::io::Result<Option<u64>> {
+        match self.file.seek_hole(offset) {
+            Ok(pos) => {
+                if let Some(p) = pos {
+                    self.position = p;
+                }
+                Ok(pos)
+            }
+            Err(e) => Err(e),
+        }
+    }
+
+    fn seek_data(&mut self, offset: u64) -> std::io::Result<Option<u64>> {
+        match self.file.seek_data(offset) {
+            Ok(pos) => {
+                if let Some(p) = pos {
+                    self.position = p;
+                }
+                Ok(pos)
+            }
+            Err(e) => Err(e),
+        }
+    }
+}
+
+impl Clone for RawFile {
+    fn clone(&self) -> Self {
+        RawFile {
+            file: self.file.try_clone().expect("RawFile cloning failed"),
+            alignment: self.alignment,
+            position: self.position,
+        }
+    }
+}

qcow/src/refcount.rs

@@ -2,7 +2,6 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE-BSD-3-Clause file.
 
-use std;
 use std::fmt::{self, Display};
 use std::io;
 

qcow/src/vec_cache.rs

@@ -120,7 +120,7 @@ impl<T: Cacheable> CacheMap<T> {
     {
         if self.map.len() == self.capacity {
             // TODO(dgreid) - smarter eviction strategy.
-            let to_evict = *self.map.iter().nth(0).unwrap().0;
+            let to_evict = *self.map.iter().next().unwrap().0;
             if let Some(evicted) = self.map.remove(&to_evict) {
                 if evicted.dirty() {
                     write_callback(to_evict, evicted)?;