build: Release 20.1 (bug fix release)

Signed-off-by: Rob Bradford <robert.bradford@intel.com>

.github/ISSUE_TEMPLATE/bug_report.md

@@ -0,0 +1,34 @@
+---
+name: Bug report
+about: File a bug report
+title: ''
+labels: ''
+assignees: ''
+
+---
+
+**Describe the bug**
+A clear and concise description of what the bug is.
+
+**To Reproduce**
+Steps to reproduce the behaviour:
+
+**Version**
+
+Output of `cloud-hypervisor --version`:
+
+Did you build from source, if so build command line (e.g. features):
+
+**VM configuration**
+
+What command line did you run (or JSON config data):
+
+Guest OS version details:
+
+Host OS version details:
+
+**Logs**
+
+Output of `cloud-hypervisor -v` from either standard error or via `--log-file`:
+
+Linux kernel output:

.github/dependabot.yml

@@ -0,0 +1,18 @@
+version: 2
+updates:
+- package-ecosystem: cargo
+  directory: "/"
+  schedule:
+    interval: daily
+  open-pull-requests-limit: 3
+  allow:
+  - dependency-type: direct
+  - dependency-type: indirect
+- package-ecosystem: cargo
+  directory: "/fuzz"
+  schedule:
+    interval: daily
+  open-pull-requests-limit: 3
+  allow:
+  - dependency-type: direct
+  - dependency-type: indirect

.github/workflows/audit.yaml

@@ -0,0 +1,15 @@
+name: Cloud Hypervisor Dependency Audit
+on:
+  pull_request:
+    paths: 
+      - '**/Cargo.toml'
+      - '**/Cargo.lock'
+jobs:
+  security_audit:
+    name: Audit
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v1
+      - uses: actions-rs/audit-check@v1
+        with:
+          token: ${{ secrets.GITHUB_TOKEN }}

.github/workflows/build.yaml

@@ -7,6 +7,7 @@ jobs:
     name: Build
     runs-on: ubuntu-latest
     strategy:
+      fail-fast: false
       matrix:
         rust:
           - stable
@@ -18,6 +19,9 @@ jobs:
     steps:
       - name: Code checkout
         uses: actions/checkout@v2
+        with:
+          fetch-depth: 0
+
       - name: Install Rust toolchain (${{ matrix.rust }})
         uses: actions-rs/toolchain@v1
         with:
@@ -25,5 +29,28 @@ jobs:
             target: ${{ matrix.target }}
             override: true
 
-      - name: Build
-        run: cargo build --release --target=${{ matrix.target }}
+      - name: Debug Check (default features)
+        run: |
+          git rev-list origin/main..$GITHUB_SHA | xargs -t -I % sh -c 'git checkout %; cargo check --all --target=${{ matrix.target }}'
+          git checkout $GITHUB_SHA
+
+      - name: Build (default + tdx)
+        run: cargo rustc --bin cloud-hypervisor --features "tdx" -- -D warnings
+
+      - name: Build (acpi,kvm)
+        run: cargo rustc --bin cloud-hypervisor --no-default-features --features "acpi,kvm"  -- -D warnings
+
+      - name: Build (kvm)
+        run: cargo rustc --bin cloud-hypervisor --no-default-features --features "kvm"  -- -D warnings
+
+      - name: Build (acpi,mshv)
+        run: cargo rustc --bin cloud-hypervisor --no-default-features --features "acpi,mshv"  -- -D warnings
+
+      - name: Build (mshv)
+        run: cargo rustc --bin cloud-hypervisor --no-default-features --features "mshv"  -- -D warnings
+        
+      - name: Release Build (default features)
+        run: cargo build --all --release --target=${{ matrix.target }}
+
+      - name: Check build did not modify any files
+        run: test -z "$(git status --porcelain)"

.github/workflows/dco.yaml

@@ -0,0 +1,18 @@
+name: DCO
+on:
+  pull_request:
+jobs:
+  check:
+    runs-on: ubuntu-latest
+    steps:
+    - uses: actions/checkout@v2
+    - name: Set up Python 3.x
+      uses: actions/setup-python@v1
+      with:
+        python-version: '3.x'
+    - name: Check DCO
+      env:
+        GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+      run: |
+        pip3 install -U dco-check
+        dco-check -e "49699333+dependabot[bot]@users.noreply.github.com"

.github/workflows/docker-image.yaml

@@ -0,0 +1,48 @@
+name: Cloud Hypervisor's Docker image update
+
+on:
+  push:
+    branches: main
+    paths: resources/Dockerfile
+  pull_request:
+    paths: resources/Dockerfile
+
+jobs:
+  main:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Code checkout
+        uses: actions/checkout@v2
+
+      - name: Set up QEMU
+        uses: docker/setup-qemu-action@v1
+
+      - name: Set up Docker Buildx
+        uses: docker/setup-buildx-action@v1
+
+      - name: Login to DockerHub
+        if: ${{ github.event_name == 'push' }}
+        uses: docker/login-action@v1 
+        with:
+          username: ${{ secrets.DOCKERHUB_USERNAME }}
+          password: ${{ secrets.DOCKERHUB_TOKEN }}
+
+      - name: Build and push
+        if: ${{ github.event_name == 'push' }}
+        uses: docker/build-push-action@v2
+        with:
+          file: ./resources/Dockerfile
+          platforms: linux/amd64,linux/arm64
+          push: true
+          tags: cloudhypervisor/dev:latest
+
+      - name: Build only
+        if: ${{ github.event_name == 'pull_request' }}
+        uses: docker/build-push-action@v2
+        with:
+          file: ./resources/Dockerfile
+          platforms: linux/amd64,linux/arm64
+          tags: cloudhypervisor/dev:latest
+
+      - name: Image digest
+        run: echo ${{ steps.docker_build.outputs.digest }}

.github/workflows/fuzz-build.yaml

@@ -0,0 +1,29 @@
+name: Cloud Hypervisor Cargo Fuzz Build
+on: [pull_request, create]
+
+jobs:
+  build:
+    if: github.event_name == 'pull_request'
+    name: Cargo Fuzz Build
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        rust:
+          - nightly
+        target:
+          - x86_64-unknown-linux-gnu
+    steps:
+      - name: Code checkout
+        uses: actions/checkout@v2
+      - name: Install Rust toolchain (${{ matrix.rust }})
+        uses: actions-rs/toolchain@v1
+        with:
+            toolchain: ${{ matrix.rust }}
+            target: ${{ matrix.target }}
+            override: true
+      - name: Install Cargo fuzz
+        # Temporary fix for cargo-fuzz on latest nightly: https://github.com/rust-fuzz/cargo-fuzz/issues/276
+        #run: cargo install cargo-fuzz
+        run: cargo install --git https://github.com/rust-fuzz/cargo-fuzz --rev b4df3e58f767b5cad8d1aa6753961003f56f3609
+      - name: Cargo Fuzz Build
+        run: cargo fuzz build

.github/workflows/quality-aarch64.yaml

@@ -0,0 +1,61 @@
+name: Cloud Hypervisor Quality Checks
+on: [pull_request, create]
+
+jobs:
+  build:
+    if: github.event_name == 'pull_request'
+    name: Quality (clippy, rustfmt)
+    runs-on: ubuntu-latest
+    continue-on-error: ${{ matrix.experimental }}
+    strategy:
+      fail-fast: false
+      matrix:
+        rust:
+          - stable
+        target:
+          - aarch64-unknown-linux-gnu
+        experimental: [false]
+        include:
+          - rust: beta
+            target: aarch64-unknown-linux-gnu
+            experimental: true
+    steps:
+      - name: Code checkout
+        uses: actions/checkout@v2
+      - name: Install Rust toolchain (${{ matrix.rust }})
+        uses: actions-rs/toolchain@v1
+        with:
+            toolchain: ${{ matrix.rust }}
+            target: ${{ matrix.target }}
+            override: true
+            components: rustfmt, clippy
+      - name: Formatting (rustfmt)
+        run: cargo fmt -- --check
+
+      - name: Clippy (kvm)
+        uses: actions-rs/cargo@v1
+        with:
+          use-cross: true
+          command: clippy
+          args: --target=${{ matrix.target }} --all --no-default-features --features "kvm" -- -D warnings
+
+      - name: Clippy (kvm,acpi)
+        uses: actions-rs/cargo@v1
+        with:
+          use-cross: true
+          command: clippy
+          args: --target=${{ matrix.target }} --all --no-default-features --features "kvm,acpi" -- -D warnings
+
+      - name: Clippy (all features,kvm)
+        uses: actions-rs/cargo@v1
+        with:
+          use-cross: true
+          command: clippy
+          args: --target=${{ matrix.target }} --all --no-default-features --features "common,kvm" -- -D warnings
+
+      - name: Clippy (default)
+        uses: actions-rs/cargo@v1
+        with:
+          use-cross: true
+          command: clippy
+          args: --target=${{ matrix.target }} --all -- -D warnings

.github/workflows/quality.yaml

@@ -0,0 +1,61 @@
+name: Cloud Hypervisor Quality Checks
+on: [pull_request, create]
+
+jobs:
+  build:
+    if: github.event_name == 'pull_request'
+    name: Quality (clippy, rustfmt)
+    runs-on: ubuntu-latest
+    continue-on-error: ${{ matrix.experimental }}
+    strategy:
+      fail-fast: false
+      matrix:
+        rust:
+          - stable
+        target:
+          - x86_64-unknown-linux-gnu
+        experimental: [false]
+        include:
+          - rust: beta
+            target: x86_64-unknown-linux-gnu
+            experimental: true
+    steps:
+      - name: Code checkout
+        uses: actions/checkout@v2
+      - name: Install Rust toolchain (${{ matrix.rust }})
+        uses: actions-rs/toolchain@v1
+        with:
+          toolchain: ${{ matrix.rust }}
+          target: ${{ matrix.target }}
+          override: true
+          components: rustfmt, clippy
+
+      - name: Formatting (rustfmt)
+        run: cargo fmt -- --check
+
+      - name: Clippy (all features,kvm)
+        run: cargo clippy --all --all-targets --no-default-features --tests --features "common,kvm" -- -D warnings
+
+      - name: Clippy (all features,mshv)
+        run: cargo clippy --all --all-targets --no-default-features --tests --features "common,mshv" -- -D warnings
+
+      - name: Clippy (acpi,kvm)
+        run: cargo clippy --all --all-targets --no-default-features --tests --features "acpi,kvm" -- -D warnings
+
+      - name: Clippy (acpi,kvm,tdx)
+        run: cargo clippy --all --all-targets --no-default-features --tests --features "acpi,kvm,tdx" -- -D warnings
+
+      - name: Clippy (kvm)
+        run: cargo clippy --all --all-targets --no-default-features --tests --features "kvm" -- -D warnings
+
+      - name: Clippy (acpi,mshv)
+        run: cargo clippy --all --all-targets --no-default-features --tests --features "acpi,mshv" -- -D warnings
+
+      - name: Clippy (mshv)
+        run: cargo clippy --all --all-targets --no-default-features --tests --features "mshv" -- -D warnings
+
+      - name: Clippy (integration tests)
+        run: cargo clippy --all --all-targets --tests --features "integration_tests" -- -D warnings
+
+      - name: Check build did not modify any files
+        run: test -z "$(git status --porcelain)"

.github/workflows/release.yaml

@@ -9,6 +9,8 @@ jobs:
     steps:
       - name: Code checkout
         uses: actions/checkout@v2
+      - name: Create release directory
+        run: rsync -rv --exclude=.git . ../cloud-hypervisor-${{ github.event.ref }}
       - name: Install Rust toolchain (x86_64-unknown-linux-gnu)
         uses: actions-rs/toolchain@v1
         with:
@@ -20,9 +22,30 @@ jobs:
             toolchain: stable
             target: x86_64-unknown-linux-musl
       - name: Build
-        run: cargo build --release --target=x86_64-unknown-linux-gnu
+        run: cargo build --all --release --target=x86_64-unknown-linux-gnu
       - name: Static Build
-        run: cargo build --release --target=x86_64-unknown-linux-musl
+        run: cargo build --all --release --target=x86_64-unknown-linux-musl
+      - name: Strip cloud-hypervisor binaries
+        run: strip target/*/release/cloud-hypervisor
+      - name: Install Rust toolchain (aarch64-unknown-linux-musl)
+        uses: actions-rs/toolchain@v1
+        with:
+            toolchain: stable
+            target: aarch64-unknown-linux-musl
+            override: true
+      - name: Static Build (AArch64)
+        uses: actions-rs/cargo@v1
+        with:
+            use-cross: true
+            command: build
+            args: --all --release --target=aarch64-unknown-linux-musl
+      - name: Vendor
+        working-directory: ../cloud-hypervisor-${{ github.event.ref }}
+        run: |
+          mkdir ../vendor-cargo-home
+          export CARGO_HOME=$(realpath ../vendor-cargo-home)
+          mkdir .cargo
+          cargo vendor > .cargo/config.toml
       - name: Create Release
         id: create_release
         uses: actions/create-release@v1
@@ -33,6 +56,19 @@ jobs:
           release_name: ${{ github.ref }}
           draft: true
           prerelease: true
+      - name: Create vendored source archive
+        working-directory: ../
+        run:  tar cJf cloud-hypervisor-${{ github.event.ref }}.tar.xz cloud-hypervisor-${{ github.event.ref }}
+      - name: Upload cloud-hypervisor vendored source archive
+        id: upload-release-cloud-hypervisor-vendored-sources
+        uses: actions/upload-release-asset@v1
+        env:
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+        with:
+          upload_url: ${{ steps.create_release.outputs.upload_url }}
+          asset_path: ../cloud-hypervisor-${{ github.event.ref }}.tar.xz
+          asset_name: cloud-hypervisor-${{ github.event.ref }}.tar.xz
+          asset_content_type: application/x-xz
       - name: Upload cloud-hypervisor
         id: upload-release-cloud-hypervisor
         uses: actions/upload-release-asset@v1
@@ -63,3 +99,23 @@ jobs:
           asset_path: target/x86_64-unknown-linux-gnu/release/ch-remote
           asset_name: ch-remote
           asset_content_type: application/octet-stream
+      - name: Upload static AArch64 cloud-hypervisor
+        id: upload-release-static-aarch64-cloud-hypervisor
+        uses: actions/upload-release-asset@v1
+        env:
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+        with:
+          upload_url: ${{ steps.create_release.outputs.upload_url }}
+          asset_path: target/aarch64-unknown-linux-musl/release/cloud-hypervisor
+          asset_name: cloud-hypervisor-static-aarch64
+          asset_content_type: application/octet-stream
+      - name: Upload static AArch64 ch-remote
+        id: upload-release-static-aarch64-ch-remote
+        uses: actions/upload-release-asset@v1
+        env:
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+        with:
+          upload_url: ${{ steps.create_release.outputs.upload_url }}
+          asset_path: target/aarch64-unknown-linux-musl/release/ch-remote
+          asset_name: ch-remote-static-aarch64
+          asset_content_type: application/octet-stream

CONTRIBUTING.md

@@ -1,6 +1,13 @@
 # Contributing to Cloud Hypervisor
 
-Cloud Hypervisor is an open source project licensed under the [Apache v2 License](https://opensource.org/licenses/Apache-2.0) and the [BSD 3 Clause](https://opensource.org/licenses/BSD-3-Clause) license.
+Cloud Hypervisor is an open source project licensed under the [Apache v2
+License](https://opensource.org/licenses/Apache-2.0) and the [BSD 3
+Clause](https://opensource.org/licenses/BSD-3-Clause) license. Contributions
+can be made under either license or both. Individual files contain details of
+their licensing and changes to that file are under the same license unless the
+contribution changes the license of the file. When importing code from a third
+party project (e.g. Firecracker or CrosVM) please respect the license of those
+projects.
 
 ## Coding Style
 
@@ -55,7 +62,7 @@ you want to merge your changes to `cloud-hypervisor`:
    into your github organization.
 2. Within your fork, create a branch for your contribution.
 3. [Create a pull request](https://help.github.com/articles/creating-a-pull-request-from-a-fork/)
-   against the master branch of the Cloud Hypervisor repository.
+   against the main branch of the Cloud Hypervisor repository.
 4. Add reviewers to your pull request and then work with your reviewers to address
    any comments and obtain minimum of 2 [maintainers](MAINTAINERS.md) approvals.
    To update your pull request amend existing commits whenever applicable and
@@ -88,5 +95,5 @@ Fixes #88
 Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
 ```
 
-Then, after the correspoding PR is merged, Github will automatically close that issue when parsing the
+Then, after the corresponding PR is merged, Github will automatically close that issue when parsing the
 [commit message](https://help.github.com/articles/closing-issues-via-commit-messages/).

Cargo.toml

@@ -1,71 +1,94 @@
 [package]
 name = "cloud-hypervisor"
-version = "0.7.0"
+version = "20.1.0"
 authors = ["The Cloud Hypervisor Authors"]
 edition = "2018"
 default-run = "cloud-hypervisor"
 build = "build.rs"
+license = "LICENSE-APACHE & LICENSE-BSD-3-Clause"
+description = "Open source Virtual Machine Monitor (VMM) that runs on top of KVM"
+homepage = "https://github.com/cloud-hypervisor/cloud-hypervisor"
+
+[profile.release]
+lto = true
 
 [dependencies]
-arc-swap = ">=0.4.4"
-clap = { version = "2.33.0", features=["wrap_help"] }
-epoll = ">=4.0.1"
-futures = { version = "0.3.4", features = ["thread-pool"] }
-lazy_static = "1.4.0"
-libc = "0.2.69"
-log = { version = "0.4.8", features = ["std"] }
-seccomp = { git = "https://github.com/firecracker-microvm/firecracker", tag = "v0.21.1" }
-serde_json = ">=1.0.9"
-vhost_user_backend = { path = "vhost_user_backend"}
-vhost_user_block = { path = "vhost_user_block"}
-vhost_user_fs = { path = "vhost_user_fs"}
-vhost_user_net = { path = "vhost_user_net"}
-virtio-bindings = "0.1.0"
+anyhow = "1.0.51"
+api_client = { path = "api_client" }
+clap = { version = "2.34.0", features = ["wrap_help"] }
+epoll = "4.3.1"
+event_monitor = { path = "event_monitor" }
+hypervisor = { path = "hypervisor" }
+libc = "0.2.108"
+log = { version = "0.4.14", features = ["std"] }
+option_parser = { path = "option_parser" }
+seccompiler = "0.2.0"
+serde_json = "1.0.72"
+signal-hook = "0.3.10"
+thiserror = "1.0.30"
 vmm = { path = "vmm" }
-vm-device = { path = "vm-device" }
-vm-memory = "0.2.0"
-vmm-sys-util = "0.5.0"
-vm-virtio = { path = "vm-virtio" }
-vhost_rs = { git = "https://github.com/cloud-hypervisor/vhost", branch = "dragonball", package = "vhost", features = ["vhost-user-slave"] }
+vmm-sys-util = "0.9.0"
+vm-memory = "0.6.0"
+
+[build-dependencies]
+clap = { version = "2.34.0", features = ["wrap_help"] }
+
+# List of patched crates
+[patch.crates-io]
+kvm-bindings = { git = "https://github.com/cloud-hypervisor/kvm-bindings", branch = "ch-v0.5.0", features = ["with-serde", "fam-wrappers"] }
+kvm-ioctls = { git = "https://github.com/rust-vmm/kvm-ioctls", branch = "main" }
+versionize_derive = { git = "https://github.com/cloud-hypervisor/versionize_derive", branch = "ch" }
 
 [dev-dependencies]
-ssh2 = "0.8.0"
-dirs = "2.0.2"
 credibility = "0.1.3"
-tempdir= "0.3.7"
+dirs = "4.0.0"
 lazy_static= "1.4.0"
-tempfile = "3.1.0"
-serde_json = ">=1.0.9"
+net_util = { path = "net_util" }
+serde_json = "1.0.72"
+test_infra = { path = "test_infra" }
+wait-timeout = "0.2.0"
 
 [features]
-default = ["acpi", "pci", "cmos"]
+default = ["common", "kvm"]
+# Common features for all hypervisors
+common = ["acpi", "cmos", "fwdebug", "io_uring"]
 acpi = ["vmm/acpi"]
-pci = ["vmm/pci_support"]
-mmio = ["vmm/mmio_support"]
 cmos = ["vmm/cmos"]
 fwdebug = ["vmm/fwdebug"]
+kvm = ["vmm/kvm"]
+mshv = ["vmm/mshv"]
+io_uring = ["vmm/io_uring"]
+tdx = ["vmm/tdx"]
 
 # Integration tests require a special environment to run in
 integration_tests = []
 
 [workspace]
 members = [
+    "acpi_tables",
+    "api_client",
     "arch",
+    "block_util",
     "devices",
-    "qcow",
+    "event_monitor",
+    "hypervisor",
+    "net_gen",
+    "net_util",
+    "option_parser",
     "pci",
+    "qcow",
+    "rate_limiter",
+    "vfio_user",
+    "vhdx",
+    "vhost_user_backend",
+    "vhost_user_block",
+    "vhost_user_net",
+    "virtio-devices",
+    "virtio-queue",
     "vmm",
-    "vm-virtio",
+    "vm-allocator",
     "vm-device",
     "vm-migration",
-    "vhost_user_block",
-    "vhost_user_backend",
-    "vhost_user_fs",
-    "vhost_user_net",
-    "vfio",
-    "net_util",
-    "acpi_tables",
-    "arch_gen",
-    "net_gen",
-    "vm-allocator",
+    "vm-virtio"
 ]
+exclude = ["test_infra"]

Jenkinsfile

@@ -2,7 +2,7 @@ pipeline{
 	agent none
 	stages {
 		stage ('Early checks') {
-			agent { node { label 'master' } }
+			agent { node { label 'built-in' } }
 			stages {
 				stage ('Check for RFC/WIP builds') {
 					when {
@@ -14,7 +14,7 @@ pipeline{
 					}
 				}
 				stage ('Cancel older builds') {
-					when { not { branch 'master' } }
+					when { not { branch 'main' } }
 					steps {
 						cancelPreviousBuilds()
 					}
@@ -22,33 +22,38 @@ pipeline{
 			}
 		}
 		stage ('Build') {
-			failFast true
-            parallel {
-				stage ('Master build') {
-					agent { node { label 'master' } }
+            		parallel {
+				stage ('Worker build') {
+					agent { node { label 'hirsute' } }
 					stages {
 						stage ('Checkout') {
 							steps {
 								checkout scm
 							}
 						}
-						stage ('Run Cargo tests') {
-							steps {
-								sh "scripts/dev_cli.sh tests --cargo"
-							}
-						}
 						stage ('Run OpenAPI tests') {
 							steps {
 								sh "scripts/run_openapi_tests.sh"
 							}
 						}
+						stage ('Run unit tests') {
+							steps {
+								sh "scripts/dev_cli.sh tests --unit"
+							}
+						}
+						stage ('Run integration tests') {
+							options {
+								timeout(time: 1, unit: 'HOURS')
+							}
+							steps {
+								sh "sudo modprobe openvswitch"
+								sh "scripts/dev_cli.sh tests --integration"
+							}
+						}
 					}
-				}	
-				stage ('Worker build') {
-					agent { node { label 'bionic' } }
-					options {
-						timeout(time: 1, unit: 'HOURS')
-					}
+				}
+				stage ('AArch64 worker build') {
+					agent { node { label 'bionic-arm64' } }
 					stages {
 						stage ('Checkout') {
 							steps {
@@ -61,24 +66,199 @@ pipeline{
 							}
 						}
 						stage ('Run integration tests') {
+							options {
+								timeout(time: 1, unit: 'HOURS')
+							}
 							steps {
+								sh "sudo modprobe openvswitch"
 								sh "scripts/dev_cli.sh tests --integration"
 							}
 						}
+					}
+					post {
+						always {
+							sh "sudo chown -R jenkins.jenkins ${WORKSPACE}"
+							deleteDir()
+						}
+					}
+				}
+				stage ('Worker build (musl)') {
+					agent { node { label 'hirsute' } }
+					stages {
+						stage ('Checkout') {
+							steps {
+								checkout scm
+							}
+						}
 						stage ('Run unit tests for musl') {
-							when { branch 'master' }
 							steps {
 								sh "scripts/dev_cli.sh tests --unit --libc musl"
 							}
 						}
 						stage ('Run integration tests for musl') {
-							when { branch 'master' }
+							options {
+								timeout(time: 1, unit: 'HOURS')
+							}
 							steps {
+								sh "sudo modprobe openvswitch"
 								sh "scripts/dev_cli.sh tests --integration --libc musl"
 							}
 						}
 					}
 				}
+				stage ('Worker build SGX') {
+					agent { node { label 'bionic-sgx' } }
+					when {
+						beforeAgent true
+						branch 'main'
+					}
+					stages {
+						stage ('Checkout') {
+							steps {
+								checkout scm
+							}
+						}
+						stage ('Run SGX integration tests') {
+							options {
+								timeout(time: 1, unit: 'HOURS')
+							}
+							steps {
+								sh "scripts/dev_cli.sh tests --integration-sgx"
+							}
+						}
+						stage ('Run SGX integration tests for musl') {
+							options {
+								timeout(time: 1, unit: 'HOURS')
+							}
+							steps {
+								sh "scripts/dev_cli.sh tests --integration-sgx --libc musl"
+							}
+						}
+					}
+					post {
+						always {
+							sh "sudo chown -R jenkins.jenkins ${WORKSPACE}"
+							deleteDir()
+						}
+					}
+				}
+				stage ('Worker build VFIO') {
+					agent { node { label 'bionic-vfio' } }
+					when {
+						beforeAgent true
+						branch 'main'
+					}
+					stages {
+						stage ('Checkout') {
+							steps {
+								checkout scm
+							}
+						}
+						stage ('Run VFIO integration tests') {
+							options {
+								timeout(time: 1, unit: 'HOURS')
+							}
+							steps {
+								sh "scripts/dev_cli.sh tests --integration-vfio"
+							}
+						}
+						stage ('Run VFIO integration tests for musl') {
+							options {
+								timeout(time: 1, unit: 'HOURS')
+							}
+							steps {
+								sh "scripts/dev_cli.sh tests --integration-vfio --libc musl"
+							}
+						}
+					}
+					post {
+						always {
+							sh "sudo chown -R jenkins.jenkins ${WORKSPACE}"
+							deleteDir()
+						}
+					}
+				}
+				stage ('Worker build - Windows guest') {
+					agent { node { label 'hirsute' } }
+					environment {
+        					AZURE_CONNECTION_STRING = credentials('46b4e7d6-315f-4cc1-8333-b58780863b9b')
+					}
+					stages {
+						stage ('Checkout') {
+							steps {
+								checkout scm
+							}
+						}
+						stage ('Download assets') {
+							steps {
+								sh "sudo apt install -y azure-cli"
+								sh "mkdir ${env.HOME}/workloads"
+								sh 'az storage blob download --container-name private-images --file "$HOME/workloads/OVMF-4b47d0c6c8.fd" --name OVMF-4b47d0c6c8.fd --connection-string "$AZURE_CONNECTION_STRING"'
+								sh 'az storage blob download --container-name private-images --file "$HOME/workloads/windows-server-2019.raw" --name windows-server-2019.raw --connection-string "$AZURE_CONNECTION_STRING"'
+							}
+						}
+						stage ('Run Windows guest integration tests') {
+							options {
+								timeout(time: 1, unit: 'HOURS')
+							}
+							steps {
+								sh "scripts/dev_cli.sh tests --integration-windows"
+							}
+						}
+						stage ('Run Windows guest integration tests for musl') {
+							options {
+								timeout(time: 1, unit: 'HOURS')
+							}
+							steps {
+								sh "scripts/dev_cli.sh tests --integration-windows --libc musl"
+							}
+						}
+					}
+				}
+				stage ('Worker build - Live Migration') {
+					agent { node { label 'hirsute-small' } }
+					stages {
+						stage ('Checkout') {
+							steps {
+								checkout scm
+							}
+						}
+						stage ('Run live-migration integration tests') {
+							options {
+								timeout(time: 1, unit: 'HOURS')
+							}
+							steps {
+								sh "sudo modprobe openvswitch"
+								sh "scripts/dev_cli.sh tests --integration-live-migration"
+							}
+						}
+						stage ('Run live-migration integration tests for musl') {
+							options {
+								timeout(time: 1, unit: 'HOURS')
+							}
+							steps {
+								sh "sudo modprobe openvswitch"
+								sh "scripts/dev_cli.sh tests --integration-live-migration --libc musl"
+							}
+						}
+					}
+				}
+			}
+		}
+	}
+	post {
+		regression {
+			script {
+				if (env.BRANCH_NAME == 'main') {
+					slackSend (color: '#ff0000', message: '"main" branch build is now failing')
+				}
+			}
+		}
+		fixed {
+			script {
+				if (env.BRANCH_NAME == 'main') {
+					slackSend (color: '#00ff00', message: '"main" branch build is now fixed')
+				}
 			}
 		}
 	}
@@ -97,4 +277,4 @@ def cancelPreviousBuilds() {
 				build.doStop()
 			}
 		}
-}
+}

MAINTAINERS.md

@@ -1,6 +1,7 @@
 # Maintainers
 
-- Sebastien Boeuf <sebastien.boeuf@intel.com> @sboeuf
-- Robert Bradford <robert.bradford@intel.com> @rbradford
-- Samuel Ortiz <sameo@linux.intel.com> @sameo
-- Chao P Peng <chao.p.peng@linux.intel.com> @chao-p
+- Sebastien Boeuf - @sboeuf
+- Robert Bradford - @rbradford
+- Samuel Ortiz - @sameo
+- Wei Liu - @liuw
+- Michael Zhao - @michael2012z

README.md

@@ -1,35 +1,35 @@
-[![Build Status](https://travis-ci.com/cloud-hypervisor/cloud-hypervisor.svg?branch=master)](https://travis-ci.com/cloud-hypervisor/cloud-hypervisor)
-
-1. [What is Cloud Hypervisor?](#1-what-is-cloud-hypervisor)
-   * [Requirements](#requirements)
-	 + [High Level](#high-level)
-     + [Architectures](#architectures)
-	 + [Guest OS](#guest-os)
-2. [Getting Started](#2-getting-started)
-   * [Clone and build](#clone-and-build)
-   * [Run](#run)
-	 + [Cloud image](#cloud-image)
-	 + [Custom kernel and disk image](#custom-kernel-and-disk-image)
-		 - [Building your kernel](#building-your-kernel)
-		 - [Disk image](#disk-image)
-		 - [Booting the guest VM](#booting-the-guest-vm)
-3. [Status](#2-status)
-	* [Device Model](#device-model)
-	* [TODO](#todo)
-4. [rust-vmm dependency](#4-rust-vmm-dependency)
-	* [Firecracker and crosvm](#firecracker-and-crosvm)
-5. [Community](#5-community)
-	* [Join us](#join-us)
-6. [Security](#6-security)
+- [1. What is Cloud Hypervisor?](#1-what-is-cloud-hypervisor)
+  - [Objectives](#objectives)
+    - [High Level](#high-level)
+    - [Architectures](#architectures)
+    - [Guest OS](#guest-os)
+- [2. Getting Started](#2-getting-started)
+  - [Install prerequisites](#install-prerequisites)
+  - [Clone and build](#clone-and-build)
+    - [Containerized builds and tests](#containerized-builds-and-tests)
+  - [Run](#run)
+    - [Cloud image](#cloud-image)
+    - [Custom kernel and disk image](#custom-kernel-and-disk-image)
+      - [Building your kernel](#building-your-kernel)
+      - [Disk image](#disk-image)
+      - [Booting the guest VM](#booting-the-guest-vm)
+- [3. Status](#3-status)
+  - [Hot Plug](#hot-plug)
+  - [Device Model](#device-model)
+  - [TODO](#todo)
+- [4. `rust-vmm` project dependency](#4-rust-vmm-project-dependency)
+  - [Firecracker and crosvm](#firecracker-and-crosvm)
+- [5. Community](#5-community)
+  - [Contribute](#contribute)
+  - [Join us](#join-us)
+  - [Security issues](#security-issues)
 
 # 1. What is Cloud Hypervisor?
 
-**This project is an experiment and should not be used with production workloads.**
+Cloud Hypervisor is an open source Virtual Machine Monitor (VMM) that runs on top of [KVM](https://www.kernel.org/doc/Documentation/virtual/kvm/api.txt) and the MSHV hypervisors .
 
-Cloud Hypervisor is an open source Virtual Machine Monitor (VMM) that runs on top of [KVM](https://www.kernel.org/doc/Documentation/virtual/kvm/api.txt).
 The project focuses on exclusively running modern, cloud workloads, on top of a limited set of hardware architectures and platforms.
-Cloud workloads refers to those that are usually run by customers inside a cloud provider. For our purposes this means modern
-Linux* distributions with most I/O handled by paravirtualised devices (i.e. virtio), no requirement for legacy devices and recent CPUs and KVM.
+Cloud workloads refers to those that are usually run by customers inside a cloud provider. For our purposes this means modern operating systems with most I/O handled by paravirtualised devices (i.e. virtio), no requirement for legacy devices, and 64-bit CPUs.
 
 Cloud Hypervisor is implemented in [Rust](https://www.rust-lang.org/) and is based on the [rust-vmm](https://github.com/rust-vmm) crates.
 
@@ -37,30 +37,33 @@ Cloud Hypervisor is implemented in [Rust](https://www.rust-lang.org/) and is bas
 
 ### High Level
 
-* KVM and KVM only based
-* Minimal emulation
-* Low latency
-* Low memory footprint
-* Low complexity
-* High performance
-* Small attack surface
-* 64-bit support only
-* Build time configurable CPU, memory, PCI and NVDIMM hotplug
-* Machine to machine migration
+- Runs on KVM or MSHV
+- Minimal emulation
+- Low latency
+- Low memory footprint
+- Low complexity
+- High performance
+- Small attack surface
+- 64-bit support only
+- CPU, memory, PCI hotplug
+- Machine to machine migration
 
 ### Architectures
 
-`cloud-hypervisor` only supports the `x86-64` CPU architecture for now.
-
-We're planning to add support for the `AArch64` architecture in the future.
+Cloud Hypervisor supports the `x86-64` and `AArch64` architectures. There are some small differences in functionality between the two architectures (see [#1125](https://github.com/cloud-hypervisor/cloud-hypervisor/issues/1125)).
 
 ### Guest OS
-* `64-bit Linux`
 
-Support for *modern* 64-bit Windows guest is being evaluated.
+Cloud Hypervisor supports `64-bit Linux` and Windows 10/Windows Server 2019.
 
 # 2. Getting Started
 
+Below sections describe how to build and run Cloud Hypervisor on the `x86_64`
+platform. For getting started on the `AArch64` platform, please refer to the
+[Arm64 documentation](docs/arm64.md).
+
+## Preparation
+
 We create a folder to build and run `cloud-hypervisor` at `$HOME/cloud-hypervisor`
 
 ```shell
@@ -68,6 +71,23 @@ $ export CLOUDH=$HOME/cloud-hypervisor
 $ mkdir $CLOUDH
 ```
 
+## Install prerequisites
+
+You need to install some prerequisite packages in order to build and test Cloud Hypervisor.
+Here, all the steps are based on Ubuntu, for other Linux distributions please replace the
+package manager and package name.
+
+```shell
+# Install git
+$ sudo apt install git
+# Install rust tool chain
+$ curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh
+# Install build-essential
+$ sudo apt install build-essential
+# If you want to build statically linked binary please add musl target
+$ rustup target add x86_64-unknown-linux-musl
+```
+
 ## Clone and build
 
 First you need to clone and build the cloud-hypervisor repo:
@@ -81,6 +101,8 @@ $ cargo build --release
 # We need to give the cloud-hypervisor binary the NET_ADMIN capabilities for it to set TAP interfaces up on the host.
 $ sudo setcap cap_net_admin+ep ./target/release/cloud-hypervisor
 
+# If you want to build statically linked binary
+$ cargo build --release --target=x86_64-unknown-linux-musl --all
 $ popd
 ```
 
@@ -120,20 +142,20 @@ You can run a guest VM by either using an existing cloud image or booting into y
 
 ### Cloud image
 
-`cloud-hypervisor` supports booting disk images containing all needed
-components to run cloud workloads, a.k.a. cloud images.  To do that we rely on
+Cloud Hypervisor supports booting disk images containing all needed
+components to run cloud workloads, a.k.a. cloud images. To do that we rely on
 the [Rust Hypervisor
 Firmware](https://github.com/cloud-hypervisor/rust-hypervisor-firmware) project to provide
 an ELF
 formatted KVM firmware for `cloud-hypervisor` to directly boot into.
 
-We need to get the latest `rust-hypervisor-firmware` release and also a working cloud image. Here we will use a Clear Linux image:
+We need to get the latest `rust-hypervisor-firmware` release and also a working cloud image. Here we will use a Ubuntu image:
 
 ```shell
 $ pushd $CLOUDH
-$ wget https://download.clearlinux.org/releases/31890/clear/clear-31890-kvm.img.xz
-$ unxz clear-31890-kvm.img.xz
-$ wget https://github.com/cloud-hypervisor/rust-hypervisor-firmware/releases/download/0.2.6/hypervisor-fw
+$ wget https://cloud-images.ubuntu.com/focal/current/focal-server-cloudimg-amd64.img
+$ qemu-img convert -p -f qcow2 -O raw focal-server-cloudimg-amd64.img focal-server-cloudimg-amd64.raw
+$ wget https://github.com/cloud-hypervisor/rust-hypervisor-firmware/releases/download/0.3.2/hypervisor-fw
 $ popd
 ```
 
@@ -142,7 +164,7 @@ $ pushd $CLOUDH
 $ sudo setcap cap_net_admin+ep ./cloud-hypervisor/target/release/cloud-hypervisor
 $ ./cloud-hypervisor/target/release/cloud-hypervisor \
 	--kernel ./hypervisor-fw \
-	--disk path=clear-31890-kvm.img \
+	--disk path=focal-server-cloudimg-amd64.raw \
 	--cpus boot=4 \
 	--memory size=1024M \
 	--net "tap=,mac=,ip=,mask=" \
@@ -156,8 +178,7 @@ Multiple arguments can be given to the `--disk` parameter.
 
 #### Building your kernel
 
-`cloud-hypervisor` also supports direct kernel boot into a `vmlinux` ELF kernel
-image. In order to support virtio-fs and virtio-iommu we have our own development branch. You are of course able to use your own kernel but these instructions will continue with the version that we develop and test against.
+Cloud Hypervisor also supports direct kernel boot into a `vmlinux` ELF kernel. In order to support virtio-iommu we have our own development branch. You are of course able to use your own kernel but these instructions will continue with the version that we develop and test against.
 
 To build the kernel:
 
@@ -165,11 +186,11 @@ To build the kernel:
 
 # Clone the Cloud Hypervisor Linux branch
 $ pushd $CLOUDH
-$ git clone --depth 1 https://github.com/cloud-hypervisor/linux.git -b virtio-fs-virtio-iommu-virtio-mem-5.6-rc4 linux-cloud-hypervisor
+$ git clone --depth 1 https://github.com/cloud-hypervisor/linux.git -b ch-5.14 linux-cloud-hypervisor
 $ pushd linux-cloud-hypervisor
 
 # Use the cloud-hypervisor kernel config to build your kernel
-$ cp $CLOUDH/cloud-hypervisor/resources/linux-config .config
+$ cp $CLOUDH/cloud-hypervisor/resources/linux-config-x86_64 .config
 $ make bzImage -j `nproc`
 $ popd
 ```
@@ -178,27 +199,27 @@ The `vmlinux` kernel image will then be located at `linux-cloud-hypervisor/arch/
 
 #### Disk image
 
-For the disk image, we will use a Clear Linux cloud image that contains a root partition:
+For the disk image, we will use a Ubuntu cloud image that contains a root partition:
 
 ```shell
 $ pushd $CLOUDH
-$ wget https://download.clearlinux.org/releases/31890/clear/clear-31890-kvm.img.xz
-$ unxz clear-31890-kvm.img.xz
+$ wget https://cloud-images.ubuntu.com/focal/current/focal-server-cloudimg-amd64.img
+$ qemu-img convert -p -f qcow2 -O raw focal-server-cloudimg-amd64.img focal-server-cloudimg-amd64.raw
 $ popd
 ```
 
 #### Booting the guest VM
 
-Now we can directly boot into our custom kernel and make it use the Clear Linux root partition.
-If we want to have 4 vCPUs and 512 MBytes of memory:
+Now we can directly boot into our custom kernel and make it use the Ubuntu root partition.
+If we want to have 4 vCPUs and 1024 MBytes of memory:
 
 ```shell
 $ pushd $CLOUDH
 $ sudo setcap cap_net_admin+ep ./cloud-hypervisor/target/release/cloud-hypervisor
 $ ./cloud-hypervisor/target/release/cloud-hypervisor \
 	--kernel ./linux-cloud-hypervisor/arch/x86/boot/compressed/vmlinux.bin \
-	--disk path=clear-31890-kvm.img \
-	--cmdline "console=hvc0 reboot=k panic=1 nomodules i8042.noaux i8042.nomux i8042.nopnp i8042.dumbkbd root=/dev/vda3" \
+	--disk path=focal-server-cloudimg-amd64.raw \
+	--cmdline "console=hvc0 root=/dev/vda1 rw" \
 	--cpus boot=4 \
 	--memory size=1024M \
 	--net "tap=,mac=,ip=,mask=" \
@@ -217,8 +238,8 @@ $ ./cloud-hypervisor/target/release/cloud-hypervisor \
 	--kernel ./linux-cloud-hypervisor/arch/x86/boot/compressed/vmlinux.bin \
 	--console off \
 	--serial tty \
-	--disk path=clear-31890-kvm.img \
-	--cmdline "console=ttyS0 reboot=k panic=1 nomodules i8042.noaux i8042.nomux i8042.nopnp i8042.dumbkbd root=/dev/vda3" \
+	--disk path=focal-server-cloudimg-amd64.raw \
+	--cmdline "console=ttyS0 root=/dev/vda1 rw" \
 	--cpus boot=4 \
 	--memory size=1024M \
 	--net "tap=,mac=,ip=,mask=" \
@@ -227,52 +248,69 @@ $ ./cloud-hypervisor/target/release/cloud-hypervisor \
 
 # 3. Status
 
-`cloud-hypervisor` is in a very early, pre-alpha stage. Use at your own risk!
+Cloud Hypervisor is under active development. The following stability guarantees are currently made:
 
-As of 2020-04-23, the following cloud images are supported:
-* [Clear Linux](https://download.clearlinux.org/current/) (cloudguest and kvm)
-* [Ubuntu Bionic](https://cloud-images.ubuntu.com/bionic/current/) (cloudimg)
-* [Ubuntu Focal](https://cloud-images.ubuntu.com/focal/current/) (cloudimg)
+* The API (including command line options) will not be removed or changed in a
+  breaking way without a minimum of 2 releases notice. Where possible warnings
+  will be given about the use of deprecated functionality and the deprecations
+  will be documented in the release notes.
+* Point releases will be made between individual releases where there are
+  substantial bug fixes or security issues that need to be fixed.
 
-Direct kernel boot to userspace should work with most rootfs.
+Currently the following items are **not** guaranteed across updates:
+
+* Snapshot/restore is not supported across different versions
+* Live migration is not supported across different versions
+* The following features are considered experimental and may change
+  substantially between releases: TDX, SGX.
+
+
+As of 2021-04-29, the following cloud images are supported:
+
+- [Ubuntu Bionic](https://cloud-images.ubuntu.com/bionic/current/) (cloudimg)
+- [Ubuntu Focal](https://cloud-images.ubuntu.com/focal/current/) (cloudimg)
+- [Ubuntu Groovy](https://cloud-images.ubuntu.com/groovy/current/) (cloudimg)
+- [Ubuntu Hirsute](https://cloud-images.ubuntu.com/hirsute/current/) (cloudimg)
+
+Direct kernel boot to userspace should work with a rootfs from most distributions.
 
 ## Hot Plug
 
-This [document](https://github.com/cloud-hypervisor/cloud-hypervisor/blob/master/docs/hotplug.md) details how to add devices to
-a running VM. Currently only CPU hot plug is supported.
+Cloud Hypervisor supports hotplug of CPUs, passthrough devices (VFIO), `virtio-{net,block,pmem,fs,vsock}` and memory resizing. This [document](docs/hotplug.md) details how to add devices to
+a running VM.
 
 ## Device Model
 
-Follow this [documentation](https://github.com/cloud-hypervisor/cloud-hypervisor/blob/master/docs/device_model.md).
+Details of the device model can be found in this [documentation](docs/device_model.md).
 
 ## TODO
 
-We are not tracking the `cloud-hypervisor` TODO list from a specific git tracked file but through
+We are not tracking the Cloud Hypervisor TODO list from a specific git tracked file but through
 [github issues](https://github.com/cloud-hypervisor/cloud-hypervisor/issues/new) instead.
 
 # 4. `rust-vmm` project dependency
 
 In order to satisfy the design goal of having a high-performance, security-focused hypervisor the decision
 was made to use the [Rust](https://www.rust-lang.org/) programming language.
-The language's strong focus on memory and thread safety makes it an ideal candidate for implementing VMMs
+The language's strong focus on memory and thread safety makes it an ideal candidate for implementing VMMs.
 
-Instead of implementing the VMM components from scratch, `cloud-hypervisor` is importing the [rust-vmm](https://github.com/rust-vmm)
+Instead of implementing the VMM components from scratch, Cloud Hypervisor is importing the [rust-vmm](https://github.com/rust-vmm)
 crates, and sharing code and architecture together with other VMMs like e.g. Amazon's [Firecracker](https://firecracker-microvm.github.io/)
 and Google's [crosvm](https://chromium.googlesource.com/chromiumos/platform/crosvm/).
 
-`cloud-hypervisor` embraces the rust-vmm project goals, which is to be able to share and re-use
-as many virtualization crates as possible. As such, the `cloud-hypervisor` relationship with the rust-vmm
+Cloud Hypervisor embraces the rust-vmm project goals, which is to be able to share and re-use
+as many virtualization crates as possible. As such, the Cloud Hypervisor relationship with the rust-vmm
 project is twofold:
 
 1. It will use as much of the rust-vmm code as possible. Any new rust-vmm crate that's relevant to the project
    goals will be integrated as soon as possible.
-2. As it is likely that the rust-vmm project will lack some of the features that `cloud-hypervisor` needs (e.g. ACPI,
-   VFIO, vhost-user, etc), we will be using the `cloud-hypervisor` VMM to implement and test them, and contribute them
+2. As it is likely that the rust-vmm project will lack some of the features that Cloud Hypervisor needs (e.g. ACPI,
+   VFIO, vhost-user, etc), we will be using the Cloud Hypervisor VMM to implement and test them, and contribute them
    back to the rust-vmm project.
 
 ## Firecracker and crosvm
 
-A large part of the `cloud-hypervisor` code is based on either the Firecracker or the crosvm projects implementations.
+A large part of the Cloud Hypervisor code is based on either the Firecracker or the crosvm projects implementations.
 Both of these are VMMs written in Rust with a focus on safety and security, like Cloud Hypervisor.
 
 However we want to emphasize that the Cloud Hypervisor project is neither a fork nor a reimplementation of any of those
@@ -287,6 +325,11 @@ crates as possible.
 
 # 5. Community
 
+The Cloud Hypervisor project follows the governance, and community guidelines described in
+the [Community](https://github.com/cloud-hypervisor/community) repository.
+
+## Contribute
+
 We are working on building a global, diverse and collaborative community around the Cloud Hypervisor project.
 Anyone who is interested in [contributing](CONTRIBUTING.md) to the project is welcome to participate.
 
@@ -299,26 +342,6 @@ etc, are all equal and welcome means of contribution. See the [CONTRIBUTING](CON
 Get an [invite to our Slack channel](https://join.slack.com/t/cloud-hypervisor/shared_invite/enQtNjY3MTE3MDkwNDQ4LWQ1MTA1ZDVmODkwMWQ1MTRhYzk4ZGNlN2UwNTI3ZmFlODU0OTcwOWZjMTkwZDExYWE3YjFmNzgzY2FmNDAyMjI)
 and [join us on Slack](https://cloud-hypervisor.slack.com/).
 
-# 6. Security
+## Security issues
 
-**Reporting a Potential Security Vulnerability**: If you have discovered
-potential security vulnerability in this project, please send an e-mail to
-secure@intel.com. For issues related to Intel Products, please visit
-https://security-center.intel.com.
-
-It is important to include the following details:
-  - The projects and versions affected
-  - Detailed description of the vulnerability
-  - Information on known exploits
-
-Vulnerability information is extremely sensitive. Please encrypt all security
-vulnerability reports using our *PGP key*
-
-A member of the Intel Product Security Team will review your e-mail and
-contact you to to collaborate on resolving the issue. For more information on
-how Intel works to resolve security issues, see: *Vulnerability Handling
-Guidelines*
-
-PGP Key: https://www.intel.com/content/www/us/en/security-center/pgp-public-key.html
-
-Vulnerability Handling Guidelines: https://www.intel.com/content/www/us/en/security-center/vulnerability-handling-guidelines.html
+Please use the GitHub security advisories feature for reporting issues: https://github.com/cloud-hypervisor/cloud-hypervisor/security/advisories/new

acpi_tables/Cargo.toml

@@ -5,5 +5,4 @@ authors = ["The Cloud Hypervisor Authors"]
 edition = "2018"
 
 [dependencies]
-vm-memory = "0.2.0"
-
+vm-memory = "0.6.0"

acpi_tables/src/rsdp.rs

@@ -7,7 +7,7 @@ use vm_memory::ByteValued;
 
 #[repr(packed)]
 #[derive(Clone, Copy, Default)]
-pub struct RSDP {
+pub struct Rsdp {
     pub signature: [u8; 8],
     pub checksum: u8,
     pub oem_id: [u8; 6],
@@ -19,40 +19,41 @@ pub struct RSDP {
     _reserved: [u8; 3],
 }
 
-unsafe impl ByteValued for RSDP {}
+// SAFETY: Rsdp only contains a series of integers
+unsafe impl ByteValued for Rsdp {}
 
-impl RSDP {
+impl Rsdp {
     pub fn new(oem_id: [u8; 6], xsdt_addr: u64) -> Self {
-        let mut rsdp = RSDP {
+        let mut rsdp = Rsdp {
             signature: *b"RSD PTR ",
             checksum: 0,
             oem_id,
             revision: 2,
             _rsdt_addr: 0,
-            length: std::mem::size_of::<RSDP>() as u32,
+            length: std::mem::size_of::<Rsdp>() as u32,
             xsdt_addr,
             extended_checksum: 0,
             _reserved: [0; 3],
         };
 
         rsdp.checksum = super::generate_checksum(&rsdp.as_slice()[0..19]);
-        rsdp.extended_checksum = super::generate_checksum(&rsdp.as_slice());
+        rsdp.extended_checksum = super::generate_checksum(rsdp.as_slice());
         rsdp
     }
 
     pub fn len() -> usize {
-        std::mem::size_of::<RSDP>()
+        std::mem::size_of::<Rsdp>()
     }
 }
 
 #[cfg(test)]
 mod tests {
-    use super::RSDP;
+    use super::Rsdp;
     use vm_memory::bytes::ByteValued;
 
     #[test]
     fn test_rsdp() {
-        let rsdp = RSDP::new(*b"CHYPER", 0xdead_beef);
+        let rsdp = Rsdp::new(*b"CHYPER", 0xdead_beef);
         let sum = rsdp
             .as_slice()
             .iter()

acpi_tables/src/sdt.rs

@@ -13,23 +13,32 @@ pub struct GenericAddress {
 }
 
 impl GenericAddress {
-    pub fn io_port_address(address: u16) -> Self {
+    pub fn io_port_address<T>(address: u16) -> Self {
         GenericAddress {
             address_space_id: 1,
-            register_bit_width: 8,
+            register_bit_width: 8 * std::mem::size_of::<T>() as u8,
             register_bit_offset: 0,
-            access_size: 1,
+            access_size: std::mem::size_of::<T>() as u8,
             address: u64::from(address),
         }
     }
+    pub fn mmio_address<T>(address: u64) -> Self {
+        GenericAddress {
+            address_space_id: 0,
+            register_bit_width: 8 * std::mem::size_of::<T>() as u8,
+            register_bit_offset: 0,
+            access_size: std::mem::size_of::<T>() as u8,
+            address,
+        }
+    }
 }
 
-pub struct SDT {
+pub struct Sdt {
     data: Vec<u8>,
 }
 
 #[allow(clippy::len_without_is_empty)]
-impl SDT {
+impl Sdt {
     pub fn new(
         signature: [u8; 4],
         length: u32,
@@ -53,7 +62,7 @@ impl SDT {
         assert_eq!(data.len(), 36);
 
         data.resize(length as usize, 0);
-        let mut sdt = SDT { data };
+        let mut sdt = Sdt { data };
 
         sdt.update_checksum();
         sdt
@@ -66,7 +75,7 @@ impl SDT {
     }
 
     pub fn as_slice(&self) -> &[u8] {
-        &self.data.as_slice()
+        self.data.as_slice()
     }
 
     pub fn append<T>(&mut self, value: T) {
@@ -117,11 +126,11 @@ impl SDT {
 
 #[cfg(test)]
 mod tests {
-    use super::SDT;
+    use super::Sdt;
 
     #[test]
     fn test_sdt() {
-        let mut sdt = SDT::new(*b"TEST", 40, 1, *b"CLOUDH", *b"TESTTEST", 1);
+        let mut sdt = Sdt::new(*b"TEST", 40, 1, *b"CLOUDH", *b"TESTTEST", 1);
         let sum: u8 = sdt
             .as_slice()
             .iter()

api_client/Cargo.toml

@@ -0,0 +1,8 @@
+[package]
+name = "api_client"
+version = "0.1.0"
+authors = ["The Cloud Hypervisor Authors"]
+edition = "2018"
+
+[dependencies]
+vmm-sys-util = "0.9.0"

api_client/src/lib.rs

@@ -0,0 +1,187 @@
+// Copyright © 2020 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+
+use std::fmt;
+use std::io::{Read, Write};
+use std::os::unix::io::RawFd;
+use vmm_sys_util::sock_ctrl_msg::ScmSocket;
+
+#[derive(Debug)]
+pub enum Error {
+    Socket(std::io::Error),
+    SocketSendFds(vmm_sys_util::errno::Error),
+    StatusCodeParsing(std::num::ParseIntError),
+    MissingProtocol,
+    ContentLengthParsing(std::num::ParseIntError),
+    ServerResponse(StatusCode, Option<String>),
+}
+
+impl fmt::Display for Error {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        use Error::*;
+        match self {
+            Socket(e) => write!(f, "Error writing to or reading from HTTP socket: {}", e),
+            SocketSendFds(e) => write!(f, "Error writing to or reading from HTTP socket: {}", e),
+            StatusCodeParsing(e) => write!(f, "Error parsing HTTP status code: {}", e),
+            MissingProtocol => write!(f, "HTTP output is missing protocol statement"),
+            ContentLengthParsing(e) => write!(f, "Error parsing HTTP Content-Length field: {}", e),
+            ServerResponse(s, o) => {
+                if let Some(o) = o {
+                    write!(f, "Server responded with an error: {:?}: {}", s, o)
+                } else {
+                    write!(f, "Server responded with an error: {:?}", s)
+                }
+            }
+        }
+    }
+}
+
+#[derive(Clone, Copy, Debug)]
+pub enum StatusCode {
+    Continue,
+    Ok,
+    NoContent,
+    BadRequest,
+    NotFound,
+    InternalServerError,
+    NotImplemented,
+    Unknown,
+}
+
+impl StatusCode {
+    fn from_raw(code: usize) -> StatusCode {
+        match code {
+            100 => StatusCode::Continue,
+            200 => StatusCode::Ok,
+            204 => StatusCode::NoContent,
+            400 => StatusCode::BadRequest,
+            404 => StatusCode::NotFound,
+            500 => StatusCode::InternalServerError,
+            501 => StatusCode::NotImplemented,
+            _ => StatusCode::Unknown,
+        }
+    }
+
+    fn parse(code: &str) -> Result<StatusCode, Error> {
+        Ok(StatusCode::from_raw(
+            code.trim().parse().map_err(Error::StatusCodeParsing)?,
+        ))
+    }
+
+    fn is_server_error(self) -> bool {
+        !matches!(
+            self,
+            StatusCode::Ok | StatusCode::Continue | StatusCode::NoContent
+        )
+    }
+}
+
+fn get_header<'a>(res: &'a str, header: &'a str) -> Option<&'a str> {
+    let header_str = format!("{}: ", header);
+    res.find(&header_str)
+        .map(|o| &res[o + header_str.len()..o + res[o..].find('\r').unwrap()])
+}
+
+fn get_status_code(res: &str) -> Result<StatusCode, Error> {
+    if let Some(o) = res.find("HTTP/1.1") {
+        Ok(StatusCode::parse(
+            &res[o + "HTTP/1.1 ".len()..res[o..].find('\r').unwrap()],
+        )?)
+    } else {
+        Err(Error::MissingProtocol)
+    }
+}
+
+fn parse_http_response(socket: &mut dyn Read) -> Result<Option<String>, Error> {
+    let mut res = String::new();
+    let mut body_offset = None;
+    let mut content_length: Option<usize> = None;
+    loop {
+        let mut bytes = vec![0; 256];
+        let count = socket.read(&mut bytes).map_err(Error::Socket)?;
+        res.push_str(std::str::from_utf8(&bytes[0..count]).unwrap());
+
+        // End of headers
+        if let Some(o) = res.find("\r\n\r\n") {
+            body_offset = Some(o + "\r\n\r\n".len());
+
+            // With all headers available we can see if there is any body
+            content_length = if let Some(length) = get_header(&res, "Content-Length") {
+                Some(length.trim().parse().map_err(Error::ContentLengthParsing)?)
+            } else {
+                None
+            };
+
+            if content_length.is_none() {
+                break;
+            }
+        }
+
+        if let Some(body_offset) = body_offset {
+            if let Some(content_length) = content_length {
+                if res.len() >= content_length + body_offset {
+                    break;
+                }
+            }
+        }
+    }
+    let body_string = content_length.and(Some(String::from(&res[body_offset.unwrap()..])));
+    let status_code = get_status_code(&res)?;
+
+    if status_code.is_server_error() {
+        Err(Error::ServerResponse(status_code, body_string))
+    } else {
+        Ok(body_string)
+    }
+}
+
+pub fn simple_api_command_with_fds<T: Read + Write + ScmSocket>(
+    socket: &mut T,
+    method: &str,
+    c: &str,
+    request_body: Option<&str>,
+    request_fds: Vec<RawFd>,
+) -> Result<(), Error> {
+    socket
+        .send_with_fds(
+            &[format!(
+                "{} /api/v1/vm.{} HTTP/1.1\r\nHost: localhost\r\nAccept: */*\r\n",
+                method, c
+            )
+            .as_bytes()],
+            &request_fds,
+        )
+        .map_err(Error::SocketSendFds)?;
+
+    if let Some(request_body) = request_body {
+        socket
+            .write_all(format!("Content-Length: {}\r\n", request_body.len()).as_bytes())
+            .map_err(Error::Socket)?;
+    }
+
+    socket.write_all(b"\r\n").map_err(Error::Socket)?;
+
+    if let Some(request_body) = request_body {
+        socket
+            .write_all(request_body.as_bytes())
+            .map_err(Error::Socket)?;
+    }
+
+    socket.flush().map_err(Error::Socket)?;
+
+    if let Some(body) = parse_http_response(socket)? {
+        println!("{}", body);
+    }
+    Ok(())
+}
+
+pub fn simple_api_command<T: Read + Write + ScmSocket>(
+    socket: &mut T,
+    method: &str,
+    c: &str,
+    request_body: Option<&str>,
+) -> Result<(), Error> {
+    simple_api_command_with_fds(socket, method, c, request_body, Vec::new())
+}

arch/Cargo.toml

@@ -2,23 +2,30 @@
 name = "arch"
 version = "0.1.0"
 authors = ["The Chromium OS Authors"]
+edition = "2018"
 
 [features]
 default = []
+acpi = ["acpi_tables"]
+tdx = []
 
 [dependencies]
-byteorder = "1.3.4"
-kvm-bindings = { git = "https://github.com/cloud-hypervisor/kvm-bindings", branch = "ch" }
-kvm-ioctls = { git = "https://github.com/cloud-hypervisor/kvm-ioctls", branch = "ch" }
-libc = "0.2.69"
-vm-memory = { version = "0.2.0", features = ["backend-mmap"] }
-
 acpi_tables = { path = "../acpi_tables", optional = true }
-arch_gen = { path = "../arch_gen" }
+anyhow = "1.0.51"
+byteorder = "1.4.3"
+hypervisor = { path = "../hypervisor" }
+libc = "0.2.108"
+linux-loader = { version = "0.4.0", features = ["elf", "bzimage", "pe"] }
+log = "0.4.14"
+serde = { version = "1.0.130", features = ["rc"] }
+serde_derive = "1.0.130"
+thiserror = "1.0.30"
+versionize = "0.1.6"
+versionize_derive = "0.1.4"
+vm-memory = { version = "0.6.0", features = ["backend-mmap", "backend-bitmap"] }
+vm-migration = { path = "../vm-migration" }
+vmm-sys-util = { version = "0.9.0", features = ["with-serde"] }
 
-[dependencies.linux-loader]
-git = "https://github.com/rust-vmm/linux-loader"
-features = ["elf", "bzimage"]
-
-[dev-dependencies]
-rand = "0.7.3"
+[target.'cfg(target_arch = "aarch64")'.dependencies]
+fdt_parser = { version = "0.1.3", package = 'fdt'}
+vm-fdt = { git = "https://github.com/rust-vmm/vm-fdt", branch = "main" }

arch/src/aarch64/fdt.rs

@@ -0,0 +1,774 @@
+// Copyright 2020 Arm Limited (or its affiliates). All rights reserved.
+// Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style license that can be
+// found in the THIRD-PARTY file.
+
+use crate::NumaNodes;
+use byteorder::{BigEndian, ByteOrder};
+use std::cmp;
+use std::collections::HashMap;
+use std::ffi::CStr;
+use std::fmt::Debug;
+use std::result;
+use std::str;
+
+use super::super::DeviceType;
+use super::super::GuestMemoryMmap;
+use super::super::InitramfsConfig;
+use super::get_fdt_addr;
+use super::gic::GicDevice;
+use super::layout::{
+    IRQ_BASE, MEM_32BIT_DEVICES_SIZE, MEM_32BIT_DEVICES_START, MEM_PCI_IO_SIZE, MEM_PCI_IO_START,
+    PCI_HIGH_BASE, PCI_MMCONFIG_SIZE, PCI_MMCONFIG_START,
+};
+use vm_fdt::{FdtWriter, FdtWriterResult};
+use vm_memory::{Address, Bytes, GuestAddress, GuestMemory, GuestMemoryError, GuestMemoryRegion};
+
+// This is a value for uniquely identifying the FDT node declaring the interrupt controller.
+const GIC_PHANDLE: u32 = 1;
+// This is a value for uniquely identifying the FDT node declaring the MSI controller.
+const MSI_PHANDLE: u32 = 2;
+// This is a value for uniquely identifying the FDT node containing the clock definition.
+const CLOCK_PHANDLE: u32 = 3;
+// This is a value for uniquely identifying the FDT node containing the gpio controller.
+const GPIO_PHANDLE: u32 = 4;
+// This is a value for virtio-iommu. Now only one virtio-iommu device is supported.
+const VIRTIO_IOMMU_PHANDLE: u32 = 5;
+// NOTE: Keep FIRST_VCPU_PHANDLE the last PHANDLE defined.
+// This is a value for uniquely identifying the FDT node containing the first vCPU.
+// The last number of vCPU phandle depends on the number of vCPUs.
+const FIRST_VCPU_PHANDLE: u32 = 6;
+
+// Read the documentation specified when appending the root node to the FDT.
+const ADDRESS_CELLS: u32 = 0x2;
+const SIZE_CELLS: u32 = 0x2;
+
+// As per kvm tool and
+// https://www.kernel.org/doc/Documentation/devicetree/bindings/interrupt-controller/arm%2Cgic.txt
+// Look for "The 1st cell..."
+const GIC_FDT_IRQ_TYPE_SPI: u32 = 0;
+const GIC_FDT_IRQ_TYPE_PPI: u32 = 1;
+
+// From https://elixir.bootlin.com/linux/v4.9.62/source/include/dt-bindings/interrupt-controller/irq.h#L17
+const IRQ_TYPE_EDGE_RISING: u32 = 1;
+const IRQ_TYPE_LEVEL_HI: u32 = 4;
+
+// Keys and Buttons
+// System Power Down
+const KEY_POWER: u32 = 116;
+
+/// Trait for devices to be added to the Flattened Device Tree.
+pub trait DeviceInfoForFdt {
+    /// Returns the address where this device will be loaded.
+    fn addr(&self) -> u64;
+    /// Returns the associated interrupt for this device.
+    fn irq(&self) -> u32;
+    /// Returns the amount of memory that needs to be reserved for this device.
+    fn length(&self) -> u64;
+}
+
+/// Errors thrown while configuring the Flattened Device Tree for aarch64.
+#[derive(Debug)]
+pub enum Error {
+    /// Failure in writing FDT in memory.
+    WriteFdtToMemory(GuestMemoryError),
+}
+type Result<T> = result::Result<T, Error>;
+
+/// Creates the flattened device tree for this aarch64 VM.
+#[allow(clippy::too_many_arguments)]
+pub fn create_fdt<T: DeviceInfoForFdt + Clone + Debug, S: ::std::hash::BuildHasher>(
+    guest_mem: &GuestMemoryMmap,
+    cmdline: &str,
+    vcpu_mpidr: Vec<u64>,
+    vcpu_topology: Option<(u8, u8, u8)>,
+    device_info: &HashMap<(DeviceType, String), T, S>,
+    gic_device: &dyn GicDevice,
+    initrd: &Option<InitramfsConfig>,
+    pci_space_address: &(u64, u64),
+    numa_nodes: &NumaNodes,
+    virtio_iommu_bdf: Option<u32>,
+) -> FdtWriterResult<Vec<u8>> {
+    // Allocate stuff necessary for the holding the blob.
+    let mut fdt = FdtWriter::new().unwrap();
+
+    // For an explanation why these nodes were introduced in the blob take a look at
+    // https://github.com/torvalds/linux/blob/master/Documentation/devicetree/booting-without-of.txt#L845
+    // Look for "Required nodes and properties".
+
+    // Header or the root node as per above mentioned documentation.
+    let root_node = fdt.begin_node("")?;
+    fdt.property_string("compatible", "linux,dummy-virt")?;
+    // For info on #address-cells and size-cells read "Note about cells and address representation"
+    // from the above mentioned txt file.
+    fdt.property_u32("#address-cells", ADDRESS_CELLS)?;
+    fdt.property_u32("#size-cells", SIZE_CELLS)?;
+    // This is not mandatory but we use it to point the root node to the node
+    // containing description of the interrupt controller for this VM.
+    fdt.property_u32("interrupt-parent", GIC_PHANDLE)?;
+    create_cpu_nodes(&mut fdt, &vcpu_mpidr, vcpu_topology, numa_nodes)?;
+    create_memory_node(&mut fdt, guest_mem, numa_nodes)?;
+    create_chosen_node(&mut fdt, cmdline, initrd)?;
+    create_gic_node(&mut fdt, gic_device)?;
+    create_timer_node(&mut fdt)?;
+    create_clock_node(&mut fdt)?;
+    create_psci_node(&mut fdt)?;
+    create_devices_node(&mut fdt, device_info)?;
+    create_pci_nodes(
+        &mut fdt,
+        pci_space_address.0,
+        pci_space_address.1,
+        virtio_iommu_bdf,
+    )?;
+    if numa_nodes.len() > 1 {
+        create_distance_map_node(&mut fdt, numa_nodes)?;
+    }
+
+    // End Header node.
+    fdt.end_node(root_node)?;
+
+    let fdt_final = fdt.finish()?;
+
+    Ok(fdt_final)
+}
+
+pub fn write_fdt_to_memory(fdt_final: Vec<u8>, guest_mem: &GuestMemoryMmap) -> Result<()> {
+    // Write FDT to memory.
+    let fdt_address = GuestAddress(get_fdt_addr());
+    guest_mem
+        .write_slice(fdt_final.as_slice(), fdt_address)
+        .map_err(Error::WriteFdtToMemory)?;
+    Ok(())
+}
+
+// Following are the auxiliary function for creating the different nodes that we append to our FDT.
+fn create_cpu_nodes(
+    fdt: &mut FdtWriter,
+    vcpu_mpidr: &[u64],
+    vcpu_topology: Option<(u8, u8, u8)>,
+    numa_nodes: &NumaNodes,
+) -> FdtWriterResult<()> {
+    // See https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/arm/cpus.yaml.
+    let cpus_node = fdt.begin_node("cpus")?;
+    fdt.property_u32("#address-cells", 0x1)?;
+    fdt.property_u32("#size-cells", 0x0)?;
+
+    let num_cpus = vcpu_mpidr.len();
+    let threads_per_core = vcpu_topology.unwrap_or_default().0 as u8;
+    let cores_per_package = vcpu_topology.unwrap_or_default().1 as u8;
+    let packages = vcpu_topology.unwrap_or_default().2 as u8;
+
+    for (cpu_id, mpidr) in vcpu_mpidr.iter().enumerate().take(num_cpus) {
+        let cpu_name = format!("cpu@{:x}", cpu_id);
+        let cpu_node = fdt.begin_node(&cpu_name)?;
+        fdt.property_string("device_type", "cpu")?;
+        fdt.property_string("compatible", "arm,arm-v8")?;
+        if num_cpus > 1 {
+            // This is required on armv8 64-bit. See aforementioned documentation.
+            fdt.property_string("enable-method", "psci")?;
+        }
+        // Set the field to first 24 bits of the MPIDR - Multiprocessor Affinity Register.
+        // See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0488c/BABHBJCI.html.
+        fdt.property_u32("reg", (mpidr & 0x7FFFFF) as u32)?;
+        fdt.property_u32("phandle", cpu_id as u32 + FIRST_VCPU_PHANDLE)?;
+
+        // Add `numa-node-id` property if there is any numa config.
+        if numa_nodes.len() > 1 {
+            for numa_node_idx in 0..numa_nodes.len() {
+                let numa_node = numa_nodes.get(&(numa_node_idx as u32));
+                if numa_node.unwrap().cpus.contains(&(cpu_id as u8)) {
+                    fdt.property_u32("numa-node-id", numa_node_idx as u32)?;
+                }
+            }
+        }
+
+        fdt.end_node(cpu_node)?;
+    }
+
+    // If there is a valid cpu topology config, create the cpu-map node.
+    if (threads_per_core > 0)
+        && (cores_per_package > 0)
+        && (packages > 0)
+        && (num_cpus as u8 == threads_per_core * cores_per_package * packages)
+    {
+        let cpu_map_node = fdt.begin_node("cpu-map")?;
+        // Create mappings between CPU index and cluster,core, and thread.
+        let mut cluster_core_thread_to_cpuidx = HashMap::new();
+        for cpu_idx in 0..num_cpus as u8 {
+            if threads_per_core > 1 {
+                cluster_core_thread_to_cpuidx.insert(
+                    (
+                        cpu_idx / (cores_per_package * threads_per_core),
+                        (cpu_idx / threads_per_core) % cores_per_package,
+                        cpu_idx % threads_per_core,
+                    ),
+                    cpu_idx,
+                );
+            } else {
+                cluster_core_thread_to_cpuidx.insert(
+                    (cpu_idx / cores_per_package, cpu_idx % cores_per_package, 0),
+                    cpu_idx,
+                );
+            }
+        }
+
+        // Create device tree nodes with regard of above mapping.
+        for cluster_idx in 0..packages {
+            let cluster_name = format!("cluster{:x}", cluster_idx);
+            let cluster_node = fdt.begin_node(&cluster_name)?;
+
+            for core_idx in 0..cores_per_package {
+                let core_name = format!("core{:x}", core_idx);
+                let core_node = fdt.begin_node(&core_name)?;
+
+                if threads_per_core > 1 {
+                    for thread_idx in 0..threads_per_core {
+                        let thread_name = format!("thread{:x}", thread_idx);
+                        let thread_node = fdt.begin_node(&thread_name)?;
+                        let cpu_idx = cluster_core_thread_to_cpuidx
+                            .get(&(cluster_idx, core_idx, thread_idx))
+                            .unwrap();
+
+                        fdt.property_u32("cpu", *cpu_idx as u32 + FIRST_VCPU_PHANDLE)?;
+                        fdt.end_node(thread_node)?;
+                    }
+                } else {
+                    let cpu_idx = cluster_core_thread_to_cpuidx
+                        .get(&(cluster_idx, core_idx, 0))
+                        .unwrap();
+
+                    fdt.property_u32("cpu", *cpu_idx as u32 + FIRST_VCPU_PHANDLE)?;
+                }
+                fdt.end_node(core_node)?;
+            }
+            fdt.end_node(cluster_node)?;
+        }
+        fdt.end_node(cpu_map_node)?;
+    } else {
+        debug!("Boot using device tree, CPU topology is not (correctly) specified");
+    }
+
+    fdt.end_node(cpus_node)?;
+
+    Ok(())
+}
+
+fn create_memory_node(
+    fdt: &mut FdtWriter,
+    guest_mem: &GuestMemoryMmap,
+    numa_nodes: &NumaNodes,
+) -> FdtWriterResult<()> {
+    if numa_nodes.len() > 1 {
+        for numa_node_idx in 0..numa_nodes.len() {
+            let numa_node = numa_nodes.get(&(numa_node_idx as u32));
+            // Each memory zone of numa will have its own memory node, but
+            // different numa nodes should not share same memory zones.
+            for memory_region in numa_node.unwrap().memory_regions.iter() {
+                let memory_region_start_addr: u64 = memory_region.start_addr().raw_value();
+                let memory_region_size: u64 = memory_region.size() as u64;
+                let mem_reg_prop = [memory_region_start_addr, memory_region_size];
+                // With feature `acpi` enabled, RAM at 0-4M is for edk2 only
+                // and should be hidden to the guest.
+                #[cfg(feature = "acpi")]
+                if memory_region_start_addr == 0 {
+                    continue;
+                }
+
+                let memory_node_name = format!("memory@{:x}", memory_region_start_addr);
+                let memory_node = fdt.begin_node(&memory_node_name)?;
+                fdt.property_string("device_type", "memory")?;
+                fdt.property_array_u64("reg", &mem_reg_prop)?;
+                fdt.property_u32("numa-node-id", numa_node_idx as u32)?;
+                fdt.end_node(memory_node)?;
+            }
+        }
+    } else {
+        let mem_size = guest_mem.last_addr().raw_value() - super::layout::RAM_64BIT_START + 1;
+        // See https://github.com/torvalds/linux/blob/master/Documentation/devicetree/booting-without-of.txt#L960
+        // for an explanation of this.
+        let mem_reg_prop = [super::layout::RAM_64BIT_START as u64, mem_size as u64];
+        let memory_node = fdt.begin_node("memory")?;
+
+        fdt.property_string("device_type", "memory")?;
+        fdt.property_array_u64("reg", &mem_reg_prop)?;
+        fdt.end_node(memory_node)?;
+    }
+
+    Ok(())
+}
+
+fn create_chosen_node(
+    fdt: &mut FdtWriter,
+    cmdline: &str,
+    initrd: &Option<InitramfsConfig>,
+) -> FdtWriterResult<()> {
+    let chosen_node = fdt.begin_node("chosen")?;
+    fdt.property_string("bootargs", cmdline)?;
+
+    if let Some(initrd_config) = initrd {
+        let initrd_start = initrd_config.address.raw_value() as u64;
+        let initrd_end = initrd_config.address.raw_value() + initrd_config.size as u64;
+        fdt.property_u64("linux,initrd-start", initrd_start)?;
+        fdt.property_u64("linux,initrd-end", initrd_end)?;
+    }
+
+    fdt.end_node(chosen_node)?;
+
+    Ok(())
+}
+
+fn create_gic_node(fdt: &mut FdtWriter, gic_device: &dyn GicDevice) -> FdtWriterResult<()> {
+    let gic_reg_prop = gic_device.device_properties();
+
+    let intc_node = fdt.begin_node("intc")?;
+
+    fdt.property_string("compatible", gic_device.fdt_compatibility())?;
+    fdt.property_null("interrupt-controller")?;
+    // "interrupt-cells" field specifies the number of cells needed to encode an
+    // interrupt source. The type shall be a <u32> and the value shall be 3 if no PPI affinity description
+    // is required.
+    fdt.property_u32("#interrupt-cells", 3)?;
+    fdt.property_array_u64("reg", gic_reg_prop)?;
+    fdt.property_u32("phandle", GIC_PHANDLE)?;
+    fdt.property_u32("#address-cells", 2)?;
+    fdt.property_u32("#size-cells", 2)?;
+    fdt.property_null("ranges")?;
+
+    let gic_intr_prop = [
+        GIC_FDT_IRQ_TYPE_PPI,
+        gic_device.fdt_maint_irq(),
+        IRQ_TYPE_LEVEL_HI,
+    ];
+    fdt.property_array_u32("interrupts", &gic_intr_prop)?;
+
+    if gic_device.msi_compatible() {
+        let msic_node = fdt.begin_node("msic")?;
+        fdt.property_string("compatible", gic_device.msi_compatibility())?;
+        fdt.property_null("msi-controller")?;
+        fdt.property_u32("phandle", MSI_PHANDLE)?;
+        let msi_reg_prop = gic_device.msi_properties();
+        fdt.property_array_u64("reg", msi_reg_prop)?;
+        fdt.end_node(msic_node)?;
+    }
+
+    fdt.end_node(intc_node)?;
+
+    Ok(())
+}
+
+fn create_clock_node(fdt: &mut FdtWriter) -> FdtWriterResult<()> {
+    // The Advanced Peripheral Bus (APB) is part of the Advanced Microcontroller Bus Architecture
+    // (AMBA) protocol family. It defines a low-cost interface that is optimized for minimal power
+    // consumption and reduced interface complexity.
+    // PCLK is the clock source and this node defines exactly the clock for the APB.
+    let clock_node = fdt.begin_node("apb-pclk")?;
+    fdt.property_string("compatible", "fixed-clock")?;
+    fdt.property_u32("#clock-cells", 0x0)?;
+    fdt.property_u32("clock-frequency", 24000000)?;
+    fdt.property_string("clock-output-names", "clk24mhz")?;
+    fdt.property_u32("phandle", CLOCK_PHANDLE)?;
+    fdt.end_node(clock_node)?;
+
+    Ok(())
+}
+
+fn create_timer_node(fdt: &mut FdtWriter) -> FdtWriterResult<()> {
+    // See
+    // https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/interrupt-controller/arch_timer.txt
+    // These are fixed interrupt numbers for the timer device.
+    let irqs = [13, 14, 11, 10];
+    let compatible = "arm,armv8-timer";
+
+    let mut timer_reg_cells: Vec<u32> = Vec::new();
+    for &irq in irqs.iter() {
+        timer_reg_cells.push(GIC_FDT_IRQ_TYPE_PPI);
+        timer_reg_cells.push(irq);
+        timer_reg_cells.push(IRQ_TYPE_LEVEL_HI);
+    }
+
+    let timer_node = fdt.begin_node("timer")?;
+    fdt.property_string("compatible", compatible)?;
+    fdt.property_null("always-on")?;
+    fdt.property_array_u32("interrupts", &timer_reg_cells)?;
+    fdt.end_node(timer_node)?;
+
+    Ok(())
+}
+
+fn create_psci_node(fdt: &mut FdtWriter) -> FdtWriterResult<()> {
+    let compatible = "arm,psci-0.2";
+    let psci_node = fdt.begin_node("psci")?;
+    fdt.property_string("compatible", compatible)?;
+    // Two methods available: hvc and smc.
+    // As per documentation, PSCI calls between a guest and hypervisor may use the HVC conduit instead of SMC.
+    // So, since we are using kvm, we need to use hvc.
+    fdt.property_string("method", "hvc")?;
+    fdt.end_node(psci_node)?;
+
+    Ok(())
+}
+
+fn create_virtio_node<T: DeviceInfoForFdt + Clone + Debug>(
+    fdt: &mut FdtWriter,
+    dev_info: &T,
+) -> FdtWriterResult<()> {
+    let device_reg_prop = [dev_info.addr(), dev_info.length()];
+    let irq = [GIC_FDT_IRQ_TYPE_SPI, dev_info.irq(), IRQ_TYPE_EDGE_RISING];
+
+    let virtio_node = fdt.begin_node(&format!("virtio_mmio@{:x}", dev_info.addr()))?;
+    fdt.property_string("compatible", "virtio,mmio")?;
+    fdt.property_array_u64("reg", &device_reg_prop)?;
+    fdt.property_array_u32("interrupts", &irq)?;
+    fdt.property_u32("interrupt-parent", GIC_PHANDLE)?;
+    fdt.end_node(virtio_node)?;
+
+    Ok(())
+}
+
+fn create_serial_node<T: DeviceInfoForFdt + Clone + Debug>(
+    fdt: &mut FdtWriter,
+    dev_info: &T,
+) -> FdtWriterResult<()> {
+    let compatible = b"arm,pl011\0arm,primecell\0";
+    let serial_reg_prop = [dev_info.addr(), dev_info.length()];
+    let irq = [
+        GIC_FDT_IRQ_TYPE_SPI,
+        dev_info.irq() - IRQ_BASE,
+        IRQ_TYPE_EDGE_RISING,
+    ];
+
+    let serial_node = fdt.begin_node(&format!("pl011@{:x}", dev_info.addr()))?;
+    fdt.property("compatible", compatible)?;
+    fdt.property_array_u64("reg", &serial_reg_prop)?;
+    fdt.property_u32("clocks", CLOCK_PHANDLE)?;
+    fdt.property_string("clock-names", "apb_pclk")?;
+    fdt.property_array_u32("interrupts", &irq)?;
+    fdt.end_node(serial_node)?;
+
+    Ok(())
+}
+
+fn create_rtc_node<T: DeviceInfoForFdt + Clone + Debug>(
+    fdt: &mut FdtWriter,
+    dev_info: &T,
+) -> FdtWriterResult<()> {
+    let compatible = b"arm,pl031\0arm,primecell\0";
+    let rtc_reg_prop = [dev_info.addr(), dev_info.length()];
+    let irq = [
+        GIC_FDT_IRQ_TYPE_SPI,
+        dev_info.irq() - IRQ_BASE,
+        IRQ_TYPE_LEVEL_HI,
+    ];
+
+    let rtc_node = fdt.begin_node(&format!("rtc@{:x}", dev_info.addr()))?;
+    fdt.property("compatible", compatible)?;
+    fdt.property_array_u64("reg", &rtc_reg_prop)?;
+    fdt.property_array_u32("interrupts", &irq)?;
+    fdt.property_u32("clocks", CLOCK_PHANDLE)?;
+    fdt.property_string("clock-names", "apb_pclk")?;
+    fdt.end_node(rtc_node)?;
+
+    Ok(())
+}
+
+fn create_gpio_node<T: DeviceInfoForFdt + Clone + Debug>(
+    fdt: &mut FdtWriter,
+    dev_info: &T,
+) -> FdtWriterResult<()> {
+    // PL061 GPIO controller node
+    let compatible = b"arm,pl061\0arm,primecell\0";
+    let gpio_reg_prop = [dev_info.addr(), dev_info.length()];
+    let irq = [
+        GIC_FDT_IRQ_TYPE_SPI,
+        dev_info.irq() - IRQ_BASE,
+        IRQ_TYPE_EDGE_RISING,
+    ];
+
+    let gpio_node = fdt.begin_node(&format!("pl061@{:x}", dev_info.addr()))?;
+    fdt.property("compatible", compatible)?;
+    fdt.property_array_u64("reg", &gpio_reg_prop)?;
+    fdt.property_array_u32("interrupts", &irq)?;
+    fdt.property_null("gpio-controller")?;
+    fdt.property_u32("#gpio-cells", 2)?;
+    fdt.property_u32("clocks", CLOCK_PHANDLE)?;
+    fdt.property_string("clock-names", "apb_pclk")?;
+    fdt.property_u32("phandle", GPIO_PHANDLE)?;
+    fdt.end_node(gpio_node)?;
+
+    // gpio-keys node
+    let gpio_keys_node = fdt.begin_node("gpio-keys")?;
+    fdt.property_string("compatible", "gpio-keys")?;
+    fdt.property_u32("#size-cells", 0)?;
+    fdt.property_u32("#address-cells", 1)?;
+    let gpio_keys_poweroff_node = fdt.begin_node("button@1")?;
+    fdt.property_string("label", "GPIO Key Poweroff")?;
+    fdt.property_u32("linux,code", KEY_POWER)?;
+    let gpios = [GPIO_PHANDLE, 3, 0];
+    fdt.property_array_u32("gpios", &gpios)?;
+    fdt.end_node(gpio_keys_poweroff_node)?;
+    fdt.end_node(gpio_keys_node)?;
+
+    Ok(())
+}
+
+fn create_devices_node<T: DeviceInfoForFdt + Clone + Debug, S: ::std::hash::BuildHasher>(
+    fdt: &mut FdtWriter,
+    dev_info: &HashMap<(DeviceType, String), T, S>,
+) -> FdtWriterResult<()> {
+    // Create one temp Vec to store all virtio devices
+    let mut ordered_virtio_device: Vec<&T> = Vec::new();
+
+    for ((device_type, _device_id), info) in dev_info {
+        match device_type {
+            DeviceType::Gpio => create_gpio_node(fdt, info)?,
+            DeviceType::Rtc => create_rtc_node(fdt, info)?,
+            DeviceType::Serial => create_serial_node(fdt, info)?,
+            DeviceType::Virtio(_) => {
+                ordered_virtio_device.push(info);
+            }
+        }
+    }
+
+    // Sort out virtio devices by address from low to high and insert them into fdt table.
+    ordered_virtio_device.sort_by_key(|&a| a.addr());
+    // Current address allocation strategy in cloud-hypervisor is: the first created device
+    // will be allocated to higher address. Here we reverse the vector to make sure that
+    // the older created device will appear in front of the newer created device in FDT.
+    ordered_virtio_device.reverse();
+    for ordered_device_info in ordered_virtio_device.drain(..) {
+        create_virtio_node(fdt, ordered_device_info)?;
+    }
+
+    Ok(())
+}
+
+fn create_pci_nodes(
+    fdt: &mut FdtWriter,
+    pci_device_base: u64,
+    pci_device_size: u64,
+    virtio_iommu_bdf: Option<u32>,
+) -> FdtWriterResult<()> {
+    // Add node for PCIe controller.
+    // See Documentation/devicetree/bindings/pci/host-generic-pci.txt in the kernel
+    // and https://elinux.org/Device_Tree_Usage.
+
+    // EDK2 requires the PCIe high space above 4G address.
+    // The actual space in CLH follows the RAM. If the RAM space is small, the PCIe high space
+    // could fall bellow 4G.
+    // Here we put it above 512G in FDT to workaround the EDK2 check.
+    // But the address written in ACPI is not impacted.
+    let pci_device_base_64bit: u64 = if cfg!(feature = "acpi") {
+        pci_device_base + PCI_HIGH_BASE
+    } else {
+        pci_device_base
+    };
+    let pci_device_size_64bit: u64 = if cfg!(feature = "acpi") {
+        pci_device_size - PCI_HIGH_BASE
+    } else {
+        pci_device_size
+    };
+
+    let ranges = [
+        // io addresses
+        0x1000000,
+        0_u32,
+        0_u32,
+        (MEM_PCI_IO_START.0 >> 32) as u32,
+        MEM_PCI_IO_START.0 as u32,
+        (MEM_PCI_IO_SIZE >> 32) as u32,
+        MEM_PCI_IO_SIZE as u32,
+        // mmio addresses
+        0x2000000,                                // (ss = 10: 32-bit memory space)
+        (MEM_32BIT_DEVICES_START.0 >> 32) as u32, // PCI address
+        MEM_32BIT_DEVICES_START.0 as u32,
+        (MEM_32BIT_DEVICES_START.0 >> 32) as u32, // CPU address
+        MEM_32BIT_DEVICES_START.0 as u32,
+        (MEM_32BIT_DEVICES_SIZE >> 32) as u32, // size
+        MEM_32BIT_DEVICES_SIZE as u32,
+        // device addresses
+        0x3000000,                            // (ss = 11: 64-bit memory space)
+        (pci_device_base_64bit >> 32) as u32, // PCI address
+        pci_device_base_64bit as u32,
+        (pci_device_base_64bit >> 32) as u32, // CPU address
+        pci_device_base_64bit as u32,
+        (pci_device_size_64bit >> 32) as u32, // size
+        pci_device_size_64bit as u32,
+    ];
+    let bus_range = [0, 0]; // Only bus 0
+    let reg = [PCI_MMCONFIG_START.0, PCI_MMCONFIG_SIZE];
+
+    let pci_node = fdt.begin_node("pci")?;
+    fdt.property_string("compatible", "pci-host-ecam-generic")?;
+    fdt.property_string("device_type", "pci")?;
+    fdt.property_array_u32("ranges", &ranges)?;
+    fdt.property_array_u32("bus-range", &bus_range)?;
+    fdt.property_u32("#address-cells", 3)?;
+    fdt.property_u32("#size-cells", 2)?;
+    fdt.property_array_u64("reg", &reg)?;
+    fdt.property_u32("#interrupt-cells", 1)?;
+    fdt.property_null("interrupt-map")?;
+    fdt.property_null("interrupt-map-mask")?;
+    fdt.property_null("dma-coherent")?;
+    fdt.property_u32("msi-parent", MSI_PHANDLE)?;
+
+    if let Some(virtio_iommu_bdf) = virtio_iommu_bdf {
+        // See kernel document Documentation/devicetree/bindings/pci/pci-iommu.txt
+        // for 'iommu-map' attribute setting.
+        let iommu_map = [
+            0_u32,
+            VIRTIO_IOMMU_PHANDLE,
+            0_u32,
+            virtio_iommu_bdf,
+            virtio_iommu_bdf + 1,
+            VIRTIO_IOMMU_PHANDLE,
+            virtio_iommu_bdf + 1,
+            0xffff - virtio_iommu_bdf,
+        ];
+        fdt.property_array_u32("iommu-map", &iommu_map)?;
+
+        // See kernel document Documentation/devicetree/bindings/virtio/iommu.txt
+        // for virtio-iommu node settings.
+        let virtio_iommu_node_name = format!("virtio_iommu@{:x}", virtio_iommu_bdf);
+        let virtio_iommu_node = fdt.begin_node(&virtio_iommu_node_name)?;
+        fdt.property_u32("#iommu-cells", 1)?;
+        fdt.property_string("compatible", "virtio,pci-iommu")?;
+
+        // 'reg' is a five-cell address encoded as
+        // (phys.hi phys.mid phys.lo size.hi size.lo). phys.hi should contain the
+        // device's BDF as 0b00000000 bbbbbbbb dddddfff 00000000. The other cells
+        // should be zero.
+        let reg = [virtio_iommu_bdf << 8, 0_u32, 0_u32, 0_u32, 0_u32];
+        fdt.property_array_u32("reg", &reg)?;
+        fdt.property_u32("phandle", VIRTIO_IOMMU_PHANDLE)?;
+
+        fdt.end_node(virtio_iommu_node)?;
+    }
+
+    fdt.end_node(pci_node)?;
+
+    Ok(())
+}
+
+fn create_distance_map_node(fdt: &mut FdtWriter, numa_nodes: &NumaNodes) -> FdtWriterResult<()> {
+    let distance_map_node = fdt.begin_node("distance-map")?;
+    fdt.property_string("compatible", "numa-distance-map-v1")?;
+    // Construct the distance matrix.
+    // 1. We use the word entry to describe a distance from a node to
+    // its destination, e.g. 0 -> 1 = 20 is described as <0 1 20>.
+    // 2. Each entry represents distance from first node to second node.
+    // The distances are equal in either direction.
+    // 3. The distance from a node to self (local distance) is represented
+    // with value 10 and all internode distance should be represented with
+    // a value greater than 10.
+    // 4. distance-matrix should have entries in lexicographical ascending
+    // order of nodes.
+    let mut distance_matrix = Vec::new();
+    for numa_node_idx in 0..numa_nodes.len() {
+        let numa_node = numa_nodes.get(&(numa_node_idx as u32));
+        for dest_numa_node in 0..numa_node.unwrap().distances.len() + 1 {
+            if numa_node_idx == dest_numa_node {
+                distance_matrix.push(numa_node_idx as u32);
+                distance_matrix.push(dest_numa_node as u32);
+                distance_matrix.push(10_u32);
+                continue;
+            }
+
+            distance_matrix.push(numa_node_idx as u32);
+            distance_matrix.push(dest_numa_node as u32);
+            distance_matrix.push(
+                *numa_node
+                    .unwrap()
+                    .distances
+                    .get(&(dest_numa_node as u32))
+                    .unwrap() as u32,
+            );
+        }
+    }
+    fdt.property_array_u32("distance-matrix", distance_matrix.as_ref())?;
+    fdt.end_node(distance_map_node)?;
+
+    Ok(())
+}
+
+// Parse the DTB binary and print for debugging
+pub fn print_fdt(dtb: &[u8]) {
+    match fdt_parser::Fdt::new(dtb) {
+        Ok(fdt) => {
+            if let Some(root) = fdt.find_node("/") {
+                debug!("Printing the FDT:");
+                print_node(root, 0);
+            } else {
+                debug!("Failed to find root node in FDT for debugging.");
+            }
+        }
+        Err(_) => debug!("Failed to parse FDT for debugging."),
+    }
+}
+
+fn print_node(node: fdt_parser::node::FdtNode<'_, '_>, n_spaces: usize) {
+    debug!("{:indent$}{}/", "", node.name, indent = n_spaces);
+    for property in node.properties() {
+        let name = property.name;
+
+        // If the property is 'compatible', its value requires special handling.
+        // The u8 array could contain multiple null-terminated strings.
+        // We copy the original array and simply replace all 'null' characters with spaces.
+        let value = if name == "compatible" {
+            let mut compatible = vec![0u8; 256];
+            let handled_value = property
+                .value
+                .iter()
+                .map(|&c| if c == 0 { b' ' } else { c })
+                .collect::<Vec<_>>();
+            let len = cmp::min(255, handled_value.len());
+            compatible[..len].copy_from_slice(&handled_value[..len]);
+            compatible[..(len + 1)].to_vec()
+        } else {
+            property.value.to_vec()
+        };
+        let value = &value;
+
+        // Now the value can be either:
+        //   - A null-terminated C string, or
+        //   - Binary data
+        // We follow a very simple logic to present the value:
+        //   - At first, try to convert it to CStr and print,
+        //   - If failed, print it as u32 array.
+        let value_result = match CStr::from_bytes_with_nul(value) {
+            Ok(value_cstr) => match value_cstr.to_str() {
+                Ok(value_str) => Some(value_str),
+                Err(_e) => None,
+            },
+            Err(_e) => None,
+        };
+
+        if let Some(value_str) = value_result {
+            debug!(
+                "{:indent$}{} : {:#?}",
+                "",
+                name,
+                value_str,
+                indent = (n_spaces + 2)
+            );
+        } else {
+            let mut array = Vec::with_capacity(256);
+            array.resize(value.len() / 4, 0u32);
+            BigEndian::read_u32_into(value, &mut array);
+            debug!(
+                "{:indent$}{} : {:X?}",
+                "",
+                name,
+                array,
+                indent = (n_spaces + 2)
+            );
+        };
+    }
+
+    // Print children nodes if there is any
+    for child in node.children() {
+        print_node(child, n_spaces + 2);
+    }
+}

arch/src/aarch64/gic/dist_regs.rs

@@ -0,0 +1,182 @@
+// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+// SPDX-License-Identifier: Apache-2.0
+
+use super::{Error, Result};
+use crate::layout::IRQ_BASE;
+use hypervisor::kvm::kvm_bindings::{
+    kvm_device_attr, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
+};
+use std::sync::Arc;
+
+/*
+ Distributor registers as detailed at page 456 from
+ https://static.docs.arm.com/ihi0069/c/IHI0069C_gic_architecture_specification.pdf.
+ Address offsets are relative to the Distributor base address defined
+by the system memory map. Unless otherwise stated in the register description,
+all GIC registers are 32-bits wide.
+ */
+const GICD_CTLR: u32 = 0x0;
+const GICD_STATUSR: u32 = 0x0010;
+const GICD_IGROUPR: u32 = 0x0080;
+const GICD_ISENABLER: u32 = 0x0100;
+const GICD_ICENABLER: u32 = 0x0180;
+const GICD_ISPENDR: u32 = 0x0200;
+const GICD_ICPENDR: u32 = 0x0280;
+const GICD_ISACTIVER: u32 = 0x0300;
+const GICD_ICACTIVER: u32 = 0x0380;
+const GICD_IPRIORITYR: u32 = 0x0400;
+const GICD_ICFGR: u32 = 0x0C00;
+const GICD_IROUTER: u32 = 0x6000;
+
+/// This is how we represent the registers of the vgic's distributor.
+/// Some of the distributor register )(i.e GICD_STATUSR) are simple
+/// registers (i.e they are associated to a 32 bit value).
+/// However, there are other registers that have variable lengths since
+/// they dedicate some of the 32 bits to some specific interrupt. So, their length
+/// depends on the number of interrupts (i.e the ones that are represented as GICD_REG<n>)
+/// in the documentation mentioned above.
+struct DistReg {
+    /// Offset from distributor address.
+    base: u32,
+    /// Bits per interrupt.
+    /// Relevant for registers that DO share IRQs.
+    bpi: u8,
+    /// Length of the register.
+    /// Relevant for registers that DO NOT share IRQs.
+    length: u16,
+}
+
+// All or at least the registers we are interested in are 32 bit, so
+// we use a constant for size(u32).
+const REG_SIZE: u8 = 4;
+
+// Creates a vgic distributor register.
+macro_rules! VGIC_DIST_REG {
+    ($base:expr, $bpi:expr, $length:expr) => {
+        DistReg {
+            base: $base,
+            bpi: $bpi,
+            length: $length,
+        }
+    };
+}
+
+// List with relevant distributor registers that we will be restoring.
+// Order is taken from qemu.
+static VGIC_DIST_REGS: &'static [DistReg] = &[
+    VGIC_DIST_REG!(GICD_STATUSR, 0, 4),
+    VGIC_DIST_REG!(GICD_ICENABLER, 1, 0),
+    VGIC_DIST_REG!(GICD_ISENABLER, 1, 0),
+    VGIC_DIST_REG!(GICD_IGROUPR, 1, 0),
+    VGIC_DIST_REG!(GICD_IROUTER, 64, 0),
+    VGIC_DIST_REG!(GICD_ICFGR, 2, 0),
+    VGIC_DIST_REG!(GICD_ICPENDR, 1, 0),
+    VGIC_DIST_REG!(GICD_ISPENDR, 1, 0),
+    VGIC_DIST_REG!(GICD_ICACTIVER, 1, 0),
+    VGIC_DIST_REG!(GICD_ISACTIVER, 1, 0),
+    VGIC_DIST_REG!(GICD_IPRIORITYR, 8, 0),
+];
+
+fn dist_attr_access(
+    gic: &Arc<dyn hypervisor::Device>,
+    offset: u32,
+    val: &u32,
+    set: bool,
+) -> Result<()> {
+    let mut gic_dist_attr = kvm_device_attr {
+        group: KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
+        attr: offset as u64,
+        addr: val as *const u32 as u64,
+        flags: 0,
+    };
+    if set {
+        gic.set_device_attr(&gic_dist_attr)
+            .map_err(Error::SetDeviceAttribute)?;
+    } else {
+        gic.get_device_attr(&mut gic_dist_attr)
+            .map_err(Error::GetDeviceAttribute)?;
+    }
+    Ok(())
+}
+
+/// Get the distributor control register.
+pub fn read_ctlr(gic: &Arc<dyn hypervisor::Device>) -> Result<u32> {
+    let val: u32 = 0;
+    dist_attr_access(gic, GICD_CTLR, &val, false)?;
+    Ok(val)
+}
+
+/// Set the distributor control register.
+pub fn write_ctlr(gic: &Arc<dyn hypervisor::Device>, val: u32) -> Result<()> {
+    dist_attr_access(gic, GICD_CTLR, &val, true)
+}
+
+fn get_interrupts_num(gic: &Arc<dyn hypervisor::Device>) -> Result<u32> {
+    let num_irq = 0;
+
+    let mut nr_irqs_attr = kvm_device_attr {
+        group: KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
+        attr: 0,
+        addr: &num_irq as *const u32 as u64,
+        flags: 0,
+    };
+    gic.get_device_attr(&mut nr_irqs_attr)
+        .map_err(Error::GetDeviceAttribute)?;
+    Ok(num_irq)
+}
+
+fn compute_reg_len(gic: &Arc<dyn hypervisor::Device>, reg: &DistReg, base: u32) -> Result<u32> {
+    let mut end = base;
+    let num_irq = get_interrupts_num(gic)?;
+    if reg.length > 0 {
+        // This is the single type register (i.e one that is not DIST_X<n>) and for which
+        // the bpi is 0.
+        // Look in the kernel for REGISTER_DESC_WITH_LENGTH.
+        end = base + reg.length as u32;
+    }
+    if reg.bpi > 0 {
+        // This is the type of register that takes into account the number of interrupts
+        // that the model has. It is also the type of register where
+        // a register relates to multiple interrupts.
+        end = base + (reg.bpi as u32 * (num_irq - IRQ_BASE) / 8);
+        if reg.bpi as u32 * (num_irq - IRQ_BASE) % 8 > 0 {
+            end += REG_SIZE as u32;
+        }
+    }
+    Ok(end)
+}
+
+/// Set distributor registers of the GIC.
+pub fn set_dist_regs(gic: &Arc<dyn hypervisor::Device>, state: &[u32]) -> Result<()> {
+    let mut idx = 0;
+
+    for dreg in VGIC_DIST_REGS {
+        let mut base = dreg.base + REG_SIZE as u32 * dreg.bpi as u32;
+        let end = compute_reg_len(gic, dreg, base)?;
+
+        while base < end {
+            let val = state[idx];
+            dist_attr_access(gic, base, &val, true)?;
+            idx += 1;
+            base += REG_SIZE as u32;
+        }
+    }
+    Ok(())
+}
+/// Get distributor registers of the GIC.
+pub fn get_dist_regs(gic: &Arc<dyn hypervisor::Device>) -> Result<Vec<u32>> {
+    let mut state = Vec::new();
+
+    for dreg in VGIC_DIST_REGS {
+        let mut base = dreg.base + REG_SIZE as u32 * dreg.bpi as u32;
+        let end = compute_reg_len(gic, dreg, base)?;
+
+        while base < end {
+            let val: u32 = 0;
+            dist_attr_access(gic, base, &val, false)?;
+            state.push(val);
+            base += REG_SIZE as u32;
+        }
+    }
+    Ok(state)
+}

arch/src/aarch64/gic/gicv3.rs

@@ -0,0 +1,261 @@
+// Copyright 2021 Arm Limited (or its affiliates). All rights reserved.
+// Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+// SPDX-License-Identifier: Apache-2.0
+//
+// This file implements the GicV3 device.
+
+pub mod kvm {
+    use crate::aarch64::gic::dist_regs::{get_dist_regs, read_ctlr, set_dist_regs, write_ctlr};
+    use crate::aarch64::gic::icc_regs::{get_icc_regs, set_icc_regs};
+    use crate::aarch64::gic::kvm::{save_pending_tables, KvmGicDevice};
+    use crate::aarch64::gic::redist_regs::{
+        construct_gicr_typers, get_redist_regs, set_redist_regs,
+    };
+    use crate::aarch64::gic::GicDevice;
+    use crate::layout;
+    use anyhow::anyhow;
+    use hypervisor::kvm::kvm_bindings;
+    use hypervisor::CpuState;
+    use std::any::Any;
+    use std::convert::TryInto;
+    use std::sync::Arc;
+    use std::{boxed::Box, result};
+    use versionize::{VersionMap, Versionize, VersionizeResult};
+    use versionize_derive::Versionize;
+    use vm_migration::{
+        Migratable, MigratableError, Pausable, Snapshot, Snapshottable, Transportable,
+        VersionMapped,
+    };
+
+    /// Errors thrown while saving/restoring the GICv3.
+    #[derive(Debug)]
+    pub enum Error {
+        /// Error in saving RDIST pending tables into guest RAM.
+        SavePendingTables(crate::aarch64::gic::Error),
+        /// Error in saving GIC distributor registers.
+        SaveDistributorRegisters(crate::aarch64::gic::Error),
+        /// Error in restoring GIC distributor registers.
+        RestoreDistributorRegisters(crate::aarch64::gic::Error),
+        /// Error in saving GIC distributor control registers.
+        SaveDistributorCtrlRegisters(crate::aarch64::gic::Error),
+        /// Error in restoring GIC distributor control registers.
+        RestoreDistributorCtrlRegisters(crate::aarch64::gic::Error),
+        /// Error in saving GIC redistributor registers.
+        SaveRedistributorRegisters(crate::aarch64::gic::Error),
+        /// Error in restoring GIC redistributor registers.
+        RestoreRedistributorRegisters(crate::aarch64::gic::Error),
+        /// Error in saving GIC CPU interface registers.
+        SaveIccRegisters(crate::aarch64::gic::Error),
+        /// Error in restoring GIC CPU interface registers.
+        RestoreIccRegisters(crate::aarch64::gic::Error),
+    }
+
+    type Result<T> = result::Result<T, Error>;
+
+    pub struct KvmGicV3 {
+        /// The hypervisor agnostic device for the GicV3
+        device: Arc<dyn hypervisor::Device>,
+
+        /// Vector holding values of GICR_TYPER for each vCPU
+        gicr_typers: Vec<u64>,
+
+        /// GIC device properties, to be used for setting up the fdt entry
+        properties: [u64; 4],
+
+        /// Number of CPUs handled by the device
+        vcpu_count: u64,
+    }
+
+    #[derive(Versionize)]
+    pub struct Gicv3State {
+        dist: Vec<u32>,
+        rdist: Vec<u32>,
+        icc: Vec<u32>,
+        // special register that enables interrupts and affinity routing
+        gicd_ctlr: u32,
+    }
+
+    impl VersionMapped for Gicv3State {}
+
+    impl KvmGicV3 {
+        // Device trees specific constants
+        pub const ARCH_GIC_V3_MAINT_IRQ: u32 = 9;
+
+        /// Get the address of the GIC distributor.
+        pub fn get_dist_addr() -> u64 {
+            layout::GIC_V3_DIST_START
+        }
+
+        /// Get the size of the GIC distributor.
+        pub fn get_dist_size() -> u64 {
+            layout::GIC_V3_DIST_SIZE
+        }
+
+        /// Get the address of the GIC redistributors.
+        pub fn get_redists_addr(vcpu_count: u64) -> u64 {
+            KvmGicV3::get_dist_addr() - KvmGicV3::get_redists_size(vcpu_count)
+        }
+
+        /// Get the size of the GIC redistributors.
+        pub fn get_redists_size(vcpu_count: u64) -> u64 {
+            vcpu_count * layout::GIC_V3_REDIST_SIZE
+        }
+
+        /// Save the state of GIC.
+        fn state(&self, gicr_typers: &[u64]) -> Result<Gicv3State> {
+            let gicd_ctlr =
+                read_ctlr(self.device()).map_err(Error::SaveDistributorCtrlRegisters)?;
+
+            let dist_state =
+                get_dist_regs(self.device()).map_err(Error::SaveDistributorRegisters)?;
+
+            let rdist_state = get_redist_regs(self.device(), gicr_typers)
+                .map_err(Error::SaveRedistributorRegisters)?;
+
+            let icc_state =
+                get_icc_regs(self.device(), gicr_typers).map_err(Error::SaveIccRegisters)?;
+
+            Ok(Gicv3State {
+                dist: dist_state,
+                rdist: rdist_state,
+                icc: icc_state,
+                gicd_ctlr,
+            })
+        }
+
+        /// Restore the state of GIC.
+        fn set_state(&mut self, gicr_typers: &[u64], state: &Gicv3State) -> Result<()> {
+            write_ctlr(self.device(), state.gicd_ctlr)
+                .map_err(Error::RestoreDistributorCtrlRegisters)?;
+
+            set_dist_regs(self.device(), &state.dist)
+                .map_err(Error::RestoreDistributorRegisters)?;
+
+            set_redist_regs(self.device(), gicr_typers, &state.rdist)
+                .map_err(Error::RestoreRedistributorRegisters)?;
+
+            set_icc_regs(self.device(), gicr_typers, &state.icc)
+                .map_err(Error::RestoreIccRegisters)?;
+
+            Ok(())
+        }
+    }
+
+    impl GicDevice for KvmGicV3 {
+        fn device(&self) -> &Arc<dyn hypervisor::Device> {
+            &self.device
+        }
+
+        fn fdt_compatibility(&self) -> &str {
+            "arm,gic-v3"
+        }
+
+        fn fdt_maint_irq(&self) -> u32 {
+            KvmGicV3::ARCH_GIC_V3_MAINT_IRQ
+        }
+
+        fn device_properties(&self) -> &[u64] {
+            &self.properties
+        }
+
+        fn vcpu_count(&self) -> u64 {
+            self.vcpu_count
+        }
+
+        fn set_its_device(&mut self, _its_device: Option<Arc<dyn hypervisor::Device>>) {}
+
+        fn set_gicr_typers(&mut self, vcpu_states: &[CpuState]) {
+            let gicr_typers = construct_gicr_typers(vcpu_states);
+            self.gicr_typers = gicr_typers;
+        }
+
+        fn as_any_concrete_mut(&mut self) -> &mut dyn Any {
+            self
+        }
+    }
+
+    impl KvmGicDevice for KvmGicV3 {
+        fn version() -> u32 {
+            kvm_bindings::kvm_device_type_KVM_DEV_TYPE_ARM_VGIC_V3
+        }
+
+        fn create_device(
+            device: Arc<dyn hypervisor::Device>,
+            vcpu_count: u64,
+        ) -> Box<dyn GicDevice> {
+            Box::new(KvmGicV3 {
+                device,
+                gicr_typers: vec![0; vcpu_count.try_into().unwrap()],
+                properties: [
+                    KvmGicV3::get_dist_addr(),
+                    KvmGicV3::get_dist_size(),
+                    KvmGicV3::get_redists_addr(vcpu_count),
+                    KvmGicV3::get_redists_size(vcpu_count),
+                ],
+                vcpu_count,
+            })
+        }
+
+        fn init_device_attributes(
+            _vm: &Arc<dyn hypervisor::Vm>,
+            gic_device: &mut dyn GicDevice,
+        ) -> crate::aarch64::gic::Result<()> {
+            /* Setting up the distributor attribute.
+             We are placing the GIC below 1GB so we need to substract the size of the distributor.
+            */
+            Self::set_device_attribute(
+                gic_device.device(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ADDR,
+                u64::from(kvm_bindings::KVM_VGIC_V3_ADDR_TYPE_DIST),
+                &KvmGicV3::get_dist_addr() as *const u64 as u64,
+                0,
+            )?;
+
+            /* Setting up the redistributors' attribute.
+            We are calculating here the start of the redistributors address. We have one per CPU.
+            */
+            Self::set_device_attribute(
+                gic_device.device(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ADDR,
+                u64::from(kvm_bindings::KVM_VGIC_V3_ADDR_TYPE_REDIST),
+                &KvmGicV3::get_redists_addr(gic_device.vcpu_count()) as *const u64 as u64,
+                0,
+            )?;
+
+            Ok(())
+        }
+    }
+
+    pub const GIC_V3_SNAPSHOT_ID: &str = "gic-v3";
+    impl Snapshottable for KvmGicV3 {
+        fn id(&self) -> String {
+            GIC_V3_SNAPSHOT_ID.to_string()
+        }
+
+        fn snapshot(&mut self) -> std::result::Result<Snapshot, MigratableError> {
+            let gicr_typers = self.gicr_typers.clone();
+            Snapshot::new_from_versioned_state(&self.id(), &self.state(&gicr_typers).unwrap())
+        }
+
+        fn restore(&mut self, snapshot: Snapshot) -> std::result::Result<(), MigratableError> {
+            let gicr_typers = self.gicr_typers.clone();
+            self.set_state(&gicr_typers, &snapshot.to_versioned_state(&self.id())?)
+                .map_err(|e| {
+                    MigratableError::Restore(anyhow!("Could not restore GICv3 state {:?}", e))
+                })
+        }
+    }
+
+    impl Pausable for KvmGicV3 {
+        fn pause(&mut self) -> std::result::Result<(), MigratableError> {
+            // Flush redistributors pending tables to guest RAM.
+            save_pending_tables(self.device()).map_err(|e| {
+                MigratableError::Pause(anyhow!("Could not save GICv3 GIC pending tables {:?}", e))
+            })?;
+
+            Ok(())
+        }
+    }
+    impl Transportable for KvmGicV3 {}
+    impl Migratable for KvmGicV3 {}
+}

arch/src/aarch64/gic/gicv3_its.rs

@@ -0,0 +1,515 @@
+// Copyright 2021 Arm Limited (or its affiliates). All rights reserved.
+// SPDX-License-Identifier: Apache-2.0
+//
+// This file implements the GicV3 device with ITS (Virtual Interrupt Translation Service).
+
+pub mod kvm {
+    use crate::aarch64::gic::dist_regs::{get_dist_regs, read_ctlr, set_dist_regs, write_ctlr};
+    use crate::aarch64::gic::icc_regs::{get_icc_regs, set_icc_regs};
+    use crate::aarch64::gic::redist_regs::{
+        construct_gicr_typers, get_redist_regs, set_redist_regs,
+    };
+
+    use crate::aarch64::gic::gicv3::kvm::KvmGicV3;
+    use crate::aarch64::gic::kvm::{save_pending_tables, KvmGicDevice};
+    use crate::aarch64::gic::GicDevice;
+    use crate::layout;
+    use anyhow::anyhow;
+    use hypervisor::kvm::kvm_bindings;
+    use hypervisor::CpuState;
+    use std::any::Any;
+    use std::convert::TryInto;
+    use std::sync::Arc;
+    use std::{boxed::Box, result};
+    use versionize::{VersionMap, Versionize, VersionizeResult};
+    use versionize_derive::Versionize;
+    use vm_migration::{
+        Migratable, MigratableError, Pausable, Snapshot, Snapshottable, Transportable,
+        VersionMapped,
+    };
+
+    const GITS_CTLR: u32 = 0x0000;
+    const GITS_IIDR: u32 = 0x0004;
+    const GITS_CBASER: u32 = 0x0080;
+    const GITS_CWRITER: u32 = 0x0088;
+    const GITS_CREADR: u32 = 0x0090;
+    const GITS_BASER: u32 = 0x0100;
+
+    /// Errors thrown while saving/restoring the GICv3ITS.
+    #[derive(Debug)]
+    pub enum Error {
+        /// Error in saving RDIST pending tables into guest RAM.
+        SavePendingTables(crate::aarch64::gic::Error),
+        /// Error in saving GIC distributor registers.
+        SaveDistributorRegisters(crate::aarch64::gic::Error),
+        /// Error in restoring GIC distributor registers.
+        RestoreDistributorRegisters(crate::aarch64::gic::Error),
+        /// Error in saving GIC distributor control registers.
+        SaveDistributorCtrlRegisters(crate::aarch64::gic::Error),
+        /// Error in restoring GIC distributor control registers.
+        RestoreDistributorCtrlRegisters(crate::aarch64::gic::Error),
+        /// Error in saving GIC redistributor registers.
+        SaveRedistributorRegisters(crate::aarch64::gic::Error),
+        /// Error in restoring GIC redistributor registers.
+        RestoreRedistributorRegisters(crate::aarch64::gic::Error),
+        /// Error in saving GIC CPU interface registers.
+        SaveIccRegisters(crate::aarch64::gic::Error),
+        /// Error in restoring GIC CPU interface registers.
+        RestoreIccRegisters(crate::aarch64::gic::Error),
+        /// Error in saving GICv3ITS IIDR register.
+        SaveITSIIDR(crate::aarch64::gic::Error),
+        /// Error in restoring GICv3ITS IIDR register.
+        RestoreITSIIDR(crate::aarch64::gic::Error),
+        /// Error in saving GICv3ITS CBASER register.
+        SaveITSCBASER(crate::aarch64::gic::Error),
+        /// Error in restoring GICv3ITS CBASER register.
+        RestoreITSCBASER(crate::aarch64::gic::Error),
+        /// Error in saving GICv3ITS CREADR register.
+        SaveITSCREADR(crate::aarch64::gic::Error),
+        /// Error in restoring GICv3ITS CREADR register.
+        RestoreITSCREADR(crate::aarch64::gic::Error),
+        /// Error in saving GICv3ITS CWRITER register.
+        SaveITSCWRITER(crate::aarch64::gic::Error),
+        /// Error in restoring GICv3ITS CWRITER register.
+        RestoreITSCWRITER(crate::aarch64::gic::Error),
+        /// Error in saving GICv3ITS BASER register.
+        SaveITSBASER(crate::aarch64::gic::Error),
+        /// Error in restoring GICv3ITS BASER register.
+        RestoreITSBASER(crate::aarch64::gic::Error),
+        /// Error in saving GICv3ITS CTLR register.
+        SaveITSCTLR(crate::aarch64::gic::Error),
+        /// Error in restoring GICv3ITS CTLR register.
+        RestoreITSCTLR(crate::aarch64::gic::Error),
+        /// Error in saving GICv3ITS restore tables.
+        SaveITSTables(crate::aarch64::gic::Error),
+        /// Error in restoring GICv3ITS restore tables.
+        RestoreITSTables(crate::aarch64::gic::Error),
+    }
+
+    type Result<T> = result::Result<T, Error>;
+
+    /// Access an ITS device attribute.
+    ///
+    /// This is a helper function to get/set the ITS device attribute depending
+    /// the bool parameter `set` provided.
+    pub fn gicv3_its_attr_access(
+        its_device: &Arc<dyn hypervisor::Device>,
+        group: u32,
+        attr: u32,
+        val: &u64,
+        set: bool,
+    ) -> crate::aarch64::gic::Result<()> {
+        let mut gicv3_its_attr = kvm_bindings::kvm_device_attr {
+            group,
+            attr: attr as u64,
+            addr: val as *const u64 as u64,
+            flags: 0,
+        };
+        if set {
+            its_device
+                .set_device_attr(&gicv3_its_attr)
+                .map_err(crate::aarch64::gic::Error::SetDeviceAttribute)?;
+        } else {
+            its_device
+                .get_device_attr(&mut gicv3_its_attr)
+                .map_err(crate::aarch64::gic::Error::GetDeviceAttribute)?;
+        }
+        Ok(())
+    }
+
+    /// Function that saves/restores ITS tables into guest RAM.
+    ///
+    /// The tables get flushed to guest RAM whenever the VM gets stopped.
+    pub fn gicv3_its_tables_access(
+        its_device: &Arc<dyn hypervisor::Device>,
+        save: bool,
+    ) -> crate::aarch64::gic::Result<()> {
+        let attr: u64;
+        if save {
+            attr = u64::from(kvm_bindings::KVM_DEV_ARM_ITS_SAVE_TABLES);
+        } else {
+            attr = u64::from(kvm_bindings::KVM_DEV_ARM_ITS_RESTORE_TABLES);
+        }
+
+        let init_gic_attr = kvm_bindings::kvm_device_attr {
+            group: kvm_bindings::KVM_DEV_ARM_VGIC_GRP_CTRL,
+            attr,
+            addr: 0,
+            flags: 0,
+        };
+        its_device
+            .set_device_attr(&init_gic_attr)
+            .map_err(crate::aarch64::gic::Error::SetDeviceAttribute)
+    }
+
+    pub struct KvmGicV3Its {
+        /// The hypervisor agnostic device for the GicV3
+        device: Arc<dyn hypervisor::Device>,
+
+        /// The hypervisor agnostic device for the Its device
+        its_device: Option<Arc<dyn hypervisor::Device>>,
+
+        /// Vector holding values of GICR_TYPER for each vCPU
+        gicr_typers: Vec<u64>,
+
+        /// GIC device properties, to be used for setting up the fdt entry
+        gic_properties: [u64; 4],
+
+        /// MSI device properties, to be used for setting up the fdt entry
+        msi_properties: [u64; 2],
+
+        /// Number of CPUs handled by the device
+        vcpu_count: u64,
+    }
+
+    #[derive(Versionize)]
+    pub struct Gicv3ItsState {
+        dist: Vec<u32>,
+        rdist: Vec<u32>,
+        icc: Vec<u32>,
+        // special register that enables interrupts and affinity routing
+        gicd_ctlr: u32,
+        its_ctlr: u64,
+        its_iidr: u64,
+        its_cbaser: u64,
+        its_cwriter: u64,
+        its_creadr: u64,
+        its_baser: [u64; 8],
+    }
+
+    impl VersionMapped for Gicv3ItsState {}
+
+    impl KvmGicV3Its {
+        fn get_msi_size() -> u64 {
+            layout::GIC_V3_ITS_SIZE
+        }
+
+        fn get_msi_addr(vcpu_count: u64) -> u64 {
+            KvmGicV3::get_redists_addr(vcpu_count) - KvmGicV3Its::get_msi_size()
+        }
+
+        /// Save the state of GICv3ITS.
+        fn state(&self, gicr_typers: &[u64]) -> Result<Gicv3ItsState> {
+            let gicd_ctlr =
+                read_ctlr(self.device()).map_err(Error::SaveDistributorCtrlRegisters)?;
+
+            let dist_state =
+                get_dist_regs(self.device()).map_err(Error::SaveDistributorRegisters)?;
+
+            let rdist_state = get_redist_regs(self.device(), gicr_typers)
+                .map_err(Error::SaveRedistributorRegisters)?;
+
+            let icc_state =
+                get_icc_regs(self.device(), gicr_typers).map_err(Error::SaveIccRegisters)?;
+
+            let its_baser_state: [u64; 8] = [0; 8];
+            for i in 0..8 {
+                gicv3_its_attr_access(
+                    self.its_device().unwrap(),
+                    kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                    GITS_BASER + i * 8,
+                    &its_baser_state[i as usize],
+                    false,
+                )
+                .map_err(Error::SaveITSBASER)?;
+            }
+
+            let its_ctlr_state: u64 = 0;
+            gicv3_its_attr_access(
+                self.its_device().unwrap(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                GITS_CTLR,
+                &its_ctlr_state,
+                false,
+            )
+            .map_err(Error::SaveITSCTLR)?;
+
+            let its_cbaser_state: u64 = 0;
+            gicv3_its_attr_access(
+                self.its_device().unwrap(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                GITS_CBASER,
+                &its_cbaser_state,
+                false,
+            )
+            .map_err(Error::SaveITSCBASER)?;
+
+            let its_creadr_state: u64 = 0;
+            gicv3_its_attr_access(
+                self.its_device().unwrap(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                GITS_CREADR,
+                &its_creadr_state,
+                false,
+            )
+            .map_err(Error::SaveITSCREADR)?;
+
+            let its_cwriter_state: u64 = 0;
+            gicv3_its_attr_access(
+                self.its_device().unwrap(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                GITS_CWRITER,
+                &its_cwriter_state,
+                false,
+            )
+            .map_err(Error::SaveITSCWRITER)?;
+
+            let its_iidr_state: u64 = 0;
+            gicv3_its_attr_access(
+                self.its_device().unwrap(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                GITS_IIDR,
+                &its_iidr_state,
+                false,
+            )
+            .map_err(Error::SaveITSIIDR)?;
+
+            Ok(Gicv3ItsState {
+                dist: dist_state,
+                rdist: rdist_state,
+                icc: icc_state,
+                gicd_ctlr,
+                its_ctlr: its_ctlr_state,
+                its_iidr: its_iidr_state,
+                its_cbaser: its_cbaser_state,
+                its_cwriter: its_cwriter_state,
+                its_creadr: its_creadr_state,
+                its_baser: its_baser_state,
+            })
+        }
+
+        /// Restore the state of GICv3ITS.
+        fn set_state(&mut self, gicr_typers: &[u64], state: &Gicv3ItsState) -> Result<()> {
+            write_ctlr(self.device(), state.gicd_ctlr)
+                .map_err(Error::RestoreDistributorCtrlRegisters)?;
+
+            set_dist_regs(self.device(), &state.dist)
+                .map_err(Error::RestoreDistributorRegisters)?;
+
+            set_redist_regs(self.device(), gicr_typers, &state.rdist)
+                .map_err(Error::RestoreRedistributorRegisters)?;
+
+            set_icc_regs(self.device(), gicr_typers, &state.icc)
+                .map_err(Error::RestoreIccRegisters)?;
+
+            //Restore GICv3ITS registers
+            gicv3_its_attr_access(
+                self.its_device().unwrap(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                GITS_IIDR,
+                &state.its_iidr,
+                true,
+            )
+            .map_err(Error::RestoreITSIIDR)?;
+
+            gicv3_its_attr_access(
+                self.its_device().unwrap(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                GITS_CBASER,
+                &state.its_cbaser,
+                true,
+            )
+            .map_err(Error::RestoreITSCBASER)?;
+
+            gicv3_its_attr_access(
+                self.its_device().unwrap(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                GITS_CREADR,
+                &state.its_creadr,
+                true,
+            )
+            .map_err(Error::RestoreITSCREADR)?;
+
+            gicv3_its_attr_access(
+                self.its_device().unwrap(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                GITS_CWRITER,
+                &state.its_cwriter,
+                true,
+            )
+            .map_err(Error::RestoreITSCWRITER)?;
+
+            for i in 0..8 {
+                gicv3_its_attr_access(
+                    self.its_device().unwrap(),
+                    kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                    GITS_BASER + i * 8,
+                    &state.its_baser[i as usize],
+                    true,
+                )
+                .map_err(Error::RestoreITSBASER)?;
+            }
+
+            // Restore ITS tables
+            gicv3_its_tables_access(self.its_device().unwrap(), false)
+                .map_err(Error::RestoreITSTables)?;
+
+            gicv3_its_attr_access(
+                self.its_device().unwrap(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ITS_REGS,
+                GITS_CTLR,
+                &state.its_ctlr,
+                true,
+            )
+            .map_err(Error::RestoreITSCTLR)?;
+
+            Ok(())
+        }
+    }
+
+    impl GicDevice for KvmGicV3Its {
+        fn device(&self) -> &Arc<dyn hypervisor::Device> {
+            &self.device
+        }
+
+        fn its_device(&self) -> Option<&Arc<dyn hypervisor::Device>> {
+            self.its_device.as_ref()
+        }
+
+        fn fdt_compatibility(&self) -> &str {
+            "arm,gic-v3"
+        }
+
+        fn msi_compatible(&self) -> bool {
+            true
+        }
+
+        fn msi_compatibility(&self) -> &str {
+            "arm,gic-v3-its"
+        }
+
+        fn fdt_maint_irq(&self) -> u32 {
+            KvmGicV3::ARCH_GIC_V3_MAINT_IRQ
+        }
+
+        fn msi_properties(&self) -> &[u64] {
+            &self.msi_properties
+        }
+
+        fn device_properties(&self) -> &[u64] {
+            &self.gic_properties
+        }
+
+        fn vcpu_count(&self) -> u64 {
+            self.vcpu_count
+        }
+
+        fn set_its_device(&mut self, its_device: Option<Arc<dyn hypervisor::Device>>) {
+            self.its_device = its_device;
+        }
+
+        fn set_gicr_typers(&mut self, vcpu_states: &[CpuState]) {
+            let gicr_typers = construct_gicr_typers(vcpu_states);
+            self.gicr_typers = gicr_typers;
+        }
+
+        fn as_any_concrete_mut(&mut self) -> &mut dyn Any {
+            self
+        }
+    }
+
+    impl KvmGicDevice for KvmGicV3Its {
+        fn version() -> u32 {
+            KvmGicV3::version()
+        }
+
+        fn create_device(
+            device: Arc<dyn hypervisor::Device>,
+            vcpu_count: u64,
+        ) -> Box<dyn GicDevice> {
+            Box::new(KvmGicV3Its {
+                device,
+                its_device: None,
+                gicr_typers: vec![0; vcpu_count.try_into().unwrap()],
+                gic_properties: [
+                    KvmGicV3::get_dist_addr(),
+                    KvmGicV3::get_dist_size(),
+                    KvmGicV3::get_redists_addr(vcpu_count),
+                    KvmGicV3::get_redists_size(vcpu_count),
+                ],
+                msi_properties: [
+                    KvmGicV3Its::get_msi_addr(vcpu_count),
+                    KvmGicV3Its::get_msi_size(),
+                ],
+                vcpu_count,
+            })
+        }
+
+        fn init_device_attributes(
+            vm: &Arc<dyn hypervisor::Vm>,
+            gic_device: &mut dyn GicDevice,
+        ) -> crate::aarch64::gic::Result<()> {
+            KvmGicV3::init_device_attributes(vm, gic_device)?;
+
+            let mut its_device = kvm_bindings::kvm_create_device {
+                type_: kvm_bindings::kvm_device_type_KVM_DEV_TYPE_ARM_VGIC_ITS,
+                fd: 0,
+                flags: 0,
+            };
+
+            let its_fd = vm
+                .create_device(&mut its_device)
+                .map_err(crate::aarch64::gic::Error::CreateGic)?;
+
+            Self::set_device_attribute(
+                &its_fd,
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ADDR,
+                u64::from(kvm_bindings::KVM_VGIC_ITS_ADDR_TYPE),
+                &KvmGicV3Its::get_msi_addr(gic_device.vcpu_count()) as *const u64 as u64,
+                0,
+            )?;
+
+            Self::set_device_attribute(
+                &its_fd,
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_CTRL,
+                u64::from(kvm_bindings::KVM_DEV_ARM_VGIC_CTRL_INIT),
+                0,
+                0,
+            )?;
+
+            gic_device.set_its_device(Some(its_fd));
+
+            Ok(())
+        }
+    }
+
+    pub const GIC_V3_ITS_SNAPSHOT_ID: &str = "gic-v3-its";
+    impl Snapshottable for KvmGicV3Its {
+        fn id(&self) -> String {
+            GIC_V3_ITS_SNAPSHOT_ID.to_string()
+        }
+
+        fn snapshot(&mut self) -> std::result::Result<Snapshot, MigratableError> {
+            let gicr_typers = self.gicr_typers.clone();
+            Snapshot::new_from_versioned_state(&self.id(), &self.state(&gicr_typers).unwrap())
+        }
+
+        fn restore(&mut self, snapshot: Snapshot) -> std::result::Result<(), MigratableError> {
+            let gicr_typers = self.gicr_typers.clone();
+            self.set_state(&gicr_typers, &snapshot.to_versioned_state(&self.id())?)
+                .map_err(|e| {
+                    MigratableError::Restore(anyhow!("Could not restore GICv3ITS state {:?}", e))
+                })
+        }
+    }
+
+    impl Pausable for KvmGicV3Its {
+        fn pause(&mut self) -> std::result::Result<(), MigratableError> {
+            // Flush redistributors pending tables to guest RAM.
+            save_pending_tables(self.device()).map_err(|e| {
+                MigratableError::Pause(anyhow!(
+                    "Could not save GICv3ITS GIC pending tables {:?}",
+                    e
+                ))
+            })?;
+            // Flush ITS tables to guest RAM.
+            gicv3_its_tables_access(self.its_device().unwrap(), true).map_err(|e| {
+                MigratableError::Pause(anyhow!("Could not save GICv3ITS ITS tables {:?}", e))
+            })?;
+
+            Ok(())
+        }
+    }
+    impl Transportable for KvmGicV3Its {}
+    impl Migratable for KvmGicV3Its {}
+}

arch/src/aarch64/gic/icc_regs.rs

@@ -0,0 +1,196 @@
+// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+// SPDX-License-Identifier: Apache-2.0
+
+use super::{Error, Result};
+use hypervisor::kvm::kvm_bindings::{
+    kvm_device_attr, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, KVM_REG_ARM64_SYSREG_CRM_MASK,
+    KVM_REG_ARM64_SYSREG_CRM_SHIFT, KVM_REG_ARM64_SYSREG_CRN_MASK, KVM_REG_ARM64_SYSREG_CRN_SHIFT,
+    KVM_REG_ARM64_SYSREG_OP0_MASK, KVM_REG_ARM64_SYSREG_OP0_SHIFT, KVM_REG_ARM64_SYSREG_OP1_MASK,
+    KVM_REG_ARM64_SYSREG_OP1_SHIFT, KVM_REG_ARM64_SYSREG_OP2_MASK, KVM_REG_ARM64_SYSREG_OP2_SHIFT,
+};
+use std::sync::Arc;
+
+const KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT: u32 = 32;
+const KVM_DEV_ARM_VGIC_V3_MPIDR_MASK: u64 = 0xffffffff << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT as u64;
+
+const ICC_CTLR_EL1_PRIBITS_SHIFT: u32 = 8;
+const ICC_CTLR_EL1_PRIBITS_MASK: u32 = 7 << ICC_CTLR_EL1_PRIBITS_SHIFT;
+
+macro_rules! arm64_vgic_sys_reg {
+    ($name: tt, $op0: tt, $op1: tt, $crn: tt, $crm: tt, $op2: expr) => {
+        const $name: u64 = ((($op0 as u64) << KVM_REG_ARM64_SYSREG_OP0_SHIFT)
+            & KVM_REG_ARM64_SYSREG_OP0_MASK as u64)
+            | ((($op1 as u64) << KVM_REG_ARM64_SYSREG_OP1_SHIFT)
+                & KVM_REG_ARM64_SYSREG_OP1_MASK as u64)
+            | ((($crn as u64) << KVM_REG_ARM64_SYSREG_CRN_SHIFT)
+                & KVM_REG_ARM64_SYSREG_CRN_MASK as u64)
+            | ((($crm as u64) << KVM_REG_ARM64_SYSREG_CRM_SHIFT)
+                & KVM_REG_ARM64_SYSREG_CRM_MASK as u64)
+            | ((($op2 as u64) << KVM_REG_ARM64_SYSREG_OP2_SHIFT)
+                & KVM_REG_ARM64_SYSREG_OP2_MASK as u64);
+    };
+}
+
+macro_rules! SYS_ICC_AP0Rn_EL1 {
+    ($name: tt, $n: tt) => {
+        arm64_vgic_sys_reg!($name, 3, 0, 12, 8, (4 | $n));
+    };
+}
+
+macro_rules! SYS_ICC_AP1Rn_EL1 {
+    ($name: tt, $n: tt) => {
+        arm64_vgic_sys_reg!($name, 3, 0, 12, 9, $n);
+    };
+}
+
+arm64_vgic_sys_reg!(SYS_ICC_SRE_EL1, 3, 0, 12, 12, 5);
+arm64_vgic_sys_reg!(SYS_ICC_CTLR_EL1, 3, 0, 12, 12, 4);
+arm64_vgic_sys_reg!(SYS_ICC_IGRPEN0_EL1, 3, 0, 12, 12, 6);
+arm64_vgic_sys_reg!(SYS_ICC_IGRPEN1_EL1, 3, 0, 12, 12, 7);
+arm64_vgic_sys_reg!(SYS_ICC_PMR_EL1, 3, 0, 4, 6, 0);
+arm64_vgic_sys_reg!(SYS_ICC_BPR0_EL1, 3, 0, 12, 8, 3);
+arm64_vgic_sys_reg!(SYS_ICC_BPR1_EL1, 3, 0, 12, 12, 3);
+SYS_ICC_AP0Rn_EL1!(SYS_ICC_AP0R0_EL1, 0);
+SYS_ICC_AP0Rn_EL1!(SYS_ICC_AP0R1_EL1, 1);
+SYS_ICC_AP0Rn_EL1!(SYS_ICC_AP0R2_EL1, 2);
+SYS_ICC_AP0Rn_EL1!(SYS_ICC_AP0R3_EL1, 3);
+SYS_ICC_AP1Rn_EL1!(SYS_ICC_AP1R0_EL1, 0);
+SYS_ICC_AP1Rn_EL1!(SYS_ICC_AP1R1_EL1, 1);
+SYS_ICC_AP1Rn_EL1!(SYS_ICC_AP1R2_EL1, 2);
+SYS_ICC_AP1Rn_EL1!(SYS_ICC_AP1R3_EL1, 3);
+
+static VGIC_ICC_REGS: &'static [u64] = &[
+    SYS_ICC_SRE_EL1,
+    SYS_ICC_CTLR_EL1,
+    SYS_ICC_IGRPEN0_EL1,
+    SYS_ICC_IGRPEN1_EL1,
+    SYS_ICC_PMR_EL1,
+    SYS_ICC_BPR0_EL1,
+    SYS_ICC_BPR1_EL1,
+    SYS_ICC_AP0R0_EL1,
+    SYS_ICC_AP0R1_EL1,
+    SYS_ICC_AP0R2_EL1,
+    SYS_ICC_AP0R3_EL1,
+    SYS_ICC_AP1R0_EL1,
+    SYS_ICC_AP1R1_EL1,
+    SYS_ICC_AP1R2_EL1,
+    SYS_ICC_AP1R3_EL1,
+];
+
+fn icc_attr_access(
+    gic: &Arc<dyn hypervisor::Device>,
+    offset: u64,
+    typer: u64,
+    val: &u32,
+    set: bool,
+) -> Result<()> {
+    let mut gic_icc_attr = kvm_device_attr {
+        group: KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
+        attr: ((typer & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) | offset), // this needs the mpidr
+        addr: val as *const u32 as u64,
+        flags: 0,
+    };
+    if set {
+        #[allow(clippy::unnecessary_mut_passed)]
+        gic.set_device_attr(&mut gic_icc_attr)
+            .map_err(Error::SetDeviceAttribute)?;
+    } else {
+        gic.get_device_attr(&mut gic_icc_attr)
+            .map_err(Error::GetDeviceAttribute)?;
+    }
+    Ok(())
+}
+
+/// Get ICC registers.
+pub fn get_icc_regs(gic: &Arc<dyn hypervisor::Device>, gicr_typer: &[u64]) -> Result<Vec<u32>> {
+    let mut state: Vec<u32> = Vec::new();
+    // We need this for the ICC_AP<m>R<n>_EL1 registers.
+    let mut num_priority_bits = 0;
+
+    for ix in gicr_typer {
+        let i = *ix;
+        for icc_offset in VGIC_ICC_REGS {
+            let val = 0;
+            if *icc_offset == SYS_ICC_CTLR_EL1 {
+                // calculate priority bits by reading the ctrl_el1 register.
+                icc_attr_access(gic, *icc_offset, i, &val, false)?;
+                // The priority bits are found in the ICC_CTLR_EL1 register (bits from  10:8).
+                // See page 194 from https://static.docs.arm.com/ihi0069/c/IHI0069C_gic_
+                // architecture_specification.pdf.
+                // Citation:
+                // "Priority bits. Read-only and writes are ignored. The number of priority bits
+                // implemented, minus one."
+                num_priority_bits =
+                    ((val & ICC_CTLR_EL1_PRIBITS_MASK) >> ICC_CTLR_EL1_PRIBITS_SHIFT) + 1;
+                state.push(val);
+            }
+            // As per ARMv8 documentation: https://static.docs.arm.com/ihi0069/c/IHI0069C_
+            // gic_architecture_specification.pdf
+            // page 178,
+            // ICC_AP0R1_EL1 is only implemented in implementations that support 6 or more bits of
+            // priority.
+            // ICC_AP0R2_EL1 and ICC_AP0R3_EL1 are only implemented in implementations that support
+            // 7 bits of priority.
+            else if *icc_offset == SYS_ICC_AP0R1_EL1 || *icc_offset == SYS_ICC_AP1R1_EL1 {
+                if num_priority_bits >= 6 {
+                    icc_attr_access(gic, *icc_offset, i, &val, false)?;
+                    state.push(val);
+                }
+            } else if *icc_offset == SYS_ICC_AP0R2_EL1
+                || *icc_offset == SYS_ICC_AP0R3_EL1
+                || *icc_offset == SYS_ICC_AP1R2_EL1
+                || *icc_offset == SYS_ICC_AP1R3_EL1
+            {
+                if num_priority_bits == 7 {
+                    icc_attr_access(gic, *icc_offset, i, &val, false)?;
+                    state.push(val);
+                }
+            } else {
+                icc_attr_access(gic, *icc_offset, i, &val, false)?;
+                state.push(val);
+            }
+        }
+    }
+    Ok(state)
+}
+
+/// Set ICC registers.
+pub fn set_icc_regs(
+    gic: &Arc<dyn hypervisor::Device>,
+    gicr_typer: &[u64],
+    state: &[u32],
+) -> Result<()> {
+    let mut num_priority_bits = 0;
+    let mut idx = 0;
+    for ix in gicr_typer {
+        let i = *ix;
+        for icc_offset in VGIC_ICC_REGS {
+            if *icc_offset == SYS_ICC_CTLR_EL1 {
+                let ctrl_el1 = state[idx];
+                num_priority_bits =
+                    ((ctrl_el1 & ICC_CTLR_EL1_PRIBITS_MASK) >> ICC_CTLR_EL1_PRIBITS_SHIFT) + 1;
+            }
+            if *icc_offset == SYS_ICC_AP0R1_EL1 || *icc_offset == SYS_ICC_AP1R1_EL1 {
+                if num_priority_bits >= 6 {
+                    icc_attr_access(gic, *icc_offset, i, &state[idx], true)?;
+                    idx += 1;
+                }
+                continue;
+            }
+            if *icc_offset == SYS_ICC_AP0R2_EL1
+                || *icc_offset == SYS_ICC_AP0R3_EL1
+                || *icc_offset == SYS_ICC_AP1R2_EL1
+                || *icc_offset == SYS_ICC_AP1R3_EL1
+            {
+                if num_priority_bits == 7 {
+                    icc_attr_access(gic, *icc_offset, i, &state[idx], true)?;
+                    idx += 1;
+                }
+                continue;
+            }
+            icc_attr_access(gic, *icc_offset, i, &state[idx], true)?;
+            idx += 1;
+        }
+    }
+    Ok(())
+}

arch/src/aarch64/gic/mod.rs

@@ -0,0 +1,220 @@
+// Copyright 2021 Arm Limited (or its affiliates). All rights reserved.
+// Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+// SPDX-License-Identifier: Apache-2.0
+
+pub mod dist_regs;
+pub mod gicv3;
+pub mod gicv3_its;
+pub mod icc_regs;
+pub mod redist_regs;
+
+pub use self::dist_regs::{get_dist_regs, read_ctlr, set_dist_regs, write_ctlr};
+pub use self::icc_regs::{get_icc_regs, set_icc_regs};
+pub use self::redist_regs::{get_redist_regs, set_redist_regs};
+use hypervisor::CpuState;
+use std::any::Any;
+use std::result;
+use std::sync::Arc;
+
+/// Errors thrown while setting up the GIC.
+#[derive(Debug)]
+pub enum Error {
+    /// Error while calling KVM ioctl for setting up the global interrupt controller.
+    CreateGic(hypervisor::HypervisorVmError),
+    /// Error while setting device attributes for the GIC.
+    SetDeviceAttribute(hypervisor::HypervisorDeviceError),
+    /// Error while getting device attributes for the GIC.
+    GetDeviceAttribute(hypervisor::HypervisorDeviceError),
+}
+type Result<T> = result::Result<T, Error>;
+
+pub trait GicDevice: Send {
+    /// Returns the hypervisor agnostic Device of the GIC device
+    fn device(&self) -> &Arc<dyn hypervisor::Device>;
+
+    /// Returns the hypervisor agnostic Device of the ITS device
+    fn its_device(&self) -> Option<&Arc<dyn hypervisor::Device>> {
+        None
+    }
+
+    /// Returns the fdt compatibility property of the device
+    fn fdt_compatibility(&self) -> &str;
+
+    /// Returns the maint_irq fdt property of the device
+    fn fdt_maint_irq(&self) -> u32;
+
+    /// Returns an array with GIC device properties
+    fn device_properties(&self) -> &[u64];
+
+    /// Returns the number of vCPUs this GIC handles
+    fn vcpu_count(&self) -> u64;
+
+    /// Returns whether the GIC device is MSI compatible or not
+    fn msi_compatible(&self) -> bool {
+        false
+    }
+
+    /// Returns the MSI compatibility property of the device
+    fn msi_compatibility(&self) -> &str {
+        ""
+    }
+
+    /// Returns the MSI reg property of the device
+    fn msi_properties(&self) -> &[u64] {
+        &[]
+    }
+
+    fn set_its_device(&mut self, its_device: Option<Arc<dyn hypervisor::Device>>);
+
+    /// Get the values of GICR_TYPER for each vCPU.
+    fn set_gicr_typers(&mut self, vcpu_states: &[CpuState]);
+
+    /// Downcast the trait object to its concrete type.
+    fn as_any_concrete_mut(&mut self) -> &mut dyn Any;
+}
+
+pub mod kvm {
+    use super::GicDevice;
+    use super::Result;
+    use crate::aarch64::gic::gicv3_its::kvm::KvmGicV3Its;
+    use crate::layout;
+    use hypervisor::kvm::kvm_bindings;
+    use std::boxed::Box;
+    use std::sync::Arc;
+
+    /// Trait for GIC devices.
+    pub trait KvmGicDevice: Send + Sync + GicDevice {
+        /// Returns the GIC version of the device
+        fn version() -> u32;
+
+        /// Create the GIC device object
+        fn create_device(
+            device: Arc<dyn hypervisor::Device>,
+            vcpu_count: u64,
+        ) -> Box<dyn GicDevice>;
+
+        /// Setup the device-specific attributes
+        fn init_device_attributes(
+            vm: &Arc<dyn hypervisor::Vm>,
+            gic_device: &mut dyn GicDevice,
+        ) -> Result<()>;
+
+        /// Initialize a GIC device
+        fn init_device(vm: &Arc<dyn hypervisor::Vm>) -> Result<Arc<dyn hypervisor::Device>> {
+            let mut gic_device = kvm_bindings::kvm_create_device {
+                type_: Self::version(),
+                fd: 0,
+                flags: 0,
+            };
+
+            vm.create_device(&mut gic_device)
+                .map_err(super::Error::CreateGic)
+        }
+
+        /// Set a GIC device attribute
+        fn set_device_attribute(
+            device: &Arc<dyn hypervisor::Device>,
+            group: u32,
+            attr: u64,
+            addr: u64,
+            flags: u32,
+        ) -> Result<()> {
+            let attr = kvm_bindings::kvm_device_attr {
+                flags,
+                group,
+                attr,
+                addr,
+            };
+            device
+                .set_device_attr(&attr)
+                .map_err(super::Error::SetDeviceAttribute)?;
+
+            Ok(())
+        }
+
+        /// Get a GIC device attribute
+        fn get_device_attribute(
+            device: &Arc<dyn hypervisor::Device>,
+            group: u32,
+            attr: u64,
+            addr: u64,
+            flags: u32,
+        ) -> Result<()> {
+            let mut attr = kvm_bindings::kvm_device_attr {
+                flags,
+                group,
+                attr,
+                addr,
+            };
+            device
+                .get_device_attr(&mut attr)
+                .map_err(super::Error::GetDeviceAttribute)?;
+
+            Ok(())
+        }
+
+        /// Finalize the setup of a GIC device
+        fn finalize_device(gic_device: &dyn GicDevice) -> Result<()> {
+            /* We need to tell the kernel how many irqs to support with this vgic.
+             * See the `layout` module for details.
+             */
+            let nr_irqs: u32 = layout::IRQ_NUM;
+            let nr_irqs_ptr = &nr_irqs as *const u32;
+            Self::set_device_attribute(
+                gic_device.device(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
+                0,
+                nr_irqs_ptr as u64,
+                0,
+            )?;
+
+            /* Finalize the GIC.
+             * See https://code.woboq.org/linux/linux/virt/kvm/arm/vgic/vgic-kvm-device.c.html#211.
+             */
+            Self::set_device_attribute(
+                gic_device.device(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_CTRL,
+                u64::from(kvm_bindings::KVM_DEV_ARM_VGIC_CTRL_INIT),
+                0,
+                0,
+            )?;
+
+            Ok(())
+        }
+
+        /// Method to initialize the GIC device
+        #[allow(clippy::new_ret_no_self)]
+        fn new(vm: &Arc<dyn hypervisor::Vm>, vcpu_count: u64) -> Result<Box<dyn GicDevice>> {
+            let vgic_fd = Self::init_device(vm)?;
+
+            let mut device = Self::create_device(vgic_fd, vcpu_count);
+
+            Self::init_device_attributes(vm, &mut *device)?;
+
+            Self::finalize_device(&*device)?;
+
+            Ok(device)
+        }
+    }
+
+    /// Create a GICv3-ITS device.
+    ///
+    pub fn create_gic(vm: &Arc<dyn hypervisor::Vm>, vcpu_count: u64) -> Result<Box<dyn GicDevice>> {
+        debug!("creating a GICv3-ITS");
+        KvmGicV3Its::new(vm, vcpu_count)
+    }
+
+    /// Function that saves RDIST pending tables into guest RAM.
+    ///
+    /// The tables get flushed to guest RAM whenever the VM gets stopped.
+    pub fn save_pending_tables(gic: &Arc<dyn hypervisor::Device>) -> Result<()> {
+        let init_gic_attr = kvm_bindings::kvm_device_attr {
+            group: kvm_bindings::KVM_DEV_ARM_VGIC_GRP_CTRL,
+            attr: u64::from(kvm_bindings::KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES),
+            addr: 0,
+            flags: 0,
+        };
+        gic.set_device_attr(&init_gic_attr)
+            .map_err(super::Error::SetDeviceAttribute)
+    }
+}

arch/src/aarch64/gic/redist_regs.rs

@@ -0,0 +1,211 @@
+// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+// SPDX-License-Identifier: Apache-2.0
+
+use super::{Error, Result};
+use hypervisor::kvm::kvm_bindings::{kvm_device_attr, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS};
+use hypervisor::CpuState;
+use std::sync::Arc;
+
+// Relevant redistributor registers that we want to save/restore.
+const GICR_CTLR: u32 = 0x0000;
+const GICR_STATUSR: u32 = 0x0010;
+const GICR_WAKER: u32 = 0x0014;
+const GICR_PROPBASER: u32 = 0x0070;
+const GICR_PENDBASER: u32 = 0x0078;
+
+/* SGI and PPI Redistributor registers, offsets from RD_base */
+/*
+ * Redistributor frame offsets from RD_base which is actually SZ_
+ */
+const GICR_SGI_OFFSET: u32 = 0x0001_0000;
+const GICR_IGROUPR0: u32 = GICR_SGI_OFFSET + 0x0080;
+const GICR_ICENABLER0: u32 = GICR_SGI_OFFSET + 0x0180;
+const GICR_ISENABLER0: u32 = GICR_SGI_OFFSET + 0x0100;
+const GICR_ISPENDR0: u32 = GICR_SGI_OFFSET + 0x0200;
+const GICR_ICPENDR0: u32 = GICR_SGI_OFFSET + 0x0280;
+const GICR_ISACTIVER0: u32 = GICR_SGI_OFFSET + 0x0300;
+const GICR_ICACTIVER0: u32 = GICR_SGI_OFFSET + 0x0380;
+const GICR_IPRIORITYR0: u32 = GICR_SGI_OFFSET + 0x0400;
+const GICR_ICFGR0: u32 = GICR_SGI_OFFSET + 0x0C00;
+
+const KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT: u32 = 32;
+const KVM_DEV_ARM_VGIC_V3_MPIDR_MASK: u64 = 0xffffffff << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT as u64;
+
+/// This is how we represent the registers of a distributor.
+/// It is relrvant their offset from the base address of the
+/// distributor.
+/// Each register has a different number
+/// of bits_per_irq and is therefore variable length.
+/// First 32 interrupts (0-32) are private to each CPU (SGIs and PPIs).
+/// and so we save the first irq to identify between the type of the interrupt
+/// that the respective register deals with.
+struct RdistReg {
+    /// Offset from distributor address.
+    base: u32,
+    /// Length of the register.
+    length: u8,
+}
+
+// All or at least the registers we are interested in are 32 bit, so
+// we use a constant for size(u32).
+const REG_SIZE: u8 = 4;
+
+// Creates a vgic redistributor register.
+macro_rules! VGIC_RDIST_REG {
+    ($base:expr, $len:expr) => {
+        RdistReg {
+            base: $base,
+            length: $len,
+        }
+    };
+}
+
+// List with relevant distributor registers that we will be restoring.
+static VGIC_RDIST_REGS: &'static [RdistReg] = &[
+    VGIC_RDIST_REG!(GICR_STATUSR, 4),
+    VGIC_RDIST_REG!(GICR_WAKER, 4),
+    VGIC_RDIST_REG!(GICR_PROPBASER, 8),
+    VGIC_RDIST_REG!(GICR_PENDBASER, 8),
+    VGIC_RDIST_REG!(GICR_CTLR, 4),
+];
+
+// List with relevant distributor registers that we will be restoring.
+static VGIC_SGI_REGS: &'static [RdistReg] = &[
+    VGIC_RDIST_REG!(GICR_IGROUPR0, 4),
+    VGIC_RDIST_REG!(GICR_ICENABLER0, 4),
+    VGIC_RDIST_REG!(GICR_ISENABLER0, 4),
+    VGIC_RDIST_REG!(GICR_ICFGR0, 8),
+    VGIC_RDIST_REG!(GICR_ICPENDR0, 4),
+    VGIC_RDIST_REG!(GICR_ISPENDR0, 4),
+    VGIC_RDIST_REG!(GICR_ICACTIVER0, 4),
+    VGIC_RDIST_REG!(GICR_ISACTIVER0, 4),
+    VGIC_RDIST_REG!(GICR_IPRIORITYR0, 32),
+];
+
+fn redist_attr_access(
+    gic: &Arc<dyn hypervisor::Device>,
+    offset: u32,
+    typer: u64,
+    val: &u32,
+    set: bool,
+) -> Result<()> {
+    let mut gic_dist_attr = kvm_device_attr {
+        group: KVM_DEV_ARM_VGIC_GRP_REDIST_REGS,
+        attr: (typer & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) | (offset as u64), // this needs the mpidr
+        addr: val as *const u32 as u64,
+        flags: 0,
+    };
+    if set {
+        #[allow(clippy::unnecessary_mut_passed)]
+        gic.set_device_attr(&mut gic_dist_attr)
+            .map_err(Error::SetDeviceAttribute)?;
+    } else {
+        gic.get_device_attr(&mut gic_dist_attr)
+            .map_err(Error::GetDeviceAttribute)?;
+    }
+    Ok(())
+}
+
+fn access_redists_aux(
+    gic: &Arc<dyn hypervisor::Device>,
+    gicr_typer: &[u64],
+    state: &mut Vec<u32>,
+    reg_list: &'static [RdistReg],
+    idx: &mut usize,
+    set: bool,
+) -> Result<()> {
+    for i in gicr_typer {
+        for rdreg in reg_list {
+            let mut base = rdreg.base;
+            let end = base + rdreg.length as u32;
+
+            while base < end {
+                let mut val = 0;
+                if set {
+                    val = state[*idx];
+                    redist_attr_access(gic, base, *i, &val, true)?;
+                    *idx += 1;
+                } else {
+                    redist_attr_access(gic, base, *i, &val, false)?;
+                    state.push(val);
+                }
+                base += REG_SIZE as u32;
+            }
+        }
+    }
+    Ok(())
+}
+
+/// Get redistributor registers.
+pub fn get_redist_regs(gic: &Arc<dyn hypervisor::Device>, gicr_typer: &[u64]) -> Result<Vec<u32>> {
+    let mut state = Vec::new();
+    let mut idx: usize = 0;
+    access_redists_aux(
+        gic,
+        gicr_typer,
+        &mut state,
+        VGIC_RDIST_REGS,
+        &mut idx,
+        false,
+    )?;
+
+    access_redists_aux(gic, gicr_typer, &mut state, VGIC_SGI_REGS, &mut idx, false)?;
+    Ok(state)
+}
+
+/// Set redistributor registers.
+pub fn set_redist_regs(
+    gic: &Arc<dyn hypervisor::Device>,
+    gicr_typer: &[u64],
+    state: &[u32],
+) -> Result<()> {
+    let mut idx: usize = 0;
+    let mut mut_state = state.to_owned();
+    access_redists_aux(
+        gic,
+        gicr_typer,
+        &mut mut_state,
+        VGIC_RDIST_REGS,
+        &mut idx,
+        true,
+    )?;
+    access_redists_aux(
+        gic,
+        gicr_typer,
+        &mut mut_state,
+        VGIC_SGI_REGS,
+        &mut idx,
+        true,
+    )
+}
+
+pub fn construct_gicr_typers(vcpu_states: &[CpuState]) -> Vec<u64> {
+    /* Pre-construct the GICR_TYPER:
+     * For our implementation:
+     *  Top 32 bits are the affinity value of the associated CPU
+     *  CommonLPIAff == 01 (redistributors with same Aff3 share LPI table)
+     *  Processor_Number == CPU index starting from 0
+     *  DPGS == 0 (GICR_CTLR.DPG* not supported)
+     *  Last == 1 if this is the last redistributor in a series of
+     *            contiguous redistributor pages
+     *  DirectLPI == 0 (direct injection of LPIs not supported)
+     *  VLPIS == 0 (virtual LPIs not supported)
+     *  PLPIS == 0 (physical LPIs not supported)
+     */
+    let mut gicr_typers: Vec<u64> = Vec::new();
+    for (index, state) in vcpu_states.iter().enumerate() {
+        let last = {
+            if index == vcpu_states.len() - 1 {
+                1
+            } else {
+                0
+            }
+        };
+        //calculate affinity
+        let mut cpu_affid = state.mpidr & 1095233437695;
+        cpu_affid = ((cpu_affid & 0xFF00000000) >> 8) | (cpu_affid & 0xFFFFFF);
+        gicr_typers.push((cpu_affid << 32) | (1 << 24) | (index as u64) << 8 | (last << 4));
+    }
+
+    gicr_typers
+}

arch/src/aarch64/layout.rs

@@ -1,7 +1,121 @@
+// Copyright 2020 Arm Limited (or its affiliates). All rights reserved.
 // Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 // SPDX-License-Identifier: Apache-2.0
 
-/// Kernel command line start address.
-pub const CMDLINE_START: usize = 0x0;
-/// Kernel command line start address maximum size.
-pub const CMDLINE_MAX_SIZE: usize = 0x0;
+//
+// Memory layout of Aarch64 guest:
+//
+// Physical  +---------------------------------------------------------------+
+// address   |                                                               |
+// end       |                                                               |
+//           ~                   ~                       ~                   ~
+//           |                                                               |
+//           |                      Highmem PCI MMIO space                   |
+//           |                                                               |
+// RAM end   +---------------------------------------------------------------+
+// (dynamic, |                                                               |
+// including |                                                               |
+// hotplug   ~                   ~                       ~                   ~
+// memory)   |                                                               |
+//           |                            DRAM                               |
+//           |                                                               |
+//           |                                                               |
+//           |                                                               |
+// 1GB       +---------------------------------------------------------------+
+//           |                                                               |
+//           |                        PCI MMCONFIG space                     |
+//           |                                                               |
+// 768 M     +---------------------------------------------------------------+
+//           |                                                               |
+//           |                                                               |
+//           |                           PCI MMIO space                      |
+//           |                                                               |
+// 256 M     +---------------------------------------------------------------|
+//           |                                                               |
+//           |                        Legacy devices space                   |
+//           |                                                               |
+// 144 M     +---------------------------------------------------------------|
+//           |                    Reserved (now GIC is here)                 |
+// 64  M     +---------------------------------------------------------------+
+//           |                                                               |
+//           |                          UEFI space                           |
+//           |                                                               |
+// 0GB       +---------------------------------------------------------------+
+//
+//
+
+use vm_memory::GuestAddress;
+
+/// 0x0 ~ 0x40_0000 (4 MiB) is reserved to UEFI
+/// UEFI binary size is required less than 3 MiB, reserving 4 MiB is enough.
+pub const UEFI_START: u64 = 0x0;
+pub const MEM_UEFI_START: GuestAddress = GuestAddress(0);
+pub const UEFI_SIZE: u64 = 0x040_0000;
+
+/// Below this address will reside the GIC, above this address will reside the MMIO devices.
+pub const MAPPED_IO_START: u64 = 0x0900_0000;
+
+/// See kernel file arch/arm64/include/uapi/asm/kvm.h for the GIC related definitions.
+/// 0x08ff_0000 ~ 0x0900_0000 is reserved for GICv3 Distributor
+pub const GIC_V3_DIST_SIZE: u64 = 0x01_0000;
+pub const GIC_V3_DIST_START: u64 = MAPPED_IO_START - GIC_V3_DIST_SIZE;
+/// Below 0x08ff_0000 is reserved for GICv3 Redistributor.
+/// The size defined here is for each vcpu.
+/// The total size is 'number_of_vcpu * GIC_V3_REDIST_SIZE'
+pub const GIC_V3_REDIST_SIZE: u64 = 0x02_0000;
+/// Below Redistributor area is GICv3 ITS
+pub const GIC_V3_ITS_SIZE: u64 = 0x02_0000;
+
+/// Space 0x0900_0000 ~ 0x0905_0000 is reserved for legacy devices.
+pub const LEGACY_SERIAL_MAPPED_IO_START: u64 = 0x0900_0000;
+pub const LEGACY_RTC_MAPPED_IO_START: u64 = 0x0901_0000;
+pub const LEGACY_GPIO_MAPPED_IO_START: u64 = 0x0902_0000;
+
+/// Space 0x0905_0000 ~ 0x0906_0000 is reserved for pcie io address
+pub const MEM_PCI_IO_START: GuestAddress = GuestAddress(0x0905_0000);
+pub const MEM_PCI_IO_SIZE: u64 = 0x10000;
+
+/// Starting from 0x1000_0000 (256MiB) to 0x3000_0000 (768MiB) is used for PCIE MMIO
+pub const MEM_32BIT_DEVICES_START: GuestAddress = GuestAddress(0x1000_0000);
+pub const MEM_32BIT_DEVICES_SIZE: u64 = 0x2000_0000;
+
+/// PCI MMCONFIG space (start: after the device space at 1 GiB, length: 256MiB)
+pub const PCI_MMCONFIG_START: GuestAddress = GuestAddress(0x3000_0000);
+pub const PCI_MMCONFIG_SIZE: u64 = 256 << 20;
+// One bus with potentially 256 devices (32 slots x 8 functions).
+pub const PCI_MMIO_CONFIG_SIZE_PER_SEGMENT: u64 = 4096 * 256;
+
+/// Start of RAM on 64 bit ARM.
+pub const RAM_64BIT_START: u64 = 0x4000_0000;
+
+/// Kernel command line maximum size.
+/// As per `arch/arm64/include/uapi/asm/setup.h`.
+pub const CMDLINE_MAX_SIZE: usize = 2048;
+
+/// FDT is at the beginning of RAM.
+/// Maximum size of the device tree blob as specified in https://www.kernel.org/doc/Documentation/arm64/booting.txt.
+pub const FDT_START: u64 = RAM_64BIT_START;
+pub const FDT_MAX_SIZE: usize = 0x20_0000;
+
+/// Put ACPI table above dtb
+pub const ACPI_START: u64 = RAM_64BIT_START + FDT_MAX_SIZE as u64;
+pub const ACPI_MAX_SIZE: usize = 0x20_0000;
+pub const RSDP_POINTER: GuestAddress = GuestAddress(ACPI_START);
+
+/// Kernel start after FDT and ACPI
+pub const KERNEL_START: u64 = ACPI_START + ACPI_MAX_SIZE as u64;
+
+/// Pci high memory base
+pub const PCI_HIGH_BASE: u64 = 0x80_0000_0000_u64;
+
+// As per virt/kvm/arm/vgic/vgic-kvm-device.c we need
+// the number of interrupts our GIC will support to be:
+// * bigger than 32
+// * less than 1023 and
+// * a multiple of 32.
+// We are setting up our interrupt controller to support a maximum of 256 interrupts.
+/// First usable interrupt on aarch64
+pub const IRQ_BASE: u32 = 32;
+
+/// Number of supported interrupts
+pub const IRQ_NUM: u32 = 256;

arch/src/aarch64/mod.rs

@@ -1,27 +1,233 @@
+// Copyright 2020 Arm Limited (or its affiliates). All rights reserved.
 // Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 // SPDX-License-Identifier: Apache-2.0
 
+/// Module for the flattened device tree.
+pub mod fdt;
+/// Module for the global interrupt controller configuration.
+pub mod gic;
+/// Layout for this aarch64 system.
 pub mod layout;
+/// Logic for configuring aarch64 registers.
+pub mod regs;
+/// Module for loading UEFI binary.
+pub mod uefi;
 
-use memory_model::{GuestAddress, GuestMemory};
+pub use self::fdt::DeviceInfoForFdt;
+use crate::{DeviceType, GuestMemoryMmap, NumaNodes, RegionType};
+use gic::GicDevice;
+use log::{log_enabled, Level};
+use std::collections::HashMap;
+use std::convert::TryInto;
+use std::fmt::Debug;
+use std::sync::Arc;
+use vm_memory::{
+    Address, GuestAddress, GuestAddressSpace, GuestMemory, GuestMemoryAtomic, GuestUsize,
+};
 
-/// Stub function that needs to be implemented when aarch64 functionality is added.
-pub fn arch_memory_regions(size: usize) -> Vec<(GuestAddress, usize, RegionType)> {
-    vec![(GuestAddress(0), size, RegionType::Ram)]
+/// Errors thrown while configuring aarch64 system.
+#[derive(Debug)]
+pub enum Error {
+    /// Failed to create a FDT.
+    SetupFdt,
+
+    /// Failed to write FDT to memory.
+    WriteFdtToMemory(fdt::Error),
+
+    /// Failed to create a GIC.
+    SetupGic(gic::Error),
+
+    /// Failed to compute the initramfs address.
+    InitramfsAddress,
+
+    /// Error configuring the general purpose registers
+    RegsConfiguration(regs::Error),
+
+    /// Error configuring the MPIDR register
+    VcpuRegMpidr(hypervisor::HypervisorCpuError),
 }
 
-/// Stub function that needs to be implemented when aarch64 functionality is added.
-pub fn configure_system(
-    _guest_mem: &GuestMemory,
-    _cmdline_addr: GuestAddress,
-    _cmdline_size: usize,
-    _num_cpus: u8,
-    _rsdp_addr: Option<GuestAddress>,
+impl From<Error> for super::Error {
+    fn from(e: Error) -> super::Error {
+        super::Error::AArch64Setup(e)
+    }
+}
+
+#[derive(Debug, Copy, Clone)]
+/// Specifies the entry point address where the guest must start
+/// executing code.
+pub struct EntryPoint {
+    /// Address in guest memory where the guest must start execution
+    pub entry_addr: GuestAddress,
+}
+
+/// Configure the specified VCPU, and return its MPIDR.
+pub fn configure_vcpu(
+    fd: &Arc<dyn hypervisor::Vcpu>,
+    id: u8,
+    kernel_entry_point: Option<EntryPoint>,
+    vm_memory: &GuestMemoryAtomic<GuestMemoryMmap>,
+) -> super::Result<u64> {
+    if let Some(kernel_entry_point) = kernel_entry_point {
+        regs::setup_regs(
+            fd,
+            id,
+            kernel_entry_point.entry_addr.raw_value(),
+            &vm_memory.memory(),
+        )
+        .map_err(Error::RegsConfiguration)?;
+    }
+
+    let mpidr = fd.read_mpidr().map_err(Error::VcpuRegMpidr)?;
+    Ok(mpidr)
+}
+
+pub fn arch_memory_regions(size: GuestUsize) -> Vec<(GuestAddress, usize, RegionType)> {
+    // Normally UEFI should be loaded to a flash area at the beginning of memory.
+    // But now flash memory type is not supported.
+    // As a workaround, we take 4 MiB memory from the main RAM for UEFI.
+    // As a result, the RAM that the guest can see is less than what has been
+    // assigned in command line, when ACPI and UEFI is enabled.
+    let ram_deduction = if cfg!(feature = "acpi") {
+        layout::UEFI_SIZE
+    } else {
+        0
+    };
+
+    vec![
+        // 0 ~ 4 MiB: Reserved for UEFI space
+        #[cfg(feature = "acpi")]
+        (GuestAddress(0), layout::UEFI_SIZE as usize, RegionType::Ram),
+        #[cfg(not(feature = "acpi"))]
+        (
+            GuestAddress(0),
+            layout::UEFI_SIZE as usize,
+            RegionType::Reserved,
+        ),
+        // 4 MiB ~ 256 MiB: Gic and legacy devices
+        (
+            GuestAddress(layout::UEFI_SIZE),
+            (layout::MEM_32BIT_DEVICES_START.0 - layout::UEFI_SIZE) as usize,
+            RegionType::Reserved,
+        ),
+        // 256 MiB ~ 768 MiB: MMIO space
+        (
+            layout::MEM_32BIT_DEVICES_START,
+            layout::MEM_32BIT_DEVICES_SIZE as usize,
+            RegionType::SubRegion,
+        ),
+        // 768 MiB ~ 1 GiB: reserved. The leading 256M for PCIe MMCONFIG space
+        (
+            layout::PCI_MMCONFIG_START,
+            layout::PCI_MMCONFIG_SIZE as usize,
+            RegionType::Reserved,
+        ),
+        // 1 GiB ~ : Ram
+        (
+            GuestAddress(layout::RAM_64BIT_START),
+            (size - ram_deduction) as usize,
+            RegionType::Ram,
+        ),
+    ]
+}
+
+/// Configures the system and should be called once per vm before starting vcpu threads.
+#[allow(clippy::too_many_arguments)]
+pub fn configure_system<T: DeviceInfoForFdt + Clone + Debug, S: ::std::hash::BuildHasher>(
+    guest_mem: &GuestMemoryMmap,
+    cmdline: &str,
+    vcpu_mpidr: Vec<u64>,
+    vcpu_topology: Option<(u8, u8, u8)>,
+    device_info: &HashMap<(DeviceType, String), T, S>,
+    initrd: &Option<super::InitramfsConfig>,
+    pci_space_address: &(u64, u64),
+    virtio_iommu_bdf: Option<u32>,
+    gic_device: &dyn GicDevice,
+    numa_nodes: &NumaNodes,
 ) -> super::Result<()> {
+    let fdt_final = fdt::create_fdt(
+        guest_mem,
+        cmdline,
+        vcpu_mpidr,
+        vcpu_topology,
+        device_info,
+        gic_device,
+        initrd,
+        pci_space_address,
+        numa_nodes,
+        virtio_iommu_bdf,
+    )
+    .map_err(|_| Error::SetupFdt)?;
+
+    if log_enabled!(Level::Debug) {
+        fdt::print_fdt(&fdt_final);
+    }
+
+    fdt::write_fdt_to_memory(fdt_final, guest_mem).map_err(Error::WriteFdtToMemory)?;
+
     Ok(())
 }
 
-/// Stub function that needs to be implemented when aarch64 functionality is added.
-pub fn get_reserved_mem_addr() -> usize {
-    0
+/// Returns the memory address where the initramfs could be loaded.
+pub fn initramfs_load_addr(
+    guest_mem: &GuestMemoryMmap,
+    initramfs_size: usize,
+) -> super::Result<u64> {
+    let round_to_pagesize = |size| (size + (super::PAGE_SIZE - 1)) & !(super::PAGE_SIZE - 1);
+    match guest_mem
+        .last_addr()
+        .checked_sub(round_to_pagesize(initramfs_size) as u64 - 1)
+    {
+        Some(offset) => {
+            if guest_mem.address_in_range(offset) {
+                Ok(offset.raw_value())
+            } else {
+                Err(super::Error::AArch64Setup(Error::InitramfsAddress))
+            }
+        }
+        None => Err(super::Error::AArch64Setup(Error::InitramfsAddress)),
+    }
+}
+
+/// Returns the memory address where the kernel could be loaded.
+pub fn get_kernel_start() -> u64 {
+    layout::KERNEL_START
+}
+
+///Return guest memory address where the uefi should be loaded.
+pub fn get_uefi_start() -> u64 {
+    layout::UEFI_START
+}
+
+// Auxiliary function to get the address where the device tree blob is loaded.
+fn get_fdt_addr() -> u64 {
+    layout::FDT_START
+}
+
+pub fn get_host_cpu_phys_bits() -> u8 {
+    // A dummy hypervisor created only for querying the host IPA size and will
+    // be freed after the query.
+    let hv = hypervisor::new().unwrap();
+    let host_cpu_phys_bits = hv.get_host_ipa_limit().try_into().unwrap();
+    if host_cpu_phys_bits == 0 {
+        // Host kernel does not support `get_host_ipa_limit`,
+        // we return the default value 40 here.
+        40
+    } else {
+        host_cpu_phys_bits
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_arch_memory_regions_dram() {
+        let regions = arch_memory_regions((1usize << 32) as u64); //4GB
+        assert_eq!(5, regions.len());
+        assert_eq!(GuestAddress(layout::RAM_64BIT_START), regions[4].0);
+        assert_eq!(1usize << 32, regions[4].1);
+        assert_eq!(RegionType::Ram, regions[4].2);
+    }
 }

arch/src/aarch64/regs.rs

@@ -0,0 +1,81 @@
+// Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style license that can be
+// found in the THIRD-PARTY file.
+
+use super::get_fdt_addr;
+use crate::GuestMemoryMmap;
+use hypervisor::kvm::kvm_bindings::{
+    kvm_regs, user_pt_regs, KVM_REG_ARM64, KVM_REG_ARM_CORE, KVM_REG_SIZE_U64,
+};
+use hypervisor::{arm64_core_reg_id, offset__of};
+use std::sync::Arc;
+use std::{mem, result};
+
+/// Errors thrown while setting aarch64 registers.
+#[derive(Debug)]
+pub enum Error {
+    /// Failed to set core register (PC, PSTATE or general purpose ones).
+    SetCoreRegister(hypervisor::HypervisorCpuError),
+    /// Failed to get a system register.
+    GetSysRegister(hypervisor::HypervisorCpuError),
+}
+type Result<T> = result::Result<T, Error>;
+
+#[allow(non_upper_case_globals)]
+// PSR (Processor State Register) bits.
+// Taken from arch/arm64/include/uapi/asm/ptrace.h.
+const PSR_MODE_EL1h: u64 = 0x0000_0005;
+const PSR_F_BIT: u64 = 0x0000_0040;
+const PSR_I_BIT: u64 = 0x0000_0080;
+const PSR_A_BIT: u64 = 0x0000_0100;
+const PSR_D_BIT: u64 = 0x0000_0200;
+// Taken from arch/arm64/kvm/inject_fault.c.
+const PSTATE_FAULT_BITS_64: u64 = PSR_MODE_EL1h | PSR_A_BIT | PSR_F_BIT | PSR_I_BIT | PSR_D_BIT;
+
+/// Configure core registers for a given CPU.
+///
+/// # Arguments
+///
+/// * `vcpu` - Structure for the VCPU that holds the VCPU's fd.
+/// * `cpu_id` - Index of current vcpu.
+/// * `boot_ip` - Starting instruction pointer.
+/// * `mem` - Reserved DRAM for current VM.
+pub fn setup_regs(
+    vcpu: &Arc<dyn hypervisor::Vcpu>,
+    cpu_id: u8,
+    boot_ip: u64,
+    _mem: &GuestMemoryMmap,
+) -> Result<()> {
+    let kreg_off = offset__of!(kvm_regs, regs);
+
+    // Get the register index of the PSTATE (Processor State) register.
+    let pstate = offset__of!(user_pt_regs, pstate) + kreg_off;
+    vcpu.set_reg(
+        arm64_core_reg_id!(KVM_REG_SIZE_U64, pstate),
+        PSTATE_FAULT_BITS_64,
+    )
+    .map_err(Error::SetCoreRegister)?;
+
+    // Other vCPUs are powered off initially awaiting PSCI wakeup.
+    if cpu_id == 0 {
+        // Setting the PC (Processor Counter) to the current program address (kernel address).
+        let pc = offset__of!(user_pt_regs, pc) + kreg_off;
+        vcpu.set_reg(arm64_core_reg_id!(KVM_REG_SIZE_U64, pc), boot_ip as u64)
+            .map_err(Error::SetCoreRegister)?;
+
+        // Last mandatory thing to set -> the address pointing to the FDT (also called DTB).
+        // "The device tree blob (dtb) must be placed on an 8-byte boundary and must
+        // not exceed 2 megabytes in size." -> https://www.kernel.org/doc/Documentation/arm64/booting.txt.
+        // We are choosing to place it the end of DRAM. See `get_fdt_addr`.
+        let regs0 = offset__of!(user_pt_regs, regs) + kreg_off;
+        vcpu.set_reg(
+            arm64_core_reg_id!(KVM_REG_SIZE_U64, regs0),
+            get_fdt_addr() as u64,
+        )
+        .map_err(Error::SetCoreRegister)?;
+    }
+    Ok(())
+}

arch/src/aarch64/uefi.rs

@@ -0,0 +1,43 @@
+// Copyright 2020 Arm Limited (or its affiliates). All rights reserved.
+
+use std::io::{Read, Seek, SeekFrom};
+use std::result;
+use vm_memory::{Bytes, GuestAddress, GuestMemory};
+
+/// Errors thrown while loading UEFI binary
+#[derive(Debug)]
+pub enum Error {
+    /// Unable to seek to UEFI image start.
+    SeekUefiStart,
+    /// Unable to seek to UEFI image end.
+    SeekUefiEnd,
+    /// UEFI image too big.
+    UefiTooBig,
+    /// Unable to read UEFI image
+    ReadUefiImage,
+}
+type Result<T> = result::Result<T, Error>;
+
+pub fn load_uefi<F, M: GuestMemory>(
+    guest_mem: &M,
+    guest_addr: GuestAddress,
+    uefi_image: &mut F,
+) -> Result<()>
+where
+    F: Read + Seek,
+{
+    let uefi_size = uefi_image
+        .seek(SeekFrom::End(0))
+        .map_err(|_| Error::SeekUefiEnd)? as usize;
+
+    // edk2 image on virtual platform is smaller than 3M
+    if uefi_size > 0x300000 {
+        return Err(Error::UefiTooBig);
+    }
+    uefi_image
+        .seek(SeekFrom::Start(0))
+        .map_err(|_| Error::SeekUefiStart)?;
+    guest_mem
+        .read_exact_from(guest_addr, uefi_image, uefi_size)
+        .map_err(|_| Error::ReadUefiImage)
+}

arch/src/lib.rs

@@ -1,34 +1,40 @@
+// Copyright 2020 Arm Limited (or its affiliates). All rights reserved.
 // Copyright © 2020, Oracle and/or its affiliates.
 //
 // Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 // SPDX-License-Identifier: Apache-2.0
 
-#![allow(
-    clippy::unreadable_literal,
-    clippy::redundant_static_lifetimes,
-    clippy::cast_lossless,
-    clippy::transmute_ptr_to_ptr,
-    clippy::cast_ptr_alignment
-)]
+//! Implements platform specific functionality.
+//! Supported platforms: x86_64, aarch64.
+#![allow(clippy::transmute_ptr_to_ptr, clippy::redundant_static_lifetimes)]
 
-extern crate byteorder;
-extern crate kvm_bindings;
-extern crate libc;
-
-#[cfg(feature = "acpi")]
-extern crate acpi_tables;
-extern crate arch_gen;
-extern crate kvm_ioctls;
-extern crate linux_loader;
-extern crate vm_memory;
+#[macro_use]
+extern crate log;
+#[macro_use]
+extern crate serde_derive;
 
+#[cfg(target_arch = "x86_64")]
+use crate::x86_64::SgxEpcSection;
+use std::collections::BTreeMap;
+use std::fmt;
 use std::result;
+use std::sync::Arc;
+use versionize::{VersionMap, Versionize, VersionizeError, VersionizeResult};
+use versionize_derive::Versionize;
+use vm_migration::VersionMapped;
 
+type GuestMemoryMmap = vm_memory::GuestMemoryMmap<vm_memory::bitmap::AtomicBitmap>;
+type GuestRegionMmap = vm_memory::GuestRegionMmap<vm_memory::bitmap::AtomicBitmap>;
+
+/// Type for returning error code.
 #[derive(Debug)]
 pub enum Error {
     #[cfg(target_arch = "x86_64")]
     /// X86_64 specific error triggered during system configuration.
     X86_64Setup(x86_64::Error),
+    #[cfg(target_arch = "aarch64")]
+    /// AArch64 specific error triggered during system configuration.
+    AArch64Setup(aarch64::Error),
     /// The zero page extends past the end of guest_mem.
     ZeroPagePastRamEnd,
     /// Error writing the zero page of guest memory.
@@ -45,10 +51,15 @@ pub enum Error {
     InitramfsAddress,
     /// Error writing module entry to guest memory.
     ModlistSetup(vm_memory::GuestMemoryError),
+    /// RSDP Beyond Guest Memory
+    RsdpPastRamEnd,
 }
+
+/// Type for returning public functions outcome.
 pub type Result<T> = result::Result<T, Error>;
 
-#[derive(PartialEq)]
+/// Type for memory region types.
+#[derive(Clone, Copy, PartialEq, Debug, Serialize, Deserialize, Versionize)]
 pub enum RegionType {
     /// RAM type
     Ram,
@@ -66,13 +77,17 @@ pub enum RegionType {
     Reserved,
 }
 
+impl VersionMapped for RegionType {}
+
+/// Module for aarch64 related functionality.
 #[cfg(target_arch = "aarch64")]
 pub mod aarch64;
 
 #[cfg(target_arch = "aarch64")]
 pub use aarch64::{
-    arch_memory_regions, configure_system, get_reserved_mem_addr, layout::CMDLINE_MAX_SIZE,
-    layout::CMDLINE_START,
+    arch_memory_regions, configure_system, configure_vcpu, fdt::DeviceInfoForFdt,
+    get_host_cpu_phys_bits, get_kernel_start, get_uefi_start, initramfs_load_addr, layout,
+    layout::CMDLINE_MAX_SIZE, layout::IRQ_BASE, uefi, EntryPoint,
 };
 
 #[cfg(target_arch = "x86_64")]
@@ -80,17 +95,32 @@ pub mod x86_64;
 
 #[cfg(target_arch = "x86_64")]
 pub use x86_64::{
-    arch_memory_regions, configure_system, initramfs_load_addr, layout, layout::CMDLINE_MAX_SIZE,
-    layout::CMDLINE_START, regs, BootProtocol, EntryPoint,
+    arch_memory_regions, configure_system, configure_vcpu, generate_common_cpuid,
+    get_host_cpu_phys_bits, initramfs_load_addr, layout, layout::CMDLINE_MAX_SIZE,
+    layout::CMDLINE_START, regs, CpuidFeatureEntry, EntryPoint,
 };
 
 /// Safe wrapper for `sysconf(_SC_PAGESIZE)`.
+#[cfg(target_arch = "x86_64")]
 #[inline(always)]
 fn pagesize() -> usize {
     // Trivially safe
     unsafe { libc::sysconf(libc::_SC_PAGESIZE) as usize }
 }
 
+#[derive(Clone, Default)]
+pub struct NumaNode {
+    pub memory_regions: Vec<Arc<GuestRegionMmap>>,
+    pub hotplug_regions: Vec<Arc<GuestRegionMmap>>,
+    pub cpus: Vec<u8>,
+    pub distances: BTreeMap<u32, u8>,
+    pub memory_zones: Vec<String>,
+    #[cfg(target_arch = "x86_64")]
+    pub sgx_epc_sections: Vec<SgxEpcSection>,
+}
+
+pub type NumaNodes = BTreeMap<u32, NumaNode>;
+
 /// Type for passing information about the initramfs in the guest memory.
 pub struct InitramfsConfig {
     /// Load address of initramfs in guest memory
@@ -98,3 +128,49 @@ pub struct InitramfsConfig {
     /// Size of initramfs in guest memory
     pub size: usize,
 }
+
+/// Types of devices that can get attached to this platform.
+#[derive(Clone, Debug, PartialEq, Eq, Hash, Copy)]
+pub enum DeviceType {
+    /// Device Type: Virtio.
+    Virtio(u32),
+    /// Device Type: Serial.
+    #[cfg(target_arch = "aarch64")]
+    Serial,
+    /// Device Type: RTC.
+    #[cfg(target_arch = "aarch64")]
+    Rtc,
+    /// Device Type: GPIO.
+    #[cfg(target_arch = "aarch64")]
+    Gpio,
+}
+
+/// Default (smallest) memory page size for the supported architectures.
+pub const PAGE_SIZE: usize = 4096;
+
+impl fmt::Display for DeviceType {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        write!(f, "{:?}", self)
+    }
+}
+
+/// Structure to describe MMIO device information
+#[derive(Clone, Debug)]
+#[cfg(target_arch = "aarch64")]
+pub struct MmioDeviceInfo {
+    pub addr: u64,
+    pub irq: u32,
+}
+
+#[cfg(target_arch = "aarch64")]
+impl DeviceInfoForFdt for MmioDeviceInfo {
+    fn addr(&self) -> u64 {
+        self.addr
+    }
+    fn irq(&self) -> u32 {
+        self.irq
+    }
+    fn length(&self) -> u64 {
+        4096
+    }
+}

arch/src/x86_64/interrupts.rs

@@ -5,30 +5,22 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE-BSD-3-Clause file.
 
+use byteorder::{LittleEndian, ReadBytesExt, WriteBytesExt};
+use hypervisor::x86_64::LapicState;
 use std::io::Cursor;
 use std::mem;
 use std::result;
+use std::sync::Arc;
 
-use byteorder::{LittleEndian, ReadBytesExt, WriteBytesExt};
-
-use kvm_bindings::kvm_lapic_state;
-use kvm_ioctls;
-
-#[derive(Debug)]
-pub enum Error {
-    GetLapic(kvm_ioctls::Error),
-    SetLapic(kvm_ioctls::Error),
-}
-
-pub type Result<T> = result::Result<T, Error>;
+pub type Result<T> = result::Result<T, hypervisor::HypervisorCpuError>;
 
 // Defines poached from apicdef.h kernel header.
-const APIC_LVT0: usize = 0x350;
-const APIC_LVT1: usize = 0x360;
-const APIC_MODE_NMI: u32 = 0x4;
-const APIC_MODE_EXTINT: u32 = 0x7;
+pub const APIC_LVT0: usize = 0x350;
+pub const APIC_LVT1: usize = 0x360;
+pub const APIC_MODE_NMI: u32 = 0x4;
+pub const APIC_MODE_EXTINT: u32 = 0x7;
 
-fn get_klapic_reg(klapic: &kvm_lapic_state, reg_offset: usize) -> u32 {
+pub fn get_klapic_reg(klapic: &LapicState, reg_offset: usize) -> u32 {
     let sliceu8 = unsafe {
         // This array is only accessed as parts of a u32 word, so interpret it as a u8 array.
         // Cursors are only readable on arrays of u8, not i8(c_char).
@@ -41,7 +33,7 @@ fn get_klapic_reg(klapic: &kvm_lapic_state, reg_offset: usize) -> u32 {
         .expect("Failed to read klapic register")
 }
 
-fn set_klapic_reg(klapic: &mut kvm_lapic_state, reg_offset: usize, value: u32) {
+pub fn set_klapic_reg(klapic: &mut LapicState, reg_offset: usize, value: u32) {
     let sliceu8 = unsafe {
         // This array is only accessed as parts of a u32 word, so interpret it as a u8 array.
         // Cursors are only readable on arrays of u8, not i8(c_char).
@@ -54,7 +46,7 @@ fn set_klapic_reg(klapic: &mut kvm_lapic_state, reg_offset: usize, value: u32) {
         .expect("Failed to write klapic register")
 }
 
-fn set_apic_delivery_mode(reg: u32, mode: u32) -> u32 {
+pub fn set_apic_delivery_mode(reg: u32, mode: u32) -> u32 {
     ((reg) & !0x700) | ((mode) << 8)
 }
 
@@ -62,8 +54,8 @@ fn set_apic_delivery_mode(reg: u32, mode: u32) -> u32 {
 ///
 /// # Arguments
 /// * `vcpu` - The VCPU object to configure.
-pub fn set_lint(vcpu: &kvm_ioctls::VcpuFd) -> Result<()> {
-    let mut klapic = vcpu.get_lapic().map_err(Error::GetLapic)?;
+pub fn set_lint(vcpu: &Arc<dyn hypervisor::Vcpu>) -> Result<()> {
+    let mut klapic = vcpu.get_lapic()?;
 
     let lvt_lint0 = get_klapic_reg(&klapic, APIC_LVT0);
     set_klapic_reg(
@@ -78,24 +70,19 @@ pub fn set_lint(vcpu: &kvm_ioctls::VcpuFd) -> Result<()> {
         set_apic_delivery_mode(lvt_lint1, APIC_MODE_NMI),
     );
 
-    vcpu.set_lapic(&klapic).map_err(Error::SetLapic)
+    vcpu.set_lapic(&klapic)
 }
 
 #[cfg(test)]
 mod tests {
-    extern crate kvm_ioctls;
-    extern crate rand;
-    use self::rand::Rng;
-
     use super::*;
-    use kvm_ioctls::Kvm;
 
     const KVM_APIC_REG_SIZE: usize = 0x400;
 
     #[test]
     fn test_set_and_get_klapic_reg() {
         let reg_offset = 0x340;
-        let mut klapic = kvm_lapic_state::default();
+        let mut klapic = LapicState::default();
         set_klapic_reg(&mut klapic, reg_offset, 3);
         let value = get_klapic_reg(&klapic, reg_offset);
         assert_eq!(value, 3);
@@ -105,54 +92,7 @@ mod tests {
     #[should_panic]
     fn test_set_and_get_klapic_out_of_bounds() {
         let reg_offset = KVM_APIC_REG_SIZE + 10;
-        let mut klapic = kvm_lapic_state::default();
+        let mut klapic = LapicState::default();
         set_klapic_reg(&mut klapic, reg_offset, 3);
     }
-
-    #[test]
-    fn test_apic_delivery_mode() {
-        let mut rng = rand::thread_rng();
-        let mut v: Vec<u32> = (0..20).map(|_| rng.gen::<u32>()).collect();
-
-        v.iter_mut()
-            .for_each(|x| *x = set_apic_delivery_mode(*x, 2));
-        let after: Vec<u32> = v.iter().map(|x| ((*x & !0x700) | ((2) << 8))).collect();
-        assert_eq!(v, after);
-    }
-
-    #[test]
-    fn test_setlint() {
-        let kvm = kvm_ioctls::Kvm::new().unwrap();
-        assert!(kvm.check_extension(kvm_ioctls::Cap::Irqchip));
-        let vm = kvm.create_vm().unwrap();
-        //the get_lapic ioctl will fail if there is no irqchip created beforehand.
-        assert!(vm.create_irq_chip().is_ok());
-        let vcpu = vm.create_vcpu(0).unwrap();
-        let klapic_before: kvm_lapic_state = vcpu.get_lapic().unwrap();
-
-        // Compute the value that is expected to represent LVT0 and LVT1.
-        let lint0 = get_klapic_reg(&klapic_before, APIC_LVT0);
-        let lint1 = get_klapic_reg(&klapic_before, APIC_LVT1);
-        let lint0_mode_expected = set_apic_delivery_mode(lint0, APIC_MODE_EXTINT);
-        let lint1_mode_expected = set_apic_delivery_mode(lint1, APIC_MODE_NMI);
-
-        set_lint(&vcpu).unwrap();
-
-        // Compute the value that represents LVT0 and LVT1 after set_lint.
-        let klapic_actual: kvm_lapic_state = vcpu.get_lapic().unwrap();
-        let lint0_mode_actual = get_klapic_reg(&klapic_actual, APIC_LVT0);
-        let lint1_mode_actual = get_klapic_reg(&klapic_actual, APIC_LVT1);
-        assert_eq!(lint0_mode_expected, lint0_mode_actual);
-        assert_eq!(lint1_mode_expected, lint1_mode_actual);
-    }
-
-    #[test]
-    fn test_setlint_fails() {
-        let kvm = Kvm::new().unwrap();
-        let vm = kvm.create_vm().unwrap();
-        let vcpu = vm.create_vcpu(0).unwrap();
-        // 'get_lapic' ioctl triggered by the 'set_lint' function will fail if there is no
-        // irqchip created beforehand.
-        assert!(set_lint(&vcpu).is_err());
-    }
 }

arch/src/x86_64/layout.rs

@@ -7,7 +7,7 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE-BSD-3-Clause file.
 
-use vm_memory::{GuestAddress, GuestUsize};
+use vm_memory::GuestAddress;
 
 /*
 
@@ -47,9 +47,10 @@ pub const BOOT_STACK_START: GuestAddress = GuestAddress(0x8000);
 pub const BOOT_STACK_POINTER: GuestAddress = GuestAddress(0x8ff0);
 
 // Initial pagetables.
-pub const PML4_START: GuestAddress = GuestAddress(0x9000);
-pub const PDPTE_START: GuestAddress = GuestAddress(0xa000);
-pub const PDE_START: GuestAddress = GuestAddress(0xb000);
+pub const PML5_START: GuestAddress = GuestAddress(0x9000);
+pub const PML4_START: GuestAddress = GuestAddress(0xa000);
+pub const PDPTE_START: GuestAddress = GuestAddress(0xb000);
+pub const PDE_START: GuestAddress = GuestAddress(0xc000);
 
 /// Kernel command line start address.
 pub const CMDLINE_START: GuestAddress = GuestAddress(0x20000);
@@ -69,6 +70,8 @@ pub const EBDA_START: GuestAddress = GuestAddress(0xa0000);
 // ACPI RSDP table
 pub const RSDP_POINTER: GuestAddress = EBDA_START;
 
+pub const SMBIOS_START: u64 = 0xf0000; // First possible location per the spec.
+
 // == End of "EBDA" range ==
 
 // ** High RAM (start: 1MiB, length: 3071MiB) **
@@ -76,31 +79,38 @@ pub const HIGH_RAM_START: GuestAddress = GuestAddress(0x100000);
 
 // == No fixed addresses in the "High RAM" range ==
 
-// ** 32-bit reserved area (start: 3GiB, length: 1GiB) **
+// ** 32-bit reserved area (start: 3GiB, length: 896MiB) **
 pub const MEM_32BIT_RESERVED_START: GuestAddress = GuestAddress(0xc000_0000);
-pub const MEM_32BIT_RESERVED_SIZE: GuestUsize = 1024 << 20;
+pub const MEM_32BIT_RESERVED_SIZE: u64 = PCI_MMCONFIG_SIZE + MEM_32BIT_DEVICES_SIZE;
 
 // == Fixed constants within the "32-bit reserved" range ==
 
 // Sub range: 32-bit PCI devices (start: 3GiB, length: 640Mib)
 pub const MEM_32BIT_DEVICES_START: GuestAddress = MEM_32BIT_RESERVED_START;
-pub const MEM_32BIT_DEVICES_SIZE: GuestUsize = 640 << 20;
+pub const MEM_32BIT_DEVICES_SIZE: u64 = 640 << 20;
 
 // PCI MMCONFIG space (start: after the device space, length: 256MiB)
 pub const PCI_MMCONFIG_START: GuestAddress =
     GuestAddress(MEM_32BIT_DEVICES_START.0 + MEM_32BIT_DEVICES_SIZE);
-pub const PCI_MMCONFIG_SIZE: GuestUsize = 256 << 20;
+pub const PCI_MMCONFIG_SIZE: u64 = 256 << 20;
+// One bus with potentially 256 devices (32 slots x 8 functions).
+pub const PCI_MMIO_CONFIG_SIZE_PER_SEGMENT: u64 = 4096 * 256;
+
+// TSS is 3 pages after the PCI MMCONFIG space
+pub const KVM_TSS_START: GuestAddress = GuestAddress(PCI_MMCONFIG_START.0 + PCI_MMCONFIG_SIZE);
+pub const KVM_TSS_SIZE: u64 = (3 * 4) << 10;
+
+// Identity map is a one page region after the TSS
+pub const KVM_IDENTITY_MAP_START: GuestAddress = GuestAddress(KVM_TSS_START.0 + KVM_TSS_SIZE);
+pub const KVM_IDENTITY_MAP_SIZE: u64 = 4 << 10;
 
 // IOAPIC
 pub const IOAPIC_START: GuestAddress = GuestAddress(0xfec0_0000);
-pub const IOAPIC_SIZE: GuestUsize = 0x20;
+pub const IOAPIC_SIZE: u64 = 0x20;
 
 // APIC
 pub const APIC_START: GuestAddress = GuestAddress(0xfee0_0000);
 
-/// Address for the TSS setup.
-pub const KVM_TSS_ADDRESS: GuestAddress = GuestAddress(0xfffb_d000);
-
 // == End of "32-bit reserved" range. ==
 
 // ** 64-bit RAM start (start: 4GiB, length: varies) **

arch/src/x86_64/mpspec.rs

@@ -0,0 +1,112 @@
+// Copyright 2017 The Chromium OS Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style license that can be
+// found in the LICENSE-BSD-3-Clause file.
+
+pub const MP_PROCESSOR: ::std::os::raw::c_uint = 0;
+pub const MP_BUS: ::std::os::raw::c_uint = 1;
+pub const MP_IOAPIC: ::std::os::raw::c_uint = 2;
+pub const MP_INTSRC: ::std::os::raw::c_uint = 3;
+pub const MP_LINTSRC: ::std::os::raw::c_uint = 4;
+pub const CPU_ENABLED: ::std::os::raw::c_uint = 1;
+pub const CPU_BOOTPROCESSOR: ::std::os::raw::c_uint = 2;
+pub const MPC_APIC_USABLE: ::std::os::raw::c_uint = 1;
+pub const MP_IRQDIR_DEFAULT: ::std::os::raw::c_uint = 0;
+
+#[repr(C)]
+#[derive(Debug, Default, Copy, Clone)]
+pub struct mpf_intel {
+    pub signature: [::std::os::raw::c_char; 4usize],
+    pub physptr: ::std::os::raw::c_uint,
+    pub length: ::std::os::raw::c_uchar,
+    pub specification: ::std::os::raw::c_uchar,
+    pub checksum: ::std::os::raw::c_uchar,
+    pub feature1: ::std::os::raw::c_uchar,
+    pub feature2: ::std::os::raw::c_uchar,
+    pub feature3: ::std::os::raw::c_uchar,
+    pub feature4: ::std::os::raw::c_uchar,
+    pub feature5: ::std::os::raw::c_uchar,
+}
+
+#[repr(C)]
+#[derive(Debug, Default, Copy, Clone)]
+pub struct mpc_table {
+    pub signature: [::std::os::raw::c_char; 4usize],
+    pub length: ::std::os::raw::c_ushort,
+    pub spec: ::std::os::raw::c_char,
+    pub checksum: ::std::os::raw::c_char,
+    pub oem: [::std::os::raw::c_char; 8usize],
+    pub productid: [::std::os::raw::c_char; 12usize],
+    pub oemptr: ::std::os::raw::c_uint,
+    pub oemsize: ::std::os::raw::c_ushort,
+    pub oemcount: ::std::os::raw::c_ushort,
+    pub lapic: ::std::os::raw::c_uint,
+    pub reserved: ::std::os::raw::c_uint,
+}
+
+#[repr(C)]
+#[derive(Debug, Default, Copy, Clone)]
+pub struct mpc_cpu {
+    pub type_: ::std::os::raw::c_uchar,
+    pub apicid: ::std::os::raw::c_uchar,
+    pub apicver: ::std::os::raw::c_uchar,
+    pub cpuflag: ::std::os::raw::c_uchar,
+    pub cpufeature: ::std::os::raw::c_uint,
+    pub featureflag: ::std::os::raw::c_uint,
+    pub reserved: [::std::os::raw::c_uint; 2usize],
+}
+
+#[repr(C)]
+#[derive(Debug, Default, Copy, Clone)]
+pub struct mpc_bus {
+    pub type_: ::std::os::raw::c_uchar,
+    pub busid: ::std::os::raw::c_uchar,
+    pub bustype: [::std::os::raw::c_uchar; 6usize],
+}
+
+#[repr(C)]
+#[derive(Debug, Default, Copy, Clone)]
+pub struct mpc_ioapic {
+    pub type_: ::std::os::raw::c_uchar,
+    pub apicid: ::std::os::raw::c_uchar,
+    pub apicver: ::std::os::raw::c_uchar,
+    pub flags: ::std::os::raw::c_uchar,
+    pub apicaddr: ::std::os::raw::c_uint,
+}
+
+#[repr(C)]
+#[derive(Debug, Default, Copy, Clone)]
+pub struct mpc_intsrc {
+    pub type_: ::std::os::raw::c_uchar,
+    pub irqtype: ::std::os::raw::c_uchar,
+    pub irqflag: ::std::os::raw::c_ushort,
+    pub srcbus: ::std::os::raw::c_uchar,
+    pub srcbusirq: ::std::os::raw::c_uchar,
+    pub dstapic: ::std::os::raw::c_uchar,
+    pub dstirq: ::std::os::raw::c_uchar,
+}
+
+pub const MP_IRQ_SOURCE_TYPES_MP_INT: ::std::os::raw::c_uint = 0;
+pub const MP_IRQ_SOURCE_TYPES_MP_NMI: ::std::os::raw::c_uint = 1;
+pub const MP_IRQ_SOURCE_TYPES_MP_EXT_INT: ::std::os::raw::c_uint = 3;
+
+#[repr(C)]
+#[derive(Debug, Default, Copy, Clone)]
+pub struct mpc_lintsrc {
+    pub type_: ::std::os::raw::c_uchar,
+    pub irqtype: ::std::os::raw::c_uchar,
+    pub irqflag: ::std::os::raw::c_ushort,
+    pub srcbusid: ::std::os::raw::c_uchar,
+    pub srcbusirq: ::std::os::raw::c_uchar,
+    pub destapic: ::std::os::raw::c_uchar,
+    pub destapiclint: ::std::os::raw::c_uchar,
+}
+
+#[repr(C)]
+#[derive(Debug, Default, Copy, Clone)]
+pub struct mpc_oemtable {
+    pub signature: [::std::os::raw::c_char; 4usize],
+    pub length: ::std::os::raw::c_ushort,
+    pub rev: ::std::os::raw::c_char,
+    pub checksum: ::std::os::raw::c_char,
+    pub mpc: [::std::os::raw::c_char; 8usize],
+}

arch/src/x86_64/mptable.rs

@@ -5,16 +5,15 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE-BSD-3-Clause file.
 
+use crate::layout::{APIC_START, HIGH_RAM_START, IOAPIC_START};
+use crate::x86_64::mpspec;
+use crate::GuestMemoryMmap;
+use libc::c_char;
 use std::io;
 use std::mem;
 use std::result;
 use std::slice;
-
-use libc::c_char;
-
-use arch_gen::x86::mpspec;
-use layout::{APIC_START, IOAPIC_START, MPTABLE_START};
-use vm_memory::{Address, ByteValued, Bytes, GuestMemory, GuestMemoryError, GuestMemoryMmap};
+use vm_memory::{Address, ByteValued, Bytes, GuestAddress, GuestMemory, GuestMemoryError};
 
 // This is a workaround to the Rust enforcement specifying that any implementation of a foreign
 // trait (in this case `ByteValued`) where:
@@ -36,7 +35,7 @@ struct MpcLintsrcWrapper(mpspec::mpc_lintsrc);
 #[derive(Copy, Clone, Default)]
 struct MpfIntelWrapper(mpspec::mpf_intel);
 
-// These `mpspec` wrapper types are only data, reading them from data is a safe initialization.
+// SAFETY: These `mpspec` wrapper types are only data, reading them from data is a safe initialization.
 unsafe impl ByteValued for MpcBusWrapper {}
 unsafe impl ByteValued for MpcCpuWrapper {}
 unsafe impl ByteValued for MpcIntsrcWrapper {}
@@ -121,16 +120,21 @@ fn compute_mp_size(num_cpus: u8) -> usize {
 }
 
 /// Performs setup of the MP table for the given `num_cpus`.
-pub fn setup_mptable(mem: &GuestMemoryMmap, num_cpus: u8) -> Result<()> {
+pub fn setup_mptable(offset: GuestAddress, mem: &GuestMemoryMmap, num_cpus: u8) -> Result<()> {
     if num_cpus as u32 > MAX_SUPPORTED_CPUS {
         return Err(Error::TooManyCpus);
     }
 
     // Used to keep track of the next base pointer into the MP table.
-    let mut base_mp = MPTABLE_START;
+    let mut base_mp = offset;
 
     let mp_size = compute_mp_size(num_cpus);
 
+    if offset.unchecked_add(mp_size as u64) >= HIGH_RAM_START {
+        warn!("Skipping mptable creation due to insufficient space");
+        return Ok(());
+    }
+
     let mut checksum: u8 = 0;
     let ioapicid: u8 = num_cpus + 1;
 
@@ -215,7 +219,7 @@ pub fn setup_mptable(mem: &GuestMemoryMmap, num_cpus: u8) -> Result<()> {
         let size = mem::size_of::<MpcIntsrcWrapper>();
         let mut mpc_intsrc = MpcIntsrcWrapper(mpspec::mpc_intsrc::default());
         mpc_intsrc.0.type_ = mpspec::MP_INTSRC as u8;
-        mpc_intsrc.0.irqtype = mpspec::mp_irq_source_types_mp_INT as u8;
+        mpc_intsrc.0.irqtype = mpspec::MP_IRQ_SOURCE_TYPES_MP_INT as u8;
         mpc_intsrc.0.irqflag = mpspec::MP_IRQDIR_DEFAULT as u16;
         mpc_intsrc.0.srcbus = 0;
         mpc_intsrc.0.srcbusirq = i;
@@ -230,7 +234,7 @@ pub fn setup_mptable(mem: &GuestMemoryMmap, num_cpus: u8) -> Result<()> {
         let size = mem::size_of::<MpcLintsrcWrapper>();
         let mut mpc_lintsrc = MpcLintsrcWrapper(mpspec::mpc_lintsrc::default());
         mpc_lintsrc.0.type_ = mpspec::MP_LINTSRC as u8;
-        mpc_lintsrc.0.irqtype = mpspec::mp_irq_source_types_mp_ExtINT as u8;
+        mpc_lintsrc.0.irqtype = mpspec::MP_IRQ_SOURCE_TYPES_MP_EXT_INT as u8;
         mpc_lintsrc.0.irqflag = mpspec::MP_IRQDIR_DEFAULT as u16;
         mpc_lintsrc.0.srcbusid = 0;
         mpc_lintsrc.0.srcbusirq = 0;
@@ -245,7 +249,7 @@ pub fn setup_mptable(mem: &GuestMemoryMmap, num_cpus: u8) -> Result<()> {
         let size = mem::size_of::<MpcLintsrcWrapper>();
         let mut mpc_lintsrc = MpcLintsrcWrapper(mpspec::mpc_lintsrc::default());
         mpc_lintsrc.0.type_ = mpspec::MP_LINTSRC as u8;
-        mpc_lintsrc.0.irqtype = mpspec::mp_irq_source_types_mp_NMI as u8;
+        mpc_lintsrc.0.irqtype = mpspec::MP_IRQ_SOURCE_TYPES_MP_NMI as u8;
         mpc_lintsrc.0.irqflag = mpspec::MP_IRQDIR_DEFAULT as u16;
         mpc_lintsrc.0.srcbusid = 0;
         mpc_lintsrc.0.srcbusirq = 0;
@@ -280,6 +284,7 @@ pub fn setup_mptable(mem: &GuestMemoryMmap, num_cpus: u8) -> Result<()> {
 #[cfg(test)]
 mod tests {
     use super::*;
+    use crate::layout::MPTABLE_START;
     use vm_memory::{GuestAddress, GuestUsize};
 
     fn table_entry_size(type_: u8) -> usize {
@@ -299,7 +304,7 @@ mod tests {
         let mem =
             GuestMemoryMmap::from_ranges(&[(MPTABLE_START, compute_mp_size(num_cpus))]).unwrap();
 
-        setup_mptable(&mem, num_cpus).unwrap();
+        setup_mptable(MPTABLE_START, &mem, num_cpus).unwrap();
     }
 
     #[test]
@@ -308,7 +313,7 @@ mod tests {
         let mem = GuestMemoryMmap::from_ranges(&[(MPTABLE_START, compute_mp_size(num_cpus) - 1)])
             .unwrap();
 
-        assert!(setup_mptable(&mem, num_cpus).is_err());
+        assert!(setup_mptable(MPTABLE_START, &mem, num_cpus).is_err());
     }
 
     #[test]
@@ -317,7 +322,7 @@ mod tests {
         let mem =
             GuestMemoryMmap::from_ranges(&[(MPTABLE_START, compute_mp_size(num_cpus))]).unwrap();
 
-        setup_mptable(&mem, num_cpus).unwrap();
+        setup_mptable(MPTABLE_START, &mem, num_cpus).unwrap();
 
         let mpf_intel: MpfIntelWrapper = mem.read_obj(MPTABLE_START).unwrap();
 
@@ -333,7 +338,7 @@ mod tests {
         let mem =
             GuestMemoryMmap::from_ranges(&[(MPTABLE_START, compute_mp_size(num_cpus))]).unwrap();
 
-        setup_mptable(&mem, num_cpus).unwrap();
+        setup_mptable(MPTABLE_START, &mem, num_cpus).unwrap();
 
         let mpf_intel: MpfIntelWrapper = mem.read_obj(MPTABLE_START).unwrap();
         let mpc_offset = GuestAddress(mpf_intel.0.physptr as GuestUsize);
@@ -367,7 +372,7 @@ mod tests {
         .unwrap();
 
         for i in 0..MAX_SUPPORTED_CPUS as u8 {
-            setup_mptable(&mem, i).unwrap();
+            setup_mptable(MPTABLE_START, &mem, i).unwrap();
 
             let mpf_intel: MpfIntelWrapper = mem.read_obj(MPTABLE_START).unwrap();
             let mpc_offset = GuestAddress(mpf_intel.0.physptr as GuestUsize);
@@ -400,7 +405,7 @@ mod tests {
         let mem =
             GuestMemoryMmap::from_ranges(&[(MPTABLE_START, compute_mp_size(cpus as u8))]).unwrap();
 
-        let result = setup_mptable(&mem, cpus as u8);
+        let result = setup_mptable(MPTABLE_START, &mem, cpus as u8);
         assert!(result.is_err());
     }
 }

arch/src/x86_64/regs.rs

@@ -6,45 +6,41 @@
 // Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE-BSD-3-Clause file.
-
+use crate::layout::{BOOT_GDT_START, BOOT_IDT_START, PVH_INFO_START};
+use crate::GuestMemoryMmap;
+use hypervisor::arch::x86::gdt::{gdt_entry, segment_from_gdt};
+use hypervisor::arch::x86::regs::*;
+use hypervisor::x86_64::{FpuState, SpecialRegisters, StandardRegisters};
+use std::sync::Arc;
 use std::{mem, result};
-
-use super::gdt::{gdt_entry, kvm_segment_from_gdt};
-use super::BootProtocol;
-use arch_gen::x86::msr_index;
-use kvm_bindings::{kvm_fpu, kvm_msr_entry, kvm_regs, kvm_sregs, Msrs};
-use kvm_ioctls::VcpuFd;
-use layout::{BOOT_GDT_START, BOOT_IDT_START, PDE_START, PDPTE_START, PML4_START, PVH_INFO_START};
-use vm_memory::{Address, Bytes, GuestMemory, GuestMemoryError, GuestMemoryMmap};
-
-// MTRR constants
-const MTRR_ENABLE: u64 = 0x800; // IA32_MTRR_DEF_TYPE MSR: E (MTRRs enabled) flag, bit 11
-const MTRR_MEM_TYPE_WB: u64 = 0x6;
+use vm_memory::{Address, Bytes, GuestMemory, GuestMemoryError};
 
 #[derive(Debug)]
 pub enum Error {
     /// Failed to get SREGs for this CPU.
-    GetStatusRegisters(kvm_ioctls::Error),
+    GetStatusRegisters(hypervisor::HypervisorCpuError),
     /// Failed to set base registers for this CPU.
-    SetBaseRegisters(kvm_ioctls::Error),
+    SetBaseRegisters(hypervisor::HypervisorCpuError),
     /// Failed to configure the FPU.
-    SetFPURegisters(kvm_ioctls::Error),
+    SetFpuRegisters(hypervisor::HypervisorCpuError),
     /// Setting up MSRs failed.
-    SetModelSpecificRegisters(kvm_ioctls::Error),
+    SetModelSpecificRegisters(hypervisor::HypervisorCpuError),
     /// Failed to set SREGs for this CPU.
-    SetStatusRegisters(kvm_ioctls::Error),
+    SetStatusRegisters(hypervisor::HypervisorCpuError),
     /// Checking the GDT address failed.
-    CheckGDTAddr,
+    CheckGdtAddr,
     /// Writing the GDT to RAM failed.
-    WriteGDT(GuestMemoryError),
+    WriteGdt(GuestMemoryError),
     /// Writing the IDT to RAM failed.
-    WriteIDT(GuestMemoryError),
+    WriteIdt(GuestMemoryError),
     /// Writing PDPTE to RAM failed.
-    WritePDPTEAddress(GuestMemoryError),
+    WritePdpteAddress(GuestMemoryError),
     /// Writing PDE to RAM failed.
-    WritePDEAddress(GuestMemoryError),
+    WritePdeAddress(GuestMemoryError),
     /// Writing PML4 to RAM failed.
-    WritePML4Address(GuestMemoryError),
+    WritePml4Address(GuestMemoryError),
+    /// Writing PML5 to RAM failed.
+    WritePml5Address(GuestMemoryError),
 }
 
 pub type Result<T> = result::Result<T, Error>;
@@ -54,14 +50,14 @@ pub type Result<T> = result::Result<T, Error>;
 /// # Arguments
 ///
 /// * `vcpu` - Structure for the VCPU that holds the VCPU's fd.
-pub fn setup_fpu(vcpu: &VcpuFd) -> Result<()> {
-    let fpu: kvm_fpu = kvm_fpu {
+pub fn setup_fpu(vcpu: &Arc<dyn hypervisor::Vcpu>) -> Result<()> {
+    let fpu: FpuState = FpuState {
         fcw: 0x37f,
         mxcsr: 0x1f80,
         ..Default::default()
     };
 
-    vcpu.set_fpu(&fpu).map_err(Error::SetFPURegisters)
+    vcpu.set_fpu(&fpu).map_err(Error::SetFpuRegisters)
 }
 
 /// Configure Model Specific Registers (MSRs) for a given CPU.
@@ -69,8 +65,8 @@ pub fn setup_fpu(vcpu: &VcpuFd) -> Result<()> {
 /// # Arguments
 ///
 /// * `vcpu` - Structure for the VCPU that holds the VCPU's fd.
-pub fn setup_msrs(vcpu: &VcpuFd) -> Result<()> {
-    vcpu.set_msrs(&boot_msr_entries())
+pub fn setup_msrs(vcpu: &Arc<dyn hypervisor::Vcpu>) -> Result<()> {
+    vcpu.set_msrs(&hypervisor::x86_64::boot_msr_entries())
         .map_err(Error::SetModelSpecificRegisters)?;
 
     Ok(())
@@ -82,32 +78,12 @@ pub fn setup_msrs(vcpu: &VcpuFd) -> Result<()> {
 ///
 /// * `vcpu` - Structure for the VCPU that holds the VCPU's fd.
 /// * `boot_ip` - Starting instruction pointer.
-/// * `boot_sp` - Starting stack pointer.
-/// * `boot_si` - Must point to zero page address per Linux ABI.
-pub fn setup_regs(
-    vcpu: &VcpuFd,
-    boot_ip: u64,
-    boot_sp: u64,
-    boot_si: u64,
-    boot_prot: BootProtocol,
-) -> Result<()> {
-    let regs: kvm_regs = match boot_prot {
-        // Configure regs as required by PVH boot protocol.
-        BootProtocol::PvhBoot => kvm_regs {
-            rflags: 0x0000000000000002u64,
-            rbx: PVH_INFO_START.raw_value(),
-            rip: boot_ip,
-            ..Default::default()
-        },
-        // Configure regs as required by Linux 64-bit boot protocol.
-        BootProtocol::LinuxBoot => kvm_regs {
-            rflags: 0x0000000000000002u64,
-            rip: boot_ip,
-            rsp: boot_sp,
-            rbp: boot_sp,
-            rsi: boot_si,
-            ..Default::default()
-        },
+pub fn setup_regs(vcpu: &Arc<dyn hypervisor::Vcpu>, boot_ip: u64) -> Result<()> {
+    let regs = StandardRegisters {
+        rflags: 0x0000000000000002u64,
+        rbx: PVH_INFO_START.raw_value(),
+        rip: boot_ip,
+        ..Default::default()
     };
     vcpu.set_regs(&regs).map_err(Error::SetBaseRegisters)
 }
@@ -118,34 +94,21 @@ pub fn setup_regs(
 ///
 /// * `mem` - The memory that will be passed to the guest.
 /// * `vcpu` - Structure for the VCPU that holds the VCPU's fd.
-pub fn setup_sregs(mem: &GuestMemoryMmap, vcpu: &VcpuFd, boot_prot: BootProtocol) -> Result<()> {
-    let mut sregs: kvm_sregs = vcpu.get_sregs().map_err(Error::GetStatusRegisters)?;
-
-    configure_segments_and_sregs(mem, &mut sregs, boot_prot)?;
-
-    if let BootProtocol::LinuxBoot = boot_prot {
-        setup_page_tables(mem, &mut sregs)?; // TODO(dgreid) - Can this be done once per system instead?
-    }
-
+pub fn setup_sregs(mem: &GuestMemoryMmap, vcpu: &Arc<dyn hypervisor::Vcpu>) -> Result<()> {
+    let mut sregs: SpecialRegisters = vcpu.get_sregs().map_err(Error::GetStatusRegisters)?;
+    configure_segments_and_sregs(mem, &mut sregs)?;
     vcpu.set_sregs(&sregs).map_err(Error::SetStatusRegisters)
 }
 
 const BOOT_GDT_MAX: usize = 4;
 
-const EFER_LMA: u64 = 0x400;
-const EFER_LME: u64 = 0x100;
-
-const X86_CR0_PE: u64 = 0x1;
-const X86_CR0_PG: u64 = 0x80000000;
-const X86_CR4_PAE: u64 = 0x20;
-
 fn write_gdt_table(table: &[u64], guest_mem: &GuestMemoryMmap) -> Result<()> {
     let boot_gdt_addr = BOOT_GDT_START;
     for (index, entry) in table.iter().enumerate() {
         let addr = guest_mem
             .checked_offset(boot_gdt_addr, index * mem::size_of::<u64>())
-            .ok_or(Error::CheckGDTAddr)?;
-        guest_mem.write_obj(*entry, addr).map_err(Error::WriteGDT)?;
+            .ok_or(Error::CheckGdtAddr)?;
+        guest_mem.write_obj(*entry, addr).map_err(Error::WriteGdt)?;
     }
     Ok(())
 }
@@ -154,38 +117,26 @@ fn write_idt_value(val: u64, guest_mem: &GuestMemoryMmap) -> Result<()> {
     let boot_idt_addr = BOOT_IDT_START;
     guest_mem
         .write_obj(val, boot_idt_addr)
-        .map_err(Error::WriteIDT)
+        .map_err(Error::WriteIdt)
 }
 
-fn configure_segments_and_sregs(
+pub fn configure_segments_and_sregs(
     mem: &GuestMemoryMmap,
-    sregs: &mut kvm_sregs,
-    boot_prot: BootProtocol,
+    sregs: &mut SpecialRegisters,
 ) -> Result<()> {
-    let gdt_table: [u64; BOOT_GDT_MAX as usize] = match boot_prot {
-        BootProtocol::PvhBoot => {
-            // Configure GDT entries as specified by PVH boot protocol
-            [
-                gdt_entry(0, 0, 0),               // NULL
-                gdt_entry(0xc09b, 0, 0xffffffff), // CODE
-                gdt_entry(0xc093, 0, 0xffffffff), // DATA
-                gdt_entry(0x008b, 0, 0x67),       // TSS
-            ]
-        }
-        BootProtocol::LinuxBoot => {
-            // Configure GDT entries as specified by Linux 64bit boot protocol
-            [
-                gdt_entry(0, 0, 0),            // NULL
-                gdt_entry(0xa09b, 0, 0xfffff), // CODE
-                gdt_entry(0xc093, 0, 0xfffff), // DATA
-                gdt_entry(0x808b, 0, 0xfffff), // TSS
-            ]
-        }
+    let gdt_table: [u64; BOOT_GDT_MAX as usize] = {
+        // Configure GDT entries as specified by PVH boot protocol
+        [
+            gdt_entry(0, 0, 0),               // NULL
+            gdt_entry(0xc09b, 0, 0xffffffff), // CODE
+            gdt_entry(0xc093, 0, 0xffffffff), // DATA
+            gdt_entry(0x008b, 0, 0x67),       // TSS
+        ]
     };
 
-    let code_seg = kvm_segment_from_gdt(gdt_table[1], 1);
-    let data_seg = kvm_segment_from_gdt(gdt_table[2], 2);
-    let tss_seg = kvm_segment_from_gdt(gdt_table[3], 3);
+    let code_seg = segment_from_gdt(gdt_table[1], 1);
+    let data_seg = segment_from_gdt(gdt_table[2], 2);
+    let tss_seg = segment_from_gdt(gdt_table[3], 3);
 
     // Write segments
     write_gdt_table(&gdt_table[..], mem)?;
@@ -204,94 +155,20 @@ fn configure_segments_and_sregs(
     sregs.ss = data_seg;
     sregs.tr = tss_seg;
 
-    match boot_prot {
-        BootProtocol::PvhBoot => {
-            sregs.cr0 = X86_CR0_PE;
-            sregs.cr4 = 0;
-        }
-        BootProtocol::LinuxBoot => {
-            /* 64-bit protected mode */
-            sregs.cr0 |= X86_CR0_PE;
-            sregs.efer |= EFER_LME | EFER_LMA;
-        }
-    }
+    sregs.cr0 = CR0_PE;
+    sregs.cr4 = 0;
 
     Ok(())
 }
 
-fn setup_page_tables(mem: &GuestMemoryMmap, sregs: &mut kvm_sregs) -> Result<()> {
-    // Puts PML4 right after zero page but aligned to 4k.
-
-    // Entry covering VA [0..512GB)
-    mem.write_obj(PDPTE_START.raw_value() | 0x03, PML4_START)
-        .map_err(Error::WritePML4Address)?;
-
-    // Entry covering VA [0..1GB)
-    mem.write_obj(PDE_START.raw_value() | 0x03, PDPTE_START)
-        .map_err(Error::WritePDPTEAddress)?;
-    // 512 2MB entries together covering VA [0..1GB). Note we are assuming
-    // CPU supports 2MB pages (/proc/cpuinfo has 'pse'). All modern CPUs do.
-    for i in 0..512 {
-        mem.write_obj((i << 21) + 0x83u64, PDE_START.unchecked_add(i * 8))
-            .map_err(Error::WritePDEAddress)?;
-    }
-
-    sregs.cr3 = PML4_START.raw_value();
-    sregs.cr4 |= X86_CR4_PAE;
-    sregs.cr0 |= X86_CR0_PG;
-    Ok(())
-}
-
-macro_rules! kvm_msr {
-    ($msr:expr) => {
-        kvm_msr_entry {
-            index: $msr,
-            data: 0x0,
-            ..Default::default()
-        }
-    };
-}
-
-macro_rules! kvm_msr_data {
-    ($msr:expr, $data:expr) => {
-        kvm_msr_entry {
-            index: $msr,
-            data: $data,
-            ..Default::default()
-        }
-    };
-}
-
-pub fn boot_msr_entries() -> Msrs {
-    Msrs::from_entries(&[
-        kvm_msr!(msr_index::MSR_IA32_SYSENTER_CS),
-        kvm_msr!(msr_index::MSR_IA32_SYSENTER_ESP),
-        kvm_msr!(msr_index::MSR_IA32_SYSENTER_EIP),
-        kvm_msr!(msr_index::MSR_STAR),
-        kvm_msr!(msr_index::MSR_CSTAR),
-        kvm_msr!(msr_index::MSR_LSTAR),
-        kvm_msr!(msr_index::MSR_KERNEL_GS_BASE),
-        kvm_msr!(msr_index::MSR_SYSCALL_MASK),
-        kvm_msr!(msr_index::MSR_IA32_TSC),
-        kvm_msr_data!(
-            msr_index::MSR_IA32_MISC_ENABLE,
-            msr_index::MSR_IA32_MISC_ENABLE_FAST_STRING as u64
-        ),
-        kvm_msr_data!(msr_index::MSR_MTRRdefType, MTRR_ENABLE | MTRR_MEM_TYPE_WB),
-    ])
-}
-
 #[cfg(test)]
 mod tests {
-    extern crate kvm_ioctls;
-    extern crate vm_memory;
-
     use super::*;
-    use kvm_ioctls::Kvm;
-    use vm_memory::{GuestAddress, GuestMemoryMmap};
+    use crate::GuestMemoryMmap;
+    use vm_memory::GuestAddress;
 
     fn create_guest_mem() -> GuestMemoryMmap {
-        GuestMemoryMmap::from_ranges(&vec![(GuestAddress(0), 0x10000)]).unwrap()
+        GuestMemoryMmap::from_ranges(&[(GuestAddress(0), 0x10000)]).unwrap()
     }
 
     fn read_u64(gm: &GuestMemoryMmap, offset: GuestAddress) -> u64 {
@@ -300,38 +177,9 @@ mod tests {
 
     #[test]
     fn segments_and_sregs() {
-        let mut sregs: kvm_sregs = Default::default();
+        let mut sregs: SpecialRegisters = Default::default();
         let gm = create_guest_mem();
-        configure_segments_and_sregs(&gm, &mut sregs, BootProtocol::LinuxBoot).unwrap();
-
-        assert_eq!(0x0, read_u64(&gm, BOOT_GDT_START));
-        assert_eq!(
-            0xaf9b000000ffff,
-            read_u64(&gm, BOOT_GDT_START.unchecked_add(8))
-        );
-        assert_eq!(
-            0xcf93000000ffff,
-            read_u64(&gm, BOOT_GDT_START.unchecked_add(16))
-        );
-        assert_eq!(
-            0x8f8b000000ffff,
-            read_u64(&gm, BOOT_GDT_START.unchecked_add(24))
-        );
-        assert_eq!(0x0, read_u64(&gm, BOOT_IDT_START));
-
-        assert_eq!(0, sregs.cs.base);
-        assert_eq!(0xffffffff, sregs.ds.limit);
-        assert_eq!(0x10, sregs.es.selector);
-        assert_eq!(1, sregs.fs.present);
-        assert_eq!(1, sregs.gs.g);
-        assert_eq!(0, sregs.ss.avl);
-        assert_eq!(0, sregs.tr.base);
-        assert_eq!(0xffffffff, sregs.tr.limit);
-        assert_eq!(0, sregs.tr.avl);
-        assert_eq!(X86_CR0_PE, sregs.cr0);
-        assert_eq!(EFER_LME | EFER_LMA, sregs.efer);
-
-        configure_segments_and_sregs(&gm, &mut sregs, BootProtocol::PvhBoot).unwrap();
+        configure_segments_and_sregs(&gm, &mut sregs).unwrap();
         assert_eq!(0x0, read_u64(&gm, BOOT_GDT_START));
         assert_eq!(
             0xcf9b000000ffff,
@@ -358,119 +206,7 @@ mod tests {
         assert_eq!(0x67, sregs.tr.limit);
         assert_eq!(0xb, sregs.tr.type_);
         assert_eq!(0, sregs.tr.avl);
-        assert_eq!(X86_CR0_PE, sregs.cr0);
+        assert_eq!(CR0_PE, sregs.cr0);
         assert_eq!(0, sregs.cr4);
     }
-
-    #[test]
-    fn page_tables() {
-        let mut sregs: kvm_sregs = Default::default();
-        let gm = create_guest_mem();
-        setup_page_tables(&gm, &mut sregs).unwrap();
-
-        assert_eq!(0xa003, read_u64(&gm, PML4_START));
-        assert_eq!(0xb003, read_u64(&gm, PDPTE_START));
-        for i in 0..512 {
-            assert_eq!(
-                (i << 21) + 0x83u64,
-                read_u64(&gm, PDE_START.unchecked_add(i * 8))
-            );
-        }
-
-        assert_eq!(PML4_START.raw_value(), sregs.cr3);
-        assert_eq!(X86_CR4_PAE, sregs.cr4);
-        assert_eq!(X86_CR0_PG, sregs.cr0);
-    }
-
-    #[test]
-    fn test_setup_fpu() {
-        let kvm = Kvm::new().unwrap();
-        let vm = kvm.create_vm().unwrap();
-        let vcpu = vm.create_vcpu(0).unwrap();
-        setup_fpu(&vcpu).unwrap();
-
-        let expected_fpu: kvm_fpu = kvm_fpu {
-            fcw: 0x37f,
-            mxcsr: 0x1f80,
-            ..Default::default()
-        };
-        let actual_fpu: kvm_fpu = vcpu.get_fpu().unwrap();
-        // TODO: auto-generate kvm related structures with PartialEq on.
-        assert_eq!(expected_fpu.fcw, actual_fpu.fcw);
-        // Setting the mxcsr register from kvm_fpu inside setup_fpu does not influence anything.
-        // See 'kvm_arch_vcpu_ioctl_set_fpu' from arch/x86/kvm/x86.c.
-        // The mxcsr will stay 0 and the assert below fails. Decide whether or not we should
-        // remove it at all.
-        // assert!(expected_fpu.mxcsr == actual_fpu.mxcsr);
-    }
-
-    #[test]
-    fn test_setup_msrs() {
-        let kvm = Kvm::new().unwrap();
-        let vm = kvm.create_vm().unwrap();
-        let vcpu = vm.create_vcpu(0).unwrap();
-        setup_msrs(&vcpu).unwrap();
-
-        // This test will check against the last MSR entry configured (the tenth one).
-        // See create_msr_entries for details.
-        let mut msrs = Msrs::from_entries(&[kvm_msr_entry {
-            index: msr_index::MSR_IA32_MISC_ENABLE,
-            ..Default::default()
-        }]);
-
-        // get_msrs returns the number of msrs that it succeed in reading. We only want to read 1
-        // in this test case scenario.
-        let read_msrs = vcpu.get_msrs(&mut msrs).unwrap();
-        assert_eq!(read_msrs, 1);
-
-        // Official entries that were setup when we did setup_msrs. We need to assert that the
-        // tenth one (i.e the one with index msr_index::MSR_IA32_MISC_ENABLE has the data we
-        // expect.
-        let entry_vec = boot_msr_entries();
-        assert_eq!(entry_vec.as_slice()[9], msrs.as_slice()[0]);
-    }
-
-    #[test]
-    fn test_setup_regs() {
-        let kvm = Kvm::new().unwrap();
-        let vm = kvm.create_vm().unwrap();
-        let vcpu = vm.create_vcpu(0).unwrap();
-
-        let expected_regs: kvm_regs = kvm_regs {
-            rflags: 0x0000000000000002u64,
-            rip: 1,
-            rsp: 2,
-            rbp: 2,
-            rsi: 3,
-            ..Default::default()
-        };
-
-        setup_regs(
-            &vcpu,
-            expected_regs.rip,
-            expected_regs.rsp,
-            expected_regs.rsi,
-            BootProtocol::LinuxBoot,
-        )
-        .unwrap();
-
-        let actual_regs: kvm_regs = vcpu.get_regs().unwrap();
-        assert_eq!(actual_regs, expected_regs);
-    }
-
-    #[test]
-    fn test_setup_sregs() {
-        let kvm = Kvm::new().unwrap();
-        let vm = kvm.create_vm().unwrap();
-        let vcpu = vm.create_vcpu(0).unwrap();
-
-        let mut expected_sregs: kvm_sregs = vcpu.get_sregs().unwrap();
-        let gm = create_guest_mem();
-        configure_segments_and_sregs(&gm, &mut expected_sregs, BootProtocol::LinuxBoot).unwrap();
-        setup_page_tables(&gm, &mut expected_sregs).unwrap();
-
-        setup_sregs(&gm, &vcpu, BootProtocol::LinuxBoot).unwrap();
-        let actual_sregs: kvm_sregs = vcpu.get_sregs().unwrap();
-        assert_eq!(expected_sregs, actual_sregs);
-    }
 }

arch/src/x86_64/smbios.rs

@@ -0,0 +1,272 @@
+// Copyright © 2020 Intel Corporation
+//
+// Copyright 2019 The Chromium OS Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style license that can be
+// found in the LICENSE file.
+//
+// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
+
+use crate::layout::SMBIOS_START;
+use crate::GuestMemoryMmap;
+use std::fmt::{self, Display};
+use std::mem;
+use std::result;
+use std::slice;
+use vm_memory::ByteValued;
+use vm_memory::{Address, Bytes, GuestAddress};
+
+#[allow(unused_variables)]
+#[derive(Debug)]
+pub enum Error {
+    /// There was too little guest memory to store the entire SMBIOS table.
+    NotEnoughMemory,
+    /// The SMBIOS table has too little address space to be stored.
+    AddressOverflow,
+    /// Failure while zeroing out the memory for the SMBIOS table.
+    Clear,
+    /// Failure to write SMBIOS entrypoint structure
+    WriteSmbiosEp,
+    /// Failure to write additional data to memory
+    WriteData,
+}
+
+impl std::error::Error for Error {}
+
+impl Display for Error {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        use self::Error::*;
+
+        let description = match self {
+            NotEnoughMemory => "There was too little guest memory to store the SMBIOS table",
+            AddressOverflow => "The SMBIOS table has too little address space to be stored",
+            Clear => "Failure while zeroing out the memory for the SMBIOS table",
+            WriteSmbiosEp => "Failure to write SMBIOS entrypoint structure",
+            WriteData => "Failure to write additional data to memory",
+        };
+
+        write!(f, "SMBIOS error: {}", description)
+    }
+}
+
+pub type Result<T> = result::Result<T, Error>;
+
+// Constants sourced from SMBIOS Spec 3.2.0.
+const SM3_MAGIC_IDENT: &[u8; 5usize] = b"_SM3_";
+const BIOS_INFORMATION: u8 = 0;
+const SYSTEM_INFORMATION: u8 = 1;
+const END_OF_TABLE: u8 = 127;
+const PCI_SUPPORTED: u64 = 1 << 7;
+const IS_VIRTUAL_MACHINE: u8 = 1 << 4;
+
+fn compute_checksum<T: Copy>(v: &T) -> u8 {
+    // Safe because we are only reading the bytes within the size of the `T` reference `v`.
+    let v_slice = unsafe { slice::from_raw_parts(v as *const T as *const u8, mem::size_of::<T>()) };
+    let mut checksum: u8 = 0;
+    for i in v_slice.iter() {
+        checksum = checksum.wrapping_add(*i);
+    }
+    (!checksum).wrapping_add(1)
+}
+
+#[repr(packed)]
+#[derive(Default, Copy)]
+pub struct Smbios30Entrypoint {
+    pub signature: [u8; 5usize],
+    pub checksum: u8,
+    pub length: u8,
+    pub majorver: u8,
+    pub minorver: u8,
+    pub docrev: u8,
+    pub revision: u8,
+    pub reserved: u8,
+    pub max_size: u32,
+    pub physptr: u64,
+}
+
+impl Clone for Smbios30Entrypoint {
+    fn clone(&self) -> Self {
+        *self
+    }
+}
+
+#[repr(packed)]
+#[derive(Default, Copy)]
+pub struct SmbiosBiosInfo {
+    pub typ: u8,
+    pub length: u8,
+    pub handle: u16,
+    pub vendor: u8,
+    pub version: u8,
+    pub start_addr: u16,
+    pub release_date: u8,
+    pub rom_size: u8,
+    pub characteristics: u64,
+    pub characteristics_ext1: u8,
+    pub characteristics_ext2: u8,
+}
+
+impl Clone for SmbiosBiosInfo {
+    fn clone(&self) -> Self {
+        *self
+    }
+}
+
+#[repr(packed)]
+#[derive(Default, Copy)]
+pub struct SmbiosSysInfo {
+    pub typ: u8,
+    pub length: u8,
+    pub handle: u16,
+    pub manufacturer: u8,
+    pub product_name: u8,
+    pub version: u8,
+    pub serial_number: u8,
+    pub uuid: [u8; 16usize],
+    pub wake_up_type: u8,
+    pub sku: u8,
+    pub family: u8,
+}
+
+impl Clone for SmbiosSysInfo {
+    fn clone(&self) -> Self {
+        *self
+    }
+}
+
+// SAFETY: These data structures only contain a series of integers
+unsafe impl ByteValued for Smbios30Entrypoint {}
+unsafe impl ByteValued for SmbiosBiosInfo {}
+unsafe impl ByteValued for SmbiosSysInfo {}
+
+fn write_and_incr<T: ByteValued>(
+    mem: &GuestMemoryMmap,
+    val: T,
+    mut curptr: GuestAddress,
+) -> Result<GuestAddress> {
+    mem.write_obj(val, curptr).map_err(|_| Error::WriteData)?;
+    curptr = curptr
+        .checked_add(mem::size_of::<T>() as u64)
+        .ok_or(Error::NotEnoughMemory)?;
+    Ok(curptr)
+}
+
+fn write_string(
+    mem: &GuestMemoryMmap,
+    val: &str,
+    mut curptr: GuestAddress,
+) -> Result<GuestAddress> {
+    for c in val.as_bytes().iter() {
+        curptr = write_and_incr(mem, *c, curptr)?;
+    }
+    curptr = write_and_incr(mem, 0u8, curptr)?;
+    Ok(curptr)
+}
+
+pub fn setup_smbios(mem: &GuestMemoryMmap) -> Result<u64> {
+    let physptr = GuestAddress(SMBIOS_START)
+        .checked_add(mem::size_of::<Smbios30Entrypoint>() as u64)
+        .ok_or(Error::NotEnoughMemory)?;
+    let mut curptr = physptr;
+    let mut handle = 0;
+
+    {
+        handle += 1;
+        let smbios_biosinfo = SmbiosBiosInfo {
+            typ: BIOS_INFORMATION,
+            length: mem::size_of::<SmbiosBiosInfo>() as u8,
+            handle,
+            vendor: 1,  // First string written in this section
+            version: 2, // Second string written in this section
+            characteristics: PCI_SUPPORTED,
+            characteristics_ext2: IS_VIRTUAL_MACHINE,
+            ..Default::default()
+        };
+        curptr = write_and_incr(mem, smbios_biosinfo, curptr)?;
+        curptr = write_string(mem, "cloud-hypervisor", curptr)?;
+        curptr = write_string(mem, "0", curptr)?;
+        curptr = write_and_incr(mem, 0u8, curptr)?;
+    }
+
+    {
+        handle += 1;
+        let smbios_sysinfo = SmbiosSysInfo {
+            typ: SYSTEM_INFORMATION,
+            length: mem::size_of::<SmbiosSysInfo>() as u8,
+            handle,
+            manufacturer: 1, // First string written in this section
+            product_name: 2, // Second string written in this section
+            ..Default::default()
+        };
+        curptr = write_and_incr(mem, smbios_sysinfo, curptr)?;
+        curptr = write_string(mem, "Cloud Hypervisor", curptr)?;
+        curptr = write_string(mem, "cloud-hypervisor", curptr)?;
+        curptr = write_and_incr(mem, 0u8, curptr)?;
+    }
+
+    {
+        handle += 1;
+        let smbios_sysinfo = SmbiosSysInfo {
+            typ: END_OF_TABLE,
+            length: mem::size_of::<SmbiosSysInfo>() as u8,
+            handle,
+            ..Default::default()
+        };
+        curptr = write_and_incr(mem, smbios_sysinfo, curptr)?;
+        curptr = write_and_incr(mem, 0u8, curptr)?;
+    }
+
+    {
+        let mut smbios_ep = Smbios30Entrypoint {
+            signature: *SM3_MAGIC_IDENT,
+            length: mem::size_of::<Smbios30Entrypoint>() as u8,
+            // SMBIOS rev 3.2.0
+            majorver: 0x03,
+            minorver: 0x02,
+            docrev: 0x00,
+            revision: 0x01, // SMBIOS 3.0
+            max_size: curptr.unchecked_offset_from(physptr) as u32,
+            physptr: physptr.0,
+            ..Default::default()
+        };
+        smbios_ep.checksum = compute_checksum(&smbios_ep);
+        mem.write_obj(smbios_ep, GuestAddress(SMBIOS_START))
+            .map_err(|_| Error::WriteSmbiosEp)?;
+    }
+
+    Ok(curptr.unchecked_offset_from(physptr))
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn struct_size() {
+        assert_eq!(
+            mem::size_of::<Smbios30Entrypoint>(),
+            0x18usize,
+            concat!("Size of: ", stringify!(Smbios30Entrypoint))
+        );
+        assert_eq!(
+            mem::size_of::<SmbiosBiosInfo>(),
+            0x14usize,
+            concat!("Size of: ", stringify!(SmbiosBiosInfo))
+        );
+        assert_eq!(
+            mem::size_of::<SmbiosSysInfo>(),
+            0x1busize,
+            concat!("Size of: ", stringify!(SmbiosSysInfo))
+        );
+    }
+
+    #[test]
+    fn entrypoint_checksum() {
+        let mem = GuestMemoryMmap::from_ranges(&[(GuestAddress(SMBIOS_START), 4096)]).unwrap();
+
+        setup_smbios(&mem).unwrap();
+
+        let smbios_ep: Smbios30Entrypoint = mem.read_obj(GuestAddress(SMBIOS_START)).unwrap();
+
+        assert_eq!(compute_checksum(&smbios_ep), 0);
+    }
+}

arch/src/x86_64/tdx/mod.rs

@@ -0,0 +1,425 @@
+// Copyright © 2021 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0
+use crate::GuestMemoryMmap;
+use std::fs::File;
+use std::io::{Read, Seek, SeekFrom};
+use thiserror::Error;
+use vm_memory::{ByteValued, Bytes, GuestAddress, GuestMemoryError};
+
+#[derive(Error, Debug)]
+pub enum TdvfError {
+    #[error("Failed read TDVF descriptor: {0}")]
+    ReadDescriptor(#[source] std::io::Error),
+    #[error("Failed read TDVF descriptor offset: {0}")]
+    ReadDescriptorOffset(#[source] std::io::Error),
+    #[error("Invalid descriptor signature")]
+    InvalidDescriptorSignature,
+    #[error("Invalid descriptor size")]
+    InvalidDescriptorSize,
+    #[error("Invalid descriptor version")]
+    InvalidDescriptorVersion,
+    #[error("Failed to write HOB details to guest memory: {0}")]
+    GuestMemoryWriteHob(#[source] GuestMemoryError),
+}
+
+// TDVF_DESCRIPTOR
+#[repr(packed)]
+#[derive(Default)]
+pub struct TdvfDescriptor {
+    signature: [u8; 4],
+    length: u32,
+    version: u32,
+    num_sections: u32, // NumberOfSectionEntry
+}
+
+// TDVF_SECTION
+#[repr(packed)]
+#[derive(Clone, Copy, Default, Debug)]
+pub struct TdvfSection {
+    pub data_offset: u32,
+    pub data_size: u32, // RawDataSize
+    pub address: u64,   // MemoryAddress
+    pub size: u64,      // MemoryDataSize
+    pub r#type: TdvfSectionType,
+    pub attributes: u32,
+}
+
+#[repr(u32)]
+#[derive(Clone, Copy, Debug)]
+pub enum TdvfSectionType {
+    Bfv,
+    Cfv,
+    TdHob,
+    TempMem,
+    Reserved = 0xffffffff,
+}
+
+impl Default for TdvfSectionType {
+    fn default() -> Self {
+        TdvfSectionType::Reserved
+    }
+}
+
+#[repr(C)]
+#[derive(Clone, Copy, Default, Debug)]
+pub struct TdVmmDataRegion {
+    pub start_address: u64,
+    pub length: u64,
+    pub region_type: TdVmmDataRegionType,
+}
+
+#[repr(u16)]
+#[derive(Clone, Copy, Debug)]
+pub enum TdVmmDataRegionType {
+    Signature = 0x0000,
+    InterfaceVersion = 0x0001,
+    SystemUuid = 0x0002,
+    RamSize = 0x0003,
+    GraphicsEnabled = 0x0004,
+    SmpCpuCount = 0x0005,
+    MachineId = 0x0006,
+    KernelAddress = 0x0007,
+    KernelSize = 0x0008,
+    KernelCommandLine = 0x0009,
+    InitrdAddress = 0x000a,
+    InitrdSize = 0x000b,
+    BootDevice = 0x000c,
+    NumaData = 0x000d,
+    BootMenu = 0x000e,
+    MaximumCpuCount = 0x000f,
+    KernelEntry = 0x0010,
+    KernelData = 0x0011,
+    InitrdData = 0x0012,
+    CommandLineAddress = 0x0013,
+    CommandLineSize = 0x0014,
+    CommandLineData = 0x0015,
+    KernelSetupAddress = 0x0016,
+    KernelSetupSize = 0x0017,
+    KernelSetupData = 0x0018,
+    FileDir = 0x0019,
+    AcpiTables = 0x8000,
+    SmbiosTables = 0x8001,
+    Irq0Override = 0x8002,
+    E820Table = 0x8003,
+    HpetData = 0x8004,
+    Reserved = 0xffff,
+}
+
+impl Default for TdVmmDataRegionType {
+    fn default() -> Self {
+        TdVmmDataRegionType::Reserved
+    }
+}
+
+pub fn parse_tdvf_sections(file: &mut File) -> Result<Vec<TdvfSection>, TdvfError> {
+    // The 32-bit offset to the TDVF metadata is located 32 bytes from
+    // the end of the file.
+    // See "TDVF Metadata Pointer" in "TDX Virtual Firmware Design Guide
+    file.seek(SeekFrom::End(-0x20))
+        .map_err(TdvfError::ReadDescriptorOffset)?;
+
+    let mut descriptor_offset: [u8; 4] = [0; 4];
+    file.read_exact(&mut descriptor_offset)
+        .map_err(TdvfError::ReadDescriptorOffset)?;
+    let descriptor_offset = u32::from_le_bytes(descriptor_offset) as u64;
+
+    file.seek(SeekFrom::Start(descriptor_offset))
+        .map_err(TdvfError::ReadDescriptor)?;
+
+    let mut descriptor: TdvfDescriptor = Default::default();
+    // Safe as we read exactly the size of the descriptor header
+    file.read_exact(unsafe {
+        std::slice::from_raw_parts_mut(
+            &mut descriptor as *mut _ as *mut u8,
+            std::mem::size_of::<TdvfDescriptor>(),
+        )
+    })
+    .map_err(TdvfError::ReadDescriptor)?;
+
+    if &descriptor.signature != b"TDVF" {
+        return Err(TdvfError::InvalidDescriptorSignature);
+    }
+
+    if descriptor.length as usize
+        != std::mem::size_of::<TdvfDescriptor>()
+            + std::mem::size_of::<TdvfSection>() * descriptor.num_sections as usize
+    {
+        return Err(TdvfError::InvalidDescriptorSize);
+    }
+
+    if descriptor.version != 1 {
+        return Err(TdvfError::InvalidDescriptorVersion);
+    }
+
+    let mut sections = Vec::new();
+    sections.resize_with(descriptor.num_sections as usize, TdvfSection::default);
+
+    // Safe as we read exactly the advertised sections
+    file.read_exact(unsafe {
+        std::slice::from_raw_parts_mut(
+            sections.as_mut_ptr() as *mut u8,
+            descriptor.num_sections as usize * std::mem::size_of::<TdvfSection>(),
+        )
+    })
+    .map_err(TdvfError::ReadDescriptor)?;
+
+    Ok(sections)
+}
+
+#[repr(u16)]
+#[derive(Copy, Clone, Debug)]
+enum HobType {
+    Handoff = 0x1,
+    ResourceDescriptor = 0x3,
+    GuidExtension = 0x4,
+    Unused = 0xfffe,
+    EndOfHobList = 0xffff,
+}
+
+impl Default for HobType {
+    fn default() -> Self {
+        HobType::Unused
+    }
+}
+
+#[repr(C)]
+#[derive(Copy, Clone, Default, Debug)]
+struct HobHeader {
+    r#type: HobType,
+    length: u16,
+    reserved: u32,
+}
+
+#[repr(C)]
+#[derive(Copy, Clone, Default, Debug)]
+struct HobHandoffInfoTable {
+    header: HobHeader,
+    version: u32,
+    boot_mode: u32,
+    efi_memory_top: u64,
+    efi_memory_bottom: u64,
+    efi_free_memory_top: u64,
+    efi_free_memory_bottom: u64,
+    efi_end_of_hob_list: u64,
+}
+
+#[repr(C)]
+#[derive(Copy, Clone, Default, Debug)]
+struct EfiGuid {
+    data1: u32,
+    data2: u16,
+    data3: u16,
+    data4: [u8; 8],
+}
+
+#[repr(C)]
+#[derive(Copy, Clone, Default, Debug)]
+struct HobResourceDescriptor {
+    header: HobHeader,
+    owner: EfiGuid,
+    resource_type: u32,
+    resource_attribute: u32,
+    physical_start: u64,
+    resource_length: u64,
+}
+
+#[repr(C)]
+#[derive(Copy, Clone, Default, Debug)]
+struct HobGuidType {
+    header: HobHeader,
+    name: EfiGuid,
+}
+
+#[repr(C)]
+#[derive(Copy, Clone, Default, Debug)]
+struct TdVmmData {
+    guid_type: HobGuidType,
+    region: TdVmmDataRegion,
+}
+
+// SAFETY: These data structures only contain a series of integers
+unsafe impl ByteValued for TdVmmDataRegion {}
+unsafe impl ByteValued for HobHeader {}
+unsafe impl ByteValued for HobHandoffInfoTable {}
+unsafe impl ByteValued for HobResourceDescriptor {}
+unsafe impl ByteValued for HobGuidType {}
+unsafe impl ByteValued for TdVmmData {}
+
+pub struct TdHob {
+    start_offset: u64,
+    current_offset: u64,
+}
+
+fn align_hob(v: u64) -> u64 {
+    (v + 7) / 8 * 8
+}
+
+impl TdHob {
+    fn update_offset<T>(&mut self) {
+        self.current_offset = align_hob(self.current_offset + std::mem::size_of::<T>() as u64)
+    }
+
+    pub fn start(offset: u64) -> TdHob {
+        // Leave a gap to place the HandoffTable at the start as it can only be filled in later
+        let mut hob = TdHob {
+            start_offset: offset,
+            current_offset: offset,
+        };
+        hob.update_offset::<HobHandoffInfoTable>();
+        hob
+    }
+
+    pub fn finish(&mut self, mem: &GuestMemoryMmap) -> Result<(), TdvfError> {
+        // Write end
+        let end = HobHeader {
+            r#type: HobType::EndOfHobList,
+            length: std::mem::size_of::<HobHeader>() as u16,
+            reserved: 0,
+        };
+        info!("Writing HOB end {:x} {:x?}", self.current_offset, end);
+        mem.write_obj(end, GuestAddress(self.current_offset))
+            .map_err(TdvfError::GuestMemoryWriteHob)?;
+        self.update_offset::<HobHeader>();
+
+        // Write handoff, delayed as it needs end of HOB list
+        let efi_end_of_hob_list = self.current_offset;
+        let handoff = HobHandoffInfoTable {
+            header: HobHeader {
+                r#type: HobType::Handoff,
+                length: std::mem::size_of::<HobHandoffInfoTable>() as u16,
+                reserved: 0,
+            },
+            version: 0x9,
+            boot_mode: 0,
+            efi_memory_top: 0,
+            efi_memory_bottom: 0,
+            efi_free_memory_top: 0,
+            efi_free_memory_bottom: 0,
+            efi_end_of_hob_list,
+        };
+        info!("Writing HOB start {:x} {:x?}", self.start_offset, handoff);
+        mem.write_obj(handoff, GuestAddress(self.start_offset))
+            .map_err(TdvfError::GuestMemoryWriteHob)
+    }
+
+    pub fn add_resource(
+        &mut self,
+        mem: &GuestMemoryMmap,
+        physical_start: u64,
+        resource_length: u64,
+        resource_type: u32,
+        resource_attribute: u32,
+    ) -> Result<(), TdvfError> {
+        let resource_descriptor = HobResourceDescriptor {
+            header: HobHeader {
+                r#type: HobType::ResourceDescriptor,
+                length: std::mem::size_of::<HobResourceDescriptor>() as u16,
+                reserved: 0,
+            },
+            owner: EfiGuid::default(),
+            resource_type,
+            resource_attribute,
+            physical_start,
+            resource_length,
+        };
+        info!(
+            "Writing HOB resource {:x} {:x?}",
+            self.current_offset, resource_descriptor
+        );
+        mem.write_obj(resource_descriptor, GuestAddress(self.current_offset))
+            .map_err(TdvfError::GuestMemoryWriteHob)?;
+        self.update_offset::<HobResourceDescriptor>();
+        Ok(())
+    }
+
+    pub fn add_memory_resource(
+        &mut self,
+        mem: &GuestMemoryMmap,
+        physical_start: u64,
+        resource_length: u64,
+        ram: bool,
+    ) -> Result<(), TdvfError> {
+        self.add_resource(
+            mem,
+            physical_start,
+            resource_length,
+            if ram {
+                0 /* EFI_RESOURCE_SYSTEM_MEMORY */
+            } else {
+                0x5 /*EFI_RESOURCE_MEMORY_RESERVED */
+            },
+            /* TODO:
+             * QEMU currently fills it in like this:
+             * EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_ENCRYPTED | EFI_RESOURCE_ATTRIBUTE_TESTED
+             * which differs from the spec (due to TDVF implementation issue?)
+             */
+            0x04000007,
+        )
+    }
+
+    pub fn add_mmio_resource(
+        &mut self,
+        mem: &GuestMemoryMmap,
+        physical_start: u64,
+        resource_length: u64,
+    ) -> Result<(), TdvfError> {
+        self.add_resource(
+            mem,
+            physical_start,
+            resource_length,
+            0x1, /* EFI_RESOURCE_MEMORY_MAPPED_IO */
+            /*
+             * EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
+             */
+            0x403,
+        )
+    }
+
+    pub fn add_td_vmm_data(
+        &mut self,
+        mem: &GuestMemoryMmap,
+        region: TdVmmDataRegion,
+    ) -> Result<(), TdvfError> {
+        let td_vmm_data = TdVmmData {
+            guid_type: HobGuidType {
+                header: HobHeader {
+                    r#type: HobType::GuidExtension,
+                    length: std::mem::size_of::<TdVmmData>() as u16,
+                    reserved: 0,
+                },
+                // TD_VMM_DATA_GUID CF2643E4-C0D3-46FF-0000-72EE623DDE38
+                name: EfiGuid {
+                    data1: 0xcf26_43e4,
+                    data2: 0xc0d3,
+                    data3: 0x46ff,
+                    data4: [0x00, 0x00, 0x72, 0xee, 0x62, 0x3d, 0xde, 0x38],
+                },
+            },
+            region,
+        };
+        info!(
+            "Writing HOB TD_VMM_DATA {:x} {:x?}",
+            self.current_offset, td_vmm_data
+        );
+        mem.write_obj(td_vmm_data, GuestAddress(self.current_offset))
+            .map_err(TdvfError::GuestMemoryWriteHob)?;
+        self.update_offset::<TdVmmData>();
+        Ok(())
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    #[ignore]
+    fn test_parse_tdvf_sections() {
+        let mut f = std::fs::File::open("tdvf.fd").unwrap();
+        let sections = parse_tdvf_sections(&mut f).unwrap();
+        for section in sections {
+            eprintln!("{:x?}", section)
+        }
+    }
+}

arch_gen/Cargo.lock

@@ -1,6 +0,0 @@
-# This file is automatically @generated by Cargo.
-# It is not intended for manual editing.
-[[package]]
-name = "arch_gen"
-version = "0.1.0"
-

arch_gen/Cargo.toml

@@ -1,7 +0,0 @@
-[package]
-name = "arch_gen"
-version = "0.1.0"
-authors = ["Amazon firecracker team <firecracker-devel@amazon.com>"]
-
-[dependencies]
-

arch_gen/src/lib.rs

@@ -1,5 +0,0 @@
-// Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
-// SPDX-License-Identifier: Apache-2.0
-
-#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
-pub mod x86;

arch_gen/src/x86/mod.rs

@@ -1,25 +0,0 @@
-// Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
-// Use of this source code is governed by a BSD-style license that can be
-// found in the LICENSE-BSD-3-Clause file.
-
-#[allow(non_upper_case_globals)]
-#[allow(non_camel_case_types)]
-#[allow(non_snake_case)]
-#[allow(
-    clippy::unreadable_literal,
-    clippy::redundant_static_lifetimes,
-    clippy::trivially_copy_pass_by_ref,
-    clippy::useless_transmute,
-    clippy::should_implement_trait,
-    clippy::transmute_ptr_to_ptr
-)]
-#[allow(non_camel_case_types)]
-#[allow(non_upper_case_globals)]
-#[allow(clippy::unreadable_literal, clippy::redundant_static_lifetimes)]
-pub mod mpspec;
-#[allow(non_upper_case_globals)]
-#[allow(clippy::unreadable_literal, clippy::redundant_static_lifetimes)]
-pub mod msr_index;

arch_gen/src/x86/mpspec.rs

@@ -1,832 +0,0 @@
-// Copyright 2017 The Chromium OS Authors. All rights reserved.
-// Use of this source code is governed by a BSD-style license that can be
-// found in the LICENSE-BSD-3-Clause file.
-
-/* automatically generated by rust-bindgen */
-
-pub const MPC_SIGNATURE: &'static [u8; 5usize] = b"PCMP\x00";
-pub const MP_PROCESSOR: ::std::os::raw::c_uint = 0;
-pub const MP_BUS: ::std::os::raw::c_uint = 1;
-pub const MP_IOAPIC: ::std::os::raw::c_uint = 2;
-pub const MP_INTSRC: ::std::os::raw::c_uint = 3;
-pub const MP_LINTSRC: ::std::os::raw::c_uint = 4;
-pub const MP_TRANSLATION: ::std::os::raw::c_uint = 192;
-pub const CPU_ENABLED: ::std::os::raw::c_uint = 1;
-pub const CPU_BOOTPROCESSOR: ::std::os::raw::c_uint = 2;
-pub const CPU_STEPPING_MASK: ::std::os::raw::c_uint = 15;
-pub const CPU_MODEL_MASK: ::std::os::raw::c_uint = 240;
-pub const CPU_FAMILY_MASK: ::std::os::raw::c_uint = 3840;
-pub const BUSTYPE_EISA: &'static [u8; 5usize] = b"EISA\x00";
-pub const BUSTYPE_ISA: &'static [u8; 4usize] = b"ISA\x00";
-pub const BUSTYPE_INTERN: &'static [u8; 7usize] = b"INTERN\x00";
-pub const BUSTYPE_MCA: &'static [u8; 4usize] = b"MCA\x00";
-pub const BUSTYPE_VL: &'static [u8; 3usize] = b"VL\x00";
-pub const BUSTYPE_PCI: &'static [u8; 4usize] = b"PCI\x00";
-pub const BUSTYPE_PCMCIA: &'static [u8; 7usize] = b"PCMCIA\x00";
-pub const BUSTYPE_CBUS: &'static [u8; 5usize] = b"CBUS\x00";
-pub const BUSTYPE_CBUSII: &'static [u8; 7usize] = b"CBUSII\x00";
-pub const BUSTYPE_FUTURE: &'static [u8; 7usize] = b"FUTURE\x00";
-pub const BUSTYPE_MBI: &'static [u8; 4usize] = b"MBI\x00";
-pub const BUSTYPE_MBII: &'static [u8; 5usize] = b"MBII\x00";
-pub const BUSTYPE_MPI: &'static [u8; 4usize] = b"MPI\x00";
-pub const BUSTYPE_MPSA: &'static [u8; 5usize] = b"MPSA\x00";
-pub const BUSTYPE_NUBUS: &'static [u8; 6usize] = b"NUBUS\x00";
-pub const BUSTYPE_TC: &'static [u8; 3usize] = b"TC\x00";
-pub const BUSTYPE_VME: &'static [u8; 4usize] = b"VME\x00";
-pub const BUSTYPE_XPRESS: &'static [u8; 7usize] = b"XPRESS\x00";
-pub const MPC_APIC_USABLE: ::std::os::raw::c_uint = 1;
-pub const MP_IRQDIR_DEFAULT: ::std::os::raw::c_uint = 0;
-pub const MP_IRQDIR_HIGH: ::std::os::raw::c_uint = 1;
-pub const MP_IRQDIR_LOW: ::std::os::raw::c_uint = 3;
-pub const MP_APIC_ALL: ::std::os::raw::c_uint = 255;
-pub const MPC_OEM_SIGNATURE: &'static [u8; 5usize] = b"_OEM\x00";
-#[repr(C)]
-#[derive(Debug, Default, Copy)]
-pub struct mpf_intel {
-    pub signature: [::std::os::raw::c_char; 4usize],
-    pub physptr: ::std::os::raw::c_uint,
-    pub length: ::std::os::raw::c_uchar,
-    pub specification: ::std::os::raw::c_uchar,
-    pub checksum: ::std::os::raw::c_uchar,
-    pub feature1: ::std::os::raw::c_uchar,
-    pub feature2: ::std::os::raw::c_uchar,
-    pub feature3: ::std::os::raw::c_uchar,
-    pub feature4: ::std::os::raw::c_uchar,
-    pub feature5: ::std::os::raw::c_uchar,
-}
-#[test]
-fn bindgen_test_layout_mpf_intel() {
-    assert_eq!(
-        ::std::mem::size_of::<mpf_intel>(),
-        16usize,
-        concat!("Size of: ", stringify!(mpf_intel))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<mpf_intel>(),
-        4usize,
-        concat!("Alignment of ", stringify!(mpf_intel))
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpf_intel)).signature as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpf_intel),
-            "::",
-            stringify!(signature)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpf_intel)).physptr as *const _ as usize },
-        4usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpf_intel),
-            "::",
-            stringify!(physptr)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpf_intel)).length as *const _ as usize },
-        8usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpf_intel),
-            "::",
-            stringify!(length)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpf_intel)).specification as *const _ as usize },
-        9usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpf_intel),
-            "::",
-            stringify!(specification)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpf_intel)).checksum as *const _ as usize },
-        10usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpf_intel),
-            "::",
-            stringify!(checksum)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpf_intel)).feature1 as *const _ as usize },
-        11usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpf_intel),
-            "::",
-            stringify!(feature1)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpf_intel)).feature2 as *const _ as usize },
-        12usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpf_intel),
-            "::",
-            stringify!(feature2)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpf_intel)).feature3 as *const _ as usize },
-        13usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpf_intel),
-            "::",
-            stringify!(feature3)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpf_intel)).feature4 as *const _ as usize },
-        14usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpf_intel),
-            "::",
-            stringify!(feature4)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpf_intel)).feature5 as *const _ as usize },
-        15usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpf_intel),
-            "::",
-            stringify!(feature5)
-        )
-    );
-}
-impl Clone for mpf_intel {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
-#[repr(C)]
-#[derive(Debug, Default, Copy)]
-pub struct mpc_table {
-    pub signature: [::std::os::raw::c_char; 4usize],
-    pub length: ::std::os::raw::c_ushort,
-    pub spec: ::std::os::raw::c_char,
-    pub checksum: ::std::os::raw::c_char,
-    pub oem: [::std::os::raw::c_char; 8usize],
-    pub productid: [::std::os::raw::c_char; 12usize],
-    pub oemptr: ::std::os::raw::c_uint,
-    pub oemsize: ::std::os::raw::c_ushort,
-    pub oemcount: ::std::os::raw::c_ushort,
-    pub lapic: ::std::os::raw::c_uint,
-    pub reserved: ::std::os::raw::c_uint,
-}
-#[test]
-fn bindgen_test_layout_mpc_table() {
-    assert_eq!(
-        ::std::mem::size_of::<mpc_table>(),
-        44usize,
-        concat!("Size of: ", stringify!(mpc_table))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<mpc_table>(),
-        4usize,
-        concat!("Alignment of ", stringify!(mpc_table))
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_table)).signature as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_table),
-            "::",
-            stringify!(signature)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_table)).length as *const _ as usize },
-        4usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_table),
-            "::",
-            stringify!(length)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_table)).spec as *const _ as usize },
-        6usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_table),
-            "::",
-            stringify!(spec)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_table)).checksum as *const _ as usize },
-        7usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_table),
-            "::",
-            stringify!(checksum)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_table)).oem as *const _ as usize },
-        8usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_table),
-            "::",
-            stringify!(oem)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_table)).productid as *const _ as usize },
-        16usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_table),
-            "::",
-            stringify!(productid)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_table)).oemptr as *const _ as usize },
-        28usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_table),
-            "::",
-            stringify!(oemptr)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_table)).oemsize as *const _ as usize },
-        32usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_table),
-            "::",
-            stringify!(oemsize)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_table)).oemcount as *const _ as usize },
-        34usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_table),
-            "::",
-            stringify!(oemcount)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_table)).lapic as *const _ as usize },
-        36usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_table),
-            "::",
-            stringify!(lapic)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_table)).reserved as *const _ as usize },
-        40usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_table),
-            "::",
-            stringify!(reserved)
-        )
-    );
-}
-impl Clone for mpc_table {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
-#[repr(C)]
-#[derive(Debug, Default, Copy)]
-pub struct mpc_cpu {
-    pub type_: ::std::os::raw::c_uchar,
-    pub apicid: ::std::os::raw::c_uchar,
-    pub apicver: ::std::os::raw::c_uchar,
-    pub cpuflag: ::std::os::raw::c_uchar,
-    pub cpufeature: ::std::os::raw::c_uint,
-    pub featureflag: ::std::os::raw::c_uint,
-    pub reserved: [::std::os::raw::c_uint; 2usize],
-}
-#[test]
-fn bindgen_test_layout_mpc_cpu() {
-    assert_eq!(
-        ::std::mem::size_of::<mpc_cpu>(),
-        20usize,
-        concat!("Size of: ", stringify!(mpc_cpu))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<mpc_cpu>(),
-        4usize,
-        concat!("Alignment of ", stringify!(mpc_cpu))
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_cpu)).type_ as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_cpu),
-            "::",
-            stringify!(type_)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_cpu)).apicid as *const _ as usize },
-        1usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_cpu),
-            "::",
-            stringify!(apicid)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_cpu)).apicver as *const _ as usize },
-        2usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_cpu),
-            "::",
-            stringify!(apicver)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_cpu)).cpuflag as *const _ as usize },
-        3usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_cpu),
-            "::",
-            stringify!(cpuflag)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_cpu)).cpufeature as *const _ as usize },
-        4usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_cpu),
-            "::",
-            stringify!(cpufeature)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_cpu)).featureflag as *const _ as usize },
-        8usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_cpu),
-            "::",
-            stringify!(featureflag)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_cpu)).reserved as *const _ as usize },
-        12usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_cpu),
-            "::",
-            stringify!(reserved)
-        )
-    );
-}
-impl Clone for mpc_cpu {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
-#[repr(C)]
-#[derive(Debug, Default, Copy)]
-pub struct mpc_bus {
-    pub type_: ::std::os::raw::c_uchar,
-    pub busid: ::std::os::raw::c_uchar,
-    pub bustype: [::std::os::raw::c_uchar; 6usize],
-}
-#[test]
-fn bindgen_test_layout_mpc_bus() {
-    assert_eq!(
-        ::std::mem::size_of::<mpc_bus>(),
-        8usize,
-        concat!("Size of: ", stringify!(mpc_bus))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<mpc_bus>(),
-        1usize,
-        concat!("Alignment of ", stringify!(mpc_bus))
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_bus)).type_ as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_bus),
-            "::",
-            stringify!(type_)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_bus)).busid as *const _ as usize },
-        1usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_bus),
-            "::",
-            stringify!(busid)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_bus)).bustype as *const _ as usize },
-        2usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_bus),
-            "::",
-            stringify!(bustype)
-        )
-    );
-}
-impl Clone for mpc_bus {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
-#[repr(C)]
-#[derive(Debug, Default, Copy)]
-pub struct mpc_ioapic {
-    pub type_: ::std::os::raw::c_uchar,
-    pub apicid: ::std::os::raw::c_uchar,
-    pub apicver: ::std::os::raw::c_uchar,
-    pub flags: ::std::os::raw::c_uchar,
-    pub apicaddr: ::std::os::raw::c_uint,
-}
-#[test]
-fn bindgen_test_layout_mpc_ioapic() {
-    assert_eq!(
-        ::std::mem::size_of::<mpc_ioapic>(),
-        8usize,
-        concat!("Size of: ", stringify!(mpc_ioapic))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<mpc_ioapic>(),
-        4usize,
-        concat!("Alignment of ", stringify!(mpc_ioapic))
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_ioapic)).type_ as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_ioapic),
-            "::",
-            stringify!(type_)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_ioapic)).apicid as *const _ as usize },
-        1usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_ioapic),
-            "::",
-            stringify!(apicid)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_ioapic)).apicver as *const _ as usize },
-        2usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_ioapic),
-            "::",
-            stringify!(apicver)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_ioapic)).flags as *const _ as usize },
-        3usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_ioapic),
-            "::",
-            stringify!(flags)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_ioapic)).apicaddr as *const _ as usize },
-        4usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_ioapic),
-            "::",
-            stringify!(apicaddr)
-        )
-    );
-}
-impl Clone for mpc_ioapic {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
-#[repr(C)]
-#[derive(Debug, Default, Copy)]
-pub struct mpc_intsrc {
-    pub type_: ::std::os::raw::c_uchar,
-    pub irqtype: ::std::os::raw::c_uchar,
-    pub irqflag: ::std::os::raw::c_ushort,
-    pub srcbus: ::std::os::raw::c_uchar,
-    pub srcbusirq: ::std::os::raw::c_uchar,
-    pub dstapic: ::std::os::raw::c_uchar,
-    pub dstirq: ::std::os::raw::c_uchar,
-}
-#[test]
-fn bindgen_test_layout_mpc_intsrc() {
-    assert_eq!(
-        ::std::mem::size_of::<mpc_intsrc>(),
-        8usize,
-        concat!("Size of: ", stringify!(mpc_intsrc))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<mpc_intsrc>(),
-        2usize,
-        concat!("Alignment of ", stringify!(mpc_intsrc))
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_intsrc)).type_ as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_intsrc),
-            "::",
-            stringify!(type_)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_intsrc)).irqtype as *const _ as usize },
-        1usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_intsrc),
-            "::",
-            stringify!(irqtype)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_intsrc)).irqflag as *const _ as usize },
-        2usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_intsrc),
-            "::",
-            stringify!(irqflag)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_intsrc)).srcbus as *const _ as usize },
-        4usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_intsrc),
-            "::",
-            stringify!(srcbus)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_intsrc)).srcbusirq as *const _ as usize },
-        5usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_intsrc),
-            "::",
-            stringify!(srcbusirq)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_intsrc)).dstapic as *const _ as usize },
-        6usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_intsrc),
-            "::",
-            stringify!(dstapic)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_intsrc)).dstirq as *const _ as usize },
-        7usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_intsrc),
-            "::",
-            stringify!(dstirq)
-        )
-    );
-}
-impl Clone for mpc_intsrc {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
-pub const mp_irq_source_types_mp_INT: mp_irq_source_types = 0;
-pub const mp_irq_source_types_mp_NMI: mp_irq_source_types = 1;
-pub const mp_irq_source_types_mp_SMI: mp_irq_source_types = 2;
-pub const mp_irq_source_types_mp_ExtINT: mp_irq_source_types = 3;
-pub type mp_irq_source_types = ::std::os::raw::c_uint;
-#[repr(C)]
-#[derive(Debug, Default, Copy)]
-pub struct mpc_lintsrc {
-    pub type_: ::std::os::raw::c_uchar,
-    pub irqtype: ::std::os::raw::c_uchar,
-    pub irqflag: ::std::os::raw::c_ushort,
-    pub srcbusid: ::std::os::raw::c_uchar,
-    pub srcbusirq: ::std::os::raw::c_uchar,
-    pub destapic: ::std::os::raw::c_uchar,
-    pub destapiclint: ::std::os::raw::c_uchar,
-}
-#[test]
-fn bindgen_test_layout_mpc_lintsrc() {
-    assert_eq!(
-        ::std::mem::size_of::<mpc_lintsrc>(),
-        8usize,
-        concat!("Size of: ", stringify!(mpc_lintsrc))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<mpc_lintsrc>(),
-        2usize,
-        concat!("Alignment of ", stringify!(mpc_lintsrc))
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_lintsrc)).type_ as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_lintsrc),
-            "::",
-            stringify!(type_)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_lintsrc)).irqtype as *const _ as usize },
-        1usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_lintsrc),
-            "::",
-            stringify!(irqtype)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_lintsrc)).irqflag as *const _ as usize },
-        2usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_lintsrc),
-            "::",
-            stringify!(irqflag)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_lintsrc)).srcbusid as *const _ as usize },
-        4usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_lintsrc),
-            "::",
-            stringify!(srcbusid)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_lintsrc)).srcbusirq as *const _ as usize },
-        5usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_lintsrc),
-            "::",
-            stringify!(srcbusirq)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_lintsrc)).destapic as *const _ as usize },
-        6usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_lintsrc),
-            "::",
-            stringify!(destapic)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_lintsrc)).destapiclint as *const _ as usize },
-        7usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_lintsrc),
-            "::",
-            stringify!(destapiclint)
-        )
-    );
-}
-impl Clone for mpc_lintsrc {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
-#[repr(C)]
-#[derive(Debug, Default, Copy)]
-pub struct mpc_oemtable {
-    pub signature: [::std::os::raw::c_char; 4usize],
-    pub length: ::std::os::raw::c_ushort,
-    pub rev: ::std::os::raw::c_char,
-    pub checksum: ::std::os::raw::c_char,
-    pub mpc: [::std::os::raw::c_char; 8usize],
-}
-#[test]
-fn bindgen_test_layout_mpc_oemtable() {
-    assert_eq!(
-        ::std::mem::size_of::<mpc_oemtable>(),
-        16usize,
-        concat!("Size of: ", stringify!(mpc_oemtable))
-    );
-    assert_eq!(
-        ::std::mem::align_of::<mpc_oemtable>(),
-        2usize,
-        concat!("Alignment of ", stringify!(mpc_oemtable))
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_oemtable)).signature as *const _ as usize },
-        0usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_oemtable),
-            "::",
-            stringify!(signature)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_oemtable)).length as *const _ as usize },
-        4usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_oemtable),
-            "::",
-            stringify!(length)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_oemtable)).rev as *const _ as usize },
-        6usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_oemtable),
-            "::",
-            stringify!(rev)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_oemtable)).checksum as *const _ as usize },
-        7usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_oemtable),
-            "::",
-            stringify!(checksum)
-        )
-    );
-    assert_eq!(
-        unsafe { &(*(0 as *const mpc_oemtable)).mpc as *const _ as usize },
-        8usize,
-        concat!(
-            "Alignment of field: ",
-            stringify!(mpc_oemtable),
-            "::",
-            stringify!(mpc)
-        )
-    );
-}
-impl Clone for mpc_oemtable {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
-pub const mp_bustype_MP_BUS_ISA: mp_bustype = 1;
-pub const mp_bustype_MP_BUS_EISA: mp_bustype = 2;
-pub const mp_bustype_MP_BUS_PCI: mp_bustype = 3;
-pub type mp_bustype = ::std::os::raw::c_uint;

block_util/Cargo.toml

@@ -0,0 +1,25 @@
+[package]
+name = "block_util"
+version = "0.1.0"
+authors = ["The Cloud Hypervisor Authors"]
+edition = "2018"
+
+[features]
+default = []
+io_uring = []
+
+[dependencies]
+io-uring = "0.5.2"
+libc = "0.2.108"
+log = "0.4.14"
+qcow = { path = "../qcow" }
+thiserror = "1.0.30"
+versionize = "0.1.6"
+versionize_derive = "0.1.4"
+vhdx = { path = "../vhdx" }
+virtio-bindings = { version = "0.1.0", features = ["virtio-v5_0_0"] }
+virtio-queue = { path = "../virtio-queue" }
+vm-memory = { version = "0.6.0", features = ["backend-mmap", "backend-atomic", "backend-bitmap"] }
+vm-virtio = { path = "../vm-virtio" }
+vmm-sys-util = "0.9.0"
+

block_util/src/async_io.rs

@@ -0,0 +1,56 @@
+// Copyright © 2021 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
+
+use thiserror::Error;
+use vmm_sys_util::eventfd::EventFd;
+
+#[derive(Error, Debug)]
+pub enum DiskFileError {
+    /// Failed getting disk file size.
+    #[error("Failed getting disk file size: {0}")]
+    Size(#[source] std::io::Error),
+    /// Failed creating a new AsyncIo.
+    #[error("Failed creating a new AsyncIo: {0}")]
+    NewAsyncIo(#[source] std::io::Error),
+}
+
+pub type DiskFileResult<T> = std::result::Result<T, DiskFileError>;
+
+pub trait DiskFile: Send + Sync {
+    fn size(&mut self) -> DiskFileResult<u64>;
+    fn new_async_io(&self, ring_depth: u32) -> DiskFileResult<Box<dyn AsyncIo>>;
+}
+
+#[derive(Error, Debug)]
+pub enum AsyncIoError {
+    /// Failed vectored reading from file.
+    #[error("Failed vectored reading from file: {0}")]
+    ReadVectored(#[source] std::io::Error),
+    /// Failed vectored writing to file.
+    #[error("Failed vectored writing to file: {0}")]
+    WriteVectored(#[source] std::io::Error),
+    /// Failed synchronizing file.
+    #[error("Failed synchronizing file: {0}")]
+    Fsync(#[source] std::io::Error),
+}
+
+pub type AsyncIoResult<T> = std::result::Result<T, AsyncIoError>;
+
+pub trait AsyncIo: Send + Sync {
+    fn notifier(&self) -> &EventFd;
+    fn read_vectored(
+        &mut self,
+        offset: libc::off_t,
+        iovecs: Vec<libc::iovec>,
+        user_data: u64,
+    ) -> AsyncIoResult<()>;
+    fn write_vectored(
+        &mut self,
+        offset: libc::off_t,
+        iovecs: Vec<libc::iovec>,
+        user_data: u64,
+    ) -> AsyncIoResult<()>;
+    fn fsync(&mut self, user_data: Option<u64>) -> AsyncIoResult<()>;
+    fn complete(&mut self) -> Vec<(u64, i32)>;
+}

block_util/src/fixed_vhd_async.rs

@@ -0,0 +1,110 @@
+// Copyright © 2021 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0
+
+use crate::async_io::{
+    AsyncIo, AsyncIoError, AsyncIoResult, DiskFile, DiskFileError, DiskFileResult,
+};
+use crate::raw_async::RawFileAsync;
+use crate::vhd::VhdFooter;
+use std::fs::File;
+use std::os::unix::io::{AsRawFd, RawFd};
+use vmm_sys_util::eventfd::EventFd;
+
+pub struct FixedVhdDiskAsync {
+    file: File,
+    size: u64,
+}
+
+impl FixedVhdDiskAsync {
+    pub fn new(mut file: File) -> std::io::Result<Self> {
+        let footer = VhdFooter::new(&mut file)?;
+
+        Ok(FixedVhdDiskAsync {
+            file,
+            size: footer.current_size(),
+        })
+    }
+}
+
+impl DiskFile for FixedVhdDiskAsync {
+    fn size(&mut self) -> DiskFileResult<u64> {
+        Ok(self.size)
+    }
+
+    fn new_async_io(&self, ring_depth: u32) -> DiskFileResult<Box<dyn AsyncIo>> {
+        Ok(Box::new(
+            FixedVhdAsync::new(self.file.as_raw_fd(), ring_depth, self.size)
+                .map_err(DiskFileError::NewAsyncIo)?,
+        ) as Box<dyn AsyncIo>)
+    }
+}
+
+pub struct FixedVhdAsync {
+    raw_file_async: RawFileAsync,
+    size: u64,
+}
+
+impl FixedVhdAsync {
+    pub fn new(fd: RawFd, ring_depth: u32, size: u64) -> std::io::Result<Self> {
+        let raw_file_async = RawFileAsync::new(fd, ring_depth)?;
+
+        Ok(FixedVhdAsync {
+            raw_file_async,
+            size,
+        })
+    }
+}
+
+impl AsyncIo for FixedVhdAsync {
+    fn notifier(&self) -> &EventFd {
+        self.raw_file_async.notifier()
+    }
+
+    fn read_vectored(
+        &mut self,
+        offset: libc::off_t,
+        iovecs: Vec<libc::iovec>,
+        user_data: u64,
+    ) -> AsyncIoResult<()> {
+        if offset as u64 >= self.size {
+            return Err(AsyncIoError::ReadVectored(std::io::Error::new(
+                std::io::ErrorKind::InvalidData,
+                format!(
+                    "Invalid offset {}, can't be larger than file size {}",
+                    offset, self.size
+                ),
+            )));
+        }
+
+        self.raw_file_async.read_vectored(offset, iovecs, user_data)
+    }
+
+    fn write_vectored(
+        &mut self,
+        offset: libc::off_t,
+        iovecs: Vec<libc::iovec>,
+        user_data: u64,
+    ) -> AsyncIoResult<()> {
+        if offset as u64 >= self.size {
+            return Err(AsyncIoError::WriteVectored(std::io::Error::new(
+                std::io::ErrorKind::InvalidData,
+                format!(
+                    "Invalid offset {}, can't be larger than file size {}",
+                    offset, self.size
+                ),
+            )));
+        }
+
+        self.raw_file_async
+            .write_vectored(offset, iovecs, user_data)
+    }
+
+    fn fsync(&mut self, user_data: Option<u64>) -> AsyncIoResult<()> {
+        self.raw_file_async.fsync(user_data)
+    }
+
+    fn complete(&mut self) -> Vec<(u64, i32)> {
+        self.raw_file_async.complete()
+    }
+}

block_util/src/fixed_vhd_sync.rs

@@ -0,0 +1,107 @@
+// Copyright © 2021 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0
+
+use crate::async_io::{
+    AsyncIo, AsyncIoError, AsyncIoResult, DiskFile, DiskFileError, DiskFileResult,
+};
+use crate::raw_sync::RawFileSync;
+use crate::vhd::VhdFooter;
+use std::fs::File;
+use std::os::unix::io::{AsRawFd, RawFd};
+use vmm_sys_util::eventfd::EventFd;
+
+pub struct FixedVhdDiskSync {
+    file: File,
+    size: u64,
+}
+
+impl FixedVhdDiskSync {
+    pub fn new(mut file: File) -> std::io::Result<Self> {
+        let footer = VhdFooter::new(&mut file)?;
+
+        Ok(FixedVhdDiskSync {
+            file,
+            size: footer.current_size(),
+        })
+    }
+}
+
+impl DiskFile for FixedVhdDiskSync {
+    fn size(&mut self) -> DiskFileResult<u64> {
+        Ok(self.size)
+    }
+
+    fn new_async_io(&self, _ring_depth: u32) -> DiskFileResult<Box<dyn AsyncIo>> {
+        Ok(Box::new(
+            FixedVhdSync::new(self.file.as_raw_fd(), self.size)
+                .map_err(DiskFileError::NewAsyncIo)?,
+        ) as Box<dyn AsyncIo>)
+    }
+}
+
+pub struct FixedVhdSync {
+    raw_file_sync: RawFileSync,
+    size: u64,
+}
+
+impl FixedVhdSync {
+    pub fn new(fd: RawFd, size: u64) -> std::io::Result<Self> {
+        Ok(FixedVhdSync {
+            raw_file_sync: RawFileSync::new(fd),
+            size,
+        })
+    }
+}
+
+impl AsyncIo for FixedVhdSync {
+    fn notifier(&self) -> &EventFd {
+        self.raw_file_sync.notifier()
+    }
+
+    fn read_vectored(
+        &mut self,
+        offset: libc::off_t,
+        iovecs: Vec<libc::iovec>,
+        user_data: u64,
+    ) -> AsyncIoResult<()> {
+        if offset as u64 >= self.size {
+            return Err(AsyncIoError::ReadVectored(std::io::Error::new(
+                std::io::ErrorKind::InvalidData,
+                format!(
+                    "Invalid offset {}, can't be larger than file size {}",
+                    offset, self.size
+                ),
+            )));
+        }
+
+        self.raw_file_sync.read_vectored(offset, iovecs, user_data)
+    }
+
+    fn write_vectored(
+        &mut self,
+        offset: libc::off_t,
+        iovecs: Vec<libc::iovec>,
+        user_data: u64,
+    ) -> AsyncIoResult<()> {
+        if offset as u64 >= self.size {
+            return Err(AsyncIoError::WriteVectored(std::io::Error::new(
+                std::io::ErrorKind::InvalidData,
+                format!(
+                    "Invalid offset {}, can't be larger than file size {}",
+                    offset, self.size
+                ),
+            )));
+        }
+
+        self.raw_file_sync.write_vectored(offset, iovecs, user_data)
+    }
+
+    fn fsync(&mut self, user_data: Option<u64>) -> AsyncIoResult<()> {
+        self.raw_file_sync.fsync(user_data)
+    }
+
+    fn complete(&mut self) -> Vec<(u64, i32)> {
+        self.raw_file_sync.complete()
+    }
+}

block_util/src/lib.rs

@@ -0,0 +1,623 @@
+// Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+//
+// Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style license that can be
+// found in the LICENSE-BSD-3-Clause file.
+//
+// Copyright © 2020 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
+
+#[macro_use]
+extern crate log;
+
+pub mod async_io;
+pub mod fixed_vhd_async;
+pub mod fixed_vhd_sync;
+pub mod qcow_sync;
+pub mod raw_async;
+pub mod raw_sync;
+pub mod vhd;
+pub mod vhdx_sync;
+
+use crate::async_io::{AsyncIo, AsyncIoError, AsyncIoResult, DiskFileError, DiskFileResult};
+#[cfg(feature = "io_uring")]
+use io_uring::{opcode, IoUring, Probe};
+use std::cmp;
+use std::convert::TryInto;
+use std::fs::File;
+use std::io::{self, IoSlice, IoSliceMut, Read, Seek, SeekFrom, Write};
+use std::os::linux::fs::MetadataExt;
+use std::path::Path;
+use std::result;
+use std::sync::{Arc, Mutex};
+use versionize::{VersionMap, Versionize, VersionizeResult};
+use versionize_derive::Versionize;
+use virtio_bindings::bindings::virtio_blk::*;
+use virtio_queue::DescriptorChain;
+use vm_memory::{
+    bitmap::AtomicBitmap, bitmap::Bitmap, ByteValued, Bytes, GuestAddress, GuestMemory,
+    GuestMemoryAtomic, GuestMemoryError,
+};
+use vmm_sys_util::eventfd::EventFd;
+
+type GuestMemoryMmap = vm_memory::GuestMemoryMmap<AtomicBitmap>;
+
+const SECTOR_SHIFT: u8 = 9;
+pub const SECTOR_SIZE: u64 = 0x01 << SECTOR_SHIFT;
+
+#[derive(Debug)]
+pub enum Error {
+    /// Guest gave us bad memory addresses.
+    GuestMemory(GuestMemoryError),
+    /// Guest gave us offsets that would have overflowed a usize.
+    CheckedOffset(GuestAddress, usize),
+    /// Guest gave us a write only descriptor that protocol says to read from.
+    UnexpectedWriteOnlyDescriptor,
+    /// Guest gave us a read only descriptor that protocol says to write to.
+    UnexpectedReadOnlyDescriptor,
+    /// Guest gave us too few descriptors in a descriptor chain.
+    DescriptorChainTooShort,
+    /// Guest gave us a descriptor that was too short to use.
+    DescriptorLengthTooSmall,
+    /// Getting a block's metadata fails for any reason.
+    GetFileMetadata,
+    /// The requested operation would cause a seek beyond disk end.
+    InvalidOffset,
+    /// The requested operation does not support multiple descriptors.
+    TooManyDescriptors,
+}
+
+fn build_device_id(disk_path: &Path) -> result::Result<String, Error> {
+    let blk_metadata = match disk_path.metadata() {
+        Err(_) => return Err(Error::GetFileMetadata),
+        Ok(m) => m,
+    };
+    // This is how kvmtool does it.
+    let device_id = format!(
+        "{}{}{}",
+        blk_metadata.st_dev(),
+        blk_metadata.st_rdev(),
+        blk_metadata.st_ino()
+    );
+    Ok(device_id)
+}
+
+pub fn build_disk_image_id(disk_path: &Path) -> Vec<u8> {
+    let mut default_disk_image_id = vec![0; VIRTIO_BLK_ID_BYTES as usize];
+    match build_device_id(disk_path) {
+        Err(_) => {
+            warn!("Could not generate device id. We'll use a default.");
+        }
+        Ok(m) => {
+            // The kernel only knows to read a maximum of VIRTIO_BLK_ID_BYTES.
+            // This will also zero out any leftover bytes.
+            let disk_id = m.as_bytes();
+            let bytes_to_copy = cmp::min(disk_id.len(), VIRTIO_BLK_ID_BYTES as usize);
+            default_disk_image_id[..bytes_to_copy].clone_from_slice(&disk_id[..bytes_to_copy])
+        }
+    }
+    default_disk_image_id
+}
+
+#[derive(Debug)]
+pub enum ExecuteError {
+    BadRequest(Error),
+    Flush(io::Error),
+    Read(GuestMemoryError),
+    Seek(io::Error),
+    Write(GuestMemoryError),
+    Unsupported(u32),
+    SubmitIoUring(io::Error),
+    GetHostAddress(GuestMemoryError),
+    AsyncRead(AsyncIoError),
+    AsyncWrite(AsyncIoError),
+    AsyncFlush(AsyncIoError),
+}
+
+impl ExecuteError {
+    pub fn status(&self) -> u32 {
+        match *self {
+            ExecuteError::BadRequest(_) => VIRTIO_BLK_S_IOERR,
+            ExecuteError::Flush(_) => VIRTIO_BLK_S_IOERR,
+            ExecuteError::Read(_) => VIRTIO_BLK_S_IOERR,
+            ExecuteError::Seek(_) => VIRTIO_BLK_S_IOERR,
+            ExecuteError::Write(_) => VIRTIO_BLK_S_IOERR,
+            ExecuteError::Unsupported(_) => VIRTIO_BLK_S_UNSUPP,
+            ExecuteError::SubmitIoUring(_) => VIRTIO_BLK_S_IOERR,
+            ExecuteError::GetHostAddress(_) => VIRTIO_BLK_S_IOERR,
+            ExecuteError::AsyncRead(_) => VIRTIO_BLK_S_IOERR,
+            ExecuteError::AsyncWrite(_) => VIRTIO_BLK_S_IOERR,
+            ExecuteError::AsyncFlush(_) => VIRTIO_BLK_S_IOERR,
+        }
+    }
+}
+
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RequestType {
+    In,
+    Out,
+    Flush,
+    GetDeviceId,
+    Unsupported(u32),
+}
+
+pub fn request_type(
+    mem: &GuestMemoryMmap,
+    desc_addr: GuestAddress,
+) -> result::Result<RequestType, Error> {
+    let type_ = mem.read_obj(desc_addr).map_err(Error::GuestMemory)?;
+    match type_ {
+        VIRTIO_BLK_T_IN => Ok(RequestType::In),
+        VIRTIO_BLK_T_OUT => Ok(RequestType::Out),
+        VIRTIO_BLK_T_FLUSH => Ok(RequestType::Flush),
+        VIRTIO_BLK_T_GET_ID => Ok(RequestType::GetDeviceId),
+        t => Ok(RequestType::Unsupported(t)),
+    }
+}
+
+fn sector(mem: &GuestMemoryMmap, desc_addr: GuestAddress) -> result::Result<u64, Error> {
+    const SECTOR_OFFSET: usize = 8;
+    let addr = match mem.checked_offset(desc_addr, SECTOR_OFFSET) {
+        Some(v) => v,
+        None => return Err(Error::CheckedOffset(desc_addr, SECTOR_OFFSET)),
+    };
+
+    mem.read_obj(addr).map_err(Error::GuestMemory)
+}
+
+#[derive(Debug)]
+pub struct Request {
+    pub request_type: RequestType,
+    pub sector: u64,
+    pub data_descriptors: Vec<(GuestAddress, u32)>,
+    pub status_addr: GuestAddress,
+    pub writeback: bool,
+}
+
+impl Request {
+    pub fn parse(
+        desc_chain: &mut DescriptorChain<GuestMemoryAtomic<GuestMemoryMmap>>,
+    ) -> result::Result<Request, Error> {
+        let hdr_desc = desc_chain
+            .next()
+            .ok_or(Error::DescriptorChainTooShort)
+            .map_err(|e| {
+                error!("Missing head descriptor");
+                e
+            })?;
+
+        // The head contains the request type which MUST be readable.
+        if hdr_desc.is_write_only() {
+            return Err(Error::UnexpectedWriteOnlyDescriptor);
+        }
+
+        let mut req = Request {
+            request_type: request_type(desc_chain.memory(), hdr_desc.addr())?,
+            sector: sector(desc_chain.memory(), hdr_desc.addr())?,
+            data_descriptors: Vec::new(),
+            status_addr: GuestAddress(0),
+            writeback: true,
+        };
+
+        let status_desc;
+        let mut desc = desc_chain
+            .next()
+            .ok_or(Error::DescriptorChainTooShort)
+            .map_err(|e| {
+                error!("Only head descriptor present: request = {:?}", req);
+                e
+            })?;
+
+        if !desc.has_next() {
+            status_desc = desc;
+            // Only flush requests are allowed to skip the data descriptor.
+            if req.request_type != RequestType::Flush {
+                error!("Need a data descriptor: request = {:?}", req);
+                return Err(Error::DescriptorChainTooShort);
+            }
+        } else {
+            while desc.has_next() {
+                if desc.is_write_only() && req.request_type == RequestType::Out {
+                    return Err(Error::UnexpectedWriteOnlyDescriptor);
+                }
+                if !desc.is_write_only() && req.request_type == RequestType::In {
+                    return Err(Error::UnexpectedReadOnlyDescriptor);
+                }
+                if !desc.is_write_only() && req.request_type == RequestType::GetDeviceId {
+                    return Err(Error::UnexpectedReadOnlyDescriptor);
+                }
+                req.data_descriptors.push((desc.addr(), desc.len()));
+                desc = desc_chain
+                    .next()
+                    .ok_or(Error::DescriptorChainTooShort)
+                    .map_err(|e| {
+                        error!("DescriptorChain corrupted: request = {:?}", req);
+                        e
+                    })?;
+            }
+            status_desc = desc;
+        }
+
+        // The status MUST always be writable.
+        if !status_desc.is_write_only() {
+            return Err(Error::UnexpectedReadOnlyDescriptor);
+        }
+
+        if status_desc.len() < 1 {
+            return Err(Error::DescriptorLengthTooSmall);
+        }
+
+        req.status_addr = status_desc.addr();
+
+        Ok(req)
+    }
+
+    #[allow(clippy::ptr_arg)]
+    pub fn execute<T: Seek + Read + Write>(
+        &self,
+        disk: &mut T,
+        disk_nsectors: u64,
+        mem: &GuestMemoryMmap,
+        disk_id: &Vec<u8>,
+    ) -> result::Result<u32, ExecuteError> {
+        disk.seek(SeekFrom::Start(self.sector << SECTOR_SHIFT))
+            .map_err(ExecuteError::Seek)?;
+        let mut len = 0;
+        for (data_addr, data_len) in &self.data_descriptors {
+            let mut top: u64 = u64::from(*data_len) / SECTOR_SIZE;
+            if u64::from(*data_len) % SECTOR_SIZE != 0 {
+                top += 1;
+            }
+            top = top
+                .checked_add(self.sector)
+                .ok_or(ExecuteError::BadRequest(Error::InvalidOffset))?;
+            if top > disk_nsectors {
+                return Err(ExecuteError::BadRequest(Error::InvalidOffset));
+            }
+
+            match self.request_type {
+                RequestType::In => {
+                    mem.read_exact_from(*data_addr, disk, *data_len as usize)
+                        .map_err(ExecuteError::Read)?;
+                    len += data_len;
+                }
+                RequestType::Out => {
+                    mem.write_all_to(*data_addr, disk, *data_len as usize)
+                        .map_err(ExecuteError::Write)?;
+                    if !self.writeback {
+                        disk.flush().map_err(ExecuteError::Flush)?;
+                    }
+                }
+                RequestType::Flush => disk.flush().map_err(ExecuteError::Flush)?,
+                RequestType::GetDeviceId => {
+                    if (*data_len as usize) < disk_id.len() {
+                        return Err(ExecuteError::BadRequest(Error::InvalidOffset));
+                    }
+                    mem.write_slice(disk_id.as_slice(), *data_addr)
+                        .map_err(ExecuteError::Write)?;
+                }
+                RequestType::Unsupported(t) => return Err(ExecuteError::Unsupported(t)),
+            };
+        }
+        Ok(len)
+    }
+
+    pub fn execute_async(
+        &self,
+        mem: &GuestMemoryMmap,
+        disk_nsectors: u64,
+        disk_image: &mut dyn AsyncIo,
+        disk_id: &[u8],
+        user_data: u64,
+    ) -> result::Result<bool, ExecuteError> {
+        let sector = self.sector;
+        let request_type = self.request_type;
+        let offset = (sector << SECTOR_SHIFT) as libc::off_t;
+
+        let mut iovecs = Vec::new();
+        for (data_addr, data_len) in &self.data_descriptors {
+            let mut top: u64 = u64::from(*data_len) / SECTOR_SIZE;
+            if u64::from(*data_len) % SECTOR_SIZE != 0 {
+                top += 1;
+            }
+            top = top
+                .checked_add(sector)
+                .ok_or(ExecuteError::BadRequest(Error::InvalidOffset))?;
+            if top > disk_nsectors {
+                return Err(ExecuteError::BadRequest(Error::InvalidOffset));
+            }
+
+            let buf = mem
+                .get_slice(*data_addr, *data_len as usize)
+                .map_err(ExecuteError::GetHostAddress)?
+                .as_ptr();
+            let iovec = libc::iovec {
+                iov_base: buf as *mut libc::c_void,
+                iov_len: *data_len as libc::size_t,
+            };
+            iovecs.push(iovec);
+        }
+
+        // Queue operations expected to be submitted.
+        match request_type {
+            RequestType::In => {
+                for (data_addr, data_len) in &self.data_descriptors {
+                    mem.get_slice(*data_addr, *data_len as usize)
+                        .map_err(ExecuteError::GetHostAddress)?
+                        .bitmap()
+                        .mark_dirty(0, *data_len as usize);
+                }
+                disk_image
+                    .read_vectored(offset, iovecs, user_data)
+                    .map_err(ExecuteError::AsyncRead)?;
+            }
+            RequestType::Out => {
+                disk_image
+                    .write_vectored(offset, iovecs, user_data)
+                    .map_err(ExecuteError::AsyncWrite)?;
+            }
+            RequestType::Flush => {
+                disk_image
+                    .fsync(Some(user_data))
+                    .map_err(ExecuteError::AsyncFlush)?;
+            }
+            RequestType::GetDeviceId => {
+                let (data_addr, data_len) = if self.data_descriptors.len() == 1 {
+                    (self.data_descriptors[0].0, self.data_descriptors[0].1)
+                } else {
+                    return Err(ExecuteError::BadRequest(Error::TooManyDescriptors));
+                };
+                if (data_len as usize) < disk_id.len() {
+                    return Err(ExecuteError::BadRequest(Error::InvalidOffset));
+                }
+                mem.write_slice(disk_id, data_addr)
+                    .map_err(ExecuteError::Write)?;
+                return Ok(false);
+            }
+            RequestType::Unsupported(t) => return Err(ExecuteError::Unsupported(t)),
+        }
+
+        Ok(true)
+    }
+
+    pub fn set_writeback(&mut self, writeback: bool) {
+        self.writeback = writeback
+    }
+}
+
+#[derive(Copy, Clone, Debug, Default, Versionize)]
+#[repr(C, packed)]
+pub struct VirtioBlockConfig {
+    pub capacity: u64,
+    pub size_max: u32,
+    pub seg_max: u32,
+    pub geometry: VirtioBlockGeometry,
+    pub blk_size: u32,
+    pub physical_block_exp: u8,
+    pub alignment_offset: u8,
+    pub min_io_size: u16,
+    pub opt_io_size: u32,
+    pub writeback: u8,
+    pub unused: u8,
+    pub num_queues: u16,
+    pub max_discard_sectors: u32,
+    pub max_discard_seg: u32,
+    pub discard_sector_alignment: u32,
+    pub max_write_zeroes_sectors: u32,
+    pub max_write_zeroes_seg: u32,
+    pub write_zeroes_may_unmap: u8,
+    pub unused1: [u8; 3],
+}
+#[derive(Copy, Clone, Debug, Default, Versionize)]
+#[repr(C, packed)]
+pub struct VirtioBlockGeometry {
+    pub cylinders: u16,
+    pub heads: u8,
+    pub sectors: u8,
+}
+
+// SAFETY: these data structures only contain a series of integers
+unsafe impl ByteValued for VirtioBlockConfig {}
+unsafe impl ByteValued for VirtioBlockGeometry {}
+
+/// Check if io_uring for block device can be used on the current system, as
+/// it correctly supports the expected io_uring features.
+#[cfg(feature = "io_uring")]
+pub fn block_io_uring_is_supported() -> bool {
+    let error_msg = "io_uring not supported:";
+
+    // Check we can create an io_uring instance, which effectively verifies
+    // that io_uring_setup() syscall is supported.
+    let io_uring = match IoUring::new(1) {
+        Ok(io_uring) => io_uring,
+        Err(e) => {
+            info!("{} failed to create io_uring instance: {}", error_msg, e);
+            return false;
+        }
+    };
+
+    let submitter = io_uring.submitter();
+
+    let mut probe = Probe::new();
+
+    // Check we can register a probe to validate supported operations.
+    match submitter.register_probe(&mut probe) {
+        Ok(_) => {}
+        Err(e) => {
+            info!("{} failed to register a probe: {}", error_msg, e);
+            return false;
+        }
+    }
+
+    // Check IORING_OP_FSYNC is supported
+    if !probe.is_supported(opcode::Fsync::CODE) {
+        info!("{} IORING_OP_FSYNC operation not supported", error_msg);
+        return false;
+    }
+
+    // Check IORING_OP_READ is supported
+    if !probe.is_supported(opcode::Read::CODE) {
+        info!("{} IORING_OP_READ operation not supported", error_msg);
+        return false;
+    }
+
+    // Check IORING_OP_WRITE is supported
+    if !probe.is_supported(opcode::Write::CODE) {
+        info!("{} IORING_OP_WRITE operation not supported", error_msg);
+        return false;
+    }
+
+    true
+}
+
+#[cfg(not(feature = "io_uring"))]
+pub fn block_io_uring_is_supported() -> bool {
+    false
+}
+
+pub fn disk_size(file: &mut dyn Seek, semaphore: &mut Arc<Mutex<()>>) -> DiskFileResult<u64> {
+    // Take the semaphore to ensure other threads are not interacting with
+    // the underlying file.
+    let _lock = semaphore.lock().unwrap();
+
+    Ok(file.seek(SeekFrom::End(0)).map_err(DiskFileError::Size)? as u64)
+}
+
+pub trait ReadSeekFile: Read + Seek {}
+impl<F: Read + Seek> ReadSeekFile for F {}
+
+pub fn read_vectored_sync(
+    offset: libc::off_t,
+    iovecs: Vec<libc::iovec>,
+    user_data: u64,
+    file: &mut dyn ReadSeekFile,
+    eventfd: &EventFd,
+    completion_list: &mut Vec<(u64, i32)>,
+    semaphore: &mut Arc<Mutex<()>>,
+) -> AsyncIoResult<()> {
+    // Convert libc::iovec into IoSliceMut
+    let mut slices = Vec::new();
+    for iovec in iovecs.iter() {
+        slices.push(IoSliceMut::new(unsafe { std::mem::transmute(*iovec) }));
+    }
+
+    let result = {
+        // Take the semaphore to ensure other threads are not interacting
+        // with the underlying file.
+        let _lock = semaphore.lock().unwrap();
+
+        // Move the cursor to the right offset
+        file.seek(SeekFrom::Start(offset as u64))
+            .map_err(AsyncIoError::ReadVectored)?;
+
+        // Read vectored
+        file.read_vectored(slices.as_mut_slice())
+            .map_err(AsyncIoError::ReadVectored)?
+    };
+
+    completion_list.push((user_data, result as i32));
+    eventfd.write(1).unwrap();
+
+    Ok(())
+}
+
+pub trait WriteSeekFile: Write + Seek {}
+impl<F: Write + Seek> WriteSeekFile for F {}
+
+pub fn write_vectored_sync(
+    offset: libc::off_t,
+    iovecs: Vec<libc::iovec>,
+    user_data: u64,
+    file: &mut dyn WriteSeekFile,
+    eventfd: &EventFd,
+    completion_list: &mut Vec<(u64, i32)>,
+    semaphore: &mut Arc<Mutex<()>>,
+) -> AsyncIoResult<()> {
+    // Convert libc::iovec into IoSlice
+    let mut slices = Vec::new();
+    for iovec in iovecs.iter() {
+        slices.push(IoSlice::new(unsafe { std::mem::transmute(*iovec) }));
+    }
+
+    let result = {
+        // Take the semaphore to ensure other threads are not interacting
+        // with the underlying file.
+        let _lock = semaphore.lock().unwrap();
+
+        // Move the cursor to the right offset
+        file.seek(SeekFrom::Start(offset as u64))
+            .map_err(AsyncIoError::WriteVectored)?;
+
+        // Write vectored
+        file.write_vectored(slices.as_slice())
+            .map_err(AsyncIoError::WriteVectored)?
+    };
+
+    completion_list.push((user_data, result as i32));
+    eventfd.write(1).unwrap();
+
+    Ok(())
+}
+
+pub fn fsync_sync(
+    user_data: Option<u64>,
+    file: &mut dyn Write,
+    eventfd: &EventFd,
+    completion_list: &mut Vec<(u64, i32)>,
+    semaphore: &mut Arc<Mutex<()>>,
+) -> AsyncIoResult<()> {
+    let result: i32 = {
+        // Take the semaphore to ensure other threads are not interacting
+        // with the underlying file.
+        let _lock = semaphore.lock().unwrap();
+
+        // Flush
+        file.flush().map_err(AsyncIoError::Fsync)?;
+
+        0
+    };
+
+    if let Some(user_data) = user_data {
+        completion_list.push((user_data, result));
+        eventfd.write(1).unwrap();
+    }
+
+    Ok(())
+}
+
+pub enum ImageType {
+    FixedVhd,
+    Qcow2,
+    Raw,
+    Vhdx,
+}
+
+const QCOW_MAGIC: u32 = 0x5146_49fb;
+const VHDX_SIGN: u64 = 0x656C_6966_7864_6876;
+
+/// Determine image type through file parsing.
+pub fn detect_image_type(f: &mut File) -> std::io::Result<ImageType> {
+    // We must create a buffer aligned on 512 bytes with a size being a
+    // multiple of 512 bytes as the file might be opened with O_DIRECT flag.
+    #[repr(align(512))]
+    struct Sector {
+        data: [u8; 512],
+    }
+    let mut s = Sector { data: [0; 512] };
+
+    f.read_exact(&mut s.data)?;
+
+    // Check 4 first bytes to get the header value and determine the image type
+    let image_type = if u32::from_be_bytes(s.data[0..4].try_into().unwrap()) == QCOW_MAGIC {
+        ImageType::Qcow2
+    } else if vhd::is_fixed_vhd(f)? {
+        ImageType::FixedVhd
+    } else if u64::from_le_bytes(s.data[0..8].try_into().unwrap()) == VHDX_SIGN {
+        ImageType::Vhdx
+    } else {
+        ImageType::Raw
+    };
+
+    Ok(image_type)
+}

block_util/src/qcow_sync.rs

@@ -0,0 +1,110 @@
+// Copyright © 2021 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
+
+use crate::async_io::{AsyncIo, AsyncIoResult, DiskFile, DiskFileResult};
+use crate::{disk_size, fsync_sync, read_vectored_sync, write_vectored_sync};
+use qcow::{QcowFile, RawFile, Result as QcowResult};
+use std::fs::File;
+use std::sync::{Arc, Mutex};
+use vmm_sys_util::eventfd::EventFd;
+
+pub struct QcowDiskSync {
+    qcow_file: QcowFile,
+    semaphore: Arc<Mutex<()>>,
+}
+
+impl QcowDiskSync {
+    pub fn new(file: File, direct_io: bool) -> QcowResult<Self> {
+        Ok(QcowDiskSync {
+            qcow_file: QcowFile::from(RawFile::new(file, direct_io))?,
+            semaphore: Arc::new(Mutex::new(())),
+        })
+    }
+}
+
+impl DiskFile for QcowDiskSync {
+    fn size(&mut self) -> DiskFileResult<u64> {
+        disk_size(&mut self.qcow_file, &mut self.semaphore)
+    }
+
+    fn new_async_io(&self, _ring_depth: u32) -> DiskFileResult<Box<dyn AsyncIo>> {
+        Ok(Box::new(QcowSync::new(
+            self.qcow_file.clone(),
+            self.semaphore.clone(),
+        )) as Box<dyn AsyncIo>)
+    }
+}
+
+pub struct QcowSync {
+    qcow_file: QcowFile,
+    eventfd: EventFd,
+    completion_list: Vec<(u64, i32)>,
+    semaphore: Arc<Mutex<()>>,
+}
+
+impl QcowSync {
+    pub fn new(qcow_file: QcowFile, semaphore: Arc<Mutex<()>>) -> Self {
+        QcowSync {
+            qcow_file,
+            eventfd: EventFd::new(libc::EFD_NONBLOCK)
+                .expect("Failed creating EventFd for QcowSync"),
+            completion_list: Vec::new(),
+            semaphore,
+        }
+    }
+}
+
+impl AsyncIo for QcowSync {
+    fn notifier(&self) -> &EventFd {
+        &self.eventfd
+    }
+
+    fn read_vectored(
+        &mut self,
+        offset: libc::off_t,
+        iovecs: Vec<libc::iovec>,
+        user_data: u64,
+    ) -> AsyncIoResult<()> {
+        read_vectored_sync(
+            offset,
+            iovecs,
+            user_data,
+            &mut self.qcow_file,
+            &self.eventfd,
+            &mut self.completion_list,
+            &mut self.semaphore,
+        )
+    }
+
+    fn write_vectored(
+        &mut self,
+        offset: libc::off_t,
+        iovecs: Vec<libc::iovec>,
+        user_data: u64,
+    ) -> AsyncIoResult<()> {
+        write_vectored_sync(
+            offset,
+            iovecs,
+            user_data,
+            &mut self.qcow_file,
+            &self.eventfd,
+            &mut self.completion_list,
+            &mut self.semaphore,
+        )
+    }
+
+    fn fsync(&mut self, user_data: Option<u64>) -> AsyncIoResult<()> {
+        fsync_sync(
+            user_data,
+            &mut self.qcow_file,
+            &self.eventfd,
+            &mut self.completion_list,
+            &mut self.semaphore,
+        )
+    }
+
+    fn complete(&mut self) -> Vec<(u64, i32)> {
+        self.completion_list.drain(..).collect()
+    }
+}

block_util/src/raw_async.rs

@@ -0,0 +1,159 @@
+// Copyright © 2021 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
+
+use crate::async_io::{
+    AsyncIo, AsyncIoError, AsyncIoResult, DiskFile, DiskFileError, DiskFileResult,
+};
+use io_uring::{opcode, squeue, types, IoUring};
+use std::fs::File;
+use std::io::{Seek, SeekFrom};
+use std::os::unix::io::{AsRawFd, RawFd};
+use vmm_sys_util::eventfd::EventFd;
+
+pub struct RawFileDisk {
+    file: File,
+}
+
+impl RawFileDisk {
+    pub fn new(file: File) -> Self {
+        RawFileDisk { file }
+    }
+}
+
+impl DiskFile for RawFileDisk {
+    fn size(&mut self) -> DiskFileResult<u64> {
+        Ok(self
+            .file
+            .seek(SeekFrom::End(0))
+            .map_err(DiskFileError::Size)? as u64)
+    }
+
+    fn new_async_io(&self, ring_depth: u32) -> DiskFileResult<Box<dyn AsyncIo>> {
+        Ok(Box::new(
+            RawFileAsync::new(self.file.as_raw_fd(), ring_depth)
+                .map_err(DiskFileError::NewAsyncIo)?,
+        ) as Box<dyn AsyncIo>)
+    }
+}
+
+pub struct RawFileAsync {
+    fd: RawFd,
+    io_uring: IoUring,
+    eventfd: EventFd,
+}
+
+impl RawFileAsync {
+    pub fn new(fd: RawFd, ring_depth: u32) -> std::io::Result<Self> {
+        let io_uring = IoUring::new(ring_depth)?;
+        let eventfd = EventFd::new(libc::EFD_NONBLOCK)?;
+
+        // Register the io_uring eventfd that will notify when something in
+        // the completion queue is ready.
+        io_uring.submitter().register_eventfd(eventfd.as_raw_fd())?;
+
+        Ok(RawFileAsync {
+            fd,
+            io_uring,
+            eventfd,
+        })
+    }
+}
+
+impl AsyncIo for RawFileAsync {
+    fn notifier(&self) -> &EventFd {
+        &self.eventfd
+    }
+
+    fn read_vectored(
+        &mut self,
+        offset: libc::off_t,
+        iovecs: Vec<libc::iovec>,
+        user_data: u64,
+    ) -> AsyncIoResult<()> {
+        let (submitter, mut sq, _) = self.io_uring.split();
+
+        // Safe because we know the file descriptor is valid and we
+        // relied on vm-memory to provide the buffer address.
+        let _ = unsafe {
+            sq.push(
+                &opcode::Readv::new(types::Fd(self.fd), iovecs.as_ptr(), iovecs.len() as u32)
+                    .offset(offset)
+                    .build()
+                    .flags(squeue::Flags::ASYNC)
+                    .user_data(user_data),
+            )
+        };
+
+        // Update the submission queue and submit new operations to the
+        // io_uring instance.
+        sq.sync();
+        submitter.submit().map_err(AsyncIoError::ReadVectored)?;
+
+        Ok(())
+    }
+
+    fn write_vectored(
+        &mut self,
+        offset: libc::off_t,
+        iovecs: Vec<libc::iovec>,
+        user_data: u64,
+    ) -> AsyncIoResult<()> {
+        let (submitter, mut sq, _) = self.io_uring.split();
+
+        // Safe because we know the file descriptor is valid and we
+        // relied on vm-memory to provide the buffer address.
+        let _ = unsafe {
+            sq.push(
+                &opcode::Writev::new(types::Fd(self.fd), iovecs.as_ptr(), iovecs.len() as u32)
+                    .offset(offset)
+                    .build()
+                    .flags(squeue::Flags::ASYNC)
+                    .user_data(user_data),
+            )
+        };
+
+        // Update the submission queue and submit new operations to the
+        // io_uring instance.
+        sq.sync();
+        submitter.submit().map_err(AsyncIoError::WriteVectored)?;
+
+        Ok(())
+    }
+
+    fn fsync(&mut self, user_data: Option<u64>) -> AsyncIoResult<()> {
+        if let Some(user_data) = user_data {
+            let (submitter, mut sq, _) = self.io_uring.split();
+
+            // Safe because we know the file descriptor is valid.
+            let _ = unsafe {
+                sq.push(
+                    &opcode::Fsync::new(types::Fd(self.fd))
+                        .build()
+                        .flags(squeue::Flags::ASYNC)
+                        .user_data(user_data),
+                )
+            };
+
+            // Update the submission queue and submit new operations to the
+            // io_uring instance.
+            sq.sync();
+            submitter.submit().map_err(AsyncIoError::Fsync)?;
+        } else {
+            unsafe { libc::fsync(self.fd) };
+        }
+
+        Ok(())
+    }
+
+    fn complete(&mut self) -> Vec<(u64, i32)> {
+        let mut completion_list = Vec::new();
+
+        let cq = self.io_uring.completion();
+        for cq_entry in cq {
+            completion_list.push((cq_entry.user_data(), cq_entry.result()));
+        }
+
+        completion_list
+    }
+}

block_util/src/raw_sync.rs

@@ -0,0 +1,122 @@
+// Copyright © 2021 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
+
+use crate::async_io::{
+    AsyncIo, AsyncIoError, AsyncIoResult, DiskFile, DiskFileError, DiskFileResult,
+};
+use std::fs::File;
+use std::io::{Seek, SeekFrom};
+use std::os::unix::io::{AsRawFd, RawFd};
+use vmm_sys_util::eventfd::EventFd;
+
+pub struct RawFileDiskSync {
+    file: File,
+}
+
+impl RawFileDiskSync {
+    pub fn new(file: File) -> Self {
+        RawFileDiskSync { file }
+    }
+}
+
+impl DiskFile for RawFileDiskSync {
+    fn size(&mut self) -> DiskFileResult<u64> {
+        Ok(self
+            .file
+            .seek(SeekFrom::End(0))
+            .map_err(DiskFileError::Size)? as u64)
+    }
+
+    fn new_async_io(&self, _ring_depth: u32) -> DiskFileResult<Box<dyn AsyncIo>> {
+        Ok(Box::new(RawFileSync::new(self.file.as_raw_fd())) as Box<dyn AsyncIo>)
+    }
+}
+
+pub struct RawFileSync {
+    fd: RawFd,
+    eventfd: EventFd,
+    completion_list: Vec<(u64, i32)>,
+}
+
+impl RawFileSync {
+    pub fn new(fd: RawFd) -> Self {
+        RawFileSync {
+            fd,
+            eventfd: EventFd::new(libc::EFD_NONBLOCK).expect("Failed creating EventFd for RawFile"),
+            completion_list: Vec::new(),
+        }
+    }
+}
+
+impl AsyncIo for RawFileSync {
+    fn notifier(&self) -> &EventFd {
+        &self.eventfd
+    }
+
+    fn read_vectored(
+        &mut self,
+        offset: libc::off_t,
+        iovecs: Vec<libc::iovec>,
+        user_data: u64,
+    ) -> AsyncIoResult<()> {
+        let result = unsafe {
+            libc::preadv(
+                self.fd as libc::c_int,
+                iovecs.as_ptr() as *const libc::iovec,
+                iovecs.len() as libc::c_int,
+                offset,
+            )
+        };
+        if result < 0 {
+            return Err(AsyncIoError::ReadVectored(std::io::Error::last_os_error()));
+        }
+
+        self.completion_list.push((user_data, result as i32));
+        self.eventfd.write(1).unwrap();
+
+        Ok(())
+    }
+
+    fn write_vectored(
+        &mut self,
+        offset: libc::off_t,
+        iovecs: Vec<libc::iovec>,
+        user_data: u64,
+    ) -> AsyncIoResult<()> {
+        let result = unsafe {
+            libc::pwritev(
+                self.fd as libc::c_int,
+                iovecs.as_ptr() as *const libc::iovec,
+                iovecs.len() as libc::c_int,
+                offset,
+            )
+        };
+        if result < 0 {
+            return Err(AsyncIoError::WriteVectored(std::io::Error::last_os_error()));
+        }
+
+        self.completion_list.push((user_data, result as i32));
+        self.eventfd.write(1).unwrap();
+
+        Ok(())
+    }
+
+    fn fsync(&mut self, user_data: Option<u64>) -> AsyncIoResult<()> {
+        let result = unsafe { libc::fsync(self.fd as libc::c_int) };
+        if result < 0 {
+            return Err(AsyncIoError::Fsync(std::io::Error::last_os_error()));
+        }
+
+        if let Some(user_data) = user_data {
+            self.completion_list.push((user_data, result as i32));
+            self.eventfd.write(1).unwrap();
+        }
+
+        Ok(())
+    }
+
+    fn complete(&mut self) -> Vec<(u64, i32)> {
+        self.completion_list.drain(..).collect()
+    }
+}

block_util/src/vhd.rs

@@ -0,0 +1,221 @@
+// Copyright © 2021 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0
+
+use std::convert::TryInto;
+use std::fs::File;
+use std::io::{Read, Seek, SeekFrom};
+
+#[derive(Clone, Copy)]
+pub struct VhdFooter {
+    cookie: u64,
+    features: u32,
+    file_format_version: u32,
+    data_offset: u64,
+    time_stamp: u32,
+    creator_application: u32,
+    creator_version: u32,
+    creator_host_os: u32,
+    original_size: u64,
+    current_size: u64,
+    disk_geometry: u32,
+    disk_type: u32,
+    checksum: u32,
+    unique_id: u128,
+    saved_state: u8,
+}
+
+impl VhdFooter {
+    pub fn new(file: &mut File) -> std::io::Result<VhdFooter> {
+        // We must create a buffer aligned on 512 bytes with a size being a
+        // multiple of 512 bytes as the file might be opened with O_DIRECT flag.
+        #[repr(align(512))]
+        struct Sector {
+            data: [u8; 512],
+        }
+        let mut s = Sector { data: [0; 512] };
+
+        // Place the cursor 512 bytes before the end of the file, as this is
+        // where the footer starts.
+        file.seek(SeekFrom::End(-512))?;
+
+        // Fill in the VhdFooter structure
+        file.read_exact(&mut s.data)?;
+
+        Ok(VhdFooter {
+            cookie: u64::from_be_bytes(s.data[0..8].try_into().unwrap()),
+            features: u32::from_be_bytes(s.data[8..12].try_into().unwrap()),
+            file_format_version: u32::from_be_bytes(s.data[12..16].try_into().unwrap()),
+            data_offset: u64::from_be_bytes(s.data[16..24].try_into().unwrap()),
+            time_stamp: u32::from_be_bytes(s.data[24..28].try_into().unwrap()),
+            creator_application: u32::from_be_bytes(s.data[28..32].try_into().unwrap()),
+            creator_version: u32::from_be_bytes(s.data[32..36].try_into().unwrap()),
+            creator_host_os: u32::from_be_bytes(s.data[36..40].try_into().unwrap()),
+            original_size: u64::from_be_bytes(s.data[40..48].try_into().unwrap()),
+            current_size: u64::from_be_bytes(s.data[48..56].try_into().unwrap()),
+            disk_geometry: u32::from_be_bytes(s.data[56..60].try_into().unwrap()),
+            disk_type: u32::from_be_bytes(s.data[60..64].try_into().unwrap()),
+            checksum: u32::from_be_bytes(s.data[64..68].try_into().unwrap()),
+            unique_id: u128::from_be_bytes(s.data[68..84].try_into().unwrap()),
+            saved_state: u8::from_be_bytes(s.data[84..85].try_into().unwrap()),
+        })
+    }
+
+    pub fn cookie(&self) -> u64 {
+        self.cookie
+    }
+    pub fn features(&self) -> u32 {
+        self.features
+    }
+    pub fn file_format_version(&self) -> u32 {
+        self.file_format_version
+    }
+    pub fn data_offset(&self) -> u64 {
+        self.data_offset
+    }
+    pub fn time_stamp(&self) -> u32 {
+        self.time_stamp
+    }
+    pub fn creator_application(&self) -> u32 {
+        self.creator_application
+    }
+    pub fn creator_version(&self) -> u32 {
+        self.creator_version
+    }
+    pub fn creator_host_os(&self) -> u32 {
+        self.creator_host_os
+    }
+    pub fn original_size(&self) -> u64 {
+        self.original_size
+    }
+    pub fn current_size(&self) -> u64 {
+        self.current_size
+    }
+    pub fn disk_geometry(&self) -> u32 {
+        self.disk_geometry
+    }
+    pub fn disk_type(&self) -> u32 {
+        self.disk_type
+    }
+    pub fn checksum(&self) -> u32 {
+        self.checksum
+    }
+    pub fn unique_id(&self) -> u128 {
+        self.unique_id
+    }
+    pub fn saved_state(&self) -> u8 {
+        self.saved_state
+    }
+}
+
+/// Determine image type through file parsing.
+pub fn is_fixed_vhd(f: &mut File) -> std::io::Result<bool> {
+    let footer = VhdFooter::new(f)?;
+
+    // "conectix" => 0x636f6e6563746978
+    Ok(footer.cookie() == 0x636f6e6563746978
+        && footer.file_format_version() == 0x0001_0000
+        && footer.data_offset() == 0xffff_ffff_ffff_ffff
+        && footer.disk_type() == 0x2)
+}
+
+#[cfg(test)]
+mod tests {
+    use super::{is_fixed_vhd, VhdFooter};
+    use std::fs::File;
+    use std::io::{Seek, SeekFrom, Write};
+    use vmm_sys_util::tempfile::TempFile;
+
+    fn valid_fixed_vhd_footer() -> Vec<u8> {
+        vec![
+            0x63, 0x6f, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x78, // cookie
+            0x00, 0x00, 0x00, 0x02, // features
+            0x00, 0x01, 0x00, 0x00, // file format version
+            0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // data offset
+            0x27, 0xa6, 0xa6, 0x5d, // time stamp
+            0x71, 0x65, 0x6d, 0x75, // creator application
+            0x00, 0x05, 0x00, 0x03, // creator version
+            0x57, 0x69, 0x32, 0x6b, // creator host os
+            0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, // original size
+            0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, // current size
+            0x11, 0xe0, 0x10, 0x3f, // disk geometry
+            0x00, 0x00, 0x00, 0x02, // disk type
+            0x00, 0x00, 0x00, 0x00, // checksum
+            0x98, 0x7b, 0xb1, 0xcd, 0x84, 0x14, 0x41, 0xfc, 0xa4, 0xab, 0xd0, 0x69, 0x45, 0x2b,
+            0xf2, 0x23, // unique id
+            0x00, // saved state
+        ]
+    }
+
+    fn valid_dynamic_vhd_footer() -> Vec<u8> {
+        vec![
+            0x63, 0x6f, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x78, // cookie
+            0x00, 0x00, 0x00, 0x02, // features
+            0x00, 0x01, 0x00, 0x00, // file format version
+            0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // data offset
+            0x27, 0xa6, 0xa6, 0x5d, // time stamp
+            0x71, 0x65, 0x6d, 0x75, // creator application
+            0x00, 0x05, 0x00, 0x03, // creator version
+            0x57, 0x69, 0x32, 0x6b, // creator host os
+            0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, // original size
+            0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, // current size
+            0x11, 0xe0, 0x10, 0x3f, // disk geometry
+            0x00, 0x00, 0x00, 0x03, // disk type
+            0x00, 0x00, 0x00, 0x00, // checksum
+            0x98, 0x7b, 0xb1, 0xcd, 0x84, 0x14, 0x41, 0xfc, 0xa4, 0xab, 0xd0, 0x69, 0x45, 0x2b,
+            0xf2, 0x23, // unique id
+            0x00, // saved state
+        ]
+    }
+
+    fn with_file<F>(footer: &[u8], mut testfn: F)
+    where
+        F: FnMut(File),
+    {
+        let mut disk_file: File = TempFile::new().unwrap().into_file();
+        disk_file.set_len(0x1000_0200).unwrap();
+        disk_file.seek(SeekFrom::Start(0x1000_0000)).unwrap();
+        disk_file.write_all(footer).unwrap();
+
+        testfn(disk_file); // File closed when the function exits.
+    }
+
+    #[test]
+    fn test_check_vhd_footer() {
+        with_file(&valid_fixed_vhd_footer(), |mut file: File| {
+            let vhd_footer = VhdFooter::new(&mut file).expect("Failed to create VHD footer");
+            assert_eq!(vhd_footer.cookie(), 0x636f_6e65_6374_6978);
+            assert_eq!(vhd_footer.features(), 0x0000_0002);
+            assert_eq!(vhd_footer.file_format_version(), 0x0001_0000);
+            assert_eq!(vhd_footer.data_offset(), 0xffff_ffff_ffff_ffff);
+            assert_eq!(vhd_footer.time_stamp(), 0x27a6_a65d);
+            assert_eq!(vhd_footer.creator_application(), 0x7165_6d75);
+            assert_eq!(vhd_footer.creator_version(), 0x0005_0003);
+            assert_eq!(vhd_footer.creator_host_os(), 0x5769_326b);
+            assert_eq!(vhd_footer.original_size(), 0x0000_0000_1000_0000);
+            assert_eq!(vhd_footer.current_size(), 0x0000_0000_1000_0000);
+            assert_eq!(vhd_footer.disk_geometry(), 0x11e0_103f);
+            assert_eq!(vhd_footer.disk_type(), 0x0000_0002);
+            assert_eq!(vhd_footer.checksum(), 0x0000_0000);
+            assert_eq!(
+                vhd_footer.unique_id(),
+                0x987b_b1cd_8414_41fc_a4ab_d069_452b_f223
+            );
+            assert_eq!(vhd_footer.saved_state(), 0x00);
+        });
+    }
+
+    #[test]
+    fn test_is_fixed_vhd() {
+        with_file(&valid_fixed_vhd_footer(), |mut file: File| {
+            assert!(is_fixed_vhd(&mut file).unwrap());
+        });
+    }
+
+    #[test]
+    fn test_is_not_fixed_vhd() {
+        with_file(&valid_dynamic_vhd_footer(), |mut file: File| {
+            assert!(!(is_fixed_vhd(&mut file).unwrap()));
+        });
+    }
+}

block_util/src/vhdx_sync.rs

@@ -0,0 +1,113 @@
+// Copyright © 2021 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0
+
+use crate::async_io::{AsyncIo, AsyncIoResult, DiskFile, DiskFileError, DiskFileResult};
+use crate::{fsync_sync, read_vectored_sync, write_vectored_sync};
+use std::fs::File;
+use std::ops::DerefMut;
+use std::sync::{Arc, Mutex};
+use vhdx::vhdx::{Result as VhdxResult, Vhdx};
+use vmm_sys_util::eventfd::EventFd;
+
+pub struct VhdxDiskSync {
+    vhdx_file: Arc<Mutex<Vhdx>>,
+    semaphore: Arc<Mutex<()>>,
+}
+
+impl VhdxDiskSync {
+    pub fn new(f: File) -> VhdxResult<Self> {
+        let vhdx = Vhdx::new(f)?;
+        let vhdx_file = Arc::new(Mutex::new(vhdx));
+
+        Ok(VhdxDiskSync {
+            vhdx_file,
+            semaphore: Arc::new(Mutex::new(())),
+        })
+    }
+}
+
+impl DiskFile for VhdxDiskSync {
+    fn size(&mut self) -> DiskFileResult<u64> {
+        Ok(self.vhdx_file.lock().unwrap().virtual_disk_size())
+    }
+
+    fn new_async_io(&self, _ring_depth: u32) -> DiskFileResult<Box<dyn AsyncIo>> {
+        Ok(Box::new(
+            VhdxSync::new(self.vhdx_file.clone(), self.semaphore.clone())
+                .map_err(DiskFileError::NewAsyncIo)?,
+        ) as Box<dyn AsyncIo>)
+    }
+}
+
+pub struct VhdxSync {
+    vhdx_file: Arc<Mutex<Vhdx>>,
+    eventfd: EventFd,
+    completion_list: Vec<(u64, i32)>,
+    semaphore: Arc<Mutex<()>>,
+}
+
+impl VhdxSync {
+    pub fn new(vhdx_file: Arc<Mutex<Vhdx>>, semaphore: Arc<Mutex<()>>) -> std::io::Result<Self> {
+        Ok(VhdxSync {
+            vhdx_file,
+            eventfd: EventFd::new(libc::EFD_NONBLOCK)?,
+            completion_list: Vec::new(),
+            semaphore,
+        })
+    }
+}
+
+impl AsyncIo for VhdxSync {
+    fn notifier(&self) -> &EventFd {
+        &self.eventfd
+    }
+
+    fn read_vectored(
+        &mut self,
+        offset: libc::off_t,
+        iovecs: Vec<libc::iovec>,
+        user_data: u64,
+    ) -> AsyncIoResult<()> {
+        read_vectored_sync(
+            offset,
+            iovecs,
+            user_data,
+            self.vhdx_file.lock().unwrap().deref_mut(),
+            &self.eventfd,
+            &mut self.completion_list,
+            &mut self.semaphore,
+        )
+    }
+
+    fn write_vectored(
+        &mut self,
+        offset: libc::off_t,
+        iovecs: Vec<libc::iovec>,
+        user_data: u64,
+    ) -> AsyncIoResult<()> {
+        write_vectored_sync(
+            offset,
+            iovecs,
+            user_data,
+            self.vhdx_file.lock().unwrap().deref_mut(),
+            &self.eventfd,
+            &mut self.completion_list,
+            &mut self.semaphore,
+        )
+    }
+
+    fn fsync(&mut self, user_data: Option<u64>) -> AsyncIoResult<()> {
+        fsync_sync(
+            user_data,
+            self.vhdx_file.lock().unwrap().deref_mut(),
+            &self.eventfd,
+            &mut self.completion_list,
+            &mut self.semaphore,
+        )
+    }
+
+    fn complete(&mut self) -> Vec<(u64, i32)> {
+        self.completion_list.drain(..).collect()
+    }
+}

build.rs

@@ -3,20 +3,25 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 
+#[macro_use(crate_version)]
+extern crate clap;
+
 use std::process::Command;
 
 fn main() {
-    let git_out = Command::new("git")
-        .args(&["describe", "--dirty"])
-        .output()
-        .expect("Expect to get git describe output");
+    let mut version = "v".to_owned() + crate_version!();
+
+    if let Ok(git_out) = Command::new("git").args(&["describe", "--dirty"]).output() {
+        if git_out.status.success() {
+            if let Ok(git_out_str) = String::from_utf8(git_out.stdout) {
+                version = git_out_str;
+            }
+        }
+    }
 
     // This println!() has a special behavior, as it will set the environment
     // variable BUILT_VERSION, so that it can be reused from the binary.
     // Particularly, this is used from src/main.rs to display the exact
     // version.
-    println!(
-        "cargo:rustc-env=BUILT_VERSION={}",
-        String::from_utf8(git_out.stdout).unwrap()
-    );
+    println!("cargo:rustc-env=BUILT_VERSION={}", version);
 }

devices/Cargo.toml

@@ -2,25 +2,23 @@
 name = "devices"
 version = "0.1.0"
 authors = ["The Chromium OS Authors"]
+edition = "2018"
 
 [dependencies]
-anyhow = "1.0"
-bitflags = ">=1.2.1"
-byteorder = "1.3.4"
-epoll = ">=4.0.1"
-libc = "0.2.69"
-log = "0.4.8"
-serde = {version = ">=1.0.27", features = ["rc"] }
-serde_derive = ">=1.0.27"
-serde_json = ">=1.0.9"
-vm-device = { path = "../vm-device" }
 acpi_tables = { path = "../acpi_tables", optional = true }
-vm-memory = "0.2.0"
+anyhow = "1.0.51"
+arch = { path = "../arch" }
+bitflags = "1.3.2"
+byteorder = "1.4.3"
+epoll = "4.3.1"
+libc = "0.2.108"
+log = "0.4.14"
+versionize = "0.1.6"
+versionize_derive = "0.1.4"
+vm-device = { path = "../vm-device" }
+vm-memory = "0.6.0"
 vm-migration = { path = "../vm-migration" }
-vmm-sys-util = ">=0.3.1"
-
-[dev-dependencies]
-tempfile = "3.1.0"
+vmm-sys-util = "0.9.0"
 
 [features]
 default = []

devices/src/acpi.rs

@@ -3,12 +3,16 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 
+use super::AcpiNotificationFlags;
 use acpi_tables::{aml, aml::Aml};
-use std::sync::Arc;
+use std::sync::{Arc, Barrier};
+use std::time::Instant;
 use vm_device::interrupt::InterruptSourceGroup;
+use vm_device::BusDevice;
+use vm_memory::GuestAddress;
 use vmm_sys_util::eventfd::EventFd;
-use BusDevice;
-use HotPlugNotificationFlags;
+
+pub const GED_DEVICE_ACPI_SIZE: usize = 0x1;
 
 /// A device for handling ACPI shutdown and reboot
 pub struct AcpiShutdownDevice {
@@ -30,14 +34,12 @@ impl AcpiShutdownDevice {
 impl BusDevice for AcpiShutdownDevice {
     // Spec has all fields as zero
     fn read(&mut self, _base: u64, _offset: u64, data: &mut [u8]) {
-        for i in data.iter_mut() {
-            *i = 0;
-        }
+        data.fill(0)
     }
 
-    fn write(&mut self, _base: u64, _offset: u64, data: &[u8]) {
+    fn write(&mut self, _base: u64, _offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
         if data[0] == 1 {
-            debug!("ACPI Reboot signalled");
+            info!("ACPI Reboot signalled");
             if let Err(e) = self.reset_evt.write(1) {
                 error!("Error triggering ACPI reset event: {}", e);
             }
@@ -47,34 +49,40 @@ impl BusDevice for AcpiShutdownDevice {
         const SLEEP_STATUS_EN_BIT: u8 = 5;
         const SLEEP_VALUE_BIT: u8 = 2;
         if data[0] == (S5_SLEEP_VALUE << SLEEP_VALUE_BIT) | (1 << SLEEP_STATUS_EN_BIT) {
-            debug!("ACPI Shutdown signalled");
-            extern crate bitflags;
+            info!("ACPI Shutdown signalled");
             if let Err(e) = self.exit_evt.write(1) {
                 error!("Error triggering ACPI shutdown event: {}", e);
             }
         }
+        None
     }
 }
 
 /// A device for handling ACPI GED event generation
-pub struct AcpiGEDDevice {
-    interrupt: Arc<Box<dyn InterruptSourceGroup>>,
-    notification_type: HotPlugNotificationFlags,
+pub struct AcpiGedDevice {
+    interrupt: Arc<dyn InterruptSourceGroup>,
+    notification_type: AcpiNotificationFlags,
     ged_irq: u32,
+    address: GuestAddress,
 }
 
-impl AcpiGEDDevice {
-    pub fn new(interrupt: Arc<Box<dyn InterruptSourceGroup>>, ged_irq: u32) -> AcpiGEDDevice {
-        AcpiGEDDevice {
+impl AcpiGedDevice {
+    pub fn new(
+        interrupt: Arc<dyn InterruptSourceGroup>,
+        ged_irq: u32,
+        address: GuestAddress,
+    ) -> AcpiGedDevice {
+        AcpiGedDevice {
             interrupt,
-            notification_type: HotPlugNotificationFlags::NO_DEVICES_CHANGED,
+            notification_type: AcpiNotificationFlags::NO_DEVICES_CHANGED,
             ged_irq,
+            address,
         }
     }
 
     pub fn notify(
         &mut self,
-        notification_type: HotPlugNotificationFlags,
+        notification_type: AcpiNotificationFlags,
     ) -> Result<(), std::io::Error> {
         self.notification_type |= notification_type;
         self.interrupt.trigger(0)
@@ -86,19 +94,17 @@ impl AcpiGEDDevice {
 }
 
 // I/O port reports what type of notification was made
-impl BusDevice for AcpiGEDDevice {
+impl BusDevice for AcpiGedDevice {
     // Spec has all fields as zero
     fn read(&mut self, _base: u64, _offset: u64, data: &mut [u8]) {
         data[0] = self.notification_type.bits();
-        self.notification_type = HotPlugNotificationFlags::NO_DEVICES_CHANGED;
+        self.notification_type = AcpiNotificationFlags::NO_DEVICES_CHANGED;
     }
-
-    fn write(&mut self, _base: u64, _offset: u64, _data: &[u8]) {}
 }
 
 #[cfg(feature = "acpi")]
-impl Aml for AcpiGEDDevice {
-    fn to_aml_bytes(&self) -> Vec<u8> {
+impl Aml for AcpiGedDevice {
+    fn append_aml_bytes(&self, bytes: &mut Vec<u8>) {
         aml::Device::new(
             "_SB_.GED_".into(),
             vec![
@@ -114,7 +120,12 @@ impl Aml for AcpiGEDDevice {
                         self.ged_irq,
                     )]),
                 ),
-                &aml::OpRegion::new("GDST".into(), aml::OpRegionSpace::SystemIO, 0xb000, 0x1),
+                &aml::OpRegion::new(
+                    "GDST".into(),
+                    aml::OpRegionSpace::SystemMemory,
+                    self.address.0 as usize,
+                    GED_DEVICE_ACPI_SIZE,
+                ),
                 &aml::Field::new(
                     "GDST".into(),
                     aml::FieldAccessType::Byte,
@@ -140,12 +151,58 @@ impl Aml for AcpiGEDDevice {
                         &aml::And::new(&aml::Local(1), &aml::Local(0), &4usize),
                         &aml::If::new(
                             &aml::Equal::new(&aml::Local(1), &4usize),
-                            vec![&aml::MethodCall::new("\\_SB_.PCI0.PCNT".into(), vec![])],
+                            vec![&aml::MethodCall::new("\\_SB_.PHPR.PSCN".into(), vec![])],
+                        ),
+                        &aml::And::new(&aml::Local(1), &aml::Local(0), &8usize),
+                        &aml::If::new(
+                            &aml::Equal::new(&aml::Local(1), &8usize),
+                            vec![&aml::Notify::new(
+                                &aml::Path::new("\\_SB_.PWRB"),
+                                &0x80usize,
+                            )],
                         ),
                     ],
                 ),
             ],
         )
-        .to_aml_bytes()
+        .append_aml_bytes(bytes)
+    }
+}
+
+pub struct AcpiPmTimerDevice {
+    start: Instant,
+}
+
+impl AcpiPmTimerDevice {
+    pub fn new() -> Self {
+        Self {
+            start: Instant::now(),
+        }
+    }
+}
+
+impl Default for AcpiPmTimerDevice {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+impl BusDevice for AcpiPmTimerDevice {
+    fn read(&mut self, _base: u64, _offset: u64, data: &mut [u8]) {
+        if data.len() != std::mem::size_of::<u32>() {
+            warn!("Invalid sized read of PM timer: {}", data.len());
+            return;
+        }
+        let now = Instant::now();
+        let since = now.duration_since(self.start);
+        let nanos = since.as_nanos();
+
+        const PM_TIMER_FREQUENCY_HZ: u128 = 3_579_545;
+        const NANOS_PER_SECOND: u128 = 1_000_000_000;
+
+        let counter = (nanos * PM_TIMER_FREQUENCY_HZ) / NANOS_PER_SECOND;
+        let counter: u32 = (counter & 0xffff_ffff) as u32;
+
+        data.copy_from_slice(&counter.to_le_bytes());
     }
 }

devices/src/gic.rs

@@ -0,0 +1,98 @@
+// Copyright 2020, ARM Limited.
+//
+// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
+
+use super::interrupt_controller::{Error, InterruptController};
+extern crate arch;
+use arch::aarch64::gic::GicDevice;
+use std::result;
+use std::sync::{Arc, Mutex};
+use vm_device::interrupt::{
+    InterruptIndex, InterruptManager, InterruptSourceConfig, InterruptSourceGroup,
+    LegacyIrqSourceConfig, MsiIrqGroupConfig,
+};
+use vmm_sys_util::eventfd::EventFd;
+
+type Result<T> = result::Result<T, Error>;
+
+// Reserve 32 IRQs for legacy device.
+pub const IRQ_LEGACY_BASE: usize = arch::layout::IRQ_BASE as usize;
+pub const IRQ_LEGACY_COUNT: usize = 32;
+
+// This Gic struct implements InterruptController to provide interrupt delivery service.
+// The Gic source files in arch/ folder maintain the Aarch64 specific Gic device.
+// The 2 Gic instances could be merged together.
+// Leave this refactoring to future. Two options may be considered:
+//   1. Move Gic*.rs from arch/ folder here.
+//   2. Move this file and ioapic.rs to arch/, as they are architecture specific.
+pub struct Gic {
+    interrupt_source_group: Arc<dyn InterruptSourceGroup>,
+    gic_device: Option<Arc<Mutex<Box<dyn GicDevice>>>>,
+}
+
+impl Gic {
+    pub fn new(
+        _vcpu_count: u8,
+        interrupt_manager: Arc<dyn InterruptManager<GroupConfig = MsiIrqGroupConfig>>,
+    ) -> Result<Gic> {
+        let interrupt_source_group = interrupt_manager
+            .create_group(MsiIrqGroupConfig {
+                base: IRQ_LEGACY_BASE as InterruptIndex,
+                count: IRQ_LEGACY_COUNT as InterruptIndex,
+            })
+            .map_err(Error::CreateInterruptSourceGroup)?;
+
+        Ok(Gic {
+            interrupt_source_group,
+            gic_device: None,
+        })
+    }
+
+    pub fn set_gic_device(&mut self, gic_device: Arc<Mutex<Box<dyn GicDevice>>>) {
+        self.gic_device = Some(gic_device);
+    }
+
+    pub fn get_gic_device(&self) -> Option<&Arc<Mutex<Box<dyn GicDevice>>>> {
+        self.gic_device.as_ref()
+    }
+}
+
+impl InterruptController for Gic {
+    fn enable(&self) -> Result<()> {
+        // Set irqfd for legacy interrupts
+        self.interrupt_source_group
+            .enable()
+            .map_err(Error::EnableInterrupt)?;
+
+        // Set irq_routing for legacy interrupts.
+        //   irqchip: Hardcode to 0 as we support only 1 GIC
+        //   pin: Use irq number as pin
+        for i in IRQ_LEGACY_BASE..(IRQ_LEGACY_BASE + IRQ_LEGACY_COUNT) {
+            let config = LegacyIrqSourceConfig {
+                irqchip: 0,
+                pin: (i - IRQ_LEGACY_BASE) as u32,
+            };
+            self.interrupt_source_group
+                .update(
+                    i as InterruptIndex,
+                    InterruptSourceConfig::LegacyIrq(config),
+                )
+                .map_err(Error::EnableInterrupt)?;
+        }
+        Ok(())
+    }
+
+    // This should be called anytime an interrupt needs to be injected into the
+    // running guest.
+    fn service_irq(&mut self, irq: usize) -> Result<()> {
+        self.interrupt_source_group
+            .trigger(irq as InterruptIndex)
+            .map_err(Error::TriggerInterrupt)?;
+
+        Ok(())
+    }
+
+    fn notifier(&self, irq: usize) -> Option<EventFd> {
+        self.interrupt_source_group.notifier(irq as InterruptIndex)
+    }
+}

devices/src/interrupt_controller.rs

@@ -0,0 +1,61 @@
+// Copyright 2020, ARM Limited.
+//
+// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
+
+use std::io;
+use std::result;
+use vmm_sys_util::eventfd::EventFd;
+
+#[derive(Debug)]
+pub enum Error {
+    /// Invalid trigger mode.
+    InvalidTriggerMode,
+    /// Invalid delivery mode.
+    InvalidDeliveryMode,
+    /// Failed creating the interrupt source group.
+    CreateInterruptSourceGroup(io::Error),
+    /// Failed triggering the interrupt.
+    TriggerInterrupt(io::Error),
+    /// Failed masking the interrupt.
+    MaskInterrupt(io::Error),
+    /// Failed unmasking the interrupt.
+    UnmaskInterrupt(io::Error),
+    /// Failed updating the interrupt.
+    UpdateInterrupt(io::Error),
+    /// Failed enabling the interrupt.
+    EnableInterrupt(io::Error),
+}
+
+type Result<T> = result::Result<T, Error>;
+
+pub struct MsiMessage {
+    // Message Address Register
+    //   31-20: Base address. Fixed value (0x0FEE)
+    //   19-12: Destination ID
+    //   11-4:  Reserved
+    //   3:     Redirection Hint indication
+    //   2:     Destination Mode
+    //   1-0:   Reserved
+    pub addr: u32,
+    // Message Data Register
+    //   32-16: Reserved
+    //   15:    Trigger Mode. 0 = Edge, 1 = Level
+    //   14:    Level. 0 = Deassert, 1 = Assert
+    //   13-11: Reserved
+    //   10-8:  Delivery Mode
+    //   7-0:   Vector
+    pub data: u32,
+}
+
+// Introduce trait InterruptController to uniform the interrupt
+// service provided for devices.
+// Device manager uses this trait without caring whether it is a
+// IOAPIC (X86) or GIC (Arm).
+pub trait InterruptController: Send {
+    fn service_irq(&mut self, irq: usize) -> Result<()>;
+    #[cfg(target_arch = "aarch64")]
+    fn enable(&self) -> Result<()>;
+    #[cfg(target_arch = "x86_64")]
+    fn end_of_interrupt(&mut self, vec: u8);
+    fn notifier(&self, irq: usize) -> Option<EventFd>;
+}

devices/src/ioapic.rs

@@ -9,47 +9,23 @@
 // Implementation of an intel 82093AA Input/Output Advanced Programmable Interrupt Controller
 // See https://pdos.csail.mit.edu/6.828/2016/readings/ia32/ioapic.pdf for a specification.
 
-use crate::BusDevice;
+use super::interrupt_controller::{Error, InterruptController};
 use anyhow::anyhow;
 use byteorder::{ByteOrder, LittleEndian};
-use std::io;
 use std::result;
-use std::sync::Arc;
+use std::sync::{Arc, Barrier};
+use versionize::{VersionMap, Versionize, VersionizeResult};
+use versionize_derive::Versionize;
 use vm_device::interrupt::{
     InterruptIndex, InterruptManager, InterruptSourceConfig, InterruptSourceGroup,
     MsiIrqGroupConfig, MsiIrqSourceConfig,
 };
+use vm_device::BusDevice;
 use vm_memory::GuestAddress;
 use vm_migration::{
-    Migratable, MigratableError, Pausable, Snapshot, SnapshotDataSection, Snapshottable,
-    Transportable,
+    Migratable, MigratableError, Pausable, Snapshot, Snapshottable, Transportable, VersionMapped,
 };
-
-#[derive(Serialize, Deserialize)]
-#[serde(remote = "GuestAddress")]
-pub struct GuestAddressDef(pub u64);
-
-#[derive(Debug)]
-pub enum Error {
-    /// Invalid destination mode.
-    InvalidDestinationMode,
-    /// Invalid trigger mode.
-    InvalidTriggerMode,
-    /// Invalid delivery mode.
-    InvalidDeliveryMode,
-    /// Failed creating the interrupt source group.
-    CreateInterruptSourceGroup(io::Error),
-    /// Failed triggering the interrupt.
-    TriggerInterrupt(io::Error),
-    /// Failed masking the interrupt.
-    MaskInterrupt(io::Error),
-    /// Failed unmasking the interrupt.
-    UnmaskInterrupt(io::Error),
-    /// Failed updating the interrupt.
-    UpdateInterrupt(io::Error),
-    /// Failed enabling the interrupt.
-    EnableInterrupt(io::Error),
-}
+use vmm_sys_util::eventfd::EventFd;
 
 type Result<T> = result::Result<T, Error>;
 
@@ -89,10 +65,12 @@ fn trigger_mode(entry: RedirectionTableEntry) -> u8 {
 fn interrupt_mask(entry: RedirectionTableEntry) -> u8 {
     ((entry >> 16) & 0x1u64) as u8
 }
-fn destination_field_physical(entry: RedirectionTableEntry) -> u8 {
-    ((entry >> 56) & 0xfu64) as u8
-}
-fn destination_field_logical(entry: RedirectionTableEntry) -> u8 {
+fn destination_field(entry: RedirectionTableEntry) -> u8 {
+    // When the destination mode is physical, the destination field should only
+    // be defined through bits 56-59, as defined in the IOAPIC specification.
+    // But from the APIC specification, the APIC ID is always defined on 8 bits
+    // no matter which destination mode is selected. That's why we always
+    // retrieve the destination field based on bits 56-63.
     ((entry >> 56) & 0xffu64) as u8
 }
 fn set_delivery_status(entry: &mut RedirectionTableEntry, val: u8) {
@@ -122,12 +100,6 @@ const IOWIN_OFF: u8 = 0x10;
 const IOWIN_SCALE: u8 = 0x2;
 const REG_MAX_OFFSET: u8 = IOWIN_OFF + (NUM_IOAPIC_PINS as u8 * 2) - 1;
 
-#[repr(u8)]
-enum DestinationMode {
-    Physical = 0,
-    Logical = 1,
-}
-
 #[repr(u8)]
 enum TriggerMode {
     Edge = 0,
@@ -138,9 +110,9 @@ enum TriggerMode {
 enum DeliveryMode {
     Fixed = 0b000,
     Lowest = 0b001,
-    SMI = 0b010,        // System management interrupt
+    Smi = 0b010,        // System management interrupt
     RemoteRead = 0b011, // This is no longer supported by intel.
-    NMI = 0b100,        // Non maskable interrupt
+    Nmi = 0b100,        // Non maskable interrupt
     Init = 0b101,
     Startup = 0b110,
     External = 0b111,
@@ -162,22 +134,25 @@ pub struct Ioapic {
     reg_entries: [RedirectionTableEntry; NUM_IOAPIC_PINS],
     used_entries: [bool; NUM_IOAPIC_PINS],
     apic_address: GuestAddress,
-    interrupt_source_group: Arc<Box<dyn InterruptSourceGroup>>,
+    interrupt_source_group: Arc<dyn InterruptSourceGroup>,
 }
 
-#[derive(Serialize, Deserialize)]
+#[derive(Versionize)]
 pub struct IoapicState {
     id_reg: u32,
     reg_sel: u32,
     reg_entries: [RedirectionTableEntry; NUM_IOAPIC_PINS],
     used_entries: [bool; NUM_IOAPIC_PINS],
-    #[serde(with = "GuestAddressDef")]
-    apic_address: GuestAddress,
+    apic_address: u64,
 }
+impl VersionMapped for IoapicState {}
 
 impl BusDevice for Ioapic {
     fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
-        assert!(data.len() == 4);
+        if data.len() != std::mem::size_of::<u32>() {
+            warn!("Invalid read size on IOAPIC: {}", data.len());
+            return;
+        }
 
         debug!("IOAPIC_R @ offset 0x{:x}", offset);
 
@@ -193,8 +168,11 @@ impl BusDevice for Ioapic {
         LittleEndian::write_u32(data, value);
     }
 
-    fn write(&mut self, _base: u64, offset: u64, data: &[u8]) {
-        assert!(data.len() == 4);
+    fn write(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
+        if data.len() != std::mem::size_of::<u32>() {
+            warn!("Invalid write size on IOAPIC: {}", data.len());
+            return None;
+        }
 
         debug!("IOAPIC_W @ offset 0x{:x}", offset);
 
@@ -207,6 +185,7 @@ impl BusDevice for Ioapic {
                 error!("IOAPIC: failed writing at offset {}", offset);
             }
         }
+        None
     }
 }
 
@@ -218,55 +197,119 @@ impl Ioapic {
     ) -> Result<Ioapic> {
         let interrupt_source_group = interrupt_manager
             .create_group(MsiIrqGroupConfig {
-                base: 0 as InterruptIndex,
+                base: 0,
                 count: NUM_IOAPIC_PINS as InterruptIndex,
             })
             .map_err(Error::CreateInterruptSourceGroup)?;
 
-        interrupt_source_group
-            .enable()
-            .map_err(Error::EnableInterrupt)?;
-
+        // The IOAPIC is created with entries already masked. The guest will be
+        // in charge of unmasking them if/when necessary.
         Ok(Ioapic {
             id,
             id_reg: 0,
             reg_sel: 0,
-            reg_entries: [0; NUM_IOAPIC_PINS],
+            reg_entries: [0x10000; NUM_IOAPIC_PINS],
             used_entries: [false; NUM_IOAPIC_PINS],
             apic_address,
             interrupt_source_group,
         })
     }
 
-    // The ioapic must be informed about EOIs in order to deassert interrupts
-    // already sent.
-    pub fn end_of_interrupt(&mut self, vec: u8) {
-        for i in 0..NUM_IOAPIC_PINS {
-            let entry = &mut self.reg_entries[i];
-            // Clear Remote IRR bit
-            if vector(*entry) == vec && trigger_mode(*entry) == 1 {
-                set_remote_irr(entry, 0);
+    fn ioapic_write(&mut self, val: u32) {
+        debug!("IOAPIC_W reg 0x{:x}, val 0x{:x}", self.reg_sel, val);
+
+        match self.reg_sel as u8 {
+            IOAPIC_REG_VERSION => {
+                if val == 0 {
+                    // Windows writes zero here (see #1791)
+                } else {
+                    error!(
+                        "IOAPIC: invalid write to version register (0x{:x}): 0x{:x}",
+                        self.reg_sel, val
+                    );
+                }
+            }
+            IOAPIC_REG_ID => self.id_reg = (val >> 24) & 0xf,
+            IOWIN_OFF..=REG_MAX_OFFSET => {
+                let (index, is_high_bits) = decode_irq_from_selector(self.reg_sel as u8);
+                if index > NUM_IOAPIC_PINS {
+                    warn!("IOAPIC index out of range: {}", index);
+                    return;
+                }
+                if is_high_bits {
+                    self.reg_entries[index] &= 0xffff_ffff;
+                    self.reg_entries[index] |= u64::from(val) << 32;
+                } else {
+                    // Ensure not to override read-only bits:
+                    // - Delivery Status (bit 12)
+                    // - Remote IRR (bit 14)
+                    self.reg_entries[index] &= 0xffff_ffff_0000_5000;
+                    self.reg_entries[index] |= u64::from(val) & 0xffff_afff;
+                }
+                // The entry must be updated through the interrupt source
+                // group.
+                if let Err(e) = self.update_entry(index) {
+                    error!("Failed updating IOAPIC entry: {:?}", e);
+                }
+                // Store the information this IRQ is now being used.
+                self.used_entries[index] = true;
+            }
+            _ => error!(
+                "IOAPIC: invalid write to register offset 0x{:x}",
+                self.reg_sel
+            ),
+        }
+    }
+
+    fn ioapic_read(&self) -> u32 {
+        debug!("IOAPIC_R reg 0x{:x}", self.reg_sel);
+
+        match self.reg_sel as u8 {
+            IOAPIC_REG_VERSION => IOAPIC_VERSION_ID,
+            IOAPIC_REG_ID | IOAPIC_REG_ARBITRATION_ID => (self.id_reg & 0xf) << 24,
+            IOWIN_OFF..=REG_MAX_OFFSET => {
+                let (index, is_high_bits) = decode_irq_from_selector(self.reg_sel as u8);
+                if index > NUM_IOAPIC_PINS {
+                    warn!("IOAPIC index out of range: {}", index);
+                    return 0;
+                }
+                if is_high_bits {
+                    (self.reg_entries[index] >> 32) as u32
+                } else {
+                    (self.reg_entries[index] & 0xffff_ffff) as u32
+                }
+            }
+            _ => {
+                error!(
+                    "IOAPIC: invalid read from register offset 0x{:x}",
+                    self.reg_sel
+                );
+                0
             }
         }
     }
 
-    // This should be called anytime an interrupt needs to be injected into the
-    // running guest.
-    pub fn service_irq(&mut self, irq: usize) -> Result<()> {
-        let entry = &mut self.reg_entries[irq];
-
-        self.interrupt_source_group
-            .trigger(irq as InterruptIndex)
-            .map_err(Error::TriggerInterrupt)?;
-        debug!("Interrupt successfully delivered");
-
-        // If trigger mode is level sensitive, set the Remote IRR bit.
-        // It will be cleared when the EOI is received.
-        if trigger_mode(*entry) == 1 {
-            set_remote_irr(entry, 1);
+    fn state(&self) -> IoapicState {
+        IoapicState {
+            id_reg: self.id_reg,
+            reg_sel: self.reg_sel,
+            reg_entries: self.reg_entries,
+            used_entries: self.used_entries,
+            apic_address: self.apic_address.0,
+        }
+    }
+
+    fn set_state(&mut self, state: &IoapicState) -> Result<()> {
+        self.id_reg = state.id_reg;
+        self.reg_sel = state.reg_sel;
+        self.reg_entries = state.reg_entries;
+        self.used_entries = state.used_entries;
+        self.apic_address = GuestAddress(state.apic_address);
+        for (irq, entry) in self.used_entries.iter().enumerate() {
+            if *entry {
+                self.update_entry(irq)?;
+            }
         }
-        // Clear the Delivery Status bit
-        set_delivery_status(entry, 0);
 
         Ok(())
     }
@@ -276,11 +319,7 @@ impl Ioapic {
 
         // Validate Destination Mode value, and retrieve Destination ID
         let destination_mode = destination_mode(entry);
-        let destination_id: u8 = match destination_mode {
-            x if x == DestinationMode::Physical as u8 => destination_field_physical(entry),
-            x if x == DestinationMode::Logical as u8 => destination_field_logical(entry),
-            _ => return Err(Error::InvalidDestinationMode),
-        };
+        let destination_id = destination_field(entry);
 
         // When this bit is set, the message is directed to the processor with
         // the lowest interrupt priority among processors that can receive the
@@ -305,9 +344,9 @@ impl Ioapic {
         match delivery_mode {
             x if (x == DeliveryMode::Fixed as u8)
                 || (x == DeliveryMode::Lowest as u8)
-                || (x == DeliveryMode::SMI as u8)
+                || (x == DeliveryMode::Smi as u8)
                 || (x == DeliveryMode::RemoteRead as u8)
-                || (x == DeliveryMode::NMI as u8)
+                || (x == DeliveryMode::Nmi as u8)
                 || (x == DeliveryMode::Init as u8)
                 || (x == DeliveryMode::Startup as u8)
                 || (x == DeliveryMode::External as u8) => {}
@@ -324,6 +363,7 @@ impl Ioapic {
             high_addr: 0x0,
             low_addr,
             data,
+            devid: 0,
         };
 
         self.interrupt_source_group
@@ -342,81 +382,45 @@ impl Ioapic {
 
         Ok(())
     }
+}
 
-    fn ioapic_write(&mut self, val: u32) {
-        debug!("IOAPIC_W reg 0x{:x}, val 0x{:x}", self.reg_sel, val);
-
-        match self.reg_sel as u8 {
-            IOAPIC_REG_ID => self.id_reg = (val >> 24) & 0xf,
-            IOWIN_OFF..=REG_MAX_OFFSET => {
-                let (index, is_high_bits) = decode_irq_from_selector(self.reg_sel as u8);
-                if is_high_bits {
-                    self.reg_entries[index] &= 0xffff_ffff;
-                    self.reg_entries[index] |= u64::from(val) << 32;
-                } else {
-                    // Ensure not to override read-only bits:
-                    // - Delivery Status (bit 12)
-                    // - Remote IRR (bit 14)
-                    self.reg_entries[index] &= 0xffff_ffff_0000_5000;
-                    self.reg_entries[index] |= u64::from(val) & 0xffff_afff;
-                }
-                // The entry must be updated through the interrupt source
-                // group.
-                if let Err(e) = self.update_entry(index) {
-                    error!("Failed updating IOAPIC entry: {:?}", e);
-                }
-                // Store the information this IRQ is now being used.
-                self.used_entries[index] = true;
-            }
-            _ => error!("IOAPIC: invalid write to register offset"),
-        }
-    }
-
-    fn ioapic_read(&self) -> u32 {
-        debug!("IOAPIC_R reg 0x{:x}", self.reg_sel);
-
-        match self.reg_sel as u8 {
-            IOAPIC_REG_VERSION => IOAPIC_VERSION_ID,
-            IOAPIC_REG_ID | IOAPIC_REG_ARBITRATION_ID => (self.id_reg & 0xf) << 24,
-            IOWIN_OFF..=REG_MAX_OFFSET => {
-                let (index, is_high_bits) = decode_irq_from_selector(self.reg_sel as u8);
-                if is_high_bits {
-                    (self.reg_entries[index] >> 32) as u32
-                } else {
-                    (self.reg_entries[index] & 0xffff_ffff) as u32
-                }
-            }
-            _ => {
-                error!("IOAPIC: invalid read from register offset");
-                0
+impl InterruptController for Ioapic {
+    // The ioapic must be informed about EOIs in order to deassert interrupts
+    // already sent.
+    fn end_of_interrupt(&mut self, vec: u8) {
+        for i in 0..NUM_IOAPIC_PINS {
+            let entry = &mut self.reg_entries[i];
+            // Clear Remote IRR bit
+            if vector(*entry) == vec && trigger_mode(*entry) == 1 {
+                set_remote_irr(entry, 0);
             }
         }
     }
 
-    fn state(&self) -> IoapicState {
-        IoapicState {
-            id_reg: self.id_reg,
-            reg_sel: self.reg_sel,
-            reg_entries: self.reg_entries,
-            used_entries: self.used_entries,
-            apic_address: self.apic_address,
-        }
-    }
+    // This should be called anytime an interrupt needs to be injected into the
+    // running guest.
+    fn service_irq(&mut self, irq: usize) -> Result<()> {
+        let entry = &mut self.reg_entries[irq];
 
-    fn set_state(&mut self, state: &IoapicState) -> Result<()> {
-        self.id_reg = state.id_reg;
-        self.reg_sel = state.reg_sel;
-        self.reg_entries = state.reg_entries;
-        self.used_entries = state.used_entries;
-        self.apic_address = state.apic_address;
-        for (irq, entry) in self.used_entries.iter().enumerate() {
-            if *entry {
-                self.update_entry(irq)?;
-            }
+        self.interrupt_source_group
+            .trigger(irq as InterruptIndex)
+            .map_err(Error::TriggerInterrupt)?;
+        debug!("Interrupt successfully delivered");
+
+        // If trigger mode is level sensitive, set the Remote IRR bit.
+        // It will be cleared when the EOI is received.
+        if trigger_mode(*entry) == 1 {
+            set_remote_irr(entry, 1);
         }
+        // Clear the Delivery Status bit
+        set_delivery_status(entry, 0);
 
         Ok(())
     }
+
+    fn notifier(&self, irq: usize) -> Option<EventFd> {
+        self.interrupt_source_group.notifier(irq as InterruptIndex)
+    }
 }
 
 impl Snapshottable for Ioapic {
@@ -424,39 +428,19 @@ impl Snapshottable for Ioapic {
         self.id.clone()
     }
 
-    fn snapshot(&self) -> std::result::Result<Snapshot, MigratableError> {
-        let snapshot =
-            serde_json::to_vec(&self.state()).map_err(|e| MigratableError::Snapshot(e.into()))?;
-
-        let mut ioapic_snapshot = Snapshot::new(self.id.as_str());
-        ioapic_snapshot.add_data_section(SnapshotDataSection {
-            id: format!("{}-section", self.id),
-            snapshot,
-        });
-
-        Ok(ioapic_snapshot)
+    fn snapshot(&mut self) -> std::result::Result<Snapshot, MigratableError> {
+        Snapshot::new_from_versioned_state(&self.id, &self.state())
     }
 
     fn restore(&mut self, snapshot: Snapshot) -> std::result::Result<(), MigratableError> {
-        if let Some(ioapic_section) = snapshot.snapshot_data.get(&format!("{}-section", self.id)) {
-            let ioapic_state = match serde_json::from_slice(&ioapic_section.snapshot) {
-                Ok(state) => state,
-                Err(error) => {
-                    return Err(MigratableError::Restore(anyhow!(
-                        "Could not deserialize IOAPIC {}",
-                        error
-                    )))
-                }
-            };
-
-            return self.set_state(&ioapic_state).map_err(|e| {
-                MigratableError::Restore(anyhow!("Could not restore IOAPIC state {:?}", e))
-            });
-        }
-
-        Err(MigratableError::Restore(anyhow!(
-            "Could not find IOAPIC snapshot section"
-        )))
+        self.set_state(&snapshot.to_versioned_state(&self.id)?)
+            .map_err(|e| {
+                MigratableError::Restore(anyhow!(
+                    "Could not restore state for {}: {:?}",
+                    self.id,
+                    e
+                ))
+            })
     }
 }
 

devices/src/legacy/cmos.rs

@@ -2,11 +2,15 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
-use libc::{gmtime_r, time, time_t, tm};
+use libc::{clock_gettime, gmtime_r, timespec, tm, CLOCK_REALTIME};
 use std::cmp::min;
 use std::mem;
+use std::sync::{Arc, Barrier};
+use vm_device::BusDevice;
 
-use crate::BusDevice;
+// https://github.com/rust-lang/libc/issues/1848
+#[cfg_attr(target_env = "musl", allow(deprecated))]
+use libc::time_t;
 
 const INDEX_MASK: u8 = 0x7f;
 const INDEX_OFFSET: u64 = 0x0;
@@ -45,16 +49,18 @@ impl Cmos {
 }
 
 impl BusDevice for Cmos {
-    fn write(&mut self, _base: u64, offset: u64, data: &[u8]) {
+    fn write(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
         if data.len() != 1 {
-            return;
+            warn!("Invalid write size on CMOS device: {}", data.len());
+            return None;
         }
 
         match offset {
             INDEX_OFFSET => self.index = data[0] & INDEX_MASK,
             DATA_OFFSET => self.data[self.index as usize] = data[0],
-            o => panic!("bad write offset on CMOS device: {}", o),
-        }
+            o => warn!("bad write offset on CMOS device: {}", o),
+        };
+        None
     }
 
     fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
@@ -64,6 +70,7 @@ impl BusDevice for Cmos {
         }
 
         if data.len() != 1 {
+            warn!("Invalid read size on CMOS device: {}", data.len());
             return;
         }
 
@@ -77,14 +84,19 @@ impl BusDevice for Cmos {
                 let day;
                 let month;
                 let year;
-                // The time and gmtime_r calls are safe as long as the structs they are given are
-                // large enough, and neither of them fail. It is safe to zero initialize the tm
-                // struct because it contains only plain data.
-                unsafe {
+                // The clock_gettime and gmtime_r calls are safe as long as the structs they are
+                // given are large enough, and neither of them fail. It is safe to zero initialize
+                // the tm and timespec struct because it contains only plain data.
+                let update_in_progress = unsafe {
+                    let mut timespec: timespec = mem::zeroed();
+                    clock_gettime(CLOCK_REALTIME, &mut timespec as *mut _);
+
+                    // https://github.com/rust-lang/libc/issues/1848
+                    #[cfg_attr(target_env = "musl", allow(deprecated))]
+                    let now: time_t = timespec.tv_sec;
                     let mut tm: tm = mem::zeroed();
-                    let mut now: time_t = 0;
-                    time(&mut now as *mut _);
                     gmtime_r(&now, &mut tm as *mut _);
+
                     // The following lines of code are safe but depend on tm being in scope.
                     seconds = tm.tm_sec;
                     minutes = tm.tm_min;
@@ -93,6 +105,11 @@ impl BusDevice for Cmos {
                     day = tm.tm_mday;
                     month = tm.tm_mon + 1;
                     year = tm.tm_year;
+
+                    // Update in Progress bit held for last 224us of each second
+                    const NANOSECONDS_PER_SECOND: i64 = 1_000_000_000;
+                    const UIP_HOLD_LENGTH: i64 = 8 * NANOSECONDS_PER_SECOND / 32768;
+                    timespec.tv_nsec >= (NANOSECONDS_PER_SECOND - UIP_HOLD_LENGTH)
                 };
                 match self.index {
                     0x00 => to_bcd(seconds as u8),
@@ -102,6 +119,11 @@ impl BusDevice for Cmos {
                     0x07 => to_bcd(day as u8),
                     0x08 => to_bcd(month as u8),
                     0x09 => to_bcd((year % 100) as u8),
+                    // Bit 5 for 32kHz clock. Bit 7 for Update in Progress
+                    0x0a => 1 << 5 | (update_in_progress as u8) << 7,
+                    // Bit 0-6 are reserved and must be 0.
+                    // Bit 7 must be 1 (CMOS has power)
+                    0x0d => 1 << 7,
                     0x32 => to_bcd(((year + 1900) / 100) as u8),
                     _ => {
                         // self.index is always guaranteed to be in range via INDEX_MASK.
@@ -109,7 +131,10 @@ impl BusDevice for Cmos {
                     }
                 }
             }
-            o => panic!("bad read offset on CMOS device: {}", o),
+            o => {
+                warn!("bad read offset on CMOS device: {}", o);
+                0
+            }
         }
     }
 }

devices/src/legacy/fwdebug.rs

@@ -7,7 +7,8 @@
 // SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
 //
 
-use BusDevice;
+use std::sync::{Arc, Barrier};
+use vm_device::BusDevice;
 
 /// Provides firmware debug output via I/O port controls
 #[derive(Default)]
@@ -30,11 +31,13 @@ impl BusDevice for FwDebugDevice {
         }
     }
 
-    fn write(&mut self, _base: u64, _offset: u64, data: &[u8]) {
+    fn write(&mut self, _base: u64, _offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
         if data.len() == 1 {
             print!("{}", data[0] as char);
         } else {
             error!("Invalid write size on debug port: {}", data.len())
         }
+
+        None
     }
 }

devices/src/legacy/gpio_pl061.rs

@@ -0,0 +1,460 @@
+// Copyright 2021 Arm Limited (or its affiliates). All rights reserved.
+//
+// SPDX-License-Identifier: Apache-2.0
+
+//! ARM PrimeCell General Purpose Input/Output(PL061)
+//!
+//! This module implements an ARM PrimeCell General Purpose Input/Output(PL061) to support gracefully poweroff microvm from external.
+//!
+
+use crate::{read_le_u32, write_le_u32};
+use std::result;
+use std::sync::{Arc, Barrier};
+use std::{fmt, io};
+use versionize::{VersionMap, Versionize, VersionizeResult};
+use versionize_derive::Versionize;
+use vm_device::interrupt::InterruptSourceGroup;
+use vm_device::BusDevice;
+use vm_migration::{
+    Migratable, MigratableError, Pausable, Snapshot, Snapshottable, Transportable, VersionMapped,
+};
+
+const OFS_DATA: u64 = 0x400; // Data Register
+const GPIODIR: u64 = 0x400; // Direction Register
+const GPIOIS: u64 = 0x404; // Interrupt Sense Register
+const GPIOIBE: u64 = 0x408; // Interrupt Both Edges Register
+const GPIOIEV: u64 = 0x40c; // Interrupt Event Register
+const GPIOIE: u64 = 0x410; // Interrupt Mask Register
+const GPIORIE: u64 = 0x414; // Raw Interrupt Status Register
+const GPIOMIS: u64 = 0x418; // Masked Interrupt Status Register
+const GPIOIC: u64 = 0x41c; // Interrupt Clear Register
+const GPIOAFSEL: u64 = 0x420; // Mode Control Select Register
+                              // From 0x424 to 0xFDC => reserved space.
+                              // From 0xFE0 to 0xFFC => Peripheral and PrimeCell Identification Registers which are Read Only registers.
+                              // Thses registers can conceptually be treated as a 32-bit register, and PartNumber[11:0] is used to identify the peripheral.
+                              // We are putting the expected values (look at 'Reset value' column from above mentioned document) in an array.
+const GPIO_ID: [u8; 8] = [0x61, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1];
+// ID Margins
+const GPIO_ID_LOW: u64 = 0xfe0;
+const GPIO_ID_HIGH: u64 = 0x1000;
+
+const N_GPIOS: u32 = 8;
+
+#[derive(Debug)]
+pub enum Error {
+    BadWriteOffset(u64),
+    GpioInterruptDisabled,
+    GpioInterruptFailure(io::Error),
+    GpioTriggerKeyFailure(u32),
+}
+
+impl fmt::Display for Error {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        match self {
+            Error::BadWriteOffset(offset) => write!(f, "Bad Write Offset: {}", offset),
+            Error::GpioInterruptDisabled => write!(f, "GPIO interrupt disabled by guest driver.",),
+            Error::GpioInterruptFailure(ref e) => {
+                write!(f, "Could not trigger GPIO interrupt: {}.", e)
+            }
+            Error::GpioTriggerKeyFailure(key) => {
+                write!(f, "Invalid GPIO Input key triggerd: {}.", key)
+            }
+        }
+    }
+}
+
+type Result<T> = result::Result<T, Error>;
+
+/// A GPIO device following the PL061 specification.
+pub struct Gpio {
+    id: String,
+    // Data Register
+    data: u32,
+    old_in_data: u32,
+    // Direction Register
+    dir: u32,
+    // Interrupt Sense Register
+    isense: u32,
+    // Interrupt Both Edges Register
+    ibe: u32,
+    // Interrupt Event Register
+    iev: u32,
+    // Interrupt Mask Register
+    im: u32,
+    // Raw Interrupt Status Register
+    istate: u32,
+    // Mode Control Select Register
+    afsel: u32,
+    // GPIO irq_field
+    interrupt: Arc<dyn InterruptSourceGroup>,
+}
+
+#[derive(Versionize)]
+pub struct GpioState {
+    data: u32,
+    old_in_data: u32,
+    dir: u32,
+    isense: u32,
+    ibe: u32,
+    iev: u32,
+    im: u32,
+    istate: u32,
+    afsel: u32,
+}
+
+impl VersionMapped for GpioState {}
+
+impl Gpio {
+    /// Constructs an PL061 GPIO device.
+    pub fn new(id: String, interrupt: Arc<dyn InterruptSourceGroup>) -> Self {
+        Self {
+            id,
+            data: 0,
+            old_in_data: 0,
+            dir: 0,
+            isense: 0,
+            ibe: 0,
+            iev: 0,
+            im: 0,
+            istate: 0,
+            afsel: 0,
+            interrupt,
+        }
+    }
+
+    fn state(&self) -> GpioState {
+        GpioState {
+            data: self.data,
+            old_in_data: self.old_in_data,
+            dir: self.dir,
+            isense: self.isense,
+            ibe: self.ibe,
+            iev: self.iev,
+            im: self.im,
+            istate: self.istate,
+            afsel: self.afsel,
+        }
+    }
+
+    fn set_state(&mut self, state: &GpioState) {
+        self.data = state.data;
+        self.old_in_data = state.old_in_data;
+        self.dir = state.dir;
+        self.isense = state.isense;
+        self.ibe = state.ibe;
+        self.iev = state.iev;
+        self.im = state.im;
+        self.istate = state.istate;
+        self.afsel = state.afsel;
+    }
+
+    fn pl061_internal_update(&mut self) {
+        // FIXME:
+        //  Missing Output Interrupt Emulation.
+
+        // Input Edging Interrupt Emulation.
+        let changed = ((self.old_in_data ^ self.data) & !self.dir) as u32;
+        if changed > 0 {
+            self.old_in_data = self.data;
+            for i in 0..N_GPIOS {
+                let mask = (1 << i) as u32;
+                if (changed & mask) > 0 {
+                    // Bits set high in GPIOIS(Interrupt sense register) configure the corresponding
+                    // pins to detect levels, otherwise, detect edges.
+                    if (self.isense & mask) == 0 {
+                        if (self.ibe & mask) > 0 {
+                            // Bits set high in GPIOIBE(Interrupt both-edges register) configure the corresponding
+                            // pins to detect both falling and rising edges.
+                            // Clearing a bit configures the pin to be controlled by GPIOIEV.
+                            self.istate |= mask;
+                        } else {
+                            // Bits set to high in GPIOIEV(Interrupt event register) configure the
+                            // corresponding pin to detect rising edges, otherwise, detect falling edges.
+                            self.istate |= !(self.data ^ self.iev) & mask;
+                        }
+                    }
+                }
+            }
+        }
+
+        // Input Level Interrupt Emulation.
+        self.istate |= !(self.data ^ self.iev) & self.isense;
+    }
+
+    fn handle_write(&mut self, offset: u64, val: u32) -> Result<()> {
+        if offset < OFS_DATA {
+            // In order to write to data register, the corresponding bits in the mask, resulting
+            // from the offsite[9:2], must be HIGH. otherwise the bit values remain unchanged.
+            let mask = (offset >> 2) as u32 & self.dir;
+            self.data = (self.data & !mask) | (val & mask);
+        } else {
+            match offset {
+                GPIODIR => {
+                    /* Direction Register */
+                    self.dir = val & 0xff;
+                }
+                GPIOIS => {
+                    /* Interrupt Sense Register */
+                    self.isense = val & 0xff;
+                }
+                GPIOIBE => {
+                    /* Interrupt Both Edges Register */
+                    self.ibe = val & 0xff;
+                }
+                GPIOIEV => {
+                    /* Interrupt Event Register */
+                    self.iev = val & 0xff;
+                }
+                GPIOIE => {
+                    /* Interrupt Mask Register */
+                    self.im = val & 0xff;
+                }
+                GPIOIC => {
+                    /* Interrupt Clear Register */
+                    self.istate &= !val;
+                }
+                GPIOAFSEL => {
+                    /* Mode Control Select Register */
+                    self.afsel = val & 0xff;
+                }
+                o => {
+                    return Err(Error::BadWriteOffset(o));
+                }
+            }
+        }
+        Ok(())
+    }
+
+    pub fn trigger_key(&mut self, key: u32) -> Result<()> {
+        let mask = (1 << key) as u32;
+        if (!self.dir & mask) > 0 {
+            // emulate key event
+            // By default, Input Pin is configured to detect both rising and falling edges.
+            // So reverse the input pin data to generate a pulse.
+            self.data |= !(self.data & mask) & mask;
+            self.pl061_internal_update();
+
+            match self.trigger_gpio_interrupt() {
+                Ok(_) | Err(Error::GpioInterruptDisabled) => return Ok(()),
+                Err(e) => return Err(e),
+            }
+        }
+
+        Err(Error::GpioTriggerKeyFailure(key))
+    }
+
+    fn trigger_gpio_interrupt(&self) -> Result<()> {
+        // Bits set to high in GPIOIE(Interrupt mask register) allow the corresponding pins to
+        // trigger their individual interrupts and then the combined GPIOINTR line.
+        if (self.istate & self.im) == 0 {
+            warn!("Failed to trigger GPIO input interrupt (disabled by guest OS)");
+            return Err(Error::GpioInterruptDisabled);
+        }
+        self.interrupt
+            .trigger(0)
+            .map_err(Error::GpioInterruptFailure)?;
+        Ok(())
+    }
+}
+
+impl BusDevice for Gpio {
+    fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
+        let value;
+        let mut read_ok = true;
+
+        if (GPIO_ID_LOW..GPIO_ID_HIGH).contains(&offset) {
+            let index = ((offset - GPIO_ID_LOW) >> 2) as usize;
+            value = u32::from(GPIO_ID[index]);
+        } else if offset < OFS_DATA {
+            value = self.data & ((offset >> 2) as u32)
+        } else {
+            value = match offset {
+                GPIODIR => self.dir,
+                GPIOIS => self.isense,
+                GPIOIBE => self.ibe,
+                GPIOIEV => self.iev,
+                GPIOIE => self.im,
+                GPIORIE => self.istate,
+                GPIOMIS => self.istate & self.im,
+                GPIOAFSEL => self.afsel,
+                _ => {
+                    read_ok = false;
+                    0
+                }
+            };
+        }
+
+        if read_ok && data.len() <= 4 {
+            write_le_u32(data, value);
+        } else {
+            warn!(
+                "Invalid GPIO PL061 read: offset {}, data length {}",
+                offset,
+                data.len()
+            );
+        }
+    }
+
+    fn write(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
+        if data.len() <= 4 {
+            let value = read_le_u32(data);
+            if let Err(e) = self.handle_write(offset, value) {
+                warn!("Failed to write to GPIO PL061 device: {}", e);
+            }
+        } else {
+            warn!(
+                "Invalid GPIO PL061 write: offset {}, data length {}",
+                offset,
+                data.len()
+            );
+        }
+
+        None
+    }
+}
+
+impl Snapshottable for Gpio {
+    fn id(&self) -> String {
+        self.id.clone()
+    }
+
+    fn snapshot(&mut self) -> std::result::Result<Snapshot, MigratableError> {
+        Snapshot::new_from_versioned_state(&self.id, &self.state())
+    }
+
+    fn restore(&mut self, snapshot: Snapshot) -> std::result::Result<(), MigratableError> {
+        self.set_state(&snapshot.to_versioned_state(&self.id)?);
+        Ok(())
+    }
+}
+
+impl Pausable for Gpio {}
+impl Transportable for Gpio {}
+impl Migratable for Gpio {}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+    use crate::{read_le_u32, write_le_u32};
+    use std::sync::Arc;
+    use vm_device::interrupt::{InterruptIndex, InterruptSourceConfig};
+    use vmm_sys_util::eventfd::EventFd;
+
+    const GPIO_NAME: &str = "gpio";
+    const LEGACY_GPIO_MAPPED_IO_START: u64 = 0x0902_0000;
+
+    struct TestInterrupt {
+        event_fd: EventFd,
+    }
+
+    impl InterruptSourceGroup for TestInterrupt {
+        fn trigger(&self, _index: InterruptIndex) -> result::Result<(), std::io::Error> {
+            self.event_fd.write(1)
+        }
+
+        fn update(
+            &self,
+            _index: InterruptIndex,
+            _config: InterruptSourceConfig,
+        ) -> result::Result<(), std::io::Error> {
+            Ok(())
+        }
+
+        fn notifier(&self, _index: InterruptIndex) -> Option<EventFd> {
+            Some(self.event_fd.try_clone().unwrap())
+        }
+    }
+
+    impl TestInterrupt {
+        fn new(event_fd: EventFd) -> Self {
+            TestInterrupt { event_fd }
+        }
+    }
+
+    #[test]
+    fn test_gpio_read_write_and_event() {
+        let intr_evt = EventFd::new(libc::EFD_NONBLOCK).unwrap();
+        let mut gpio = Gpio::new(
+            String::from(GPIO_NAME),
+            Arc::new(TestInterrupt::new(intr_evt.try_clone().unwrap())),
+        );
+        let mut data = [0; 4];
+
+        // Read and write to the GPIODIR register.
+        // Set pin 0 output pin.
+        write_le_u32(&mut data, 1);
+        gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIODIR, &data);
+        gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIODIR, &mut data);
+        let v = read_le_u32(&data);
+        assert_eq!(v, 1);
+
+        // Read and write to the GPIODATA register.
+        write_le_u32(&mut data, 1);
+        // Set pin 0 high.
+        let offset = 0x00000004_u64;
+        gpio.write(LEGACY_GPIO_MAPPED_IO_START, offset, &data);
+        gpio.read(LEGACY_GPIO_MAPPED_IO_START, offset, &mut data);
+        let v = read_le_u32(&data);
+        assert_eq!(v, 1);
+
+        // Read and write to the GPIOIS register.
+        // Configure pin 0 detecting level interrupt.
+        write_le_u32(&mut data, 1);
+        gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIS, &data);
+        gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOIS, &mut data);
+        let v = read_le_u32(&data);
+        assert_eq!(v, 1);
+
+        // Read and write to the GPIOIBE register.
+        // Configure pin 1 detecting both falling and rising edges.
+        write_le_u32(&mut data, 2);
+        gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIBE, &data);
+        gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOIBE, &mut data);
+        let v = read_le_u32(&data);
+        assert_eq!(v, 2);
+
+        // Read and write to the GPIOIEV register.
+        // Configure pin 2 detecting both falling and rising edges.
+        write_le_u32(&mut data, 4);
+        gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIEV, &data);
+        gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOIEV, &mut data);
+        let v = read_le_u32(&data);
+        assert_eq!(v, 4);
+
+        // Read and write to the GPIOIE register.
+        // Configure pin 0...2 capable of triggering their individual interrupts
+        // and then the combined GPIOINTR line.
+        write_le_u32(&mut data, 7);
+        gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIE, &data);
+        gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOIE, &mut data);
+        let v = read_le_u32(&data);
+        assert_eq!(v, 7);
+
+        let mask = 0x00000002_u32;
+        // emulate an rising pulse in pin 1.
+        gpio.data |= !(gpio.data & mask) & mask;
+        gpio.pl061_internal_update();
+        // The interrupt line on pin 1 should be on.
+        // Read the GPIOMIS register.
+        gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOMIS, &mut data);
+        let v = read_le_u32(&data);
+        assert_eq!(v, 2);
+
+        // Read and Write to the GPIOIC register.
+        // clear interrupt in pin 1.
+        write_le_u32(&mut data, 2);
+        gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIC, &data);
+        gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOIC, &mut data);
+        let v = read_le_u32(&data);
+        assert_eq!(v, 2);
+
+        // Attempts to write beyond the writable space.
+        write_le_u32(&mut data, 0);
+        gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIO_ID_LOW, &data);
+
+        let mut data = [0; 4];
+        gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIO_ID_LOW, &mut data);
+        let index = GPIO_ID_LOW + 3;
+        assert_eq!(data[0], GPIO_ID[((index - GPIO_ID_LOW) >> 2) as usize]);
+    }
+}

devices/src/legacy/i8042.rs

@@ -2,10 +2,10 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE-BSD-3-Clause file.
 
+use std::sync::{Arc, Barrier};
+use vm_device::BusDevice;
 use vmm_sys_util::eventfd::EventFd;
 
-use BusDevice;
-
 /// A i8042 PS/2 controller that emulates just enough to shutdown the machine.
 pub struct I8042Device {
     reset_evt: EventFd,
@@ -32,12 +32,14 @@ impl BusDevice for I8042Device {
         }
     }
 
-    fn write(&mut self, _base: u64, offset: u64, data: &[u8]) {
+    fn write(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
         if data.len() == 1 && data[0] == 0xfe && offset == 3 {
-            debug!("i8042 reset signalled");
+            info!("i8042 reset signalled");
             if let Err(e) = self.reset_evt.write(1) {
                 error!("Error triggering i8042 reset event: {}", e);
             }
         }
+
+        None
     }
 }

devices/src/legacy/mod.rs

@@ -9,8 +9,14 @@
 mod cmos;
 #[cfg(feature = "fwdebug")]
 mod fwdebug;
+#[cfg(target_arch = "aarch64")]
+mod gpio_pl061;
 mod i8042;
+#[cfg(target_arch = "aarch64")]
+mod rtc_pl031;
 mod serial;
+#[cfg(target_arch = "aarch64")]
+mod uart_pl011;
 
 #[cfg(feature = "cmos")]
 pub use self::cmos::Cmos;
@@ -18,3 +24,12 @@ pub use self::cmos::Cmos;
 pub use self::fwdebug::FwDebugDevice;
 pub use self::i8042::I8042Device;
 pub use self::serial::Serial;
+
+#[cfg(target_arch = "aarch64")]
+pub use self::gpio_pl061::Error as GpioDeviceError;
+#[cfg(target_arch = "aarch64")]
+pub use self::gpio_pl061::Gpio;
+#[cfg(target_arch = "aarch64")]
+pub use self::rtc_pl031::Rtc;
+#[cfg(target_arch = "aarch64")]
+pub use self::uart_pl011::Pl011;

devices/src/legacy/rtc_pl031.rs

@@ -0,0 +1,584 @@
+// Copyright 2020 Arm Limited (or its affiliates). All rights reserved.
+// Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+// SPDX-License-Identifier: Apache-2.0
+
+//! ARM PL031 Real Time Clock
+//!
+//! This module implements a PL031 Real Time Clock (RTC) that provides to provides long time base counter.
+//! This is achieved by generating an interrupt signal after counting for a programmed number of cycles of
+//! a real-time clock input.
+//!
+use crate::{read_le_u32, write_le_u32};
+use std::fmt;
+use std::sync::{Arc, Barrier};
+use std::time::Instant;
+use std::{io, result};
+use vm_device::interrupt::InterruptSourceGroup;
+use vm_device::BusDevice;
+
+// As you can see in https://static.docs.arm.com/ddi0224/c/real_time_clock_pl031_r1p3_technical_reference_manual_DDI0224C.pdf
+// at section 3.2 Summary of RTC registers, the total size occupied by this device is 0x000 -> 0xFFC + 4 = 0x1000.
+// From 0x0 to 0x1C we have following registers:
+const RTCDR: u64 = 0x0; // Data Register.
+const RTCMR: u64 = 0x4; // Match Register.
+const RTCLR: u64 = 0x8; // Load Register.
+const RTCCR: u64 = 0xc; // Control Register.
+const RTCIMSC: u64 = 0x10; // Interrupt Mask Set or Clear Register.
+const RTCRIS: u64 = 0x14; // Raw Interrupt Status.
+const RTCMIS: u64 = 0x18; // Masked Interrupt Status.
+const RTCICR: u64 = 0x1c; // Interrupt Clear Register.
+                          // From 0x020 to 0xFDC => reserved space.
+                          // From 0xFE0 to 0x1000 => Peripheral and PrimeCell Identification Registers which are Read Only registers.
+                          // AMBA standard devices have CIDs (Cell IDs) and PIDs (Peripheral IDs). The linux kernel will look for these in order to assert the identity
+                          // of these devices (i.e look at the `amba_device_try_add` function).
+                          // We are putting the expected values (look at 'Reset value' column from above mentioned document) in an array.
+const PL031_ID: [u8; 8] = [0x31, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1];
+// We are only interested in the margins.
+const AMBA_ID_LOW: u64 = 0xFE0;
+const AMBA_ID_HIGH: u64 = 0x1000;
+/// Constant to convert seconds to nanoseconds.
+pub const NANOS_PER_SECOND: u64 = 1_000_000_000;
+
+#[derive(Debug)]
+pub enum Error {
+    BadWriteOffset(u64),
+    InterruptFailure(io::Error),
+}
+
+impl fmt::Display for Error {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        match self {
+            Error::BadWriteOffset(offset) => write!(f, "Bad Write Offset: {}", offset),
+            Error::InterruptFailure(e) => write!(f, "Failed to trigger interrupt: {}", e),
+        }
+    }
+}
+
+type Result<T> = result::Result<T, Error>;
+
+/// Wrapper over `libc::clockid_t` to specify Linux Kernel clock source.
+pub enum ClockType {
+    /// Equivalent to `libc::CLOCK_MONOTONIC`.
+    Monotonic,
+    /// Equivalent to `libc::CLOCK_REALTIME`.
+    #[allow(dead_code)]
+    Real,
+    /// Equivalent to `libc::CLOCK_PROCESS_CPUTIME_ID`.
+    ProcessCpu,
+    /// Equivalent to `libc::CLOCK_THREAD_CPUTIME_ID`.
+    #[allow(dead_code)]
+    ThreadCpu,
+}
+
+impl From<ClockType> for libc::clockid_t {
+    fn from(ct: ClockType) -> libc::clockid_t {
+        match ct {
+            ClockType::Monotonic => libc::CLOCK_MONOTONIC,
+            ClockType::Real => libc::CLOCK_REALTIME,
+            ClockType::ProcessCpu => libc::CLOCK_PROCESS_CPUTIME_ID,
+            ClockType::ThreadCpu => libc::CLOCK_THREAD_CPUTIME_ID,
+        }
+    }
+}
+
+/// Structure representing the date in local time with nanosecond precision.
+pub struct LocalTime {
+    /// Seconds in current minute.
+    sec: i32,
+    /// Minutes in current hour.
+    min: i32,
+    /// Hours in current day, 24H format.
+    hour: i32,
+    /// Days in current month.
+    mday: i32,
+    /// Months in current year.
+    mon: i32,
+    /// Years passed since 1900 BC.
+    year: i32,
+    /// Nanoseconds in current second.
+    nsec: i64,
+}
+
+impl LocalTime {
+    /// Returns the [LocalTime](struct.LocalTime.html) structure for the calling moment.
+    #[allow(dead_code)]
+    pub fn now() -> LocalTime {
+        let mut timespec = libc::timespec {
+            tv_sec: 0,
+            tv_nsec: 0,
+        };
+        let mut tm: libc::tm = libc::tm {
+            tm_sec: 0,
+            tm_min: 0,
+            tm_hour: 0,
+            tm_mday: 0,
+            tm_mon: 0,
+            tm_year: 0,
+            tm_wday: 0,
+            tm_yday: 0,
+            tm_isdst: 0,
+            tm_gmtoff: 0,
+            tm_zone: std::ptr::null(),
+        };
+
+        // Safe because the parameters are valid.
+        unsafe {
+            libc::clock_gettime(libc::CLOCK_REALTIME, &mut timespec);
+            libc::localtime_r(&timespec.tv_sec, &mut tm);
+        }
+
+        LocalTime {
+            sec: tm.tm_sec,
+            min: tm.tm_min,
+            hour: tm.tm_hour,
+            mday: tm.tm_mday,
+            mon: tm.tm_mon,
+            year: tm.tm_year,
+            nsec: timespec.tv_nsec,
+        }
+    }
+}
+
+impl fmt::Display for LocalTime {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(
+            f,
+            "{}-{:02}-{:02}T{:02}:{:02}:{:02}.{:09}",
+            self.year + 1900,
+            self.mon + 1,
+            self.mday,
+            self.hour,
+            self.min,
+            self.sec,
+            self.nsec
+        )
+    }
+}
+
+/// Holds a micro-second resolution timestamp with both the real time and cpu time.
+#[derive(Clone)]
+pub struct TimestampUs {
+    /// Real time in microseconds.
+    pub time_us: u64,
+    /// Cpu time in microseconds.
+    pub cputime_us: u64,
+}
+
+impl Default for TimestampUs {
+    fn default() -> TimestampUs {
+        TimestampUs {
+            time_us: get_time(ClockType::Monotonic) / 1000,
+            cputime_us: get_time(ClockType::ProcessCpu) / 1000,
+        }
+    }
+}
+
+/// Returns a timestamp in nanoseconds from a monotonic clock.
+///
+/// Uses `_rdstc` on `x86_64` and [`get_time`](fn.get_time.html) on other architectures.
+#[allow(dead_code)]
+pub fn timestamp_cycles() -> u64 {
+    #[cfg(target_arch = "x86_64")]
+    // Safe because there's nothing that can go wrong with this call.
+    unsafe {
+        std::arch::x86_64::_rdtsc() as u64
+    }
+    #[cfg(not(target_arch = "x86_64"))]
+    {
+        get_time(ClockType::Monotonic)
+    }
+}
+
+/// Returns a timestamp in nanoseconds based on the provided clock type.
+///
+/// # Arguments
+///
+/// * `clock_type` - Identifier of the Linux Kernel clock on which to act.
+pub fn get_time(clock_type: ClockType) -> u64 {
+    let mut time_struct = libc::timespec {
+        tv_sec: 0,
+        tv_nsec: 0,
+    };
+    // Safe because the parameters are valid.
+    unsafe { libc::clock_gettime(clock_type.into(), &mut time_struct) };
+    seconds_to_nanoseconds(time_struct.tv_sec).unwrap() as u64 + (time_struct.tv_nsec as u64)
+}
+
+/// Converts a timestamp in seconds to an equivalent one in nanoseconds.
+/// Returns `None` if the conversion overflows.
+///
+/// # Arguments
+///
+/// * `value` - Timestamp in seconds.
+pub fn seconds_to_nanoseconds(value: i64) -> Option<i64> {
+    value.checked_mul(NANOS_PER_SECOND as i64)
+}
+
+/// A RTC device following the PL031 specification..
+pub struct Rtc {
+    previous_now: Instant,
+    tick_offset: i64,
+    // This is used for implementing the RTC alarm. However, in Firecracker we do not need it.
+    match_value: u32,
+    // Writes to this register load an update value into the RTC.
+    load: u32,
+    imsc: u32,
+    ris: u32,
+    interrupt: Arc<dyn InterruptSourceGroup>,
+}
+
+impl Rtc {
+    /// Constructs an AMBA PL031 RTC device.
+    pub fn new(interrupt: Arc<dyn InterruptSourceGroup>) -> Self {
+        Self {
+            // This is used only for duration measuring purposes.
+            previous_now: Instant::now(),
+            tick_offset: get_time(ClockType::Real) as i64,
+            match_value: 0,
+            load: 0,
+            imsc: 0,
+            ris: 0,
+            interrupt,
+        }
+    }
+
+    fn trigger_interrupt(&mut self) -> Result<()> {
+        self.interrupt.trigger(0).map_err(Error::InterruptFailure)?;
+        Ok(())
+    }
+
+    fn get_time(&self) -> u32 {
+        let ts = (self.tick_offset as i128)
+            + (Instant::now().duration_since(self.previous_now).as_nanos() as i128);
+        (ts / NANOS_PER_SECOND as i128) as u32
+    }
+
+    fn handle_write(&mut self, offset: u64, val: u32) -> Result<()> {
+        match offset {
+            RTCMR => {
+                // The MR register is used for implementing the RTC alarm. A real time clock alarm is
+                // a feature that can be used to allow a computer to 'wake up' after shut down to execute
+                // tasks every day or on a certain day. It can sometimes be found in the 'Power Management'
+                // section of a motherboard's BIOS setup. This is functionality that extends beyond
+                // Firecracker intended use. However, we increment a metric just in case.
+                self.match_value = val;
+            }
+            RTCLR => {
+                self.load = val;
+                self.previous_now = Instant::now();
+                // If the unwrap fails, then the internal value of the clock has been corrupted and
+                // we want to terminate the execution of the process.
+                self.tick_offset = seconds_to_nanoseconds(i64::from(val)).unwrap();
+            }
+            RTCIMSC => {
+                self.imsc = val & 1;
+                self.trigger_interrupt()?;
+            }
+            RTCICR => {
+                // As per above mentioned doc, the interrupt is cleared by writing any data value to
+                // the Interrupt Clear Register.
+                self.ris = 0;
+                self.trigger_interrupt()?;
+            }
+            RTCCR => (), // ignore attempts to turn off the timer.
+            o => {
+                return Err(Error::BadWriteOffset(o));
+            }
+        }
+        Ok(())
+    }
+}
+
+impl BusDevice for Rtc {
+    fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
+        let v;
+        let mut read_ok = true;
+
+        if (AMBA_ID_LOW..AMBA_ID_HIGH).contains(&offset) {
+            let index = ((offset - AMBA_ID_LOW) >> 2) as usize;
+            v = u32::from(PL031_ID[index]);
+        } else {
+            v = match offset {
+                RTCDR => self.get_time(),
+                RTCMR => {
+                    // Even though we are not implementing RTC alarm we return the last value
+                    self.match_value
+                }
+                RTCLR => self.load,
+                RTCCR => 1, // RTC is always enabled.
+                RTCIMSC => self.imsc,
+                RTCRIS => self.ris,
+                RTCMIS => self.ris & self.imsc,
+                _ => {
+                    read_ok = false;
+                    0
+                }
+            };
+        }
+        if read_ok && data.len() <= 4 {
+            write_le_u32(data, v);
+        } else {
+            warn!(
+                "Invalid RTC PL031 read: offset {}, data length {}",
+                offset,
+                data.len()
+            );
+        }
+    }
+
+    fn write(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
+        if data.len() <= 4 {
+            let v = read_le_u32(data);
+            if let Err(e) = self.handle_write(offset, v) {
+                warn!("Failed to write to RTC PL031 device: {}", e);
+            }
+        } else {
+            warn!(
+                "Invalid RTC PL031 write: offset {}, data length {}",
+                offset,
+                data.len()
+            );
+        }
+
+        None
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+    use crate::{
+        read_be_u16, read_be_u32, read_le_i32, read_le_u16, read_le_u32, read_le_u64, write_be_u16,
+        write_be_u32, write_le_i32, write_le_u16, write_le_u32, write_le_u64,
+    };
+    use std::sync::Arc;
+    use vm_device::interrupt::{InterruptIndex, InterruptSourceConfig};
+    use vmm_sys_util::eventfd::EventFd;
+
+    const LEGACY_RTC_MAPPED_IO_START: u64 = 0x0901_0000;
+
+    #[test]
+    fn test_get_time() {
+        for _ in 0..1000 {
+            assert!(get_time(ClockType::Monotonic) <= get_time(ClockType::Monotonic));
+        }
+
+        for _ in 0..1000 {
+            assert!(get_time(ClockType::ProcessCpu) <= get_time(ClockType::ProcessCpu));
+        }
+
+        for _ in 0..1000 {
+            assert!(get_time(ClockType::ThreadCpu) <= get_time(ClockType::ThreadCpu));
+        }
+
+        assert_ne!(get_time(ClockType::Real), 0);
+    }
+
+    #[test]
+    fn test_local_time_display() {
+        let local_time = LocalTime {
+            sec: 30,
+            min: 15,
+            hour: 10,
+            mday: 4,
+            mon: 6,
+            year: 119,
+            nsec: 123_456_789,
+        };
+        assert_eq!(
+            String::from("2019-07-04T10:15:30.123456789"),
+            local_time.to_string()
+        );
+
+        let local_time = LocalTime {
+            sec: 5,
+            min: 5,
+            hour: 5,
+            mday: 23,
+            mon: 7,
+            year: 44,
+            nsec: 123,
+        };
+        assert_eq!(
+            String::from("1944-08-23T05:05:05.000000123"),
+            local_time.to_string()
+        );
+
+        let local_time = LocalTime::now();
+        assert!(local_time.mon >= 0 && local_time.mon <= 11);
+    }
+
+    #[test]
+    fn test_seconds_to_nanoseconds() {
+        assert_eq!(
+            seconds_to_nanoseconds(100).unwrap() as u64,
+            100 * NANOS_PER_SECOND
+        );
+
+        assert!(seconds_to_nanoseconds(9_223_372_037).is_none());
+    }
+
+    struct TestInterrupt {
+        event_fd: EventFd,
+    }
+
+    impl InterruptSourceGroup for TestInterrupt {
+        fn trigger(&self, _index: InterruptIndex) -> result::Result<(), std::io::Error> {
+            self.event_fd.write(1)
+        }
+
+        fn update(
+            &self,
+            _index: InterruptIndex,
+            _config: InterruptSourceConfig,
+        ) -> result::Result<(), std::io::Error> {
+            Ok(())
+        }
+
+        fn notifier(&self, _index: InterruptIndex) -> Option<EventFd> {
+            Some(self.event_fd.try_clone().unwrap())
+        }
+    }
+
+    impl TestInterrupt {
+        fn new(event_fd: EventFd) -> Self {
+            TestInterrupt { event_fd }
+        }
+    }
+
+    #[test]
+    fn test_rtc_read_write_and_event() {
+        let intr_evt = EventFd::new(libc::EFD_NONBLOCK).unwrap();
+
+        let mut rtc = Rtc::new(Arc::new(TestInterrupt::new(intr_evt.try_clone().unwrap())));
+        let mut data = [0; 4];
+
+        // Read and write to the MR register.
+        write_le_u32(&mut data, 123);
+        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCMR, &data);
+        rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCMR, &mut data);
+        let v = read_le_u32(&data);
+        assert_eq!(v, 123);
+
+        // Read and write to the LR register.
+        let v = get_time(ClockType::Real);
+        write_le_u32(&mut data, (v / NANOS_PER_SECOND) as u32);
+        let previous_now_before = rtc.previous_now;
+        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCLR, &data);
+
+        assert!(rtc.previous_now > previous_now_before);
+
+        rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCLR, &mut data);
+        let v_read = read_le_u32(&data);
+        assert_eq!((v / NANOS_PER_SECOND) as u32, v_read);
+
+        // Read and write to IMSC register.
+        // Test with non zero value.
+        let non_zero = 1;
+        write_le_u32(&mut data, non_zero);
+        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &data);
+        // The interrupt line should be on.
+        assert!(rtc.interrupt.notifier(0).unwrap().read().unwrap() == 1);
+        rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &mut data);
+        let v = read_le_u32(&data);
+        assert_eq!(non_zero & 1, v);
+
+        // Now test with 0.
+        write_le_u32(&mut data, 0);
+        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &data);
+        rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &mut data);
+        let v = read_le_u32(&data);
+        assert_eq!(0, v);
+
+        // Read and write to the ICR register.
+        write_le_u32(&mut data, 1);
+        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCICR, &data);
+        // The interrupt line should be on.
+        assert!(rtc.interrupt.notifier(0).unwrap().read().unwrap() > 1);
+        let v_before = read_le_u32(&data);
+
+        rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCICR, &mut data);
+        let v = read_le_u32(&data);
+        // ICR is a  write only register. Data received should stay equal to data sent.
+        assert_eq!(v, v_before);
+
+        // Attempts to turn off the RTC should not go through.
+        write_le_u32(&mut data, 0);
+        rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCCR, &data);
+        rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCCR, &mut data);
+        let v = read_le_u32(&data);
+        assert_eq!(v, 1);
+
+        // Attempts to write beyond the writable space. Using here the space used to read
+        // the CID and PID from.
+        write_le_u32(&mut data, 0);
+        rtc.write(LEGACY_RTC_MAPPED_IO_START, AMBA_ID_LOW, &data);
+        // However, reading from the AMBA_ID_LOW should succeed upon read.
+
+        let mut data = [0; 4];
+        rtc.read(LEGACY_RTC_MAPPED_IO_START, AMBA_ID_LOW, &mut data);
+        let index = AMBA_ID_LOW + 3;
+        assert_eq!(data[0], PL031_ID[((index - AMBA_ID_LOW) >> 2) as usize]);
+    }
+
+    macro_rules! byte_order_test_read_write {
+        ($test_name: ident, $write_fn_name: ident, $read_fn_name: ident, $is_be: expr, $data_type: ty) => {
+            #[test]
+            fn $test_name() {
+                #[allow(overflowing_literals)]
+                let test_cases = [
+                    (
+                        0x0123_4567_89AB_CDEF as u64,
+                        [0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef],
+                    ),
+                    (
+                        0x0000_0000_0000_0000 as u64,
+                        [0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00],
+                    ),
+                    (
+                        0x1923_2345_ABF3_CCD4 as u64,
+                        [0x19, 0x23, 0x23, 0x45, 0xAB, 0xF3, 0xCC, 0xD4],
+                    ),
+                    (
+                        0x0FF0_0FF0_0FF0_0FF0 as u64,
+                        [0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0],
+                    ),
+                    (
+                        0xFFFF_FFFF_FFFF_FFFF as u64,
+                        [0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF],
+                    ),
+                    (
+                        0x89AB_12D4_C2D2_09BB as u64,
+                        [0x89, 0xAB, 0x12, 0xD4, 0xC2, 0xD2, 0x09, 0xBB],
+                    ),
+                ];
+
+                let type_size = std::mem::size_of::<$data_type>();
+                for (test_val, v_arr) in &test_cases {
+                    let v = *test_val as $data_type;
+                    let cmp_iter: Box<dyn Iterator<Item = _>> = if $is_be {
+                        Box::new(v_arr[(8 - type_size)..].iter())
+                    } else {
+                        Box::new(v_arr.iter().rev())
+                    };
+                    // test write
+                    let mut write_arr = vec![Default::default(); type_size];
+                    $write_fn_name(&mut write_arr, v);
+                    for (cmp, cur) in cmp_iter.zip(write_arr.iter()) {
+                        assert_eq!(*cmp, *cur as u8)
+                    }
+                    // test read
+                    let read_val = $read_fn_name(&write_arr);
+                    assert_eq!(v, read_val);
+                }
+            }
+        };
+    }
+
+    byte_order_test_read_write!(test_le_u16, write_le_u16, read_le_u16, false, u16);
+    byte_order_test_read_write!(test_le_u32, write_le_u32, read_le_u32, false, u32);
+    byte_order_test_read_write!(test_le_u64, write_le_u64, read_le_u64, false, u64);
+    byte_order_test_read_write!(test_le_i32, write_le_i32, read_le_i32, false, i32);
+    byte_order_test_read_write!(test_be_u16, write_be_u16, read_be_u16, true, u16);
+    byte_order_test_read_write!(test_be_u32, write_be_u32, read_be_u32, true, u32);
+}

devices/src/legacy/serial.rs

@@ -5,15 +5,15 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE-BSD-3-Clause file.
 
-use crate::BusDevice;
-use anyhow::anyhow;
 use std::collections::VecDeque;
-use std::sync::Arc;
+use std::sync::{Arc, Barrier};
 use std::{io, result};
+use versionize::{VersionMap, Versionize, VersionizeResult};
+use versionize_derive::Versionize;
 use vm_device::interrupt::InterruptSourceGroup;
+use vm_device::BusDevice;
 use vm_migration::{
-    Migratable, MigratableError, Pausable, Snapshot, SnapshotDataSection, Snapshottable,
-    Transportable,
+    Migratable, MigratableError, Pausable, Snapshot, Snapshottable, Transportable, VersionMapped,
 };
 use vmm_sys_util::errno::Result;
 
@@ -63,7 +63,7 @@ pub struct Serial {
     id: String,
     interrupt_enable: u8,
     interrupt_identification: u8,
-    interrupt: Arc<Box<dyn InterruptSourceGroup>>,
+    interrupt: Arc<dyn InterruptSourceGroup>,
     line_control: u8,
     line_status: u8,
     modem_control: u8,
@@ -74,7 +74,7 @@ pub struct Serial {
     out: Option<Box<dyn io::Write + Send>>,
 }
 
-#[derive(Serialize, Deserialize)]
+#[derive(Versionize)]
 pub struct SerialState {
     interrupt_enable: u8,
     interrupt_identification: u8,
@@ -84,13 +84,14 @@ pub struct SerialState {
     modem_status: u8,
     scratch: u8,
     baud_divisor: u16,
-    in_buffer: VecDeque<u8>,
+    in_buffer: Vec<u8>,
 }
+impl VersionMapped for SerialState {}
 
 impl Serial {
     pub fn new(
         id: String,
-        interrupt: Arc<Box<dyn InterruptSourceGroup>>,
+        interrupt: Arc<dyn InterruptSourceGroup>,
         out: Option<Box<dyn io::Write + Send>>,
     ) -> Serial {
         Serial {
@@ -112,17 +113,21 @@ impl Serial {
     /// Constructs a Serial port ready for output.
     pub fn new_out(
         id: String,
-        interrupt: Arc<Box<dyn InterruptSourceGroup>>,
+        interrupt: Arc<dyn InterruptSourceGroup>,
         out: Box<dyn io::Write + Send>,
     ) -> Serial {
         Self::new(id, interrupt, Some(out))
     }
 
     /// Constructs a Serial port with no connected output.
-    pub fn new_sink(id: String, interrupt: Arc<Box<dyn InterruptSourceGroup>>) -> Serial {
+    pub fn new_sink(id: String, interrupt: Arc<dyn InterruptSourceGroup>) -> Serial {
         Self::new(id, interrupt, None)
     }
 
+    pub fn set_out(&mut self, out: Box<dyn io::Write + Send>) {
+        self.out = Some(out);
+    }
+
     /// Queues raw bytes for the guest to read and signals the interrupt if the line status would
     /// change.
     pub fn queue_input_bytes(&mut self, c: &[u8]) -> Result<()> {
@@ -133,6 +138,13 @@ impl Serial {
         Ok(())
     }
 
+    pub fn flush_output(&mut self) -> result::Result<(), io::Error> {
+        if let Some(out) = self.out.as_mut() {
+            out.flush()?;
+        }
+        Ok(())
+    }
+
     fn is_dlab_set(&self) -> bool {
         (self.line_control & LCR_DLAB_BIT) != 0
     }
@@ -227,7 +239,7 @@ impl Serial {
             modem_status: self.modem_status,
             scratch: self.scratch,
             baud_divisor: self.baud_divisor,
-            in_buffer: self.in_buffer.clone(),
+            in_buffer: self.in_buffer.clone().into(),
         }
     }
 
@@ -240,7 +252,7 @@ impl Serial {
         self.modem_status = state.modem_status;
         self.scratch = state.scratch;
         self.baud_divisor = state.baud_divisor;
-        self.in_buffer = state.in_buffer.clone();
+        self.in_buffer = state.in_buffer.clone().into();
     }
 }
 
@@ -275,12 +287,14 @@ impl BusDevice for Serial {
         };
     }
 
-    fn write(&mut self, _base: u64, offset: u64, data: &[u8]) {
+    fn write(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
         if data.len() != 1 {
-            return;
+            return None;
         }
 
-        if let Err(_e) = self.handle_write(offset as u8, data[0]) {}
+        self.handle_write(offset as u8, data[0]).ok();
+
+        None
     }
 }
 
@@ -289,39 +303,13 @@ impl Snapshottable for Serial {
         self.id.clone()
     }
 
-    fn snapshot(&self) -> std::result::Result<Snapshot, MigratableError> {
-        let snapshot =
-            serde_json::to_vec(&self.state()).map_err(|e| MigratableError::Snapshot(e.into()))?;
-
-        let mut serial_snapshot = Snapshot::new(self.id.as_str());
-        serial_snapshot.add_data_section(SnapshotDataSection {
-            id: format!("{}-section", self.id),
-            snapshot,
-        });
-
-        Ok(serial_snapshot)
+    fn snapshot(&mut self) -> std::result::Result<Snapshot, MigratableError> {
+        Snapshot::new_from_versioned_state(&self.id, &self.state())
     }
 
     fn restore(&mut self, snapshot: Snapshot) -> std::result::Result<(), MigratableError> {
-        if let Some(serial_section) = snapshot.snapshot_data.get(&format!("{}-section", self.id)) {
-            let serial_state = match serde_json::from_slice(&serial_section.snapshot) {
-                Ok(state) => state,
-                Err(error) => {
-                    return Err(MigratableError::Restore(anyhow!(
-                        "Could not deserialize SERIAL {}",
-                        error
-                    )))
-                }
-            };
-
-            self.set_state(&serial_state);
-
-            return Ok(());
-        }
-
-        Err(MigratableError::Restore(anyhow!(
-            "Could not find the serial snapshot section"
-        )))
+        self.set_state(&snapshot.to_versioned_state(&self.id)?);
+        Ok(())
     }
 }
 
@@ -354,6 +342,9 @@ mod tests {
         ) -> result::Result<(), std::io::Error> {
             Ok(())
         }
+        fn notifier(&self, _index: InterruptIndex) -> Option<EventFd> {
+            Some(self.event_fd.try_clone().unwrap())
+        }
     }
 
     impl TestInterrupt {
@@ -390,17 +381,17 @@ mod tests {
         let serial_out = SharedBuffer::new();
         let mut serial = Serial::new_out(
             String::from(SERIAL_NAME),
-            Arc::new(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap()))),
+            Arc::new(TestInterrupt::new(intr_evt.try_clone().unwrap())),
             Box::new(serial_out.clone()),
         );
 
-        serial.write(0, DATA as u64, &['x' as u8, 'y' as u8]);
-        serial.write(0, DATA as u64, &['a' as u8]);
-        serial.write(0, DATA as u64, &['b' as u8]);
-        serial.write(0, DATA as u64, &['c' as u8]);
+        serial.write(0, DATA as u64, &[b'x', b'y']);
+        serial.write(0, DATA as u64, &[b'a']);
+        serial.write(0, DATA as u64, &[b'b']);
+        serial.write(0, DATA as u64, &[b'c']);
         assert_eq!(
             serial_out.buf.lock().unwrap().as_slice(),
-            &['a' as u8, 'b' as u8, 'c' as u8]
+            &[b'a', b'b', b'c']
         );
     }
 
@@ -410,17 +401,15 @@ mod tests {
         let serial_out = SharedBuffer::new();
         let mut serial = Serial::new_out(
             String::from(SERIAL_NAME),
-            Arc::new(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap()))),
-            Box::new(serial_out.clone()),
+            Arc::new(TestInterrupt::new(intr_evt.try_clone().unwrap())),
+            Box::new(serial_out),
         );
 
         // write 1 to the interrupt event fd, so that read doesn't block in case the event fd
         // counter doesn't change (for 0 it blocks)
         assert!(intr_evt.write(1).is_ok());
         serial.write(0, IER as u64, &[IER_RECV_BIT]);
-        serial
-            .queue_input_bytes(&['a' as u8, 'b' as u8, 'c' as u8])
-            .unwrap();
+        serial.queue_input_bytes(&[b'a', b'b', b'c']).unwrap();
 
         assert_eq!(intr_evt.read().unwrap(), 2);
 
@@ -433,11 +422,11 @@ mod tests {
         serial.read(0, LSR as u64, &mut data[..]);
         assert_ne!(data[0] & LSR_DATA_BIT, 0);
         serial.read(0, DATA as u64, &mut data[..]);
-        assert_eq!(data[0], 'a' as u8);
+        assert_eq!(data[0], b'a');
         serial.read(0, DATA as u64, &mut data[..]);
-        assert_eq!(data[0], 'b' as u8);
+        assert_eq!(data[0], b'b');
         serial.read(0, DATA as u64, &mut data[..]);
-        assert_eq!(data[0], 'c' as u8);
+        assert_eq!(data[0], b'c');
 
         // check if reading from the largest u8 offset returns 0
         serial.read(0, 0xff, &mut data[..]);
@@ -449,14 +438,14 @@ mod tests {
         let intr_evt = EventFd::new(0).unwrap();
         let mut serial = Serial::new_sink(
             String::from(SERIAL_NAME),
-            Arc::new(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap()))),
+            Arc::new(TestInterrupt::new(intr_evt.try_clone().unwrap())),
         );
 
         // write 1 to the interrupt event fd, so that read doesn't block in case the event fd
         // counter doesn't change (for 0 it blocks)
         assert!(intr_evt.write(1).is_ok());
         serial.write(0, IER as u64, &[IER_THR_BIT]);
-        serial.write(0, DATA as u64, &['a' as u8]);
+        serial.write(0, DATA as u64, &[b'a']);
 
         assert_eq!(intr_evt.read().unwrap(), 2);
         let mut data = [0u8];
@@ -471,16 +460,16 @@ mod tests {
         let intr_evt = EventFd::new(0).unwrap();
         let mut serial = Serial::new_sink(
             String::from(SERIAL_NAME),
-            Arc::new(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap()))),
+            Arc::new(TestInterrupt::new(intr_evt.try_clone().unwrap())),
         );
 
-        serial.write(0, LCR as u64, &[LCR_DLAB_BIT as u8]);
-        serial.write(0, DLAB_LOW as u64, &[0x12 as u8]);
-        serial.write(0, DLAB_HIGH as u64, &[0x34 as u8]);
+        serial.write(0, LCR as u64, &[LCR_DLAB_BIT]);
+        serial.write(0, DLAB_LOW as u64, &[0x12]);
+        serial.write(0, DLAB_HIGH as u64, &[0x34]);
 
         let mut data = [0u8];
         serial.read(0, LCR as u64, &mut data[..]);
-        assert_eq!(data[0], LCR_DLAB_BIT as u8);
+        assert_eq!(data[0], LCR_DLAB_BIT);
         serial.read(0, DLAB_LOW as u64, &mut data[..]);
         assert_eq!(data[0], 0x12);
         serial.read(0, DLAB_HIGH as u64, &mut data[..]);
@@ -492,25 +481,25 @@ mod tests {
         let intr_evt = EventFd::new(0).unwrap();
         let mut serial = Serial::new_sink(
             String::from(SERIAL_NAME),
-            Arc::new(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap()))),
+            Arc::new(TestInterrupt::new(intr_evt.try_clone().unwrap())),
         );
 
-        serial.write(0, MCR as u64, &[MCR_LOOP_BIT as u8]);
-        serial.write(0, DATA as u64, &['a' as u8]);
-        serial.write(0, DATA as u64, &['b' as u8]);
-        serial.write(0, DATA as u64, &['c' as u8]);
+        serial.write(0, MCR as u64, &[MCR_LOOP_BIT]);
+        serial.write(0, DATA as u64, &[b'a']);
+        serial.write(0, DATA as u64, &[b'b']);
+        serial.write(0, DATA as u64, &[b'c']);
 
         let mut data = [0u8];
         serial.read(0, MSR as u64, &mut data[..]);
-        assert_eq!(data[0], DEFAULT_MODEM_STATUS as u8);
+        assert_eq!(data[0], DEFAULT_MODEM_STATUS);
         serial.read(0, MCR as u64, &mut data[..]);
-        assert_eq!(data[0], MCR_LOOP_BIT as u8);
+        assert_eq!(data[0], MCR_LOOP_BIT);
         serial.read(0, DATA as u64, &mut data[..]);
-        assert_eq!(data[0], 'a' as u8);
+        assert_eq!(data[0], b'a');
         serial.read(0, DATA as u64, &mut data[..]);
-        assert_eq!(data[0], 'b' as u8);
+        assert_eq!(data[0], b'b');
         serial.read(0, DATA as u64, &mut data[..]);
-        assert_eq!(data[0], 'c' as u8);
+        assert_eq!(data[0], b'c');
     }
 
     #[test]
@@ -518,13 +507,13 @@ mod tests {
         let intr_evt = EventFd::new(0).unwrap();
         let mut serial = Serial::new_sink(
             String::from(SERIAL_NAME),
-            Arc::new(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap()))),
+            Arc::new(TestInterrupt::new(intr_evt.try_clone().unwrap())),
         );
 
-        serial.write(0, SCR as u64, &[0x12 as u8]);
+        serial.write(0, SCR as u64, &[0x12]);
 
         let mut data = [0u8];
         serial.read(0, SCR as u64, &mut data[..]);
-        assert_eq!(data[0], 0x12 as u8);
+        assert_eq!(data[0], 0x12);
     }
 }

devices/src/legacy/uart_pl011.rs

@@ -0,0 +1,493 @@
+// Copyright 2021 Arm Limited (or its affiliates). All rights reserved.
+// SPDX-License-Identifier: Apache-2.0
+
+//! ARM PrimeCell UART(PL011)
+//!
+//! This module implements an ARM PrimeCell UART(PL011).
+//!
+
+use crate::{read_le_u32, write_le_u32};
+use std::collections::VecDeque;
+use std::fmt;
+use std::sync::{Arc, Barrier};
+use std::{io, result};
+use versionize::{VersionMap, Versionize, VersionizeResult};
+use versionize_derive::Versionize;
+use vm_device::interrupt::InterruptSourceGroup;
+use vm_device::BusDevice;
+use vm_migration::{
+    Migratable, MigratableError, Pausable, Snapshot, Snapshottable, Transportable, VersionMapped,
+};
+
+/* Registers */
+const UARTDR: u64 = 0;
+const UARTRSR_UARTECR: u64 = 1;
+const UARTFR: u64 = 6;
+const UARTILPR: u64 = 8;
+const UARTIBRD: u64 = 9;
+const UARTFBRD: u64 = 10;
+const UARTLCR_H: u64 = 11;
+const UARTCR: u64 = 12;
+const UARTIFLS: u64 = 13;
+const UARTIMSC: u64 = 14;
+const UARTRIS: u64 = 15;
+const UARTMIS: u64 = 16;
+const UARTICR: u64 = 17;
+const UARTDMACR: u64 = 18;
+
+const PL011_INT_TX: u32 = 0x20;
+const PL011_INT_RX: u32 = 0x10;
+
+const PL011_FLAG_RXFF: u32 = 0x40;
+const PL011_FLAG_RXFE: u32 = 0x10;
+
+const PL011_ID: [u8; 8] = [0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1];
+// We are only interested in the margins.
+const AMBA_ID_LOW: u64 = 0x3f8;
+const AMBA_ID_HIGH: u64 = 0x401;
+
+#[derive(Debug)]
+pub enum Error {
+    BadWriteOffset(u64),
+    DmaNotImplemented,
+    InterruptFailure(io::Error),
+    WriteAllFailure(io::Error),
+    FlushFailure(io::Error),
+}
+
+impl fmt::Display for Error {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        match self {
+            Error::BadWriteOffset(offset) => write!(f, "pl011_write: Bad Write Offset: {}", offset),
+            Error::DmaNotImplemented => write!(f, "pl011: DMA not implemented."),
+            Error::InterruptFailure(e) => write!(f, "Failed to trigger interrupt: {}", e),
+            Error::WriteAllFailure(e) => write!(f, "Failed to write: {}", e),
+            Error::FlushFailure(e) => write!(f, "Failed to flush: {}", e),
+        }
+    }
+}
+
+type Result<T> = result::Result<T, Error>;
+
+/// A PL011 device following the PL011 specification.
+pub struct Pl011 {
+    id: String,
+    flags: u32,
+    lcr: u32,
+    rsr: u32,
+    cr: u32,
+    dmacr: u32,
+    int_enabled: u32,
+    int_level: u32,
+    read_fifo: VecDeque<u8>,
+    ilpr: u32,
+    ibrd: u32,
+    fbrd: u32,
+    ifl: u32,
+    read_count: u32,
+    read_trigger: u32,
+    irq: Arc<dyn InterruptSourceGroup>,
+    out: Option<Box<dyn io::Write + Send>>,
+}
+
+#[derive(Versionize)]
+pub struct Pl011State {
+    flags: u32,
+    lcr: u32,
+    rsr: u32,
+    cr: u32,
+    dmacr: u32,
+    int_enabled: u32,
+    int_level: u32,
+    read_fifo: Vec<u8>,
+    ilpr: u32,
+    ibrd: u32,
+    fbrd: u32,
+    ifl: u32,
+    read_count: u32,
+    read_trigger: u32,
+}
+
+impl VersionMapped for Pl011State {}
+
+impl Pl011 {
+    /// Constructs an AMBA PL011 UART device.
+    pub fn new(
+        id: String,
+        irq: Arc<dyn InterruptSourceGroup>,
+        out: Option<Box<dyn io::Write + Send>>,
+    ) -> Self {
+        Self {
+            id,
+            flags: 0x90u32,
+            lcr: 0u32,
+            rsr: 0u32,
+            cr: 0x300u32,
+            dmacr: 0u32,
+            int_enabled: 0u32,
+            int_level: 0u32,
+            read_fifo: VecDeque::new(),
+            ilpr: 0u32,
+            ibrd: 0u32,
+            fbrd: 0u32,
+            ifl: 0x12u32,
+            read_count: 0u32,
+            read_trigger: 1u32,
+            irq,
+            out,
+        }
+    }
+
+    pub fn set_out(&mut self, out: Box<dyn io::Write + Send>) {
+        self.out = Some(out);
+    }
+
+    fn state(&self) -> Pl011State {
+        Pl011State {
+            flags: self.flags,
+            lcr: self.lcr,
+            rsr: self.rsr,
+            cr: self.cr,
+            dmacr: self.dmacr,
+            int_enabled: self.int_enabled,
+            int_level: self.int_level,
+            read_fifo: self.read_fifo.clone().into(),
+            ilpr: self.ilpr,
+            ibrd: self.ibrd,
+            fbrd: self.fbrd,
+            ifl: self.ifl,
+            read_count: self.read_count,
+            read_trigger: self.read_trigger,
+        }
+    }
+
+    fn set_state(&mut self, state: &Pl011State) {
+        self.flags = state.flags;
+        self.lcr = state.lcr;
+        self.rsr = state.rsr;
+        self.cr = state.cr;
+        self.dmacr = state.dmacr;
+        self.int_enabled = state.int_enabled;
+        self.int_level = state.int_level;
+        self.read_fifo = state.read_fifo.clone().into();
+        self.ilpr = state.ilpr;
+        self.ibrd = state.ibrd;
+        self.fbrd = state.fbrd;
+        self.ifl = state.ifl;
+        self.read_count = state.read_count;
+        self.read_trigger = state.read_trigger;
+    }
+
+    /// Queues raw bytes for the guest to read and signals the interrupt
+    pub fn queue_input_bytes(&mut self, c: &[u8]) -> vmm_sys_util::errno::Result<()> {
+        self.read_fifo.extend(c);
+        self.read_count += c.len() as u32;
+        self.flags &= !PL011_FLAG_RXFE;
+
+        if ((self.lcr & 0x10) == 0) || (self.read_count == 16) {
+            self.flags |= PL011_FLAG_RXFF;
+        }
+
+        if self.read_count >= self.read_trigger {
+            self.int_level |= PL011_INT_RX;
+            self.trigger_interrupt()?;
+        }
+
+        Ok(())
+    }
+
+    pub fn flush_output(&mut self) -> result::Result<(), io::Error> {
+        if let Some(out) = self.out.as_mut() {
+            out.flush()?;
+        }
+        Ok(())
+    }
+
+    fn pl011_get_baudrate(&self) -> u32 {
+        if self.fbrd == 0 {
+            return 0;
+        }
+
+        let clk = 24_000_000; // We set the APB_PLCK to 24M in device tree
+        (clk / ((self.ibrd << 6) + self.fbrd)) << 2
+    }
+
+    fn pl011_trace_baudrate_change(&self) {
+        debug!(
+            "=== New baudrate: {:#?} (clk: {:#?}Hz, ibrd: {:#?}, fbrd: {:#?}) ===",
+            self.pl011_get_baudrate(),
+            24_000_000, // We set the APB_PLCK to 24M in device tree
+            self.ibrd,
+            self.fbrd
+        );
+    }
+
+    fn pl011_set_read_trigger(&mut self) {
+        self.read_trigger = 1;
+    }
+
+    fn handle_write(&mut self, offset: u64, val: u32) -> Result<()> {
+        match offset >> 2 {
+            UARTDR => {
+                self.int_level |= PL011_INT_TX;
+                if let Some(out) = self.out.as_mut() {
+                    out.write_all(&[val.to_le_bytes()[0]])
+                        .map_err(Error::WriteAllFailure)?;
+                    out.flush().map_err(Error::FlushFailure)?;
+                }
+            }
+            UARTRSR_UARTECR => {
+                self.rsr = 0;
+            }
+            UARTFR => { /* Writes to Flag register are ignored.*/ }
+            UARTILPR => {
+                self.ilpr = val;
+            }
+            UARTIBRD => {
+                self.ibrd = val;
+                self.pl011_trace_baudrate_change();
+            }
+            UARTFBRD => {
+                self.fbrd = val;
+                self.pl011_trace_baudrate_change();
+            }
+            UARTLCR_H => {
+                /* Reset the FIFO state on FIFO enable or disable */
+                if ((self.lcr ^ val) & 0x10) != 0 {
+                    self.read_count = 0;
+                }
+                self.lcr = val;
+                self.pl011_set_read_trigger();
+            }
+            UARTCR => {
+                self.cr = val;
+            }
+            UARTIFLS => {
+                self.ifl = val;
+                self.pl011_set_read_trigger();
+            }
+            UARTIMSC => {
+                self.int_enabled = val;
+                self.trigger_interrupt().map_err(Error::InterruptFailure)?;
+            }
+            UARTICR => {
+                self.int_level &= !val;
+                self.trigger_interrupt().map_err(Error::InterruptFailure)?;
+            }
+            UARTDMACR => {
+                self.dmacr = val;
+                if (val & 3) != 0 {
+                    return Err(Error::DmaNotImplemented);
+                }
+            }
+            off => {
+                return Err(Error::BadWriteOffset(off));
+            }
+        }
+        Ok(())
+    }
+
+    fn trigger_interrupt(&mut self) -> result::Result<(), io::Error> {
+        self.irq.trigger(0)
+    }
+}
+
+impl BusDevice for Pl011 {
+    fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
+        let v;
+        let mut read_ok = true;
+        if (AMBA_ID_LOW..AMBA_ID_HIGH).contains(&(offset >> 2)) {
+            let index = ((offset - 0xfe0) >> 2) as usize;
+            v = u32::from(PL011_ID[index]);
+        } else {
+            v = match offset >> 2 {
+                UARTDR => {
+                    let c: u32;
+                    let r: u32;
+
+                    self.flags &= !PL011_FLAG_RXFF;
+                    c = self.read_fifo.pop_front().unwrap_or_default().into();
+                    if self.read_count > 0 {
+                        self.read_count -= 1;
+                    }
+                    if self.read_count == 0 {
+                        self.flags |= PL011_FLAG_RXFE;
+                    }
+                    if self.read_count == (self.read_trigger - 1) {
+                        self.int_level &= !PL011_INT_RX;
+                    }
+                    self.rsr = c >> 8;
+                    r = c;
+                    r
+                }
+                UARTRSR_UARTECR => self.rsr,
+                UARTFR => self.flags,
+                UARTILPR => self.ilpr,
+                UARTIBRD => self.ibrd,
+                UARTFBRD => self.fbrd,
+                UARTLCR_H => self.lcr,
+                UARTCR => self.cr,
+                UARTIFLS => self.ifl,
+                UARTIMSC => self.int_enabled,
+                UARTRIS => self.int_level,
+                UARTMIS => (self.int_level & self.int_enabled),
+                UARTDMACR => self.dmacr,
+                _ => {
+                    read_ok = false;
+                    0
+                }
+            }
+        }
+
+        if read_ok && data.len() <= 4 {
+            write_le_u32(data, v);
+        } else {
+            warn!(
+                "Invalid PL011 read: offset {}, data length {}",
+                offset,
+                data.len()
+            );
+        }
+    }
+
+    fn write(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
+        if data.len() <= 4 {
+            let v = read_le_u32(data);
+            if let Err(e) = self.handle_write(offset, v) {
+                warn!("Failed to write to PL011 device: {}", e);
+            }
+        } else {
+            warn!(
+                "Invalid PL011 write: offset {}, data length {}",
+                offset,
+                data.len()
+            );
+        }
+
+        None
+    }
+}
+
+impl Snapshottable for Pl011 {
+    fn id(&self) -> String {
+        self.id.clone()
+    }
+
+    fn snapshot(&mut self) -> std::result::Result<Snapshot, MigratableError> {
+        Snapshot::new_from_versioned_state(&self.id, &self.state())
+    }
+
+    fn restore(&mut self, snapshot: Snapshot) -> std::result::Result<(), MigratableError> {
+        self.set_state(&snapshot.to_versioned_state(&self.id)?);
+        Ok(())
+    }
+}
+
+impl Pausable for Pl011 {}
+impl Transportable for Pl011 {}
+impl Migratable for Pl011 {}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+    use std::io;
+    use std::sync::{Arc, Mutex};
+    use vm_device::interrupt::{InterruptIndex, InterruptSourceConfig};
+    use vmm_sys_util::eventfd::EventFd;
+
+    const SERIAL_NAME: &str = "serial";
+
+    struct TestInterrupt {
+        event_fd: EventFd,
+    }
+
+    impl InterruptSourceGroup for TestInterrupt {
+        fn trigger(&self, _index: InterruptIndex) -> result::Result<(), std::io::Error> {
+            self.event_fd.write(1)
+        }
+        fn update(
+            &self,
+            _index: InterruptIndex,
+            _config: InterruptSourceConfig,
+        ) -> result::Result<(), std::io::Error> {
+            Ok(())
+        }
+        fn notifier(&self, _index: InterruptIndex) -> Option<EventFd> {
+            Some(self.event_fd.try_clone().unwrap())
+        }
+    }
+
+    impl TestInterrupt {
+        fn new(event_fd: EventFd) -> Self {
+            TestInterrupt { event_fd }
+        }
+    }
+
+    #[derive(Clone)]
+    struct SharedBuffer {
+        buf: Arc<Mutex<Vec<u8>>>,
+    }
+
+    impl SharedBuffer {
+        fn new() -> SharedBuffer {
+            SharedBuffer {
+                buf: Arc::new(Mutex::new(Vec::new())),
+            }
+        }
+    }
+
+    impl io::Write for SharedBuffer {
+        fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
+            self.buf.lock().unwrap().write(buf)
+        }
+        fn flush(&mut self) -> io::Result<()> {
+            self.buf.lock().unwrap().flush()
+        }
+    }
+
+    #[test]
+    fn pl011_output() {
+        let intr_evt = EventFd::new(0).unwrap();
+        let pl011_out = SharedBuffer::new();
+        let mut pl011 = Pl011::new(
+            String::from(SERIAL_NAME),
+            Arc::new(TestInterrupt::new(intr_evt.try_clone().unwrap())),
+            Some(Box::new(pl011_out.clone())),
+        );
+
+        pl011.write(0, UARTDR as u64, &[b'x', b'y']);
+        pl011.write(0, UARTDR as u64, &[b'a']);
+        pl011.write(0, UARTDR as u64, &[b'b']);
+        pl011.write(0, UARTDR as u64, &[b'c']);
+        assert_eq!(
+            pl011_out.buf.lock().unwrap().as_slice(),
+            &[b'x', b'a', b'b', b'c']
+        );
+    }
+
+    #[test]
+    fn pl011_input() {
+        let intr_evt = EventFd::new(0).unwrap();
+        let pl011_out = SharedBuffer::new();
+        let mut pl011 = Pl011::new(
+            String::from(SERIAL_NAME),
+            Arc::new(TestInterrupt::new(intr_evt.try_clone().unwrap())),
+            Some(Box::new(pl011_out)),
+        );
+
+        // write 1 to the interrupt event fd, so that read doesn't block in case the event fd
+        // counter doesn't change (for 0 it blocks)
+        assert!(intr_evt.write(1).is_ok());
+        pl011.queue_input_bytes(&[b'a', b'b', b'c']).unwrap();
+
+        assert_eq!(intr_evt.read().unwrap(), 2);
+
+        let mut data = [0u8];
+        pl011.read(0, UARTDR as u64, &mut data);
+        assert_eq!(data[0], b'a');
+        pl011.read(0, UARTDR as u64, &mut data);
+        assert_eq!(data[0], b'b');
+        pl011.read(0, UARTDR as u64, &mut data);
+        assert_eq!(data[0], b'c');
+    }
+}

devices/src/lib.rs

@@ -6,81 +6,90 @@
 // found in the LICENSE-BSD-3-Clause file.
 
 //! Emulates virtual and hardware devices.
-extern crate anyhow;
+
 #[macro_use]
 extern crate bitflags;
-extern crate byteorder;
-extern crate epoll;
-extern crate libc;
 #[macro_use]
 extern crate log;
-#[cfg(feature = "acpi")]
-extern crate acpi_tables;
-extern crate serde;
-extern crate vm_device;
-extern crate vm_memory;
-extern crate vm_migration;
-extern crate vmm_sys_util;
-#[macro_use]
-extern crate serde_derive;
-extern crate serde_json;
-
-use std::fs::File;
-use std::io;
 
 #[cfg(feature = "acpi")]
-mod acpi;
-mod bus;
+pub mod acpi;
+#[cfg(target_arch = "aarch64")]
+pub mod gic;
+pub mod interrupt_controller;
+#[cfg(target_arch = "x86_64")]
 pub mod ioapic;
 pub mod legacy;
 
 #[cfg(feature = "acpi")]
-pub use self::acpi::{AcpiGEDDevice, AcpiShutdownDevice};
-pub use self::bus::{Bus, BusDevice, Error as BusError};
-
-pub type DeviceEventT = u16;
-
-/// The payload is used to handle events where the internal state of the VirtIO device
-/// needs to be changed.
-pub enum EpollHandlerPayload {
-    /// DrivePayload(disk_image)
-    DrivePayload(File),
-    /// Events that do not need a payload.
-    Empty,
-}
-
-type Result<T> = std::result::Result<T, Error>;
-
-pub trait EpollHandler: Send {
-    fn handle_event(
-        &mut self,
-        device_event: DeviceEventT,
-        event_flags: u32,
-        payload: EpollHandlerPayload,
-    ) -> Result<()>;
-}
-
-#[derive(Debug)]
-pub enum Error {
-    FailedReadingQueue {
-        event_type: &'static str,
-        underlying: io::Error,
-    },
-    FailedReadTap,
-    FailedSignalingUsedQueue(io::Error),
-    PayloadExpected,
-    UnknownEvent {
-        device: &'static str,
-        event: DeviceEventT,
-    },
-    IoError(io::Error),
-}
+pub use self::acpi::{AcpiGedDevice, AcpiPmTimerDevice, AcpiShutdownDevice};
 
 bitflags! {
-    pub struct HotPlugNotificationFlags: u8 {
+    pub struct AcpiNotificationFlags: u8 {
         const NO_DEVICES_CHANGED = 0;
         const CPU_DEVICES_CHANGED = 0b1;
         const MEMORY_DEVICES_CHANGED = 0b10;
         const PCI_DEVICES_CHANGED = 0b100;
+        const POWER_BUTTON_CHANGED = 0b1000;
     }
 }
+
+#[allow(unused_macros)]
+#[cfg(target_arch = "aarch64")]
+macro_rules! generate_read_fn {
+    ($fn_name: ident, $data_type: ty, $byte_type: ty, $type_size: expr, $endian_type: ident) => {
+        #[allow(dead_code)]
+        pub fn $fn_name(input: &[$byte_type]) -> $data_type {
+            assert!($type_size == std::mem::size_of::<$data_type>());
+            let mut array = [0u8; $type_size];
+            for (byte, read) in array.iter_mut().zip(input.iter().cloned()) {
+                *byte = read as u8;
+            }
+            <$data_type>::$endian_type(array)
+        }
+    };
+}
+
+#[allow(unused_macros)]
+#[cfg(target_arch = "aarch64")]
+macro_rules! generate_write_fn {
+    ($fn_name: ident, $data_type: ty, $byte_type: ty, $endian_type: ident) => {
+        #[allow(dead_code)]
+        pub fn $fn_name(buf: &mut [$byte_type], n: $data_type) {
+            for (byte, read) in buf
+                .iter_mut()
+                .zip(<$data_type>::$endian_type(n).iter().cloned())
+            {
+                *byte = read as $byte_type;
+            }
+        }
+    };
+}
+
+#[cfg(target_arch = "aarch64")]
+generate_read_fn!(read_le_u16, u16, u8, 2, from_le_bytes);
+#[cfg(target_arch = "aarch64")]
+generate_read_fn!(read_le_u32, u32, u8, 4, from_le_bytes);
+#[cfg(target_arch = "aarch64")]
+generate_read_fn!(read_le_u64, u64, u8, 8, from_le_bytes);
+#[cfg(target_arch = "aarch64")]
+generate_read_fn!(read_le_i32, i32, i8, 4, from_le_bytes);
+
+#[cfg(target_arch = "aarch64")]
+generate_read_fn!(read_be_u16, u16, u8, 2, from_be_bytes);
+#[cfg(target_arch = "aarch64")]
+generate_read_fn!(read_be_u32, u32, u8, 4, from_be_bytes);
+
+#[cfg(target_arch = "aarch64")]
+generate_write_fn!(write_le_u16, u16, u8, to_le_bytes);
+#[cfg(target_arch = "aarch64")]
+generate_write_fn!(write_le_u32, u32, u8, to_le_bytes);
+#[cfg(target_arch = "aarch64")]
+generate_write_fn!(write_le_u64, u64, u8, to_le_bytes);
+#[cfg(target_arch = "aarch64")]
+generate_write_fn!(write_le_i32, i32, i8, to_le_bytes);
+
+#[cfg(target_arch = "aarch64")]
+generate_write_fn!(write_be_u16, u16, u8, to_be_bytes);
+#[cfg(target_arch = "aarch64")]
+generate_write_fn!(write_be_u32, u32, u8, to_be_bytes);

docs/api.md

@@ -12,7 +12,7 @@
         * [Reboot a Virtual Machine](#reboot-a-virtual-machine)
         * [Shut a Virtual Machine Down](#shut-a-virtual-machine-down)
     + [Command Line Interface](#command-line-interface)
-    + [REST API and CLI Architecural Relationship](#rest-api-and-cli-architectural-relationship)
+    + [REST API and CLI Architectural Relationship](#rest-api-and-cli-architectural-relationship)
   * [Internal API](#internal-api)
     + [Goals and Design](#goals-and-design)
   * [End to End Example](#end-to-end-example)
@@ -78,25 +78,29 @@ Shut the VMM down                   | `/vmm.shutdown` | N/A          | N/A
 
 #### Virtual Machine (VM) Actions
 
-Action                             | Endpoint            | Request Body              | Response Body     | Prerequisites
------------------------------------|---------------------|---------------------------|-------------------|---------------------------
-Create the VM                      | `/vm.create`        | `/schemas/VmConfig`       | N/A               | The VM is not created yet
-Delete the VM                      | `/vm.delete`        | N/A                       | N/A               | The VM is created but not booted
-Boot the VM                        | `/vm.boot`          | N/A                       | N/A               | The VM is created
-Shut the VM down                   | `/vm.shutdown`      | N/A                       | N/A               | The VM is booted
-Reboot the VM                      | `/vm.reboot`        | N/A                       | N/A               | The VM is booted
-Pause the VM                       | `/vm.pause`         | N/A                       | N/A               | The VM is booted
-Resume the VM                      | `/vm.resume`        | N/A                       | N/A               | The VM is paused
-Add/remove CPUs to/from the VM     | `/vm.resize`        | `/schemas/VmResize`       | N/A               | The VM is booted
-Remove memory from the VM          | `/vm.resize`        | `/schemas/VmResize`       | N/A               | The VM is booted
-Dump the VM information            | `/vm.info`          | N/A                       | `/schemas/VmInfo` | The VM is created
-Add VFIO PCI device to the VM      | `/vm.add-device`    | `/schemas/VmAddDevice`    | N/A               | The VM is booted
-Remove VFIO PCI device from the VM | `/vm.remove-device` | `/schemas/VmRemoveDevice` | N/A               | The VM is booted
-Add disk device to the VM          | `/vm.add-disk`      | `/schemas/DiskConfig`     | N/A               | The VM is booted
-Add fs device to the VM            | `/vm.add-fs`        | `/schemas/FsConfig`       | N/A               | The VM is booted
-Add pmem device to the VM          | `/vm.add-pmem`      | `/schemas/PmemConfig`     | N/A               | The VM is booted
-Add network device to the VM       | `/vm.add-net`       | `/schemas/NetConfig`      | N/A               | The VM is booted
-Add vsock device to the VM         | `/vm.add-vsock`     | `/schemas/VsockConfig`    | N/A               | The VM is booted
+Action                             | Endpoint             | Request Body              | Response Body            | Prerequisites
+-----------------------------------|----------------------|---------------------------|--------------------------|---------------------------
+Create the VM                      | `/vm.create`         | `/schemas/VmConfig`       | N/A                      | The VM is not created yet
+Delete the VM                      | `/vm.delete`         | N/A                       | N/A                      | N/A
+Boot the VM                        | `/vm.boot`           | N/A                       | N/A                      | The VM is created but not booted
+Shut the VM down                   | `/vm.shutdown`       | N/A                       | N/A                      | The VM is booted
+Reboot the VM                      | `/vm.reboot`         | N/A                       | N/A                      | The VM is booted
+Trigger power button of the VM     | `/vm.power-button`   | N/A                       | N/A                      | The VM is booted
+Pause the VM                       | `/vm.pause`          | N/A                       | N/A                      | The VM is booted
+Resume the VM                      | `/vm.resume`         | N/A                       | N/A                      | The VM is paused
+Add/remove CPUs to/from the VM     | `/vm.resize`         | `/schemas/VmResize`       | N/A                      | The VM is booted
+Add/remove memory from the VM      | `/vm.resize`         | `/schemas/VmResize`       | N/A                      | The VM is booted
+Add/remove memory from a zone      | `/vm.resize-zone`    | `/schemas/VmResizeZone`   | N/A                      | The VM is booted
+Dump the VM information            | `/vm.info`           | N/A                       | `/schemas/VmInfo`        | The VM is created
+Add VFIO PCI device to the VM      | `/vm.add-device`     | `/schemas/VmAddDevice`    | `/schemas/PciDeviceInfo` | The VM is booted
+Add disk device to the VM          | `/vm.add-disk`       | `/schemas/DiskConfig`     | `/schemas/PciDeviceInfo` | The VM is booted
+Add fs device to the VM            | `/vm.add-fs`         | `/schemas/FsConfig`       | `/schemas/PciDeviceInfo` | The VM is booted
+Add pmem device to the VM          | `/vm.add-pmem`       | `/schemas/PmemConfig`     | `/schemas/PciDeviceInfo` | The VM is booted
+Add network device to the VM       | `/vm.add-net`        | `/schemas/NetConfig`      | `/schemas/PciDeviceInfo` | The VM is booted
+Add userspace PCI device to the VM | `/vm.add-user-device`| `/schemas/VmAddUserDevice`| `/schemas/PciDeviceInfo` | The VM is booted
+Add vsock device to the VM         | `/vm.add-vsock`      | `/schemas/VsockConfig`    | `/schemas/PciDeviceInfo` | The VM is booted
+Remove device from the VM          | `/vm.remove-device`  | `/schemas/VmRemoveDevice` | N/A                      | The VM is booted
+Dump the VM counters               | `/vm.counters`       | N/A                       | `/schemas/VmCounters`    | The VM is booted
 
 ### REST API Examples
 
@@ -121,10 +125,10 @@ We want to create a virtual machine with the following characteristics:
 * 4 vCPUs
 * 1 GB of RAM
 * 1 virtio based networking interface
-* Direct kernel boot from a custom 5.5.0 Linux kernel located at
+* Direct kernel boot from a custom 5.6.0-rc4 Linux kernel located at
   `/opt/clh/kernel/vmlinux-virtio-fs-virtio-iommu`
-* Using a Clear Linux image as its root filesystem, located at
-  `/opt/clh/images/clear-30080-kvm.img`
+* Using a Ubuntu image as its root filesystem, located at
+  `/opt/clh/images/focal-server-cloudimg-amd64.raw`
 
 ```shell
 #!/bin/bash
@@ -136,8 +140,8 @@ curl --unix-socket /tmp/cloud-hypervisor.sock -i \
      -d '{
          "cpus":{"boot_vcpus": 4, "max_vcpus": 4},
          "kernel":{"path":"/opt/clh/kernel/vmlinux-virtio-fs-virtio-iommu"},
-         "cmdline":{"args":"console=hvc0 reboot=k panic=1 nomodules i8042.noaux i8042.nomux i8042.nopnp i8042.dumbkbd root=/dev/vda3"},
-         "disks":[{"path":"/opt/clh/images/clear-30080-kvm.img"}],
+         "cmdline":{"args":"console=ttyS0 console=hvc0 root=/dev/vda1 rw"},
+         "disks":[{"path":"/opt/clh/images/focal-server-cloudimg-amd64.raw"}],
          "rng":{"src":"/dev/urandom"},
          "net":[{"ip":"192.168.10.10", "mask":"255.255.255.0", "mac":"12:34:56:78:90:01"}]
          }'
@@ -274,7 +278,7 @@ are received and processed by the VMM control loop.
 In order for the VMM control loop to respond to any internal API command, it
 must be able to send a response back to the MPSC sender. For that purpose, all
 internal API command payload carry the [Sender](https://doc.rust-lang.org/std/sync/mpsc/struct.Sender.html)
-end of an [MPSC](https://doc.rust-lang.org/std/sync/mpsc/) channel. 
+end of an [MPSC](https://doc.rust-lang.org/std/sync/mpsc/) channel.
 
 The sender of any internal API command is therefore responsible for:
 
@@ -304,8 +308,8 @@ APIs work together, let's look at a complete VM creation flow, from the
 		-d '{
 			"cpus":{"boot_vcpus": 4, "max_vcpus": 4},
 			"kernel":{"path":"/opt/clh/kernel/vmlinux-virtio-fs-virtio-iommu"},
-			"cmdline":{"args":"console=hvc0 reboot=k panic=1 nomodules i8042.noaux i8042.nomux i8042.nopnp i8042.dumbkbd root=/dev/vda3"},
-			"disks":[{"path":"/opt/clh/images/clear-30080-kvm.img"}],
+			"cmdline":{"args":"console=ttyS0 console=hvc0 root=/dev/vda1 rw"},
+			"disks":[{"path":"/opt/clh/images/focal-server-cloudimg-amd64.raw"}],
 			"rng":{"src":"/dev/urandom"},
 			"net":[{"ip":"192.168.10.10", "mask":"255.255.255.0", "mac":"12:34:56:78:90:01"}]
 			}'
@@ -354,7 +358,7 @@ APIs work together, let's look at a complete VM creation flow, from the
 		   } else {
 			   Err(ApiError::VmAlreadyCreated)
 		   };
-		   
+
 	       sender.send(response).map_err(Error::ApiResponseSend)?;
 	   }
    ```
@@ -375,4 +379,3 @@ APIs work together, let's look at a complete VM creation flow, from the
    user. This is abstracted by the
    [micro_http](https://github.com/firecracker-microvm/firecracker/tree/master/src/micro_http)
    crate.
-   

docs/arm64.md

@@ -0,0 +1,141 @@
+# How to build and test Cloud Hypervisor on AArch64
+
+This document introduces how to build and test Cloud Hypervisor on AArch64
+servers. Currently Cloud Hypervisor cannot be tested on Raspberry PI. Because
+on AArch64, Cloud Hypervisor requires GICv3-ITS device for PCIe MSI interrupt
+handling. But GICv3-ITS has not been equipped on any Raspberry PI product so
+far.
+
+Now Cloud Hypervisor supports 2 ways of booting on AArch64: UEFI booting and
+direct-kernel booting. The document covers both of the ways.
+
+All the steps are based on Ubuntu. We use the Ubuntu cloud image for guest VM
+disk.
+
+## Getting started
+
+We create a folder to build and run Cloud Hypervisor at `$HOME/cloud-hypervisor`
+
+```shell
+$ export CLOUDH=$HOME/cloud-hypervisor
+$ mkdir $CLOUDH
+```
+
+## Prerequisites
+
+You need to install some prerequisite packages to build and test Cloud Hypervisor.
+
+### Tools
+
+```bash
+# Install rust tool chain
+$ curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh
+# Install the tools used for building guest kernel, EDK2 and converting guest disk
+$ sudo apt-get update
+$ sudo apt-get install git build-essential m4 bison flex uuid-dev qemu-utils
+```
+
+### Building Cloud Hypervisor
+
+```bash
+$ pushd $CLOUDH
+$ git clone https://github.com/cloud-hypervisor/cloud-hypervisor.git
+$ cd cloud-hypervisor
+$ cargo build
+$ popd
+```
+
+### Disk image
+
+Download the Ubuntu cloud image and convert the image type.
+
+```bash
+$ pushd $CLOUDH
+$ wget https://cloud-images.ubuntu.com/focal/current/focal-server-cloudimg-arm64.img
+$ qemu-img convert -p -f qcow2 -O raw focal-server-cloudimg-arm64.img focal-server-cloudimg-arm64.raw
+$ popd
+```
+
+## UEFI booting
+
+This part introduces how to build EDK2 firmware and boot Cloud Hypervisor with it.
+
+### Building EDK2
+
+```bash
+$ pushd $CLOUDH
+
+# Clone source code repos
+$ git clone --depth 1 https://github.com/tianocore/edk2.git -b master
+$ cd edk2
+$ git submodule update --init
+$ cd ..
+$ git clone --depth 1 https://github.com/tianocore/edk2-platforms.git -b master
+$ git clone --depth 1 https://github.com/acpica/acpica.git -b master
+
+# Build tools
+$ export PACKAGES_PATH="$PWD/edk2:$PWD/edk2-platforms"
+$ export IASL_PREFIX="$PWD/acpica/generate/unix/bin/"
+$ make -C acpica
+$ cd edk2/
+$ . edksetup.sh
+$ cd ..
+$ make -C edk2/BaseTools
+
+# Build EDK2
+$ build -a AARCH64 -t GCC5 -p ArmVirtPkg/ArmVirtCloudHv.dsc -b RELEASE
+
+$ popd
+```
+
+If the build goes well, the EDK2 binary is available at
+`edk2/Build/ArmVirtCloudHv-AARCH64/RELEASE_GCC5/FV/CLOUDHV_EFI.fd`.
+
+### Booting the guest VM
+
+```bash
+$ pushd $CLOUDH
+$ sudo RUST_BACKTRACE=1 $CLOUDH/cloud-hypervisor/target/debug/cloud-hypervisor \
+           --api-socket /tmp/cloud-hypervisor.sock \
+           --kernel $CLOUDH/edk2/Build/ArmVirtCloudHv-AARCH64/RELEASE_GCC5/FV/CLOUDHV_EFI.fd \
+           --disk path=$CLOUDH/focal-server-cloudimg-arm64.raw \
+           --cpus boot=4 \
+           --memory size=4096M \
+           --net tap=,mac=12:34:56:78:90:01,ip=192.168.1.1,mask=255.255.255.0 \
+           --serial tty \
+           --console off
+$ popd
+```
+
+## Direct-kernel booting
+
+Alternativelly, you can build your own kernel for guest VM. This way, UEFI is
+not involved and ACPI cannot be enabled.
+
+### Building kernel
+
+```bash
+$ pushd $CLOUDH
+$ git clone --depth 1 "https://github.com/cloud-hypervisor/linux.git" -b ch-5.12
+$ cd linux
+$ cp $CLOUDH/cloud-hypervisor/resources/linux-config-aarch64 .config
+$ make -j `nproc`
+$ popd
+```
+
+### Booting the guest VM
+
+```bash
+$ pushd $CLOUDH
+$ sudo $CLOUDH/cloud-hypervisor/target/debug/cloud-hypervisor \
+           --api-socket /tmp/cloud-hypervisor.sock \
+           --kernel $CLOUDH/linux/arch/arm64/boot/Image \
+           --disk path=focal-server-cloudimg-arm64.raw \
+           --cmdline "keep_bootcon console=ttyAMA0 reboot=k panic=1 root=/dev/vda1 rw" \
+           --cpus boot=4 \
+           --memory size=4096M \
+           --net tap=,mac=12:34:56:78:90:01,ip=192.168.1.1,mask=255.255.255.0 \
+           --serial tty \
+           --console off
+$ popd
+```

docs/cpu.md

@@ -0,0 +1,189 @@
+# CPU
+
+Cloud Hypervisor has many options when it comes to the creation of virtual
+CPUs. This document aims to explain what Cloud Hypervisor is capable of and
+how it can be used to meet the needs of very different use cases.
+
+## Options
+
+`CpusConfig` or what is known as `--cpus` from the CLI perspective is the way
+to set vCPUs options for Cloud Hypervisor.
+
+```rust
+struct CpusConfig {
+    boot_vcpus: u8,
+    max_vcpus: u8,
+    topology: Option<CpuTopology>,
+    kvm_hyperv: bool,
+    max_phys_bits: u8,
+    affinity: Option<Vec<CpuAffinity>>,
+}
+```
+
+```
+--cpus boot=<boot_vcpus>,max=<max_vcpus>,topology=<threads_per_core>:<cores_per_die>:<dies_per_package>:<packages>,kvm_hyperv=on|off,max_phys_bits=<maximum_number_of_physical_bits>,affinity=<list_of_vcpus_with_their_associated_cpuset>
+```
+
+### `boot`
+
+Number of vCPUs present at boot time.
+
+This option allows to define a specific number of vCPUs to be present at the
+time the VM is started. This option is mandatory when using the `--cpus`
+parameter. If `--cpus` is not specified, this option takes the default value
+of `1`, starting the VM with a single vCPU.
+
+Value is an unsigned integer of 8 bits.
+
+_Example_
+
+```
+--cpus boot=2
+```
+
+### `max`
+
+Maximum number of vCPUs.
+
+This option defines the maximum number of vCPUs that can be assigned to the VM.
+In particular, this option is used when looking for CPU hotplug as it lets the
+provide an indication about how many vCPUs might be needed later during the
+runtime of the VM.
+For instance, if booting the VM with 2 vCPUs and a maximum of 6 vCPUs, it means
+up to 4 vCPUs can be added later at runtime by resizing the VM.
+
+The value must be greater than or equal to the number of boot vCPUs.
+The value is an unsigned integer of 8 bits.
+
+By default this option takes the value of `boot`, meaning vCPU hotplug is not
+expected and can't be performed.
+
+_Example_
+
+```
+--cpus max=3
+```
+
+### `topology`
+
+Topology of the guest platform.
+
+This option gives the user a way to describe the exact topology that should be
+exposed to the guest. It can be useful to describe to the guest the same
+topology found on the host as it allows for proper usage of the resources and
+is a way to achieve better performances.
+
+The topology is described through the following structure:
+
+```rust
+struct CpuTopology {
+    threads_per_core: u8,
+    cores_per_die: u8,
+    dies_per_package: u8,
+    packages: u8,
+}
+```
+
+or the following syntax through the CLI:
+
+```
+topology=<threads_per_core>:<cores_per_die>:<dies_per_package>:<packages>
+```
+
+By default the topology will be `1:1:1:1`.
+
+_Example_
+
+```
+--cpus boot=2,topology=1:1:2:1
+```
+
+### `kvm_hyperv`
+
+Enable KVM Hyper-V emulation.
+
+When turned on, this option relies on KVM to emulate the synthetic interrupt
+controller (SynIC) along with synthetic timers expected by a Windows guest.
+A Windows guest usually runs on top of Microsoft Hyper-V, therefore expects
+these synthetic devices to be present. That's why KVM provides a way to emulate
+them and avoids failures running a Windows guest with Cloud Hypervisor.
+
+By default this option is turned off.
+
+_Example_
+
+```
+--cpus kvm_hyperv=on
+```
+
+### `max_phys_bits`
+
+Maximum size for guest's addressable space.
+
+This option defines the maximum number of physical bits for all vCPUs, which
+sets a limit for the size of the guest's addressable space. This is mainly
+useful for debug purpose.
+
+The value is an unsigned integer of 8 bits.
+
+_Example_
+
+```
+--cpus max_phys_bits=40
+```
+
+### `affinity`
+
+Affinity of each vCPU.
+
+This option gives the user a way to provide the host CPU set associated with
+each vCPU. It is useful for achieving CPU pinning, ensuring multiple VMs won't
+affect the performance of each other. It might also be used in the context of
+NUMA as it is way of making sure the VM can run on a specific host NUMA node.
+In general, this option is used to increase the performances of a VM depending
+on the host platform and the type of workload running in the guest.
+
+The affinity is described through the following structure:
+
+```rust
+struct CpuAffinity {
+    vcpu: u8,
+    host_cpus: Vec<u8>,
+}
+```
+
+or the following syntax through the CLI:
+
+```
+affinity=[<vcpu_id1>@[<host_cpu_id1>, <host_cpu_id2>], <vcpu_id2>@[<host_cpu_id3>, <host_cpu_id4>]]
+```
+
+The outer brackets define the list of vCPUs. And for each vCPU, the inner
+brackets attached to `@` define the list of host CPUs the vCPU is allowed to
+run onto.
+
+Multiple values can be provided to define each list. Each value is an unsigned
+integer of 8 bits.
+
+For instance, if one needs to run vCPU 0 on host CPUs from 0 to 4, the syntax
+using `-` will help define a contiguous range with `affinity=0@[0-4]`. The
+same example could also be described with `affinity=0@[0,1,2,3,4]`.
+
+A combination of both `-` and `,` separators is useful when one might need to
+describe a list containing host CPUs from 0 to 99 and the host CPU 255, as it
+could simply be described with `affinity=0@[0-99,255]`.
+
+As soon as one tries to describe a list of values, `[` and `]` must be used to
+demarcate the list.
+
+By default each vCPU runs on the entire host CPU set.
+
+_Example_
+
+```
+--cpus boot=3,affinity=[0@[2,3],1@[0,1]]
+```
+
+In this example, assuming the host has 4 CPUs, vCPU 0 will run exclusively on
+host CPUs 2 and 3, while vCPU 1 will run exclusively on host CPUs 0 and 1.
+Because nothing is defined for vCPU 2, it can run on any of the 4 host CPUs.

docs/custom-image.md

@@ -1,96 +1,149 @@
-# How to create a custom Clear Linux image
+# How to create a custom Ubuntu image
 
-In the context of adding more utility to the cloudguest image being used
-for integration testing, this is a quick guide on how to achieve the creation
-of your own Clear Linux image using the official Clear Linux tooling.
-
-## Prepare the environment
-
-From the host, the goal is run a Clear Linux VM that will allow us to build
-the custom image we want.
-
-```bash
-# Get latest CL version:
-IMG_VERSION=$(curl https://download.clearlinux.org/latest)
-# Get latest clear-kvm image:
-wget -P $HOME/workloads/ https://download.clearlinux.org/current/clear-${IMG_VERSION}-kvm.img.xz
-# Extract the image
-unxz $HOME/workloads/clear-${IMG_VERSION}-kvm.img.xz
-# Make sure cloud-hypervisor binary has CAP_NET_ADMIN capability set
-sudo setcap cap_net_admin+ep cloud-hypervisor
-# Boot cloud-hypervisor VM with the downloaded image
-./cloud-hypervisor -v --kernel $HOME/workloads/vmlinux --disk path=clear-${IMG_VERSION}-kvm.img --cmdline "console=ttyS0 console=hvc0 reboot=k panic=1 nomodules root=/dev/vda3 rw" --cpus 1 --memory size=4G --net tap=,mac=
-# Setup connectivity
-# First make sure to enable IP forwarding (disabled on Linux by default)
-sudo bash -c "echo 1 > /proc/sys/net/ipv4/ip_forward"
-# Retrieve the interface name and the gateway IP
-IFACE=$(ip route | grep default | awk -F 'dev' '{print $2}' | awk -F ' ' '{print $1}')
-GW=$(ip route | grep vmtap0 | awk -F ' ' '{print $1}')
-# Create a new masquerade rule to tag the packets going out
-sudo iptables -t nat -A POSTROUTING -s ${GW} -o ${IFACE} -j MASQUERADE
-```
+In the context of adding more utilities to the Ubuntu cloud image being used
+for integration testing, this quick guide details how to achieve the proper
+modification of an official Ubuntu cloud image.
 
 ## Create the image
 
-From the guest, we can now create the image.
+Let's go through the steps on how to extend an official Ubuntu image. These
+steps can be applied to other distributions (with a few changes regarding
+package management).
+
+### Get latest Ubuntu cloud image
 
 ```bash
-# Setup connectivity
-sudo ip addr add 192.168.249.2/24 dev enp0s3
-sudo ip route add default via 192.168.249.1
-# Install necessary bundles
-sudo swupd bundle-add clr-installer
-sudo swupd bundle-add os-installer
-# Download and update cloudguest image configuration
-wget https://download.clearlinux.org/current/config/image/cloudguest.yaml
-sed -i '/size: \"864M\"/d' cloudguest.yaml
-sed -i 's/\"800M\"/\"2G\"/g' cloudguest.yaml
-sed -i 's/bootloader,/bootloader,\n    curl,\n    iperf,/g' cloudguest.yaml
-sed -i 's/systemd-networkd-autostart/sysadmin-basic,\n    systemd-networkd-autostart/g' cloudguest.yaml
-# Create the custom cloudguest image
-clr-installer -c cloudguest.yaml
-# Make the guest accessible through ssh
-sudo mkdir -p /etc/ssh
-sudo bash -c "echo 'PermitRootLogin yes' >> /etc/ssh/sshd_config"
+wget https://cloud-images.ubuntu.com/focal/current/focal-server-cloudimg-amd64.img
 ```
 
-### Retrieve the image
-
-Once the new image has been created and the guest is accessible through
-`ssh`, it is time to retrieve the image from the host.
+### Check the file format is QCOW2
 
 ```bash
-# Retrieve new image (this is a raw image)
-scp root@192.168.249.2:cloudguest.img .
-mv cloudguest.img clear-cloudguest-raw.img
-# Create the QCOW image from the RAW image
-qemu-img convert -p -f raw -O qcow2 clear-cloudguest-raw.img clear-cloudguest.img
-# Compress the QCOW image
-xz -k -T $(nproc) clear-cloudguest.img
+file focal-server-cloudimg-amd64.img
+focal-server-cloudimg-amd64.img: QEMU QCOW2 Image (v2), 2361393152 bytes
+```
+
+### Convert QCOW2 into RAW
+
+```bash
+qemu-img convert -p -f qcow2 -O raw focal-server-cloudimg-amd64.img focal-server-cloudimg-amd64.raw
+```
+
+### Identify the Linux partition
+
+The goal is to mount the image rootfs so that it can be modified as needed.
+That's why we need to identify where the Linux filesystem partition is located
+in the image.
+
+```bash
+sudo fdisk -l focal-server-cloudimg-amd64.raw
+Disk focal-server-cloudimg-amd64.raw: 2.2 GiB, 2361393152 bytes, 4612096 sectors
+Units: sectors of 1 * 512 = 512 bytes
+Sector size (logical/physical): 512 bytes / 512 bytes
+I/O size (minimum/optimal): 512 bytes / 512 bytes
+Disklabel type: gpt
+Disk identifier: A1171ABA-2BEA-4218-A467-1B2B607E5953
+
+Device                             Start     End Sectors  Size Type
+focal-server-cloudimg-amd64.raw1  227328 4612062 4384735  2.1G Linux filesystem
+focal-server-cloudimg-amd64.raw14   2048   10239    8192    4M BIOS boot
+focal-server-cloudimg-amd64.raw15  10240  227327  217088  106M EFI System
+
+Partition table entries are not in disk order.
+```
+
+### Mount the Linux partition
+
+```bash
+mkdir -p /mnt
+sudo mount -o loop,offset=$((227328 * 512)) focal-server-cloudimg-amd64.raw /mnt
+```
+
+### Change root directory
+
+Changing the root directory will allow us to install new packages to the rootfs
+contained by the cloud image.
+
+```bash
+sudo chroot /mnt
+mount -t proc proc /proc
+mount -t devpts devpts /dev/pts
+```
+
+### Install needed packages
+
+In the context Cloud Hypervisor's integration tests, we need several utilities.
+Here is the way to install them for a Ubuntu image. This step is specific to
+Ubuntu distributions.
+
+```bash
+apt update
+apt install fio iperf iperf3 socat stress
+```
+
+### Remove counterproductive packages
+
+* snapd:
+
+This prevents snapd from trying to mount squashfs filesystem when the kernel
+might not support it. This might be the case when the image is used with direct
+kernel boot. This step is specific to Ubuntu distributions.
+
+* pollinate:
+
+Remove this package which can fail and lead to the SSH daemon failing to start.
+See #2113 for details.
+
+```bash
+apt remove --purge snapd pollinate
+```
+
+
+### Cleanup the image
+
+Leave no trace in the image before unmounting its content.
+
+```bash
+umount /dev/pts
+umount /proc
+history -c
+exit
+umount /mnt
+```
+
+### Rename the image
+
+Renaming is important to identify this is a modified image.
+
+```bash
+mv focal-server-cloudimg-amd64.raw focal-server-cloudimg-amd64-custom-$(date "+%Y%m%d")-0.raw
+```
+
+The `-0` is the revision and is only necessary to change if multiple images are
+updated on the same day.
+
+### Create QCOW2 from RAW
+
+Last step is to create the QCOW2 image back from the modified image.
+
+```bash
+qemu-img convert -p -f raw -O qcow2 focal-server-cloudimg-amd64-custom-$(date "+%Y%m%d")-0.raw focal-server-cloudimg-amd64-custom-$(date "+%Y%m%d")-0.qcow2
 ```
 
 ## Switch CI to use the new image
 
 ### Upload to Azure storage
 
-The next step is to update the image stored as part of the Azure storage
-account, replacing it with the newly created image. This will make this
-new image available from the integration tests.
-This is usually achieved through the web interface.
+The next step is to update both images (QCOW2 and RAW) stored as part of the
+Azure storage account, replacing them with the newly created ones. This will
+make these new images available from the integration tests. This is usually
+achieved through the web interface.
 
 ### Update integration tests
 
 Last step is about updating the integration tests to work with this new image.
-The key point is to identify the UUID of this new image so that it can be used
-directly from the tests.
+The key point is to identify where the Linux filesystem partition is located,
+as we might need to update the direct kernel boot command line, replacing
+`/dev/vda1` with the appropriate partition number.
 
-Proceed as follow to determine this UUID:
-
-```bash
-# Mount the image
-sudo mount -o loop,offset=$((2048 * 512)) clear-cloudguest-raw.img /mnt/
-# Identify UUID
-sudo cat /mnt/loader/entries/Clear-linux-kvm-*.conf | grep "root=PARTUUID="
-# Unmount the image
-sudo umount /mnt
-```
+Update all references to the previous image name to the new one.

docs/debug-port.md

@@ -43,7 +43,7 @@ to easily grep for the tracing logs (e.g.
 ```
 ./target/debug/cloud-hypervisor \
     --kernel ~/rust-hypervisor-firmware/target/target/release/hypervisor-fw \
-    --disk path=~/hypervisor/images/clear-30080-kvm.img \
+    --disk path=~/hypervisor/images/focal-server-cloudimg-amd64.raw \
     --cpus 4 \
     --memory size=1024M \
     --rng \

docs/device_model.md

@@ -28,9 +28,13 @@ This document describes the device model supported by `cloud-hypervisor`.
 ### Serial port
 
 Simple emulation of a serial port by reading and writing to specific port I/O
-addresses. Used as the default console for Linux when booting with the option
-`console=ttyS0`, the serial port can be very useful to gather early logs from
-the operating system booted inside the VM.
+addresses. The serial port can be very useful to gather early logs from the
+operating system booted inside the VM.
+
+For x86_64, The default serial port is from an emulated 16550A device. It can
+be used as the default console for Linux when booting with the option
+`console=ttyS0`. For AArch64, the default serial port is from an emulated
+PL011 UART device. The related command line for AArch64 is `console=ttyAMA0`.
 
 This device is always built-in, and it is disabled by default. It can be
 enabled with the `--serial` option, as long as its parameter is not `off`.
@@ -44,6 +48,10 @@ This device is built-in by default, but it can be compiled out with Rust
 features. When compiled in, it is always enabled, and cannot be disabled
 from the command line.
 
+For AArch64 machines, an ARM PrimeCell Real Time Clock(PL031) is implemented.
+This device is built-in by default for the AArch64 platform, and it is always
+enabled, and cannot be disabled from the command line.
+
 ### I/O APIC
 
 `cloud-hypervisor` supports a so-called split IRQ chip implementation by
@@ -65,6 +73,11 @@ enabled by default, the handling of reboot/shutdown goes through the dedicated
 ACPI device. In case ACPI is disabled, this device is enabled to bring to the
 VM some reboot/shutdown support.
 
+### ARM PrimeCell General Purpose Input/Output (PL061)
+
+Simplified ARM PrimeCell GPIO (PL061) implementation. Only supports key 3 to
+trigger a graceful shutdown of the AArch64 guest.
+
 ### ACPI device
 
 This is a dedicated device for handling ACPI shutdown and reboot when ACPI is
@@ -75,12 +88,8 @@ feature is enabled by default.
 
 ## Virtio devices
 
-For all virtio devices listed below, both `virtio-mmio` and `virtio-pci`
-transport layers are supported, `virtio-pci` being the default.
-
-Both `virtio-mmio` and `virtio-pci` can be compiled out. `virtio-pci` is
-built-in by default, and enabled by default. If both transport layers were
-built at the same time, `virtio-pci` would be the default transport layer.
+For all virtio devices listed below, only `virtio-pci` transport layer is
+supported.
 
 ### virtio-block
 
@@ -104,9 +113,8 @@ selecting `--serial tty --console off` from the command line.
 ### virtio-iommu
 
 As we want to improve our nested guests support, we added support for exposing
-a [paravirtualized IOMMU](https://github.com/cloud-hypervisor/cloud-hypervisor/blob/master/docs/iommu.md)
-device through virtio. This allows for a safer nested virtio and directly
-assigned devices support.
+a [paravirtualized IOMMU](iommu.md) device through virtio. This allows for a
+safer nested virtio and directly assigned devices support.
 
 This device is always built-in, and it is enabled based on the presence of the
 parameter `iommu=on` in any of the virtio or VFIO devices. If at least one of
@@ -175,8 +183,8 @@ This device is always built-in, and it is enabled when `vhost_user=true` and
 shared file system, allowing for an efficient and reliable way of sharing
 a filesystem between the host and the cloud-hypervisor guest.
 
-See our [filesystem sharing](https://github.com/cloud-hypervisor/cloud-hypervisor/blob/master/docs/fs.md)
-documentation for more details on how to use virtio-fs with cloud-hypervisor.
+See our [filesystem sharing](fs.md) documentation for more details on how to
+use virtio-fs with cloud-hypervisor.
 
 This device is always built-in, and it is enabled based on the presence of the
 flag `--fs`.
@@ -197,9 +205,8 @@ VFIO (Virtual Function I/O) is a kernel framework that exposes direct device
 access to userspace. `cloud-hypervisor` uses VFIO to directly assign host
 physical devices into its guest.
 
-See our [VFIO documentation](https://github.com/cloud-hypervisor/cloud-hypervisor/blob/master/docs/vfio.md)
-for more details on how to directly assign host devices to `cloud-hypervisor`
-guests.
+See our [VFIO documentation](vfio.md) for more details on how to directly
+assign host devices to `cloud-hypervisor` guests.
 
 Because VFIO implies `vfio-pci` in the `cloud-hypervisor` context, the VFIO
 support is built-in when the `pci` feature is selected. And because the `pci`

docs/fs.md

@@ -12,7 +12,7 @@ This virtual device relies on the _vhost-user_ protocol, which assumes the backe
 
 _Build virtiofsd_
 ```bash
-git clone --depth 1 "https://github.com/sboeuf/qemu.git" -b "virtio-fs" $VIRTIOFSD_DIR
+git clone --depth 1 "https://gitlab.com/virtio-fs/qemu.git" -b "qemu5.0-virtiofs-dax" $VIRTIOFSD_DIR
 cd $VIRTIOFSD_DIR
 ./configure --prefix=$PWD --target-list=x86_64-softmmu
 make virtiofsd -j `nproc`
@@ -35,45 +35,42 @@ The `cache=none` option should be the default when using `virtiofsd` with the __
 
 The `cache=always` option will allow for the guest page cache to be used, which will increase the memory footprint of the guest. This option should be used only for specific use cases where a single VM is going to be running on a host.
 
-### The kernel
+### Kernel support
 
-In order to leverage __virtio-fs__ support from within the guest, and because the code has not been merged in upstream Linux kernel yet, it is required to build a custom kernel embedding the patches.
-
-The following branch `virtio-fs-virtio-iommu` on the repository https://github.com/cloud-hypervisor/linux.git includes all the needed patches to support __virtio-fs__.
-
-Make sure to build a kernel out of this branch that can be then used to boot the VM.
+Modern Linux kernels starting (at least v5.10) have support for virtio-fs. Use
+of older kernels, with additional patches, are not supported.
 
 ## How to share directories with cloud-hypervisor
 
 ### Start the VM
 Once the daemon is running, the option `--fs` from __cloud-hypervisor__ needs to be used.
 
-Direct kernel boot option is preferred since we need to provide the custom kernel including the __virtio-fs__ patches. We could boot from `hypervisor-fw` if we had previously edited the image to replace the kernel binary.
+Direct kernel boot is the preferred option, but we can boot from an EFI cloud image if it contains a recent enough kernel.
 
-Because _vhost-user_ expects a dedicated process (__virtiofsd__ in this case) to be able to access the guest RAM to communicate through the _virtqueues_ with the driver running in the guest, `--memory` option needs to be slightly modified. It needs to specify a backing file for the memory so that an external process can access it.
+Because _vhost-user_ expects a dedicated process (__virtiofsd__ in this case) to be able to access the guest RAM to communicate through the _virtqueues_ with the driver running in the guest, `--memory` option needs to be slightly modified. It must specify `shared=on` to share the memory pages so that an external process can access them.
 
-Assuming you have `clear-kvm.img` and `custom-vmlinux.bin` on your system, here is the __cloud-hypervisor__ command you need to run:
+Assuming you have `focal-server-cloudimg-amd64.raw` and `vmlinux` on your system, here is the __cloud-hypervisor__ command you need to run:
 ```bash
 ./cloud-hypervisor \
-    --cpus 4 \
-    --memory "size=512,file=/dev/shm" \
-    --disk path=clear-kvm.img \
-    --kernel custom-vmlinux.bin \
-    --cmdline "console=ttyS0 reboot=k panic=1 nomodules root=/dev/vda3" \ 
-    --fs tag=myfs,sock=/tmp/virtiofs,num_queues=1,queue_size=512
+    --cpus boot=1 \
+    --memory size=1G,shared=on \
+    --disk path=focal-server-cloudimg-amd64.raw \
+    --kernel vmlinux \
+    --cmdline "console=hvc0 root=/dev/vda1 rw" \
+    --fs tag=myfs,socket=/tmp/virtiofs,num_queues=1,queue_size=512
 ```
 
 By default, DAX is enabled with a cache window of 8GiB. You can specify a custom size (let's say 4GiB for this example) for the cache by explicitly setting DAX and the cache size:
 
 ```bash
---fs tag=virtiofs,sock=/tmp/virtiofs,num_queues=1,queue_size=512,dax=on,cache_size=4G
+--fs tag=myfs,socket=/tmp/virtiofs,num_queues=1,queue_size=512,dax=on,cache_size=4G
 
 ```
 
 In case you don't want to use a shared window of cache to pass the shared files content, this means you will have to explicitly disable DAX with `dax=off`. Note that in this case, the `cache_size` parameter will be ignored.
 
 ```bash
---fs tag=virtiofs,sock=/tmp/virtiofs,num_queues=1,queue_size=512,dax=off
+--fs tag=myfs,socket=/tmp/virtiofs,num_queues=1,queue_size=512,dax=off
 
 ```
 

docs/fuzzing.md

@@ -0,0 +1,35 @@
+# Fuzzing in Cloud Hypervisor
+
+Cloud Hypervisor uses [cargo-fuzz](https://github.com/rust-fuzz/cargo-fuzz) for fuzzing individual components.
+
+The fuzzers are are in the `fuzz/fuzz_targets` directory
+
+## Preparation
+
+Switch to nightly: 
+
+````
+rustup override set nightly
+````
+
+Install `cargo fuzz`: 
+
+```
+cargo install cargo-fuzz
+```
+
+## Running the fuzzers
+
+e.g. To run the `block` fuzzer using all available CPUs:
+
+```
+cargo fuzz run block -j `nproc`
+```
+
+## Adding a new fuzzer
+
+```
+cargo fuzz add <new_fuzzer>
+```
+
+Inspiration for fuzzers can be found in [crosvm](https://chromium.googlesource.com/chromiumos/platform/crosvm/+/refs/heads/master/fuzz/)

docs/hotplug.md

@@ -1,17 +1,15 @@
 # Cloud Hypervisor Hot Plug
 
-Currently Cloud Hypervisor only support hot plugging of CPU devices.
+Currently Cloud Hypervisor only supports hot plugging of CPU devices.
 
 ## Kernel support
 
 For hotplug on Cloud Hypervisor ACPI GED support is needed. This can either be achieved by turning on `CONFIG_ACPI_REDUCED_HARDWARE_ONLY` 
-or by using this kernel patch (available in 5.5rc1 and later): https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/patch/drivers/acpi/Makefile?id=ac36d37e943635fc072e9d4f47e40a48fbcdb3f0
-
-This patch is integrated into the Clear Linux KVM and cloudguest images.
+or by using this kernel patch (available in 5.5-rc1 and later): https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/patch/drivers/acpi/Makefile?id=ac36d37e943635fc072e9d4f47e40a48fbcdb3f0
 
 ## CPU Hot Plug
 
-Extra vCPUs can be added and removed from a running Cloud Hypervisor instance. This is controlled by two mechanisms:
+Extra vCPUs can be added and removed from a running `cloud-hypervisor` instance. This is controlled by two mechanisms:
 
 1. Specifying a number of maximum potential vCPUs that is greater than the number of default (boot) vCPUs.
 2. Making a HTTP API request to the VMM to ask for the additional vCPUs to be added.
@@ -22,22 +20,23 @@ To use CPU hotplug start the VM with the number of max vCPUs greater than the nu
 $ pushd $CLOUDH
 $ sudo setcap cap_net_admin+ep ./cloud-hypervisor/target/release/cloud-hypervisor
 $ ./cloud-hypervisor/target/release/cloud-hypervisor \
-	--kernel ./hypervisor-fw \
-	--disk path=clear-31890-kvm.img \
+	--kernel custom-vmlinux.bin \
+	--cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
+	--disk path=focal-server-cloudimg-amd64.raw \
 	--cpus boot=4,max=8 \
 	--memory size=1024M \
 	--net "tap=,mac=,ip=,mask=" \
 	--rng \
-    --api-socket=/tmp/ch-socket
+	--api-socket=/tmp/ch-socket
 $ popd
 ```
 
-Notice the addition of `--api-socket=/tmp/ch-socket` and a `max` parameter on `--cpus boot=4.max=8`.
+Notice the addition of `--api-socket=/tmp/ch-socket` and a `max` parameter on `--cpus boot=4,max=8`.
 
 To ask the VMM to add additional vCPUs then use the resize API:
 
 ```shell
-curl -H "Accept: application/json" -H "Content-Type: application/json" -i -XPUT --unix-socket /tmp/ch-socket -d "{ \"desired_vcpus\":8}" http://localhost/api/v1/vm.resize
+./ch-remote --api-socket=/tmp/ch-socket resize --cpus 8
 ```
 
 The extra vCPU threads will be created and advertised to the running kernel. The kernel does not bring up the CPUs immediately and instead the user must "online" them from inside the VM:
@@ -57,31 +56,36 @@ After a reboot the added CPUs will remain.
 Removing CPUs works similarly by reducing the number in the "desired_vcpus" field of the reisze API. The CPUs will be automatically offlined inside the guest so there is no need to run any commands inside the guest:
 
 ```shell
-curl -H "Accept: application/json" -H "Content-Type: application/json" -i -XPUT --unix-socket /tmp/ch-socket -d "{ \"desired_vcpus\":2}" http://localhost/api/v1/vm.resize
+./ch-remote --api-socket=/tmp/ch-socket resize --cpus 2
 ```
 
 As per adding CPUs to the guest, after a reboot the VM will be running with the reduced number of vCPUs.
 
 ## Memory Hot Plug
 
-Extra memory can be added from a runing Cloud Hypervisor instance. This is controlled by two mechanisms:
+### ACPI method
+
+Extra memory can be added from a running `cloud-hypervisor` instance. This is controlled by two mechanisms:
 
 1. Allocating some of the guest physical address space for hotplug memory.
 2. Making a HTTP API request to the VMM to ask for a new amount of RAM to be assigned to the VM. In the case of expanding the memory for the VM the new memory will be hotplugged into the running VM, if reducing the size of the memory then change will take effect after the next reboot.
 
-To use memory hotplug start the VM specifying some size RAM in the "hotplug_size" parameter to the memory configuration. Not all the memory specified in this parameter will be available to hotplug as there are spacing and alignment requirements so it is recommended to make it larger than the hotplug RAM needed.
+To use memory hotplug start the VM specifying some size RAM in the `hotplug_size` parameter to the memory configuration. Not all the memory specified in this parameter will be available to hotplug as there are spacing and alignment requirements so it is recommended to make it larger than the hotplug RAM needed.
+
+Because the ACPI method is the default, there is no need to add the extra option `hotplug_method=acpi`.
 
 ```shell
 $ pushd $CLOUDH
 $ sudo setcap cap_net_admin+ep ./cloud-hypervisor/target/release/cloud-hypervisor
 $ ./cloud-hypervisor/target/release/cloud-hypervisor \
-	--kernel ./hypervisor-fw \
-	--disk path=clear-31890-kvm.img \
+	--kernel custom-vmlinux.bin \
+	--cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
+	--disk path=focal-server-cloudimg-amd64.raw \
 	--cpus boot=4,max=8 \
 	--memory size=1024M,hotplug_size=8192M \
 	--net "tap=,mac=,ip=,mask=" \
 	--rng \
-    --api-socket=/tmp/ch-socket
+	--api-socket=/tmp/ch-socket
 $ popd
 ```
 
@@ -91,10 +95,10 @@ Before issuing the API request it is necessary to run the following command insi
 root@ch-guest ~ # echo online | sudo tee /sys/devices/system/memory/auto_online_blocks
 ```
 
-To ask the VMM to add expand the RAM for the VM  (request is in bytes):
+To ask the VMM to expand the RAM for the VM:
 
 ```shell
-curl -H "Accept: application/json" -H "Content-Type: application/json" -i -XPUT --unix-socket /tmp/ch-socket -d "{ \"desired_vcpus\": 4, \"desired_ram\" : 3221225472}" http://localhost/api/v1/vm.resize
+./ch-remote --api-socket=/tmp/ch-socket resize --memory 3G
 ```
 
 The new memory is now available to use inside the VM:
@@ -110,4 +114,137 @@ Due to guest OS limitations is is necessary to ensure that amount of memory adde
 
 The same API can also be used to reduce the desired RAM for a VM but the change will not be applied until the VM is rebooted.
 
-Memory and CPU resizing can be combined together into the same HTTP API request.
+Memory and CPU resizing can be combined together into the same HTTP API request.
+
+### virtio-mem method
+
+Extra memory can be added and removed from a running Cloud Hypervisor instance. This is controlled by two mechanisms:
+
+1. Allocating some of the guest physical address space for hotplug memory.
+2. Making a HTTP API request to the VMM to ask for a new amount of RAM to be assigned to the VM.
+
+To use memory hotplug start the VM specifying some size RAM in the `hotplug_size` parameter along with `hotplug_method=virtio-mem` to the memory configuration.
+
+```shell
+$ pushd $CLOUDH
+$ sudo setcap cap_net_admin+ep ./cloud-hypervisor/target/release/cloud-hypervisor
+$ ./cloud-hypervisor/target/release/cloud-hypervisor \
+	--kernel custom-vmlinux.bin \
+	--cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
+	--disk path=focal-server-cloudimg-amd64.raw \
+	--memory size=1024M,hotplug_size=8192M,hotplug_method=virtio-mem \
+	--net "tap=,mac=,ip=,mask=" \
+	--api-socket=/tmp/ch-socket
+$ popd
+```
+
+To ask the VMM to expand the RAM for the VM (request is in bytes):
+
+```shell
+./ch-remote --api-socket=/tmp/ch-socket resize --memory 3G
+```
+
+The new memory is now available to use inside the VM:
+
+```shell
+free -h
+              total        used        free      shared  buff/cache   available
+Mem:          3.0Gi        71Mi       2.8Gi       0.0Ki        47Mi       2.8Gi
+Swap:          32Mi          0B        32Mi
+```
+
+The same API can also be used to reduce the desired RAM for a VM. It is important to note that reducing RAM size might only partially work, as the guest might be using some of it.
+
+## PCI Device Hot Plug
+
+Extra PCI devices can be added and removed from a running `cloud-hypervisor` instance. This is controlled by making a HTTP API request to the VMM to ask for the additional device to be added, or for the existing device to be removed.
+
+Note: On AArch64 platform, PCI device hotplug can only be achieved using ACPI. Please refer to the [documentation](arm64.md#uefi-booting) for more information.
+
+To use PCI device hotplug start the VM with the HTTP server.
+
+```shell
+$ sudo setcap cap_net_admin+ep ./cloud-hypervisor/target/release/cloud-hypervisor
+$ ./cloud-hypervisor/target/release/cloud-hypervisor \
+	--kernel custom-vmlinux.bin \
+	--cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
+	--disk path=focal-server-cloudimg-amd64.raw \
+	--cpus boot=4 \
+	--memory size=1024M \
+	--net "tap=,mac=,ip=,mask=" \
+	--api-socket=/tmp/ch-socket
+```
+
+Notice the addition of `--api-socket=/tmp/ch-socket`.
+
+### Add VFIO Device
+
+To ask the VMM to add additional VFIO device then use the `add-device` API.
+
+```shell
+./ch-remote --api-socket=/tmp/ch-socket add-device path=/sys/bus/pci/devices/0000:01:00.0/
+```
+
+### Add Disk Device
+
+To ask the VMM to add additional disk device then use the `add-disk` API.
+
+```shell
+./ch-remote --api-socket=/tmp/ch-socket add-disk path=/foo/bar/cloud.img
+```
+
+### Add Fs Device
+
+To ask the VMM to add additional fs device then use the `add-fs` API.
+
+```shell
+./ch-remote --api-socket=/tmp/ch-socket add-fs tag=myfs,socket=/foo/bar/virtiofs.sock
+```
+
+### Add Net Device
+
+To ask the VMM to add additional network device then use the `add-net` API.
+
+```shell
+./ch-remote --api-socket=/tmp/ch-socket add-net tap=chtap0
+```
+
+### Add Pmem Device
+
+To ask the VMM to add additional PMEM device then use the `add-pmem` API.
+
+```shell
+./ch-remote --api-socket=/tmp/ch-socket add-pmem file=/foo/bar.cloud.img
+```
+
+### Add Vsock Device
+
+To ask the VMM to add additional vsock device then use the `add-vsock` API.
+
+```shell
+./ch-remote --api-socket=/tmp/ch-socket add-vsock cid=3,socket=/foo/bar/vsock.sock
+```
+
+### Common Across All PCI Devices
+
+The extra PCI device will be created and advertised to the running kernel. The new device can be found by checking the list of PCI devices.
+
+```shell
+root@ch-guest ~ # lspci
+00:00.0 Host bridge: Intel Corporation Device 0d57
+00:01.0 Unassigned class [ffff]: Red Hat, Inc. Virtio console (rev 01)
+00:02.0 Mass storage controller: Red Hat, Inc. Virtio block device (rev 01)
+00:03.0 Unassigned class [ffff]: Red Hat, Inc. Virtio RNG (rev 01)
+```
+
+After a reboot the added PCI device will remain.
+
+### Remove PCI device
+
+Removing a PCI device works the same way for all kind of PCI devices. The unique identifier related to the device must be provided. This identifier can be provided by the user when adding the new device, or by default Cloud Hypervisor will assign one.
+
+```shell
+./ch-remote --api-socket=/tmp/ch-socket remove-device _disk0
+```
+
+As per adding a PCI device to the guest, after a reboot the VM will be running without the removed PCI device.

docs/intel_sgx.md

@@ -0,0 +1,55 @@
+# Intel SGX
+
+Intel® Software Guard Extensions (Intel® SGX) is an Intel technology designed
+to increase the security of application code and data. Cloud Hypervisor supports
+SGX virtualization through KVM. Because SGX is built on hardware features that
+cannot be emulated in software, virtualizing SGX requires support in KVM and in
+the host kernel. The required Linux and KVM changes can be found in the
+[KVM SGX Tree](https://github.com/intel/kvm-sgx).
+
+Utilizing SGX in the guest requires a kernel/OS with SGX support, e.g. a kernel
+built using the [SGX Linux Development Tree](https://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-sgx.git)
+or the [KVM SGX Tree](https://github.com/intel/kvm-sgx). Running KVM SGX as the
+guest kernel allows nested virtualization of SGX.
+
+For more information about SGX, please refer to the [SGX Homepage](https://software.intel.com/sgx).
+
+For more information about SGX SDK and how to test SGX, please refer to the
+following [instructions](https://github.com/intel/linux-sgx).
+
+## Cloud Hypervisor support
+
+Assuming the host exposes `/dev/sgx_vepc`, we can pass SGX enclaves through
+the guest.
+
+In order to use SGX enclaves within a Cloud Hypervisor VM, we must define one
+or several Enclave Page Cache (EPC) sections. Here is an example of a VM being
+created with 2 EPC sections, the first one being 64MiB with pre-allocated
+memory, the second one being 32MiB with no pre-allocated memory.
+
+```bash
+./cloud-hypervisor \
+    --cpus boot=1 \
+    --memory size=1G \
+    --disk path=focal-server-cloudimg-amd64.raw \
+    --kernel vmlinux \
+    --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
+    --sgx-epc id=epc0,size=64M,prefault=on id=epc1,size=32M,prefault=off
+```
+
+Once booted, and assuming your guest kernel contains the patches from the
+[KVM SGX Tree](https://github.com/intel/kvm-sgx), you can validate SGX devices
+have been correctly created under `/dev/sgx`:
+
+```bash
+ls /dev/sgx*
+/dev/sgx_enclave  /dev/sgx_provision  /dev/sgx_vepc
+```
+
+From this point, it is possible to run any SGX application from the guest, as
+it will access `/dev/sgx_enclave` device to create dedicated SGX enclaves.
+
+Note: There is only one contiguous SGX EPC region, which contains all SGX EPC
+sections. This region is exposed through ACPI and marked as reserved through
+the e820 table. It is treated as yet another device, which means it should
+appear at the end of the guest address space.

docs/intel_tdx.md

@@ -0,0 +1,75 @@
+# Intel TDX
+
+Intel® Trust Domain Extensions (Intel® TDX) is an Intel technology designed to
+isolate virtual machines from the VMM, hypervisor and any other software on the
+host platform.
+
+For more information about TDX technical aspects, design and specification
+please refer to the
+[TDX Homepage](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-trust-domain-extensions.html).
+
+The required Linux changes for the host side can be found in the
+[KVM TDX tree](https://github.com/intel/tdx/tree/kvm) while the changes for
+the guest side can be found in the [Guest TDX tree](https://github.com/intel/tdx/tree/guest).
+
+The TDVF firmware can be found in the
+[EDK2 staging project](https://github.com/tianocore/edk2-staging/tree/TDVF).
+
+## Cloud Hypervisor support
+
+First, you must be running on a machine with TDX enabled in hardware, and
+with the host OS compiled from the [KVM TDX tree](https://github.com/intel/tdx/tree/kvm).
+
+Cloud Hypervisor can run TDX VM (Trust Domain) by loading the TDVF firmware,
+which will then load the guest kernel from the image. The image must be custom
+as it must include a kernel built from the [Guest TDX tree](https://github.com/intel/tdx/tree/guest).
+The firmware can be built as follows:
+
+```bash
+git clone https://github.com/tianocore/edk2-staging.git
+cd edk2-staging
+git checkout origin/TDVF
+git submodule update --init --recursive
+make -C BaseTools
+source ./edksetup.sh
+build -p OvmfPkg/OvmfCh.dsc -a X64 -t GCC5 -b RELEASE
+```
+
+If debug logs are needed, here is the alternative command:
+
+```bash
+build -p OvmfPkg/OvmfCh.dsc -a X64 -t GCC5 -D DEBUG_ON_SERIAL_PORT=TRUE
+```
+
+On the Cloud Hypervisor side, all you need is to build the project with the
+`tdx` feature enabled:
+
+```bash
+cargo build --features tdx
+```
+
+And run a TDX VM by providing the firmware previously built, along with the
+guest image containing the TDX enlightened kernel. Assuming the guest kernel
+command line contains `console=hvc0` (printing to the `virtio-console` device),
+run Cloud Hypervisor as follows:
+
+```bash
+./cloud-hypervisor \
+    --tdx firmware=edk2-staging/Build/OvmfCh/RELEASE_GCC5/FV/OVMF.fd \
+    --cpus boot=1 \
+    --memory size=1G \
+    --disk path=tdx_guest_img
+```
+
+And here is the alternative command when looking for debug logs (assuming the
+guest kernel command line contains `console=ttyS0`):
+
+```bash
+./cloud-hypervisor \
+    --tdx firmware=edk2-staging/Build/OvmfCh/DEBUG_GCC5/FV/OVMF.fd \
+    --cpus boot=1 \
+    --memory size=1G \
+    --disk path=tdx_guest_img \
+    --serial tty \
+    --console off
+```

docs/io_throttling.md

@@ -0,0 +1,44 @@
+# I/O Throttling
+
+Cloud Hypervisor now supports I/O throttling on virtio-block and virtio-net
+devices. This support is based on the [`rate-limiter` module](https://github.com/firecracker-microvm/firecracker/tree/master/src/rate_limiter)
+from Firecracker. This document explains the user interface of this
+feature, and highlights some internal implementations that can help users
+better understand the expected behavior of I/O throttling in practice.
+
+Cloud Hypervisor allows to limit both the I/O bandwidth (e.g. bytes/s)
+and I/O operations (ops/s) independently. For virtio-net devices, while
+sharing the same "rate limit" from user inputs (on both bandwidth and
+operations), the RX and TX queues are throttled independently.
+To limit the I/O bandwidth, Cloud Hypervisor
+provides three user options, i.e., `bw_size` (bytes), `bw_one_time_burst`
+(bytes), and `bw_refill_time` (ms). Both `bw_size` and `bw_refill_time`
+are required, while `bw_one_time_burst` is optional.
+Internally, these options define a TokenBucket with a maximum capacity
+(`bw_size` bytes), an initial burst size (`bw_one_time_burst`) and an
+interval for refilling purposes (`bw_refill_time`). The "refill-rate" is
+`bw_size` bytes per `bw_refill_time` ms, and it is the constant rate at
+which the tokens replenish. The refill process only starts happening
+after the initial burst budget is consumed. Consumption from the token
+bucket is unbounded in speed which allows for bursts bound in size by
+the amount of tokens available. Once the token bucket is empty,
+consumption speed is bound by the "refill-rate". Similarly, Cloud
+Hypervisor provides another three options for limiting I/O operations,
+i.e., `ops_size` (I/O operations), `bw_one_time_burst` (I/O operations),
+and `bw_refill_time` (ms).
+
+One caveat in the I/O throttling is that every-time the bucket gets
+empty, it will stop I/O operations for a fixed amount of time
+(`cool_down_time`). The `cool_down_time` now is fixed at `100 ms`, it
+can have big implications to the actual rate limit (which can be a lot
+different the expected "refill-rate" derived from user inputs). For
+example, to have a 1000 IOPS limit on a virtio-blk device, users should
+be able to provide either of the following two options:
+`ops_size=1000,ops_refill_time=1000` or
+`ops_size=10,ops_refill_time=10`. However, the actual IOPS limits are
+likely to be ~1000 IOPS and ~100 IOPS respectively. The reason is the
+actual rate limit users get can be as low as
+`ops_size/(ops_refill_time+cool_down_time)`. As a result, it is
+generally advisable to keep `bw/ops_refill_time` larger than `100 ms`
+(`cool_down_time`) to make sure the actual rate limit is close to users'
+expectation ("refill-rate").

docs/iommu.md

@@ -86,11 +86,11 @@ virtual IOMMU:
 
 ```bash
 ./cloud-hypervisor \
-    --cpus 1 \
+    --cpus boot=1 \
     --memory size=512M \
-    --disk path=clear-kvm.img,iommu=on \
-    --kernel custom-bzImage \
-    --cmdline "console=ttyS0 root=/dev/vda3" \
+    --disk path=focal-server-cloudimg-amd64.raw,iommu=on \
+    --kernel custom-vmlinux \
+    --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
 ```
 
 From a guest perspective, it is easy to verify if the device is protected by
@@ -121,6 +121,29 @@ lspci
 00:04.0 Unassigned class [ffff]: Red Hat, Inc. Virtio RNG
 ```
 
+### Work with FDT on AArch64
+
+On AArch64 architecture, the virtual IOMMU can still be used even if ACPI is not
+enabled. But the effect is different with what the aforementioned test showed.
+
+When ACPI is disabled, virtual IOMMU is supported through Flattened Device Tree
+(FDT). In this case, the guest kernel can not tell which device should be
+IOMMU-attached and which should not. No matter how many devices you attached to
+the virtual IOMMU by setting `iommu=on` option, all the devices on the PCI bus
+will be attached to the virtual IOMMU (except the IOMMU itself). Each of the
+devices will be added into a IOMMU group.
+
+As a result, the directory content of `/sys/kernel/iommu_groups` would be:
+
+```bash
+ls /sys/kernel/iommu_groups/0/devices/
+0000:00:02.0
+ls /sys/kernel/iommu_groups/1/devices/
+0000:00:03.0
+ls /sys/kernel/iommu_groups/2/devices/
+0000:00:04.0
+```
+
 ## Faster mappings
 
 By default, the guest memory is mapped with 4k pages and no huge pages, which
@@ -163,11 +186,11 @@ be consumed.
 
 ```bash
 ./cloud-hypervisor \
-    --cpus 1 \
-    --memory size=8G,file=/dev/hugepages \
-    --disk path=clear-kvm.img \
-    --kernel custom-bzImage \
-    --cmdline "console=ttyS0 root=/dev/vda3 hugepagesz=2M hugepages=2048" \
+    --cpus boot=1 \
+    --memory size=8G,hugepages=on \
+    --disk path=focal-server-cloudimg-amd64.raw \
+    --kernel custom-vmlinux \
+    --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw hugepagesz=2M hugepages=2048" \
     --net tap=,mac=,iommu=on
 ```
 
@@ -180,11 +203,11 @@ passing through is `0000:00:01.0`.
 
 ```bash
 ./cloud-hypervisor \
-    --cpus 1 \
-    --memory size=8G,file=/dev/hugepages \
-    --disk path=clear-kvm.img \
-    --kernel custom-bzImage \
-    --cmdline "console=ttyS0 root=/dev/vda3 kvm-intel.nested=1 vfio_iommu_type1.allow_unsafe_interrupts rw hugepagesz=2M hugepages=2048" \
+    --cpus boot=1 \
+    --memory size=8G,hugepages=on \
+    --disk path=focal-server-cloudimg-amd64.raw \
+    --kernel custom-vmlinux \
+    --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw kvm-intel.nested=1 vfio_iommu_type1.allow_unsafe_interrupts rw hugepagesz=2M hugepages=2048" \
     --device path=/sys/bus/pci/devices/0000:00:01.0,iommu=on
 ```
 
@@ -194,16 +217,17 @@ guest, and bind it to VFIO (it should appear as `0000:00:04.0`).
 ```bash
 echo 0000:00:04.0 > /sys/bus/pci/devices/0000\:00\:04.0/driver/unbind
 echo 8086 1502 > /sys/bus/pci/drivers/vfio-pci/new_id
+echo 0000:00:04.0 > /sys/bus/pci/drivers/vfio-pci/bind
 ```
 
 Last thing is to start the L2 guest with the huge pages memory backend.
 
 ```bash
 ./cloud-hypervisor \
-    --cpus 1 \
-    --memory size=4G,file=/dev/hugepages \
-    --disk path=clear-kvm.img \
-    --kernel custom-bzImage \
-    --cmdline "console=ttyS0 root=/dev/vda3" \
+    --cpus boot=1 \
+    --memory size=4G,hugepages=on \
+    --disk path=focal-server-cloudimg-amd64.raw \
+    --kernel custom-vmlinux \
+    --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
     --device path=/sys/bus/pci/devices/0000:00:04.0
 ```

docs/live_migration.md

@@ -0,0 +1,139 @@
+# Live Migration
+
+This document gives two examples of how to use the live migration
+support in Cloud Hypervisor:
+
+1. local migration - migrating between two VMs running on the same
+   machine;
+1. nested-vm migration - migrating between two nested VMs whose host VMs
+   are running on the same machine.
+
+## Local Migration
+Launch the source VM (on the host machine):
+```bash
+$ target/release/cloud-hypervisor
+    --kernel ~/workloads/vmlinux \
+    --disk path=~/workloads/focal.raw \
+    --cpus boot=1 --memory size=1G \
+    --cmdline "root=/dev/vda1 console=ttyS0"  \
+    --serial tty --console off --api-socket=/tmp/api1
+```
+
+Launch the destination VM from the same directory (on the host machine):
+```bash
+$ target/release/cloud-hypervisor --api-socket=/tmp/api2
+```
+
+Get ready for receiving migration for the destination VM (on the host machine):
+```bash
+$ target/release/ch-remote --api-socket=/tmp/api2 receive-migration unix:/tmp/sock
+```
+
+Start to send migration for the source VM (on the host machine):
+```bash
+$ target/release/ch-remote --api-socket=/tmp/api1 send-migration unix:/tmp/sock
+```
+
+When the above commands completed, the source VM should be successfully
+migrated to the destination VM. Now the destination VM is running while
+the source VM is terminated gracefully.
+
+## Nested-VM Migration
+
+Launch VM 1 (on the host machine) with an extra virtio-blk device for
+exposing a guest image for the nested source VM:
+> Note: the example below also attached an additional virtio-blk device
+> with a dummy image for testing purpose (which is optional).
+```bash
+$ head -c 1M < /dev/urandom > tmp.img # create a dummy image for testing
+$ sudo /target/release/cloud-hypervisor \
+        --serial tty --console off \
+        --cpus boot=1 --memory size=512M \
+        --kernel vmlinux \
+        --cmdline "root=/dev/vda1 console=ttyS0"  \
+        --disk path=focal-1.raw path=focal-nested.raw path=tmp.img\
+        --net ip=192.168.101.1
+```
+
+Launch VM 2 (on the host machine) with an extra virtio-blk device for
+exposing the same guest image for the nested destination VM:
+```bash
+$ sudo /target/release/cloud-hypervisor \
+        --serial tty --console off \
+        --cpus boot=1 --memory size=512M \
+        --kernel vmlinux \
+        --cmdline "root=/dev/vda1 console=ttyS0"  \
+        --disk path=focal-2.raw path=focal-nested.raw path=tmp.img\
+        --net ip=192.168.102.1
+```
+
+Launch the nested source VM (inside the guest OS of the VM 1) :
+```bash
+vm-1:~$ sudo ./cloud-hypervisor \
+        --serial tty --console off \
+        --memory size=128M \
+        --kernel vmlinux \
+        --cmdline "console=ttyS0 root=/dev/vda1" \
+        --disk path=/dev/vdb path=/dev/vdc \
+        --api-socket=/tmp/api1 \
+        --net ip=192.168.100.1
+vm-1:~$ # setup the guest network if needed
+vm-1:~$ sudo ip addr add 192.168.101.2/24 dev ens4
+vm-1:~$ sudo ip link set up dev ens4
+vm-1:~$ sudo ip r add default via 192.168.101.1
+```
+Optional: Run the guest workload below (on the guest OS of the nested source VM),
+which performs intensive virtio-blk operations. Now the console of the nested
+source VM should repeatedly print `"equal"`, and our goal is migrating
+this VM and the running workload without interruption.
+```bash
+#/bin/bash
+
+# On the guest OS of the nested source VM
+
+input="/dev/vdb"
+result=$(md5sum $input)
+tmp=$(md5sum $input)
+
+while  [[ "$result" == "$tmp" ]]
+do
+    echo "equal"
+    tmp=$(md5sum $input)
+done
+
+echo "not equal"
+echo "result = $result"
+echo "tmp = $tmp"
+```
+
+Launch the nested destination VM (inside the guest OS of the VM 2):
+```bash
+vm-2:~$ sudo ./cloud-hypervisor --api-socket=/tmp/api2
+vm-2:~$ # setup the guest network with the following commands if needed
+vm-2:~$ sudo ip addr add 192.168.102.2/24 dev ens4
+vm-2:~$ sudo ip link set up dev ens4
+vm-2:~$ sudo ip r add default via 192.168.102.1
+vm-2:~$ ping 192.168.101.2 # This should succeed
+```
+> Note: If the above ping failed, please check the iptables rule on the
+> host machine, e.g. whether the policy for the `FORWARD` chain is set
+> to `DROP` (which is the default setting configured by Docker).
+
+Get ready for receiving migration for the nested destination VM (inside
+the guest OS of the VM 2):
+```bash
+vm-2:~$ sudo ./ch-remote --api-socket=/tmp/api2 receive-migration unix:/tmp/sock2
+vm-2:~$ sudo socat TCP-LISTEN:6000,reuseaddr UNIX-CLIENT:/tmp/sock2
+```
+
+Start to send migration for the nested source VM (inside the guest OS of
+the VM 1):
+```bash
+vm-1:~$ sudo socat UNIX-LISTEN:/tmp/sock1,reuseaddr TCP:192.168.102.2:6000
+vm-1:~$ sudo ./ch-remote --api-socket=/tmp/api1 send-migration unix:/tmp/sock1
+```
+
+When the above commands completed, the source VM should be successfully
+migrated to the destination VM without interrupting our testing guest
+workload. Now the destination VM is running the testing guest workload
+while the source VM is terminated gracefully.

docs/logging.md

@@ -0,0 +1,43 @@
+# Logging
+
+The target audience of this document is both:
+
+* Developers who want to understand what log level to use and when,
+* Users who want to debug issues with running their workloads in Cloud Hypervisor
+
+## Control
+
+The number of `-v` parameters passed to the `cloud-hypervisor` binary will determine the log level. Currenly the default is log messages up to `WARN:` (`warn!`) are included by default. The `--log-file` allows the log to be sent to a location other than `stderr`.
+
+## Levels
+
+### `error!()`
+
+For immediate, unrecoverable errors where it does not make sense for the execution to continue as the behaviour of the VM is considerablely impacted.
+
+Cloud Hypervisor should exit shortly after reporting this error (with a non-zero exit code). Generally this should be used during initial construction of the VM state before the virtual CPUs have begun running code.
+
+A typical situation where this might occur is when the user is using command line options that conflict with each other or is trying to use a file that is not present on the filesystem.
+
+Users should react to this error by checking their initial VM configuration.
+
+### `warn!()`
+
+A serious problem has occured but the execution of the VM can continue although some functionality might be impacted.
+
+A typical example of where this level of message should be generated is during an API call request that cannot be fulfilled.
+
+The user should investigate the meaning of this warning and take steps to ensure the correct functionality.
+
+
+### `info!()`
+
+Use `-v` to enable.
+
+This level is for the benefit of developers. It should be used for sporadic and infrequent messages. The same message should not "spam" the logs. The VM should be usable when this level of debugging is enabled and trying to use `stdin/stdout` and the logs are going to `stderr`.
+
+### `debug!()`
+
+Use `-vv` to enable.
+
+For the most verbose of logging messages. It is acceptable to "spam" the log with repeated invocations of the same message. This level of logging would be combined with `--log-file`.

docs/macvtap-bridge.md

@@ -0,0 +1,32 @@
+# Using MACVTAP to Bridge onto Host Network
+
+Cloud Hypervisor supports using a MACVTAP device which is derived from a MACVLAN. Full details of configuring MACVLAN or MACVTAP is out of scope of this document. However the example below indicates how to bridge the guest directly onto the network the host is on. Due to the lack of hairpin mode it not usually possible to reach the guest directly from the host.
+
+```bash
+# The MAC address must be attached to the macvtap and be used inside the guest
+mac="c2:67:4f:53:29:cb"
+# Host network adapter to bridge the guest onto
+host_net="eno1"
+
+# Create the macvtap0 as a new virtual MAC associated with the host network
+sudo ip link add link "$host_net" name macvtap0 type macvtap
+sudo ip link set macvtap0 address "$mac" up
+sudo ip link show macvtap0
+
+# A new character device is created for this interface
+tapindex=$(< /sys/class/net/macvtap0/ifindex)
+tapdevice="/dev/tap$tapindex"
+
+# Ensure that we can access this device
+sudo chown "$UID.$UID" "$tapdevice"
+
+# Use --net fd=3 to point to fd 3 which the shell has opened to point to the /dev/tapN device
+target/debug/cloud-hypervisor \
+	--kernel ~/src/linux/vmlinux \
+	--disk path=~/workloads/focal.raw \
+	--cpus boot=1 --memory size=512M \
+	--cmdline "root=/dev/vda1 console=hvc0" \
+    --net fd=3,mac=$mac 3<>$"$tapdevice"
+```
+
+As the guest is now connected to the same L2 network as the host you can obtain an IP address based on your host network (potentially including via DHCP)

docs/memory.md

@@ -0,0 +1,549 @@
+# Memory
+
+Cloud Hypervisor has many ways to expose memory to the guest VM. This document
+aims to explain what Cloud Hypervisor is capable of and how it can be used to
+meet the needs of very different use cases.
+
+## Basic Parameters
+
+`MemoryConfig` or what is known as `--memory` from the CLI perspective is the
+easiest way to get started with Cloud Hypervisor.
+
+```rust
+struct MemoryConfig {
+    size: u64,
+    mergeable: bool,
+    hotplug_method: HotplugMethod,
+    hotplug_size: Option<u64>,
+    hotplugged_size: Option<u64>,
+    shared: bool,
+    hugepages: bool,
+    hugepage_size: Option<u64>,
+    prefault: bool,
+    zones: Option<Vec<MemoryZoneConfig>>,
+}
+```
+
+```
+--memory <memory>	Memory parameters "size=<guest_memory_size>,mergeable=on|off,shared=on|off,hugepages=on|off,hugepage_size=<hugepage_size>,hotplug_method=acpi|virtio-mem,hotplug_size=<hotpluggable_memory_size>,hotplugged_size=<hotplugged_memory_size>,prefault=on|off" [default: size=512M]
+```
+
+### `size`
+
+Size of the RAM in the guest VM.
+
+This option is mandatory when using the `--memory` parameter.
+
+Value is an unsigned integer of 64 bits.
+
+_Example_
+
+```
+--memory size=1G
+```
+
+### `mergeable`
+
+Specifies if the pages from the guest RAM must be marked as _mergeable_. In
+case this option is `true` or `on`, the pages will be marked with `madvise(2)`
+to let the host kernel know which pages are eligible for being merged by the
+KSM daemon.
+
+This option can be used when trying to reach a higher density of VMs running
+on a single host, as it will reduce the amount of memory consumed by each VM.
+
+By default this option is turned off.
+
+_Example_
+
+```
+--memory size=1G,mergeable=on
+```
+
+### `hotplug_method`
+
+Selects the way of adding and/or removing memory to/from a booted VM.
+
+Possible values are `acpi` and `virtio-mem`. Default value is `acpi`.
+
+_Example_
+
+```
+--memory size=1G,hotplug_method=acpi
+```
+
+### `hotplug_size`
+
+Amount of memory that can be dynamically added to the VM.
+
+Value is an unsigned integer of 64 bits. A value of 0 is invalid.
+
+_Example_
+
+```
+--memory size=1G,hotplug_size=1G
+```
+
+### `hotplugged_size`
+
+Amount of memory that will be dynamically added to the VM at boot. This option
+allows for starting a VM with a certain amount of memory that can be reduced
+during runtime.
+
+This is only valid when the `hotplug_method` is `virtio-mem` as it does not
+make sense for the `acpi` use case. When using ACPI, the memory can't be
+resized after it has been extended.
+
+This option is only valid when `hotplug_size` is specified, and its value can't
+exceed the value of `hotplug_size`.
+
+Value is an unsigned integer of 64 bits. A value of 0 is invalid.
+
+_Example_
+
+```
+--memory size=1G,hotplug_method=virtio-mem,hotplug_size=1G,hotplugged_size=512M
+```
+
+### `shared`
+
+Specifies if the memory must be `mmap(2)` with `MAP_SHARED` flag.
+
+By sharing a memory mapping, one can share the guest RAM with other processes
+running on the host. One can use this option when running vhost-user devices
+as part of the VM device model, as they will be driven by standalone daemons
+needing access to the guest RAM content.
+
+By default this option is turned off, which results in performing `mmap(2)`
+with `MAP_PRIVATE` flag.
+
+_Example_
+
+```
+--memory size=1G,shared=on
+```
+
+### `hugepages` and `hugepage_size`
+
+Specifies if the memory must be created and `mmap(2)` with `MAP_HUGETLB` and size
+flags. This performs a memory mapping relying on the specified huge page size.
+If no huge page size is supplied the system's default huge page size is used.
+
+By using hugepages, one can improve the overall performance of the VM, assuming
+the guest will allocate hugepages as well. Another interesting use case is VFIO
+as it speeds up the VM's boot time since the amount of IOMMU mappings are
+reduced.
+
+The user is responsible for ensuring there are sufficient huge pages of the
+specified size for the VMM to use. Failure to do so may result in strange VMM
+behaviour, e.g. error with `ReadKernelImage` is common. If there is a strange
+error with `hugepages` enabled, just disable it or check whether there are enough
+huge pages.
+
+By default this option is turned off.
+
+_Example_
+
+```
+--memory size=1G,hugepages=on,hugepage_size=2M
+```
+
+### `prefault`
+
+Specifies if the memory must be `mmap(2)` with `MAP_POPULATE` flag.
+
+By triggering prefault, one can allocate all required physical memory and create
+its page tables while calling `mmap`. With physical memory allocated, the number
+of page faults will decrease during running, and performance will also improve.
+
+Note that boot of VM will be slower with `prefault` enabled because of allocating
+physical memory and creating page tables in advance, and physical memory of the
+specified size will be consumed quickly.
+
+This option only takes effect at boot of VM. There is also a `prefault` option in
+restore and its choice will overwrite `prefault` in memory.
+
+By default this option is turned off.
+
+_Example_
+
+```
+--memory size=1G,prefault=on
+```
+
+## Advanced Parameters
+
+`MemoryZoneConfig` or what is known as `--memory-zone` from the CLI perspective
+is a power user parameter. It allows for a full description of the guest RAM,
+describing how every memory region is backed and exposed to the guest.
+
+```rust
+struct MemoryZoneConfig {
+    id: String,
+    size: u64,
+    file: Option<PathBuf>,
+    shared: bool,
+    hugepages: bool,
+    hugepage_size: Option<u64>,
+    host_numa_node: Option<u32>,
+    hotplug_size: Option<u64>,
+    hotplugged_size: Option<u64>,
+    prefault: bool,
+}
+```
+
+```
+--memory-zone <memory-zone>	User defined memory zone parameters "size=<guest_memory_region_size>,file=<backing_file>,shared=on|off,hugepages=on|off,hugepage_size=<hugepage_size>,host_numa_node=<node_id>,id=<zone_identifier>,hotplug_size=<hotpluggable_memory_size>,hotplugged_size=<hotplugged_memory_size>,prefault=on|off"
+```
+
+This parameter expects one or more occurences, allowing for a list of memory
+zones to be defined. It must be used with `--memory size=0`, clearly indicating
+that the memory will be described through advanced parameters.
+
+Each zone is given a list of options which we detail through the following
+sections.
+
+### `id`
+
+Memory zone identifier. This identifier must be unique, otherwise an error will
+be returned.
+
+This option is useful when referring to a memory zone previously created. In
+particular, the `--numa` parameter can associate a memory zone to a specific
+NUMA node based on the memory zone identifier.
+
+This option is mandatory when using the `--memory-zone` parameter.
+
+Value is a string.
+
+_Example_
+
+```
+--memory size=0
+--memory-zone id=mem0,size=1G
+```
+
+### `size`
+
+Size of the memory zone.
+
+This option is mandatory when using the `--memory-zone` parameter.
+
+Value is an unsigned integer of 64 bits.
+
+_Example_
+
+```
+--memory size=0
+--memory-zone id=mem0,size=1G
+```
+
+### `file`
+
+Path to the file backing the memory zone. This can be either a file or a
+directory. In case of a file, it will be opened and used as the backing file
+for the `mmap(2)` operation. In case of a directory, a temporary file with no
+hard link on the filesystem will be created. This file will be used as the
+backing file for the `mmap(2)` operation.
+
+This option can be particularly useful when trying to back a part of the guest
+RAM with a well known file. In the context of the snapshot/restore feature, and
+if the provided path is a file, the snapshot operation will not perform any
+copy of the guest RAM content for this specific memory zone since the user has
+access to it and it would duplicate data already stored on the current
+filesystem.
+
+Value is a string.
+
+_Example_
+
+```
+--memory size=0
+--memory-zone id=mem0,size=1G,file=/foo/bar
+```
+
+### `shared`
+
+Specifies if the memory zone must be `mmap(2)` with `MAP_SHARED` flag.
+
+By sharing a memory zone mapping, one can share part of the guest RAM with
+other processes running on the host. One can use this option when running
+vhost-user devices as part of the VM device model, as they will be driven
+by standalone daemons needing access to the guest RAM content.
+
+By default this option is turned off, which result in performing `mmap(2)`
+with `MAP_PRIVATE` flag.
+
+_Example_
+
+```
+--memory size=0
+--memory-zone id=mem0,size=1G,shared=on
+```
+
+### `hugepages` and `hugepage_size`
+
+Specifies if the memory must be created and `mmap(2)` with `MAP_HUGETLB` and size
+flags. This performs a memory mapping relying on the specified huge page size.
+If no huge page size is supplied the system's default huge page size is used.
+
+By using hugepages, one can improve the overall performance of the VM, assuming
+the guest will allocate hugepages as well. Another interesting use case is VFIO
+as it speeds up the VM's boot time since the amount of IOMMU mappings are
+reduced.
+
+The user is responsible for ensuring there are sufficient huge pages of the
+specified size for the VMM to use. Failure to do so may result in strange VMM
+behaviour, e.g. error with `ReadKernelImage` is common. If there is a strange
+error with `hugepages` enabled, just disable it or check whether there are enough
+huge pages.
+
+By default this option is turned off.
+
+_Example_
+
+```
+--memory size=0
+--memory-zone id=mem0,size=1G,hugepages=on,hugepage_size=2M
+```
+
+### `host_numa_node`
+
+Node identifier of a node present on the host. This option will let the user
+pick a specific NUMA node from which the memory must be allocated. After the
+memory zone is `mmap(2)`, the NUMA policy for this memory mapping will be
+applied through `mbind(2)`, relying on the provided node identifier. If the
+node does not exist on the host, the call to `mbind(2)` will fail.
+
+This option is useful when trying to back a VM memory with a specific type of
+memory from the host. Assuming a host has two types of memory, with one slower
+than the other, each related to a distinct NUMA node, one could create a VM
+with slower memory accesses by backing the entire guest RAM from the furthest
+NUMA node on the host.
+
+This option also gives the opportunity to create a VM with non uniform memory
+accesses as one could define a first memory zone backed by fast memory, and a
+second memory zone backed by slow memory.
+
+Value is an unsigned integer of 32 bits.
+
+_Example_
+
+```
+--memory size=0
+--memory-zone id=mem0,size=1G,host_numa_node=0
+```
+
+### `hotplug_size`
+
+Amount of memory that can be dynamically added to the memory zone. Since
+`virtio-mem` is the only way of resizing a memory zone, one must specify
+the `hotplug_method=virtio-mem` to the `--memory` parameter.
+
+Value is an unsigned integer of 64 bits. A value of 0 is invalid.
+
+_Example_
+
+```
+--memory size=0,hotplug_method=virtio-mem
+--memory-zone id=mem0,size=1G,hotplug_size=1G
+```
+
+### `hotplugged_size`
+
+Amount of memory that will be dynamically added to a memory zone at VM's boot.
+This option allows for starting a VM with a certain amount of memory that can
+be reduced during runtime.
+
+This is only valid when the `hotplug_method` is `virtio-mem` as it does not
+make sense for the `acpi` use case. When using ACPI, the memory can't be
+resized after it has been extended.
+
+This option is only valid when `hotplug_size` is specified, and its value can't
+exceed the value of `hotplug_size`.
+
+Value is an unsigned integer of 64 bits. A value of 0 is invalid.
+
+_Example_
+
+```
+--memory size=0,hotplug_method=virtio-mem
+--memory-zone id=mem0,size=1G,hotplug_size=1G,hotplugged_size=512M
+```
+
+### `prefault`
+
+Specifies if the memory must be `mmap(2)` with `MAP_POPULATE` flag.
+
+By triggering prefault, one can allocate all required physical memory and create
+its page tables while calling `mmap`. With physical memory allocated, the number
+of page faults will decrease during running, and performance will also improve.
+
+Note that boot of VM will be slower with `prefault` enabled because of allocating
+physical memory and creating page tables in advance, and physical memory of the
+specified size will be consumed quickly.
+
+This option only takes effect at boot of VM. There is also a `prefault` option in
+restore and its choice will overwrite `prefault` in memory.
+
+By default this option is turned off.
+
+_Example_
+
+```
+--memory size=0
+--memory-zone id=mem0,size=1G,prefault=on
+```
+
+## NUMA settings
+
+`NumaConfig` or what is known as `--numa` from the CLI perspective has been
+introduced to define a guest NUMA topology. It allows for a fine description
+about the CPUs and memory ranges associated with each NUMA node. Additionally
+it allows for specifying the distance between each NUMA node.
+
+```rust
+struct NumaConfig {
+    guest_numa_id: u32,
+    cpus: Option<Vec<u8>>,
+    distances: Option<Vec<NumaDistance>>,
+    memory_zones: Option<Vec<String>>,
+    sgx_epc_sections: Option<Vec<String>>,
+}
+```
+
+```
+--numa <numa>	Settings related to a given NUMA node "guest_numa_id=<node_id>,cpus=<cpus_id>,distances=<list_of_distances_to_destination_nodes>,memory_zones=<list_of_memory_zones>,sgx_epc_sections=<list_of_sgx_epc_sections>"
+```
+
+### `guest_numa_id`
+
+Node identifier of a guest NUMA node. This identifier must be unique, otherwise
+an error will be returned.
+
+This option is mandatory when using the `--numa` parameter.
+
+Value is an unsigned integer of 32 bits.
+
+_Example_
+
+```
+--numa guest_numa_id=0
+```
+
+### `cpus`
+
+List of virtual CPUs attached to the guest NUMA node identified by the
+`guest_numa_id` option. This allows for describing a list of CPUs which
+must be seen by the guest as belonging to the NUMA node `guest_numa_id`.
+
+One can use this option for a fine grained description of the NUMA topology
+regarding the CPUs associated with it, which might help the guest run more
+efficiently.
+
+Multiple values can be provided to define the list. Each value is an unsigned
+integer of 8 bits.
+
+For instance, if one needs to attach all CPUs from 0 to 4 to a specific node,
+the syntax using `-` will help define a contiguous range with `cpus=0-4`. The
+same example could also be described with `cpus=[0,1,2,3,4]`.
+
+A combination of both `-` and `,` separators is useful when one might need to
+describe a list containing all CPUs from 0 to 99 and the CPU 255, as it could
+simply be described with `cpus=[0-99,255]`.
+
+As soon as one tries to describe a list of values, `[` and `]` must be used to
+demarcate the list.
+
+_Example_
+
+```
+--cpus boot=8
+--numa guest_numa_id=0,cpus=[1-3,7] guest_numa_id=1,cpus=[0,4-6]
+```
+
+### `distances`
+
+List of distances between the current NUMA node referred by `guest_numa_id`
+and the destination NUMA nodes listed along with distances. This option let
+the user choose the distances between guest NUMA nodes. This is important to
+provide an accurate description of the way non uniform memory accesses will
+perform in the guest.
+
+One or more tuple of two values must be provided through this option. The first
+value is an unsigned integer of 32 bits as it represents the destination NUMA
+node. The second value is an unsigned integer of 8 bits as it represents the
+distance between the current NUMA node and the destination NUMA node. The two
+values are separated by `@` (`value1@value2`), meaning the destination NUMA
+node `value1` is located at a distance of `value2`. Each tuple is separated
+from the others with `,` separator.
+
+As soon as one tries to describe a list of values, `[` and `]` must be used to
+demarcate the list.
+
+For instance, if one wants to define 3 NUMA nodes, with each node located at
+different distances, it can be described with the following example.
+
+_Example_
+
+```
+--numa guest_numa_id=0,distances=[1@15,2@25] guest_numa_id=1,distances=[0@15,2@20] guest_numa_id=2,distances=[0@25,1@20]
+```
+
+### `memory_zones`
+
+List of memory zones attached to the guest NUMA node identified by the
+`guest_numa_id` option. This allows for describing a list of memory ranges
+which must be seen by the guest as belonging to the NUMA node `guest_numa_id`.
+
+This option can be very useful and powerful when combined with `host_numa_node`
+option from `--memory-zone` parameter as it allows for creating a VM with non
+uniform memory accesses, and let the guest know about it. It allows for
+exposing memory zones through different NUMA nodes, which can help the guest
+workload run more efficiently.
+
+Multiple values can be provided to define the list. Each value is a string
+referring to an existing memory zone identifier. Values are separated from
+each other with the `,` separator.
+
+As soon as one tries to describe a list of values, `[` and `]` must be used to
+demarcate the list.
+
+Note that a memory zone must belong to a single NUMA node. The following
+configuration is incorrect, therefore not allowed:
+`--numa guest_numa_id=0,memory_zones=mem0 guest_numa_id=1,memory_zones=mem0`
+
+_Example_
+
+```
+--memory size=0
+--memory-zone id=mem0,size=1G id=mem1,size=1G id=mem2,size=1G
+--numa guest_numa_id=0,memory_zones=[mem0,mem2] guest_numa_id=1,memory_zones=mem1
+```
+
+### `sgx_epc_sections`
+
+List of SGX EPC sections attached to the guest NUMA node identified by the
+`guest_numa_id` option. This allows for describing a list of SGX EPC sections
+which must be seen by the guest as belonging to the NUMA node `guest_numa_id`.
+
+Multiple values can be provided to define the list. Each value is a string
+referring to an existing SGX EPC section identifier. Values are separated from
+each other with the `,` separator.
+
+As soon as one tries to describe a list of values, `[` and `]` must be used to
+demarcate the list.
+
+_Example_
+
+```
+--sgx-epc id=epc0,size=32M id=epc1,size=64M id=epc2,size=32M
+--numa guest_numa_id=0,sgx_epc_sections=epc1 guest_numa_id=1,sgx_epc_sections=[epc0,epc2]
+```
+
+### PCI bus
+
+Cloud Hypervisor supports only one PCI bus, which is why it has been tied to
+the NUMA node 0 by default. It is the user responsibility to organize the NUMA
+nodes correctly so that vCPUs and guest RAM which should be located on the same
+NUMA node as the PCI bus end up on the NUMA node 0.

docs/networking.md

@@ -1,8 +1,8 @@
 # How to use networking
 
-cloud-hypervisor can emulate one or more virtual network interfaces, represented at the hypervisor host by [tap devices](https://www.kernel.org/doc/Documentation/networking/tuntap.txt). This guide briefly describes, in a manual and distribution neutral way, how to setup and use networking with cloud-hypevisor.
+cloud-hypervisor can emulate one or more virtual network interfaces, represented at the hypervisor host by [tap devices](https://www.kernel.org/doc/Documentation/networking/tuntap.txt). This guide briefly describes, in a manual and distribution neutral way, how to setup and use networking with cloud-hypervisor.
 
-## Multiple queue support for net devices ##
+## Multiple queue support for net devices
 
 While multiple vcpus defined for guest, to gain the benefit of vcpu scalable to improve performance, it suggests to define multiple queue pairs for net devices, one Tx/Rx queue pair per one vcpu, that means the number of queue pairs at least is equal to the vcpu count. In that case, after virtnet driver set cpu affinity for virtqueues in guest kernel, vcpus could handle interrupt from different virtqueue pairs in parallel.
 
@@ -14,7 +14,7 @@ Note:
 
 - Currently, it does not support to use ethtool to change the combined queue numbers in guest.
 - Multiple queue is enabled for vhost-user-net backend in cloud-hypervisor, however, multiple thread is not added to handle mq, thus, the performance for vhost-user-net backend is not supposed to be improved. The multiple thread will be added for backend later.
-- Performance test for vhost-user-net will be covered once vhost-user-net backend has mulitple thread supported.
+- Performance test for vhost-user-net will be covered once vhost-user-net backend has multiple thread supported.
 - Performance test for virtio-net is done by comparing 2 queue pairs with 1 queue pairs, that to run 2 iperf3 sessions in the same test environments, throughput is improved about 37%.
 
 ## Start cloud-hypervisor with net devices
@@ -23,25 +23,25 @@ Use one `--net` command-line argument from cloud-hypervisor to specify the emula
 
 ```bash
 ./cloud-hypervisor \
-    --cpus 4 \
+    --cpus boot=4 \
     --memory "size=512M" \
-    --disk path=my-root-disk.img \
+    --disk path=focal-server-cloudimg-amd64.raw \
     --kernel my-vmlinux.bin \
-    --cmdline "console=ttyS0 reboot=k panic=1 nomodules root=/dev/vda3" \
+    --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
     --net tap=ich0,mac=a4:a1:c2:00:00:01,ip=192.168.4.2,mask=255.255.255.0,num_queues=2,queue_size=256 \
           tap=ich1,mac=a4:a1:c2:00:00:02,ip=10.0.1.2,mask=255.255.255.0,num_queues=2,queue_size=256
 ```
 
 The `--net` argument takes 1 or more space-separated strings of key value pairs containing the following 4 keys or fields:
 
-| Name       | Purpose                    | Optional  |
-| -----------|----------------------------| ----------|
-| tap        | tap device name            | Yes       |
-| mac        | vNIC mac address           | Yes       |
-| ip         | tap IP IP address          | yes       |
-| mask       | tap IP netmask             | Yes       |
-| num_queues | the number of queues       | yes       |
-| queue_size | the size of each queue     | Yes       |
+| Name       | Purpose                | Optional |
+| ---------- | ---------------------- | -------- |
+| tap        | tap device name        | Yes      |
+| mac        | vNIC mac address       | Yes      |
+| ip         | tap IP IP address      | yes      |
+| mask       | tap IP netmask         | Yes      |
+| num_queues | the number of queues   | yes      |
+| queue_size | the size of each queue | Yes      |
 
 num_queues is the total number of tx and rx queues, the default value is 2, and it could be increased by multiples of 2. Additionally, num_queues is suggested to be as 2 times of vcpu count. The default value for queue_size is 256.
 
@@ -104,6 +104,7 @@ bridge name     bridge id               STP enabled     interfaces
 ich-dpl         8000.067afc1b9a67       no              ich1
 ich-int         8000.725412ffce6f       no              ich0
 ```
+
 This completes the layer 2 wiring: The cloud-hypervisor is now connected to the hypervisor host via the 2 linux bridges.
 
 ## IP (Layer 3) provisioning
@@ -116,6 +117,7 @@ On the hypervisor host add the network gateway IP address of each network to the
 root@host:~# ip addr add 192.168.4.1/24 dev ich-int
 root@host:~# ip addr add 10.0.1.1/24 dev ich-dpl
 ```
+
 The routing table of the hypervisor host should now also have corresponding routing entries:
 
 ```bash
@@ -127,9 +129,10 @@ Destination     Gateway         Genmask         Flags Metric Ref    Use Iface
 192.168.4.0     0.0.0.0         255.255.255.0   U     0      0        0 ich-int
 192.168.178.0   0.0.0.0         255.255.255.0   U     600    0        0 wlan1
 ```
+
 ### Virtual Machine
 
-Within the virtual machine set the vNIC's to up state and provision the corresponding IP addresses on the 2 vNIC's. The steps outlined below use the ip command as an example. Alternative distribution specific procedures can also apply.   
+Within the virtual machine set the vNIC's to up state and provision the corresponding IP addresses on the 2 vNIC's. The steps outlined below use the ip command as an example. Alternative distribution specific procedures can also apply.
 
 ```bash
 root@guest:~# ip link set up enp0s2
@@ -165,7 +168,7 @@ root@192.168.4.2's password:
 Linux cloud-hypervisor 5.2.0 #2 SMP Thu Jul 11 08:08:16 CEST 2019 x86_64
 
 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
-permitted by applicable law.                                                         
+permitted by applicable law.
 
 
 Last login: Fri Jul 12 13:27:56 2019 from 192.168.4.1
@@ -189,7 +192,7 @@ nameserver 192.168.178.1
 make sure that the default gateway of the hypervisor host (in this example host 192.168.178.1 which is an adsl router) has an entry in the routing table for the 192.168.4.0/24 network otherwise IP connectivity will not work.
 
 ```bash
-root@guest:~# nslookup  ftp.nl.debian.org       
+root@guest:~# nslookup  ftp.nl.debian.org
 Server:         192.168.178.1
 Address:        192.168.178.1#53
 

docs/profiling.md

@@ -0,0 +1,45 @@
+# Profiling
+
+`perf` can be used to profile the `cloud-hypervisor` binary but it is necessary to make some modifications to the build in order to produce a binary that gives useful results.
+
+## Building a suitable binary
+
+Modify the `Cargo.toml` file to add `debug = 1` to the `[profile.release]` block. It should look like this:
+
+```
+[profile.release]
+lto = true
+debug = 1
+```
+
+This adds the symbol information to the release binary but does not otherwise affect the performance.
+
+The binary must also be built with frame pointers included so that the call graph can be captured by the profiler.
+
+```
+$ cargo clean && RUSTFLAGS='-C force-frame-pointers=y' cargo build --release
+```
+
+## Profiling
+
+`perf` may then be used in the usual manner:
+
+e.g.
+
+```
+$ perf record -g target/release/cloud-hypervisor \
+        --kernel ~/src/linux/vmlinux \
+        --pmem file=~/workloads/focal.raw \
+        --cpus boot=1 --memory size=1G \
+        --cmdline "root=/dev/pmem0p1 console=ttyS0" \
+        --serial tty --console off \
+        --api-socket=/tmp/api1
+```
+
+For analysing the samples:
+
+```
+$ perf report -g
+```
+
+If profiling with a network device attached either the TAP device must be already created and configured or the profiling must be done as root so that the TAP device can be created.

docs/seccomp.md

@@ -0,0 +1,68 @@
+# Seccomp filtering
+
+As a means to harden Cloud Hypervisor's security, the project leverages seccomp
+filtering.
+
+## What is seccomp filtering
+
+A seccomp filter is a way for a process to tell the kernel which system calls
+are authorized.
+In case this process calls into a prohibited system call, the kernel will kill
+the process right away.
+
+## How does it apply to Cloud Hypervisor
+
+Cloud Hypervisor is a multi threaded application. It spawns dedicated threads
+for virtual CPUs, virtio devices and HTTP server, along with the main thread
+representing the VMM.
+
+Each of these threads has a limited scope of what it is expected to perform,
+which is why different filters are applied to each of them.
+
+By default, Cloud Hypervisor enables seccomp filtering as the project believes
+that security should not be an option.
+
+For development and debugging purposes, one might want to disable this feature
+or log the faulty system call.
+
+### Disabling seccomp filters
+
+Append `--seccomp false` to Cloud Hypervisor's command line to prevent seccomp
+filtering from being applied.
+
+### Logging prohibited system calls
+
+In the context of debug, one alternative to disabling seccomp filtering is to
+log faulty system calls that would have caused the application to be killed by
+the kernel.
+
+Append `--seccomp log` to Cloud Hypervisor's command line to enable faulty
+system calls to be logged.
+
+The kernel running on the host machine must have the `audit` parameter enabled.
+If this is not the case, update kernel boot options by appending `audit=1`.
+
+Unauthorized system calls will be logged to the journal similarly to the
+following example
+
+```
+type=SECCOMP msg=audit(1423263412.694:7878): auid=1000 uid=1000 gid=1000 ses=3 subj=unconfined_u:unconfined_r:cloud_hypervisor:s0-s0:c0.c1023 pid=1193 comm="cloud-hypervisor" exe="/usr/bin/cloud-hypervisor" sig=0 arch=c000003e syscall=47 compat=0 ip=0x7f4f63982604 code=0x50000
+```
+
+Provided `ausyscall` has been installed on the host, the system call can be
+identified with
+
+```
+$ ausyscall 47
+recvmsg
+```
+
+### Further debug with `strace`
+
+One more way of debugging seccomp related issues is to use the `strace` tool as
+it will log every system call issued by the process. It is important to use
+`-f` option in order to trace each and every thread belonging to the process.
+
+```
+strace -f ./cloud-hypervisor ...
+```

docs/snapshot_restore.md

@@ -0,0 +1,112 @@
+# Snapshot and Restore
+
+The goal for the snapshot/restore feature is to provide the user with the
+ability to take a snapshot of a previously paused virtual machine. This
+snapshot can be used as the base for creating new identical virtual machines,
+without the need to boot them from scratch. The restore codepath takes the
+snapshot and creates the exact same virtual machine, restoring the previously
+saved states. The new virtual machine is restored in a paused state, as it was
+before the snapshot was performed.
+
+This feature is important for the project as it establishes the first step
+towards the support for live migration.
+
+## Snapshot a Cloud Hypervisor VM
+
+First thing, we must run a Cloud Hypervisor VM:
+
+```bash
+./cloud-hypervisor \
+    --api-socket /tmp/cloud-hypervisor.sock \
+    --cpus boot=4 \
+    --memory size=4G \
+    --kernel vmlinux \
+    --cmdline "root=/dev/vda1 console=hvc0 rw" \
+    --disk path=focal-server-cloudimg-amd64.raw
+```
+
+At any point in time when the VM is running, one might choose to pause it:
+
+```bash
+./ch-remote --api-socket=/tmp/cloud-hypervisor.sock pause
+```
+
+Once paused, the VM can be safely snapshot into the specified directory and
+using the following command:
+
+```bash
+./ch-remote --api-socket=/tmp/cloud-hypervisor.sock snapshot file:///home/foo/snapshot
+```
+
+Given the directory was present on the system, the snapshot will succeed and
+it should contain the following files:
+
+```bash
+ll /home/foo/snapshot/
+total 4194536
+drwxrwxr-x  2 foo bar       4096 Jul 22 11:50 ./
+drwxr-xr-x 47 foo bar       4096 Jul 22 11:47 ../
+-rw-------  1 foo bar 3221225472 Jul 22 11:19 memory-region-0
+-rw-------  1 foo bar 1073741824 Jul 22 11:19 memory-region-1
+-rw-------  1 foo bar     217853 Jul 22 11:19 vm.json
+```
+
+In this particular example, we can observe that 2 memory region files were
+created. That is explained by the size of the guest RAM, which is 4GiB in this
+case. Because it exceeds 3GiB (which is where we can find a ~1GiB memory hole),
+Cloud Hypervisor needs 2 distinct memory regions to be created. Each memory
+region's content is stored through a dedicated file, which explains why we end
+up with 2 different files, the first one containing the guest RAM range 0-3GiB
+and the second one containing the guest RAM range 3-4GiB.
+
+`vm.json` gathers all information related to the virtual machine configuration
+and state. The configuration bits are used to create a similar virtual machine
+with the correct amount of CPUs, RAM, and other expected devices. The state
+bits are used to restore each component in the state it was left before the
+snapshot occurred.
+
+## Restore a Cloud Hypervisor VM
+
+Given that one has access to an existing snapshot in `/home/foo/snapshot`,
+it is possible to create a new VM based on this snapshot with the following 
+command:
+
+```bash
+./cloud-hypervisor \
+    --api-socket /tmp/cloud-hypervisor.sock \
+    --restore source_url=file:///home/foo/snapshot
+```
+
+Or using two different commands from two terminals:
+
+```bash
+# First terminal
+./cloud-hypervisor --api-socket /tmp/cloud-hypervisor.sock
+
+# Second terminal
+./ch-remote --api-socket=/tmp/cloud-hypervisor.sock restore source_url=file:///home/foo/snapshot
+```
+
+Remember the VM is restored in a `paused` state, which was the VM's state when
+it was snapshot. For this reason, one must explicitly `resume` the VM before to
+start using it.
+
+```bash
+./ch-remote --api-socket=/tmp/cloud-hypervisor.sock resume
+```
+
+At this point, the VM is fully restored and is identical to the VM which was
+snapshot earlier.
+
+## Limitations
+
+The support of snapshot/restore feature is still experimental, meaning one
+might still find some bugs associated with it.
+
+Additionally, some devices and features don't support to be snapshot and
+restored yet:
+- `vhost-user` devices
+- `virtio-mem`
+- Intel SGX
+
+VFIO devices are out of scope.

docs/uefi.md

@@ -0,0 +1,76 @@
+# UEFI Boot
+
+Cloud Hypervisor supports UEFI boot through the utilization of the EDK II based UEFI firmware. 
+
+## Building UEFI Firmware
+
+To avoid any unnecessary issues, it is recommended to use Ubuntu 18.04 and its default toolset. Any other compatible Linux distribution is otherwise suitable, however it is suggested to use a temporary Docker container with Ubuntu 18.04 for a quick build on an existing Linux machine.
+
+The commands below will compile an OVMF firmware suitable for Cloud Hypervisor.
+
+```shell
+sudo apt-get update
+sudo apt-get install uuid-dev nasm iasl build-essential python3-distutils git
+
+git clone https://github.com/cloud-hypervisor/edk2 -b ch
+cd edk2
+. edksetup.sh
+git submodule update --init
+
+echo "ACTIVE_PLATFORM=OvmfPkg/OvmfCh.dsc" >> Conf/target.txt
+echo "TARGET_ARCH=X64" >> Conf/target.txt
+echo "TOOL_CHAIN_TAG=GCC5" >> Conf/target.txt
+
+make -C ./BaseTools
+build
+```
+
+After the successful build, the resulting firmware binaries are available under `Build/OvmfCh/DEBUG_GCC5/FV` underneath the edk2 checkout.
+
+## Using OVMF Binaries
+
+Any UEFI capable image can be booted using the Cloud Hypervisor specific firmware. Windows guests under Cloud Hypervisor only support UEFI boot, therefore OVMF is mandatory there.
+
+To make Cloud Hypervisor use UEFI boot, pass the `OVMF.fd` file path as an argument to the `--kernel` option. The firmware file will be opened in read only mode.
+
+The same firmware can be used with Cloud Hypervisor or with QEMU. This is particularly useful if using QEMU for the preparation phase.
+
+## Building UEFI Firmware with Compatibility Support Module (CSM)
+
+CSM is a module that allows to boot legacy operating systems using the OVMF firmware. OVMF can embed a CSM build of SeaBIOS. To build the SeaBIOS with CSM support, add `CONFIG_CSM=y` to `.config` before the build. The outcome `out/Csm16.bin` is to be moved into `OvmfPkg/Csm/Csm16/Csm16.bin` before OVMF is built. Then, the OVMF build will have to be passed the `-D CSM_ENABLE` option in order to generate a legacy aware UEFI firmware. At the current stage, all the necessary patches are included in the Cloud Hypervisor specific [SeaBIOS branch](https://github.com/cloud-hypervisor/seabios/tree/ch). Taking into account the previous instructions, the modified command sequence to compile an OVMF binary with CSM support is the following one:
+
+```shell
+sudo apt-get update
+sudo apt-get install uuid-dev nasm iasl build-essential python3-distutils git libncurses-dev
+
+git clone https://github.com/cloud-hypervisor/seabios -b ch
+cd seabios
+make menuconfig
+# Enable `CONFIG_CSM` and `CONFIG_QEMU_HARDWARE`
+# Please make sure `python` is in your path
+make CONFIG_CSM=y CONFIG_QEMU_HARDWARE=y
+cd ..
+
+git clone https://github.com/cloud-hypervisor/edk2 -b ch
+cd edk2
+. edksetup.sh
+git submodule update --init --recursive
+cp ../seabios/out/Csm16.bin OvmfPkg/Csm/Csm16/
+
+echo "ACTIVE_PLATFORM=OvmfPkg/OvmfCh.dsc" >> Conf/target.txt
+echo "TARGET_ARCH=X64" >> Conf/target.txt
+echo "TOOL_CHAIN_TAG=GCC5" >> Conf/target.txt
+
+make -C ./BaseTools
+build -DCSM_ENABLE
+
+```
+
+Please note, that the CSM support has currently only been tested with Linux guests. There are no plans to provide legacy support for other OSes (e.g. Windows).
+
+# Links
+
+- [OVMF wiki](https://github.com/tianocore/tianocore.github.io/wiki/OVMF) 
+- [Cloud Hypervisor specific tree](https://github.com/cloud-hypervisor/edk2/tree/ch)
+- [Redhat OVMF Status Report](https://access.redhat.com/sites/default/files/attachments/ovmf-whtepaper-031815.pdf)
+- [SeaBIOS Build Overview](https://www.seabios.org/Build_overview#Build_as_a_UEFI_Compatibility_Support_Module_.28CSM.29)

docs/vfio-user.md

@@ -0,0 +1,79 @@
+# Cloud Hypervisor VFIO-user HOWTO
+
+VFIO-user is an *experimental* protocol for allowing devices to be implemented in another process and communicate over a socket; ie.e VFIO-user is to VFIO as virtio is to vhost-user.
+
+The protocol is documented here: https://github.com/nutanix/libvfio-user/blob/master/docs/vfio-user.rst
+
+The Cloud Hypervisor support for such devices is *experimental*. Not all Cloud Hypervisor functionality is supported in particular: virtio-mem and iommu are not supported.
+
+## Usage
+
+The `--user-device socket=<path>` parameter is used to create a vfio-user device when creating the VM specifying the socket to connect to. The device can also be hotplugged with `ch-remote add-user-device socket=<path>`.
+
+## Example (GPIO device)
+
+There is a simple GPIO device included in the libvfio-user repository: https://github.com/nutanix/libvfio-user#gpio
+
+Run the example from the libvfio-user repository:
+
+```sh
+rm /tmp/vfio-user.sock
+./build/dbg/samples/gpio-pci-idio-16 -v /tmp/vfio-user.sock &
+```
+
+Start Cloud Hypervisor:
+
+```sh
+target/debug/cloud-hypervisor \
+    --memory size=1G,shared=on \
+    --disk path=~/images/focal-server-cloudimg-amd64.raw \
+    --kernel ~/src/linux/vmlinux \
+    --cmdline "root=/dev/vda1 console=hvc0" \
+    --user-device socket=/tmp/vfio-user.sock 
+```
+
+Inside the VM you can test the device with:
+
+```sh
+cat /sys/class/gpio/gpiochip480/base > /sys/class/gpio/export
+for ((i=0;i<12;i++)); do cat /sys/class/gpio/OUT0/value; done
+```
+
+## Example (NVMe device)
+
+Use SPDK: https://github.com/spdk/spdk
+
+Compile with `./configure --with-vfio-user`
+
+Create an NVMe controller listening on a vfio-user socket with a simple AIO block device in spdk.
+More details of configuring SPDK bdev can be viewed in [SPDK bdev](https://spdk.io/doc/bdev.html).
+More details of setting SPDK NVMe-oF target can be viewed in [SDPK NVMe-oF tgt](https://spdk.io/doc/nvmf.html).
+
+```sh
+sudo scripts/setup.sh
+rm ~/images/test-disk.raw
+truncate ~/images/test-disk.raw -s 128M
+mkfs.ext4  ~/images/test-disk.raw
+sudo killall ./build/bin/nvmf_tgt
+sudo ./build/bin/nvmf_tgt -i 0 -e 0xFFFF -m 0x1 &
+sleep 2
+sudo ./scripts/rpc.py nvmf_create_transport -t VFIOUSER
+sudo rm -rf /tmp/nvme-vfio-user
+sudo mkdir -p /tmp/nvme-vfio-user
+sudo ./scripts/rpc.py bdev_aio_create ~/images/test-disk.raw test 512
+sudo ./scripts/rpc.py nvmf_create_subsystem nqn.2019-07.io.spdk:cnode -a -s test
+sudo ./scripts/rpc.py nvmf_subsystem_add_ns nqn.2019-07.io.spdk:cnode test
+sudo ./scripts/rpc.py nvmf_subsystem_add_listener nqn.2019-07.io.spdk:cnode -t VFIOUSER -a /tmp/nvme-vfio-user -s 0
+sudo chown $USER.$USER -R /tmp/nvme-vfio-user
+```
+
+Start Cloud Hypervisor:
+
+```sh
+target/debug/cloud-hypervisor \
+    --memory size=1G,shared=on \
+    --disk path=~/images/focal-server-cloudimg-amd64.raw \
+    --kernel ~/src/linux/vmlinux \
+    --cmdline "root=/dev/vda1 console=hvc0" \
+    --user-device socket=/tmp/nvme-vfio-user/cntrl 
+```

docs/vfio.md

@@ -11,7 +11,7 @@ by the VFIO kernel drivers. However, by default, a host device will be bound to
 its native driver, which is not the VFIO one.
 
 As a consequence, a device must be unbound from its native driver before passing
-it to `cloud-hypervisor` for assigning it to a guess.
+it to `cloud-hypervisor` for assigning it to a guest.
 
 ### Example
 
@@ -36,14 +36,22 @@ Now that we have identified the device, we must unbind it from its native driver
 First we add VFIO support to the host:
 
 ```
-$ sudo modprobe vfio_pci
-$ sudo modprobe vfio_iommu_type1 allow_unsafe_interrupts
+# modprobe -r vfio_pci
+# modprobe -r vfio_iommu_type1
+# modprobe vfio_iommu_type1 allow_unsafe_interrupts
+# modprobe vfio_pci
+```
+
+In case the VFIO drivers are built-in, enable unsafe interrupts with:
+
+```
+# echo 1 > /sys/module/vfio_iommu_type1/parameters/allow_unsafe_interrupts
 ```
 
 Then we unbind it from its native driver:
 
 ```
-$ echo 0000:01:00.0 > /sys/bus/pci/devices/0000\:01\:00.0/driver/unbind
+# echo 0000:01:00.0 > /sys/bus/pci/devices/0000\:01\:00.0/driver/unbind
 ```
 
 And finally we bind it to the VFIO driver. To do that we first need to get the
@@ -53,7 +61,14 @@ device's VID (Vendor ID) and PID (Product ID):
 $ lspci -n -s 01:00.0
 01:00.0 ff00: 10ec:525a (rev 01)
 
-$ echo 10ec 525a > /sys/bus/pci/drivers/vfio-pci/new_id
+# echo 10ec 525a > /sys/bus/pci/drivers/vfio-pci/new_id
+```
+
+If you have more than one device with the same `vendorID`/`deviceID`, starting
+with the second device, the binding is performed as follows:
+
+```
+# echo 0000:02:00.0 > /sys/bus/pci/drivers/vfio-pci/bind
 ```
 
 Now the device is managed by the VFIO framework.
@@ -66,10 +81,10 @@ takes the device's sysfs path as an argument. In our example it is
 ```
 ./target/debug/cloud-hypervisor \
     --kernel ~/vmlinux \
-    --disk path=~/clear-29160-kvm.img \
+    --disk path=~/focal-server-cloudimg-amd64.raw \
     --console off \
     --serial tty \
-    --cmdline "console=ttyS0 reboot=k panic=1 nomodules i8042.noaux i8042.nomux i8042.nopnp i8042.dumbkbd root=/dev/vda3" \
+    --cmdline "console=ttyS0 root=/dev/vda1 rw" \
     --cpus 4 \
     --memory size=512M \
     --device path=/sys/bus/pci/devices/0000:01:00.0/
@@ -79,4 +94,32 @@ The guest kernel will then detect the card reader on its PCI bus and provided
 that support for this device is enabled, it will probe and enable it for the
 guest to use.
 
+In case you want to pass multiple devices, here is the correct syntax:
 
+```
+--device path=/sys/bus/pci/devices/0000:01:00.0/ path=/sys/bus/pci/devices/0000:02:00.0/
+```
+
+### Multiple devices in the same IOMMU group
+
+There are cases where multiple devices can be found under the same IOMMU group.
+This happens often with graphics card embedding an audio controller.
+
+```
+$ lspci
+[...]
+01:00.0 VGA compatible controller: NVIDIA Corporation GK208B [GeForce GT 710] (rev a1)
+01:00.1 Audio device: NVIDIA Corporation GK208 HDMI/DP Audio Controller (rev a1)
+[...]
+```
+
+This is usually exposed as follows through `sysfs`:
+
+```
+$ ls /sys/kernel/iommu_groups/22/devices/
+0000:01:00.0  0000:01:00.1
+```
+
+This means these two devices are under the same IOMMU group 22. In such case,
+it is important to bind both devices to VFIO and pass them both through the
+VM, otherwise this could cause some functional and security issues.

docs/vhost-user-blk-testing.md

@@ -35,48 +35,66 @@ Here are some good references for detailing them.
 
 ## Test environment
 
-The below test environment is based on ubuntu release(16.04.1 LTS), as for other system, please check related document.
-The test runs with multiple queue (MQ) support enabled, using 4 queues defined for both SPDK and the virtual machine.
-Here are the details on how the test can be run.
+The below test environment is based on Ubuntu release (20.04.1 LTS), as for other system, please check related documents.
+This test runs with multiple queue (MQ) support enabled, using 4 queues defined for both SPDK and the virtual machine.
+Here are the detailed instructions.
 
-### The hugepages settings in host linux
-Add "default_hugepagesz=1G hugepagesz=1G hugepages=2" into host linux cmdline.
-As for how to change Ubuntu linux cmdline in grub file, please ref below link:
-https://www.ostechnix.com/configure-grub-2-boot-loader-settings-ubuntu-16-04/
-reboot Ubuntu
-sudo mount -t hugetlbfs -o pagesize=1G none /dev/hugepages
+### The hugepages settings on the host
+Allocate enough persistent huge pages (e.g. 2GiB) on the host:
+
+```bash
+# Assume the default hugepage size is 2MiB
+echo 1024 | sudo tee /proc/sys/vm/nr_hugepages
+# Confirm the value of "Hugepagesize" and "HugePages_Total"
+cat /proc/meminfo | grep -i huge
+```
 
 ### Download the SPDK code
+```bash
 git clone https://github.com/spdk/spdk
 cd spdk
 git submodule update --init
+```
 
 ### Create the build dep
-./scripts/pkgdep.sh
 
-### Build spdk
+```bash
+./scripts/pkgdep.sh
+```
+
+### Build SPDK
+```bash
 ./configure
 make
+```
 
-### Set the SPDk environment
+### Set the SPDK environment
+
+Run SPDK vhost target with 2 CPU cores, i.e., core 0 and 1.
+```bash
 sudo HUGEMEM=2048 scripts/setup.sh
-sudo ./app/vhost/vhost -S /var/tmp -s 1024 -m 0x3 &
+sudo ./build/bin/vhost -S /var/tmp -s 1024 -m 0x3 &
+```
 
 ### Create 512M block device
+
+Create a 512M (first parameter) block device with 512 bytes (second parameter) block size.
+```bash
 sudo scripts/rpc.py bdev_malloc_create 512 512 -b Malloc0
 sudo scripts/rpc.py vhost_create_blk_controller --cpumask 0x1 vhost.1 Malloc0
+```
 
-_Launch the VM_
+### Launch the VM
 
 VMs run in client mode. They connect to the socket created by the `dpdkvhostuser` in the SPDK backend.
 ```bash
 # From the test terminal. We need to create one vhost-user-blk device for the --disk.
 ./cloud-hypervisor \
         --cpus boot=4 \
-        --memory size=1024M,file=/dev/hugepages \
+        --memory size=1024M,hugepages=on,shared=true \
         --kernel linux/arch/x86/boot/compressed/vmlinux.bin \
-        --cmdline "console=ttyS0 reboot=k panic=1 nomodules i8042.noaux i8042.nomux i8042.nopnp i8042.dumbkbd root=/dev/vda3 iommu=off" \
-        --disk "path=images/clear-kvm.img" "num_queues=4,queue_size=128,vhost_user=true,socket=/var/tmp/vhost.1,wce=true" \
+        --cmdline "console=ttyS0 root=/dev/vda1 rw iommu=off" \
+        --disk path=images/focal-server-cloudimg-amd64.raw vhost_user=true,socket=/var/tmp/vhost.1,num_queues=4,queue_size=128 \
         --console off \
         --serial tty \
         --rng
@@ -88,11 +106,11 @@ login in guest
 
 # Use lsblk command to find out vhost-user-blk device
 lsblk
-NAME   MAJ:MIN RM  SIZE RO TYPE MOUNTPOINT
-vda    253:0    0  8.5G  0 disk
-├─vda1 253:1    0  511M  0 part
-├─vda2 253:2    0   32M  0 part [SWAP]
-└─vda3 253:3    0    8G  0 part /
+NAME    MAJ:MIN RM  SIZE RO TYPE MOUNTPOINT
+vda     252:0    0  2.2G  0 disk
+├─vda1  252:1    0  2.1G  0 part /
+├─vda14 252:14   0    4M  0 part
+└─vda15 252:15   0  106M  0 part /boot/efi
 vdb    253:16   0  512M  0 disk
 
 The vhost-user-blk device is /dev/vdb

docs/vhost-user-net-testing.md

@@ -1,27 +1,30 @@
 # How to test Vhost-user net with OpenVSwitch/DPDK
 
-The purpose of this document is to illustrate how to test vhost-user-net in cloud-hypervisor with OVS/DPDK as the backend.
+The purpose of this document is to illustrate how to test vhost-user-net
+in cloud-hypervisor with OVS/DPDK as the backend. This document was
+tested with Open vSwitch v2.13.1, DPDK v19.11.3, and Cloud Hypervisor
+v15.0 on Ubuntu 20.04.1 (host kernel v5.4.0).
 
 ## Framework
 
 It's a simple test to validate the communication between two virtual machine, connecting them to vhost-user ports respectively provided by `OVS/DPDK`.
 ```
-             +----+----------+          +-------------+-----------+-------------+          +----------+----+  
-             |    |          |          |             |           |             |          |          |    | 
-             |    |vhost-user|----------| vhost-user  |   ovs     | vhost-user  |----------|vhost-user|    |           
-             |    |net device|          | port 1      |           | port 2      |          |net device|    |           
-             |    |          |          |             |           |             |          |          |    |           
-             |    +----------+          +-------------+-----------+-------------+          +----------+    |           
-             |               |          |                                       |          |               |           
-             |vm1            |          |                  dpdk                 |          |           vm2 |           
-             |               |          |                                       |          |               |           
-          +--+---------------------------------------------------------------------------------------------+--+        
-          |  |                                       hugepages                                             |  |        
-          |  +---------------------------------------------------------------------------------------------+  |        
-          |                                                                                                   |        
-          |                                              host                                                 |        
-          |                                                                                                   |  
-          +---------------------------------------------------------------------------------------------------+        
+             +----+----------+          +-------------+-----------+-------------+          +----------+----+
+             |    |          |          |             |           |             |          |          |    |
+             |    |vhost-user|----------| vhost-user  |   ovs     | vhost-user  |----------|vhost-user|    |
+             |    |net device|          | port 1      |           | port 2      |          |net device|    |
+             |    |          |          |             |           |             |          |          |    |
+             |    +----------+          +-------------+-----------+-------------+          +----------+    |
+             |               |          |                                       |          |               |
+             |vm1            |          |                  dpdk                 |          |           vm2 |
+             |               |          |                                       |          |               |
+          +--+---------------------------------------------------------------------------------------------+--+
+          |  |                                       hugepages                                             |  |
+          |  +---------------------------------------------------------------------------------------------+  |
+          |                                                                                                   |
+          |                                              host                                                 |
+          |                                                                                                   |
+          +---------------------------------------------------------------------------------------------------+
 ```
 ## Prerequisites
 
@@ -30,44 +33,54 @@ Prior to running the test, the following steps need to be performed.
 - Install DPDK
 - Install OVS
 
-Here are some good references for detailing them.
-- Red Hat
-	* https://wiki.qemu.org/Documentation/vhost-user-ovs-dpdk
-- Ubuntu server
-	* https://help.ubuntu.com/lts/serverguide/DPDK.html
-	* https://software.intel.com/en-us/articles/set-up-open-vswitch-with-dpdk-on-ubuntu-server
+Here is a good reference for setting up OVS with DPDK from scratch:
+https://docs.openvswitch.org/en/latest/intro/install/dpdk/.
 
+On Ubuntu systems (18.04 or newer), the OpenVswitch-DPDK package can be
+easily installed with:
+```bash
+sudo apt-get update
+sudo apt-get install openvswitch-switch-dpdk
+sudo update-alternatives --set ovs-vswitchd /usr/lib/openvswitch-switch-dpdk/ovs-vswitchd-dpdk
+```
 ## Test
-The test runs with multiple queue (MQ) support enabled, using 2 pairs of TX/RX queues defined for both OVS and the virtual machine. Here are the details on how the test can be run.
+The test runs with multiple queue (MQ) support enabled, using 2 pairs of
+TX/RX queues defined for both OVS and the virtual machine. Here are the
+detailed instructions.
 
 _Setup OVS_
 
-`ovs_test.sh` is created to setup and start OVS. OVS will provide the `dpdkvhostuser` backend running in server mode.
+Here is an example how to configure a basic OpenVswitch using DPDK:
 ```bash
-mkdir -p /var/run/openvswitch
+# load the ovs kernel module
 modprobe openvswitch
-killall ovsdb-server ovs-vswitchd
-rm -f /var/run/openvswitch/vhost-user*
-rm -f /etc/openvswitch/conf.db
-export DB_SOCK=/var/run/openvswitch/db.sock
-ovsdb-tool create /etc/openvswitch/conf.db /usr/share/openvswitch/vswitch.ovsschema
-ovsdb-server --remote=punix:$DB_SOCK --remote=db:Open_vSwitch,Open_vSwitch,manager_options --pidfile --detach
-ovs-vsctl --no-wait init
-ovs-vsctl --no-wait set Open_vSwitch . other_config:dpdk-lcore-mask=0xf
-ovs-vsctl --no-wait set Open_vSwitch . other_config:dpdk-socket-mem=1024
-ovs-vsctl --no-wait set Open_vSwitch . other_config:dpdk-init=true
-ovs-vsctl --no-wait set Open_vSwitch . other_config:pmd-cpu-mask=0xf
-ovs-vswitchd unix:$DB_SOCK --pidfile --detach --log-file=/var/log/openvswitch/ovs-vswitchd.log
+sudo service openvswitch-switch start
+ovs-vsctl init
+ovs-vsctl set Open_vSwitch . other_config:dpdk-init=true
+# run on core 0-3 only
+ovs-vsctl set Open_vSwitch . other_config:dpdk-lcore-mask=0xf
+# allocate 2G huge pages (to NUMA 0 only)
+ovs-vsctl set Open_vSwitch . other_config:dpdk-socket-mem=1024
+# run PMD (Pull Mode Driver) threads on core 0-3 only
+ovs-vsctl set Open_vSwitch . other_config:pmd-cpu-mask=0xf
+sudo service openvswitch-switch restart
+# double check the configurations
+ovs-vsctl list Open_vSwitch
+```
+
+Here is an example how to create a bridge and add two DPDK ports to it
+(for later use via Cloud Hypervisor):
+```bash
+# create a bridge
 ovs-vsctl add-br ovsbr0 -- set bridge ovsbr0 datapath_type=netdev
+# create two DPDK ports and add them to the bridge
 ovs-vsctl add-port ovsbr0 vhost-user1 -- set Interface vhost-user1 type=dpdkvhostuser
-ovs-vsctl add-port ovsbr0 vhost-user2 -- set Interface vhost-user2 type=dpdkvhostuser
+ovs-vsctl add-port ovsbr0 vhost-user2 -- set Interface vhost-user2
+type=dpdkvhostuser
+# set the number of rx queues
 ovs-vsctl set Interface vhost-user1 options:n_rxq=2
 ovs-vsctl set Interface vhost-user2 options:n_rxq=2
 ```
-_Run ovs_test.sh_
-```bash
-./ovs_test.sh
-```
 
 _Launch the VMs_
 
@@ -76,32 +89,34 @@ VMs run in client mode. They connect to the socket created by the `dpdkvhostuser
 # From one terminal. We need to give the cloud-hypervisor binary the NET_ADMIN capabilities for it to set TAP interfaces up on the host.
 ./cloud-hypervisor \
         --cpus boot=2 \
-        --memory size=512M,file=/dev/hugepages   \
+        --memory size=512M,hugepages=on,shared=true \
         --kernel vmlinux \
-        --cmdline "reboot=k panic=1 nomodules i8042.noaux i8042.nomux i8042.nopnp i8042.dumbkbd root=/dev/vda3" \
-        --disk path=clear-kvm.img   \
-        --net "mac=52:54:00:02:d9:01,vhost_user=true,socket=/var/run/openvswitch/vhost-user1,num_queues=4"
+        --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
+        --disk path=focal-server-cloudimg-amd64.raw   \
+        --net mac=52:54:00:02:d9:01,vhost_user=true,socket=/var/run/openvswitch/vhost-user1,num_queues=4
 
 # From another terminal. We need to give the cloud-hypervisor binary the NET_ADMIN capabilities for it to set TAP interfaces up on the host.
 ./cloud-hypervisor \
         --cpus boot=2 \
-        --memory size=512M,file=/dev/hugepages   \
+        --memory size=512M,hugepages=on,shared=true \
         --kernel vmlinux \
-        --cmdline "reboot=k panic=1 nomodules i8042.noaux i8042.nomux i8042.nopnp i8042.dumbkbd root=/dev/vda3" \
-        --disk path=clear-kvm.img   \
-        --net "mac=52:54:20:11:C5:02,vhost_user=true,socket=/var/run/openvswitch/vhost-user2,num_queues=4"
+        --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
+        --disk path=focal-server-cloudimg-amd64.raw   \
+        --net mac=52:54:20:11:C5:02,vhost_user=true,socket=/var/run/openvswitch/vhost-user2,num_queues=4
 ```
 
 _Setup VM1_
 ```bash
 # From inside the guest
-sudo ip addr add 172.100.0.1/24 dev enp0s3
+sudo ip addr add 172.100.0.1/24 dev ens2
+sudo ip link set up dev ens2
 ```
 
 _Setup VM2_
 ```bash
 # From inside the guest
-sudo ip addr add 172.100.0.2/24 dev enp0s3
+sudo ip addr add 172.100.0.2/24 dev ens2
+sudo ip link set up dev ens2
 ```
 
 _Ping VM1 from VM2_
@@ -129,4 +144,3 @@ _Run VM2 as client_
 # From inside the guest
 iperf3 -c 172.100.0.1 -t 30 -p 4444 &
 ```
-

docs/virtiofs-root.md

@@ -0,0 +1,92 @@
+# HOWTO VirtioFS rootfs
+
+A quick guide for using virtiofs as a cloud-hypervisor guest's rootfs (i.e.
+with no root block device). This document is a quick getting started guide.
+There are many more steps to take to make this a production ready, secure
+setup.
+
+## Prerequisites
+
+1. virtiofsd from the qemu project
+   * We are using the Qemu version for now
+   * There is a Rust version being worked on that may be a better option in the future
+   * Part of the qemu-system-common package on Ubuntu
+   * Part of the qemu-common package on Fedora
+2. cloud-hypervisor - the newer the better, but I tested with 0.12
+3. a rootfs - This howto uses an alpine rootfs available here:
+   * https://dl-cdn.alpinelinux.org/alpine/v3.13/releases/x86_64/alpine-minirootfs-3.13.2-x86_64.tar.gz
+   * Others should work
+
+## To create the VM rootfs
+
+```bash
+mkdir rootfs/
+cd rootfs
+# this needs sudo to be able to set root permissions on fs components
+sudo tar -xf /path/to/alpine-minirootfs-3.13.1-x86_64.tar.gz
+# this will get created when the VM actually boots by the dhcp client
+# but we need it in the chroot to download packages
+sudo cp /etc/resolv.conf etc/
+# the alpine mini rootfs is meant for docker containers, we need a few extra
+# things for a working rootfs
+sudo chroot $PWD apk add openrc busybox-initscripts
+# we are using the paravirt console in cloud-hypervisor, so enable it in init
+# append it after the other console since it doesn't work just appending it
+sudo sed -i '/vt100/a \n# paravirt console\nhvc0::respawn:/sbin/getty -L hvc0 115200 vt100' etc/inittab
+# set no password for root user... you obviously don't want to do this for
+# any sort of production setup
+sudo sed -i 's/root:!::0:::::/root:::0:::::/' etc/shadow
+# set up init scripts
+for i in acpid crond
+    sudo ln -sf /etc/init.d/$i etc/runlevels/default/$i
+end
+for i in bootmisc hostname hwclock loadkmap modules networking swap sysctl syslog urandom
+    sudo ln -sf /etc/init.d/$i etc/runlevels/boot/$i
+end
+
+for i in killprocs mount-ro savecache
+    sudo ln -sf /etc/init.d/$i etc/runlevels/shutdown/$i
+end
+
+for i in devfs dmesg hwdrivers mdev
+    sudo ln -sf /etc/init.d/$i etc/runlevels/sysinit/$i
+end
+# setup network config
+echo 'auto lo
+iface lo inet loopback
+
+auto eth0
+iface eth0 inet dhcp
+' | sudo tee etc/network/interfaces
+
+```
+
+## To run the VM
+
+```bash
+# starting in the directory above rootfs
+sudo virtiofsd --socket-path=$PWD/virtiofs-rootfs.sock -o source=$PWD/rootfs -o cache=none &
+sudo cloud-hypervisor \
+    --cpus boot=1,max=1 \
+    --kernel vmlinux \
+    --fs tag=/dev/root,socket=$PWD/virtiofs-rootfs.sock \
+    --memory size=2G,shared=on \
+    --cmdline "console=hvc0 rootfstype=virtiofs root=/dev/root ro debug" \
+    --api-socket $PWD/ch.sock \
+    --rng \
+    --net ...
+```
+
+Note: an important part of the above is the `tag=/dev/root` and
+`root=/dev/root` parts. For whatever reason, it would only work with that as
+the tag.
+
+Note: another important bit is that the memory is shared. This is required for
+virtiofs
+
+## Message from the author
+
+If you find any issues or have suggestions, feel free to reach out to @iggy on
+the cloud-hypervisor slack. Also if this works for you, I'd like to know as
+well. It would also be nice to get steps for preparing other distribution root
+filesystems.