cpumf: Make short descriptions common for extended counter sets

The short descriptions for a counter in the extender counter
set should be identical for all models.
This patch fixes minor differences.

Signed-off-by: Thomas Richter <tmricht@linux.vnet.ibm.com>
Signed-off-by: Jan Höppner <hoeppner@linux.ibm.com>

cpumf/data/cpum-cf-extended-z13.ctr

@@ -17,7 +17,7 @@
 # Extended Counter Set
 # ---------------------------------------------------------------------
 Counter:128	Name:L1D_RO_EXCL_WRITES
-Short-Description:L1D RO Exclusive Writes
+Short-Description:L1D Read-only Exclusive Writes
 Description:
 A directory write to the Level-1 Data cache where the line was
 originally in a Read-Only state in the cache but has been updated
@@ -77,7 +77,7 @@ A translation entry has been written to the Level-2 TLB Page Table
 Entry arrays
 .
 Counter:138	Name:TLB2_CRSTE_HPAGE_WRITES
-Short-Description:TLB2 CRSTE One-Megabate Page Writes
+Short-Description:TLB2 CRSTE One-Megabyte Page Writes
 Description:
 A translation entry has been written to the Level-2 TLB Combined Region
 Segment Table Entry arrays for a one-megabyte large page translation
@@ -95,7 +95,7 @@ A TEND instruction has completed in a constrained transactional-execution
 mode
 .
 Counter:141	Name:TX_NC_TEND
-Short-Description:Completed TEND instructions in non constrained TX mode
+Short-Description:Completed TEND instructions in non-constrained TX mode
 Description:
 A TEND instruction has completed in a non-constrained
 transactional-execution mode
@@ -339,7 +339,7 @@ A directory write to the Level-1 Instruction cache directory where
 the returned cache line was sourced from On-Chip memory
 .
 Counter:218	Name:TX_NC_TABORT
-Short-Description:Aborted transaction in non constrained TX mode
+Short-Description:Aborted transactions in non-constrained TX mode
 Description:
 A transaction abort has occurred in a non-constrained
 transactional-execution mode
@@ -367,7 +367,7 @@ Description:
 Cycle count with one thread active
 .
 Counter:449	Name:MT_DIAG_CYCLES_TWO_THR_ACTIVE
-Short-Description:cycle count with two threads active
+Short-Description:Cycle count with two threads active
 Description:
 Cycle count with two threads active
 .

cpumf/data/cpum-cf-extended-z14.ctr

@@ -47,13 +47,13 @@ Table Entry array in the Level-2 TLB for a one-megabyte page or a
 Last Host Translation was done
 .
 Counter:132	Name:DTLB2_GPAGE_WRITES
-Short-Description:DTLB2 Two-Gigabye Page Writes
+Short-Description:DTLB2 Two-Gigabyte Page Writes
 Description:
 A translation entry for a two-gigabyte page was written into the
 Level-2 TLB
 .
 Counter:133	Name:L1D_L2D_SOURCED_WRITES
-Short-Description:L1D L2D SOURCED Writes
+Short-Description:L1D L2D Sourced Writes
 Description:
 A directory write to the Level-1 Data cache directory where the
 returned cache line was sourced from the Level-2 Data cache
@@ -101,7 +101,7 @@ A TEND instruction has completed in a constrained transactional-execution
 mode
 .
 Counter:141	Name:TX_NC_TEND
-Short-Description:Completed TEND instructions in non constrained TX mode
+Short-Description:Completed TEND instructions in non-constrained TX mode
 Description:
 A TEND instruction has completed in a non-constrained
 transactional-execution mode
@@ -125,7 +125,7 @@ A directory write to the Level-1 Data cache directory where the returned
 cache line was sourced from On-Chip memory
 .
 Counter:146	Name:L1D_ONCHIP_L3_SOURCED_WRITES_IV
-Short-Description:L1D On-Chip L3 Sourced Writes with intervention
+Short-Description:L1D On-Chip L3 Sourced Writes with Intervention
 Description:
 A directory write to the Level-1 Data cache directory where the returned
 cache line was sourced from an On-Chip Level-3 cache with intervention
@@ -143,7 +143,7 @@ A directory write to the Level-1 Data cache directory where the returned
 cache line was sourced from an On-Cluster memory
 .
 Counter:149	Name:L1D_ONCLUSTER_L3_SOURCED_WRITES_IV
-Short-Description:L1D On-Cluster L3 Sourced Writes with intervention
+Short-Description:L1D On-Cluster L3 Sourced Writes with Intervention
 Description:
 A directory write to the Level-1 Data cache directory where the returned
 cache line was sourced from an On-Cluster Level-3 cache with intervention
@@ -162,7 +162,7 @@ A directory write to the Level-1 Data cache directory where the returned
 cache line was sourced from Off-Cluster memory
 .
 Counter:152	Name:L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV
-Short-Description:L1D Off-Cluster L3 Sourced Writes with intervention
+Short-Description:L1D Off-Cluster L3 Sourced Writes with Intervention
 Description:
 A directory write to the Level-1 Data cache directory where the returned
 cache line was sourced from an Off-Cluster Level-3 cache with intervention
@@ -181,7 +181,7 @@ A directory write to the Level-1 Data cache directory where the returned
 cache line was sourced from Off-Drawer memory
 .
 Counter:155	Name:L1D_OFFDRAWER_L3_SOURCED_WRITES_IV
-Short-Description:L1D Off-Drawer L3 Sourced Writes with intervention
+Short-Description:L1D Off-Drawer L3 Sourced Writes with Intervention
 Description:
 A directory write to the Level-1 Data cache directory where the returned
 cache line was sourced from an Off-Drawer Level-3 cache with intervention
@@ -199,7 +199,7 @@ A directory write to the Level-1 Data cache directory where the returned
 cache line was sourced from Off-Drawer Level-4 cache
 .
 Counter:158	Name:L1D_ONCHIP_L3_SOURCED_WRITES_RO
-Short-Description:L1D On-Chip L3 Sourced Writes RO
+Short-Description:L1D On-Chip L3 Sourced Writes read-only
 Description:
 A directory write to the Level-1 Data cache directory where the returned
 cache line was sourced from On-Chip L3 but a read-only invalidate was
@@ -219,7 +219,7 @@ A directory write to the Level-1 Instruction cache directory where the
 returned cache ine was sourced from On-Chip memory
 .
 Counter:164	Name:L1I_ONCHIP_L3_SOURCED_WRITES_IV
-Short-Description:L1I On-Chip L3 Sourced Writes with intervention
+Short-Description:L1I On-Chip L3 Sourced Writes with Intervention
 Description:
 A directory write to the Level-1 Instruction cache directory where the
 returned cache ine was sourced from an On-Chip Level-3 cache with
@@ -239,7 +239,7 @@ A directory write to the Level-1 Instruction cache directory where the
 returned cache line was sourced from an On-Cluster memory
 .
 Counter:167	Name:L1I_ONCLUSTER_L3_SOURCED_WRITES_IV
-Short-Description:L1I On-Cluster L3 Sourced Writes with intervention
+Short-Description:L1I On-Cluster L3 Sourced Writes with Intervention
 Description:
 A directory write to the Level-1 Instruction cache directory where the
 returned cache line was sourced from On-Cluster Level-3 cache with
@@ -259,7 +259,7 @@ A directory write to the Level-1 Instruction cache directory where the
 returned cache line was sourced from Off-Cluster memory
 .
 Counter:170	Name:L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV
-Short-Description:L1I Off-Cluster L3 Sourced Writes with intervention
+Short-Description:L1I Off-Cluster L3 Sourced Writes with Intervention
 Description:
 A directory write to the Level-1 Instruction cache directory where the
 returned cache line was sourced from an Off-Cluster Level-3 cache with
@@ -279,7 +279,7 @@ A directory write to the Level-1 Instruction cache directory where the
 returned cache line was sourced from Off-Drawer memory
 .
 Counter:173	Name:L1I_OFFDRAWER_L3_SOURCED_WRITES_IV
-Short-Description:L1I Off-Drawer L3 Sourced Writes with intervention
+Short-Description:L1I Off-Drawer L3 Sourced Writes with Intervention
 Description:
 A directory write to the Level-1 Instruction cache directory where the
 returned cache line was sourced from an Off-Drawer Level-3 cache with
@@ -323,7 +323,7 @@ Description:
 Last Host Translation done
 .
 Counter:243	Name:TX_NC_TABORT
-Short-Description:Aborted transaction in non constrained TX mode
+Short-Description:Aborted transactions in non-constrained TX mode
 Description:
 A transaction abort has occurred in a non-constrained
 transactional-execution mode

cpumf/data/cpum-cf-extended-z196.ctr

@@ -46,7 +46,7 @@ A directory write to the Level-1 I-Cache directory where the returned
 cache line was sourced from an On Book Level-4 cache
 .
 Counter: 137	Name:L1D_RO_EXCL_WRITES
-Short-Description:L1D RO Excl Writes
+Short-Description:L1D Read-only Exclusive Writes
 Description:
 A directory write to the Level-1 D-Cache where the line was originally
 in a Read-Only state in the cache but has been updated to be in the
@@ -65,20 +65,20 @@ A directory write to the Level-1 I-Cache directory where the returned
 cache line was sourced from an Off Book Level-4 cache
 .
 Counter: 140	Name:DTLB1_HPAGE_WRITES
-Short-Description:DTLB1 HPAGE Writes
+Short-Description:DTLB1 One-Megabyte Page Writes
 Description:
 A translation entry has been written to the Level-1 Data Translation
 Lookaside Buffer for a one-megabyte page
 .
 Counter: 141	Name:L1D_LMEM_SOURCED_WRITES
-Short-Description:L1D LMEM Sourced Writes
+Short-Description:L1D Local Memory Sourced Writes
 Description:
 A directory write to the Level-1 D-Cache where the installed cache line
 was sourced from memory that is attached to the same book as the Data
 cache (Local Memory)
 .
 Counter: 142	Name:L1I_LMEM_SOURCED_WRITES
-Short-Description:L1I LMEM Sourced Writes
+Short-Description:L1I Local Memory Sourced Writes
 Description:
 A directory write to the Level-1 I-Cache where the installed cache
 line was sourced from memory that is attached to the same book as the
@@ -109,7 +109,7 @@ A translation entry has been written to the Level-2 TLB Page Table
 Entry arrays
 .
 Counter: 147	Name:TLB2_CRSTE_HPAGE_WRITES
-Short-Description:TLB2 CRSTE HPAGE Writes
+Short-Description:TLB2 CRSTE One-Megabyte Page Writes
 Description:
 A translation entry has been written to the Level-2 TLB Common Region
 Segment Table Entry arrays for a one-megabyte large page translation
@@ -121,25 +121,25 @@ A translation entry has been written to the Level-2 TLB Common Region
 Segment Table Entry arrays
 .
 Counter: 150	Name:L1D_ONCHIP_L3_SOURCED_WRITES
-Short-Description:L1D Onchip L3 Sourced Writes
+Short-Description:L1D On-Chip L3 Sourced Writes
 Description:
 A directory write to the Level-1 D-Cache directory where the returned
 cache line was sourced from an On Chip Level-3 cache
 .
 Counter: 152	Name:L1D_OFFCHIP_L3_SOURCED_WRITES
-Short-Description:L1D Offchip L3 Sourced Writes
+Short-Description:L1D Off-Chip L3 Sourced Writes
 Description:
 A directory write to the Level-1 D-Cache directory where the returned
 cache line was sourced from an Off Chip/On Book Level-3 cache
 .
 Counter: 153	Name:L1I_ONCHIP_L3_SOURCED_WRITES
-Short-Description:L1I Onchip L3 Sourced Writes
+Short-Description:L1I On-Chip L3 Sourced Writes
 Description:
 A directory write to the Level-1 I-Cache directory where the returned
 cache line was sourced from an On Chip Level-3 cache
 .
 Counter: 155	Name:L1I_OFFCHIP_L3_SOURCED_WRITES
-Short-Description:L1I Offchip L3 Sourced Writes
+Short-Description:L1I Off-Chip L3 Sourced Writes
 Description:
 A directory write to the Level-1 I-Cache directory where the returned
 cache line was sourced from an Off Chip/On Book Level-3 cache

cpumf/data/cpum-cf-extended-zEC12.ctr

@@ -49,7 +49,7 @@ line was sourced from memory that is attached to the same book as the
 Instruction cache (Local Memory)
 .
 Counter:138	Name:L1D_RO_EXCL_WRITES
-Short-Description:L1D RO Excl Writes
+Short-Description:L1D Read-only Exclusive Writes
 Description:
 A directory write to the Level-1 D-Cache where the line was originally
 in a Read-Only state in the cache but has been updated to be in the
@@ -106,7 +106,7 @@ cache line was sourced from an Off Book Level-3 cache without intervention
 .
 Counter:147	Name:L1D_ONBOOK_L4_SOURCED_WRITES
 Short-Description:L1D On-Book L4 Sourced Writes
-CDescription:
+Description:
 A directory write to the Level-1 Data cache directory where the returned
 cache line was sourced from an On Book Level-4 cache
 .
@@ -123,19 +123,19 @@ cache line was sourced from an Off Book Level-4 cache
 #    C .. constrained
 #
 Counter:149	Name:TX_NC_TEND
-Short-Description:Completed TEND instructions in non constrained TX mode
+Short-Description:Completed TEND instructions in non-constrained TX mode
 Description:
 A TEND instruction has completed in a nonconstrained
 transactional-execution mode
 .
 Counter:150	Name:L1D_ONCHIP_L3_SOURCED_WRITES_IV
-Short-Description:L1D On-Chip L3 Sourced Writes with intervention
+Short-Description:L1D On-Chip L3 Sourced Writes with Intervention
 Description:
 A directory write to the Level-1 Data cache directory where the returned
 cache line was sourced from a On Chip Level-3 cache with intervention
 .
 Counter:151	Name:L1D_OFFCHIP_L3_SOURCED_WRITES_IV
-Short-Description:L1D Off-Chip L3 Sourced Writes with intervention
+Short-Description:L1D Off-Chip L3 Sourced Writes with Intervention
 Description:
 A directory write to the Level-1 Data cache directory where the returned
 cache line was sourced from an Off Chip/On Book Level-3 cache with
@@ -143,7 +143,7 @@ intervention
 .
 # XXX Remove SOURCED from L1D_OFFBOOK_L3_SOURCED_WRITES...
 Counter:152	Name:L1D_OFFBOOK_L3_SOURCED_WRITES_IV
-Short-Description:L1D Off-Book L3 Sourced Writes with intervention
+Short-Description:L1D Off-Book L3 Sourced Writes with Intervention
 Description:
 A directory write to the Level-1 Data cache directory where the returned
 cache line was sourced from an Off Book Level-3 cache with intervention
@@ -188,28 +188,28 @@ A TEND instruction has completed in a constrained transactional-execution
 mode
 .
 Counter:159	Name:L1I_ONCHIP_L3_SOURCED_WRITES_IV
-Short-Description:L1I On-Chip L3 Sourced Writes with intervention
+Short-Description:L1I On-Chip L3 Sourced Writes with Intervention
 Description:
 A directory write to the Level-1 Instruction cache directory where the
 returned cache line was sourced from an On Chip Level-3 cache with
 intervention
 .
 Counter:160	Name:L1I_OFFCHIP_L3_SOURCED_WRITES_IV
-Short-Description:L1I Off-Chip L3 Sourced Writes with intervention
+Short-Description:L1I Off-Chip L3 Sourced Writes with Intervention
 Description:
 A directory write to the Level-1 Instruction cache directory where the
 returned cache line was sourced from an Off Chip/On Book Level-3 cache
 with intervention
 .
 Counter:161	Name:L1I_OFFBOOK_L3_SOURCED_WRITES_IV
-Short-Description:L1I Off-Book L3 Sourced Writes with intervention
+Short-Description:L1I Off-Book L3 Sourced Writes with Intervention
 Description:
 A directory write to the Level-1 Instruction cache directory where the
 returned cache line was sourced from an Off Book Level-3 cache with
 intervention
 .
 Counter:177	Name:TX_NC_TABORT
-Short-Description:Aborted transaction in non constrained TX mode
+Short-Description:Aborted transactions in non-constrained TX mode
 Description:
 A transaction abort has occurred in a nonconstrained
 transactional-execution mode