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cpumf/lscpumf: Add IBM z16 extended counter set definitions
Add IBM z16 extended counter set. For each counter in this set add the counter number, the short and long description and the counter number. Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> Acked-by: Sumanth Korikkar <sumanthk@linux.ibm.com> Signed-off-by: Jan Höppner <hoeppner@linux.ibm.com>
This commit is contained in:
Thomas Richter
committed by
Jan Höppner
Jan Höppner
parent
2515832469
commit
cce5f510c3
583
cpumf/lscpumf.c
583
cpumf/lscpumf.c
@@ -2555,6 +2555,586 @@ static struct counters cpumcf_z15_counters[] = {
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},
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};
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static struct counters cpumcf_z16_counters[] = {
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{
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.ctrnum = 128,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "L1D_RO_EXCL_WRITES",
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.desc = "A directory write to the Level-1 Data cache where"
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"\n\t\tthe line was originally in a Read-Only state in the"
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"\n\t\tcache but has been updated to be in the Exclusive"
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"\n\t\tstate that allows stores to the cache line.",
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},
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{
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.ctrnum = 129,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "DTLB2_WRITES",
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.desc = "A translation has been written into The Translation"
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"\n\t\tLookaside Buffer 2 (TLB2) and the request was made"
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"\n\t\tby the Level-1 Data cache. This is a replacement"
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"\n\t\tfor what was provided for the DTLB on z13 and prior"
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"\n\t\tmachines.",
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},
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{
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.ctrnum = 130,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "DTLB2_MISSES",
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.desc = "A TLB2 miss is in progress for a request made by"
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"\n\t\tthe Level-1 Data cache. Incremented by one for"
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"\n\t\tevery TLB2 miss in progress for the Level-1 Data"
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"\n\t\tcache on this cycle. This is a replacement for what"
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"\n\t\twas provided for the DTLB on z13 and prior"
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"\n\t\tmachines.",
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},
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{
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.ctrnum = 131,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "CRSTE_1MB_WRITES",
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.desc = "A translation entry was written into the Combined"
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"\n\t\tRegion and Segment Table Entry array in the Level-2"
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"\n\t\tTLB for a one-megabyte page.",
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},
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{
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.ctrnum = 132,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "DTLB2_GPAGE_WRITES",
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.desc = "A translation entry for a two-gigabyte page was"
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"\n\t\twritten into the Level-2 TLB.",
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},
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{
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.ctrnum = 134,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "ITLB2_WRITES",
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.desc = "A translation entry has been written into the"
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"\n\t\tTranslation Lookaside Buffer 2 (TLB2) and the"
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"\n\t\trequest was made by the instruction cache. This is"
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"\n\t\ta replacement for what was provided for the ITLB on"
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"\n\t\tz13 and prior machines.",
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},
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{
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.ctrnum = 135,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "ITLB2_MISSES",
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.desc = "A TLB2 miss is in progress for a request made by"
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"\n\t\tthe Level-1 Instruction cache. Incremented by one"
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"\n\t\tfor every TLB2 miss in progress for the Level-1"
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"\n\t\tInstruction cache in a cycle. This is a replacement"
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"\n\t\tfor what was provided for the ITLB on z13 and prior"
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"\n\t\tmachines.",
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},
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{
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.ctrnum = 137,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "TLB2_PTE_WRITES",
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.desc = "A translation entry was written into the Page Table"
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"\n\t\tEntry array in the Level-2 TLB.",
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},
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{
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.ctrnum = 138,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "TLB2_CRSTE_WRITES",
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.desc = "Translation entries were written into the Combined"
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"\n\t\tRegion and Segment Table Entry array and the Page"
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"\n\t\tTable Entry array in the Level-2 TLB.",
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},
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{
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.ctrnum = 139,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "TLB2_ENGINES_BUSY",
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.desc = "The number of Level-2 TLB translation engines busy"
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"\n\t\tin a cycle.",
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},
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{
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.ctrnum = 140,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "TX_C_TEND",
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.desc = "A TEND instruction has completed in a constrained"
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"\n\t\ttransactional-execution mode.",
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},
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{
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.ctrnum = 141,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "TX_NC_TEND",
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.desc = "A TEND instruction has completed in a non-"
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"\n\t\tconstrained transactional-execution mode.",
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},
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{
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.ctrnum = 143,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "L1C_TLB2_MISSES",
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.desc = "Increments by one for any cycle where a level-1"
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"\n\t\tcache or level-2 TLB miss is in progress.",
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},
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{
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.ctrnum = 145,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "DCW_REQ",
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.desc = "A directory write to the Level-1 Data cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tfrom the requestor’s Level-2 cache.",
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},
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{
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.ctrnum = 146,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "DCW_REQ_IV",
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.desc = "A directory write to the Level-1 Data cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tfrom the requestor’s Level-2 cache with"
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"\n\t\tintervention.",
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},
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{
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.ctrnum = 147,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "DCW_REQ_CHIP_HIT",
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.desc = "A directory write to the Level-1 Data cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tfrom the requestor’s Level-2 cache after using"
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"\n\t\tchip level horizontal persistence, Chip-HP hit.",
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},
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{
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.ctrnum = 148,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "DCW_REQ_DRAWER_HIT",
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.desc = "A directory write to the Level-1 Data cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tfrom the requestor’s Level-2 cache after using"
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"\n\t\tdrawer level horizontal persistence, Drawer-HP hit.",
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},
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{
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.ctrnum = 149,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "DCW_ON_CHIP",
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.desc = "A directory write to the Level-1 Data cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tfrom an On-Chip Level-2 cache.",
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},
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{
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.ctrnum = 150,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "DCW_ON_CHIP_IV",
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.desc = "A directory write to the Level-1 Data cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tfrom an On-Chip Level-2 cache with intervention.",
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},
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{
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.ctrnum = 151,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "DCW_ON_CHIP_CHIP_HIT",
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.desc = "A directory write to the Level-1 Data cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tfrom an On-Chip Level-2 cache after using chip"
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"\n\t\tlevel horizontal persistence, Chip-HP hit.",
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},
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{
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.ctrnum = 152,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "DCW_ON_CHIP_DRAWER_HIT",
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.desc = "A directory write to the Level-1 Data cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tfrom an On-Chip Level-2 cache using drawer level"
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"\n\t\thorizontal persistence, Drawer-HP hit.",
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},
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{
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.ctrnum = 153,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "DCW_ON_MODULE",
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.desc = "A directory write to the Level-1 Data cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tfrom an On-Module Level-2 cache.",
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},
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{
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.ctrnum = 154,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "DCW_ON_DRAWER",
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.desc = "A directory write to the Level-1 Data cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tfrom an On-Drawer Level-2 cache.",
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},
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{
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.ctrnum = 155,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "DCW_OFF_DRAWER",
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.desc = "A directory write to the Level-1 Data cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tfrom an Off-Drawer Level-2 cache.",
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},
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{
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.ctrnum = 156,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "DCW_ON_CHIP_MEMORY",
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.desc = "A directory write to the Level-1 Data cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tfrom On-Chip memory.",
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},
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{
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.ctrnum = 157,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "DCW_ON_MODULE_MEMORY",
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.desc = "A directory write to the Level-1 Data cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tfrom On-Module memory.",
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},
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{
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.ctrnum = 158,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "DCW_ON_DRAWER_MEMORY",
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.desc = "A directory write to the Level-1 Data cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tfrom On-Drawer memory.",
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},
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{
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.ctrnum = 159,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "DCW_OFF_DRAWER_MEMORY",
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.desc = "A directory write to the Level-1 Data cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tfrom Off-Drawer memory.",
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},
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{
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.ctrnum = 160,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "IDCW_ON_MODULE_IV",
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.desc = "A directory write to the Level-1 Data or Level-1"
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"\n\t\tInstruction cache directory where the returned"
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"\n\t\tcache line was sourced from an On-Module Level-2"
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"\n\t\tcache with intervention.",
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},
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{
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.ctrnum = 161,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "IDCW_ON_MODULE_CHIP_HIT",
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.desc = "A directory write to the Level-1 Data or Level-1"
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"\n\t\tInstruction cache directory where the returned"
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"\n\t\tcache line was sourced from an On-Module Level-2"
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"\n\t\tcache using chip horizontal persistence, Chip-HP"
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"\n\t\thit.",
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},
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{
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.ctrnum = 162,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "IDCW_ON_MODULE_DRAWER_HIT",
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.desc = "A directory write to the Level-1 Data or Level-1"
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"\n\t\tInstruction cache directory where the returned"
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"\n\t\tcache line was sourced from an On-Module Level-2"
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"\n\t\tcache using drawer level horizontal persistence,"
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"\n\t\tDrawer-HP hit.",
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},
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{
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.ctrnum = 163,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "IDCW_ON_DRAWER_IV",
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.desc = "A directory write to the Level-1 Data or Level-1"
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"\n\t\tInstruction cache directory where the returned"
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"\n\t\tcache line was sourced from an On-Drawer Level-2"
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"\n\t\tcache with intervention.",
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},
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{
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.ctrnum = 164,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "IDCW_ON_DRAWER_CHIP_HIT",
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.desc = "A directory write to the Level-1 Data or Level-1"
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"\n\t\tinstruction cache directory where the returned"
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"\n\t\tcache line was sourced from an On-Drawer Level-2"
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"\n\t\tcache using chip level horizontal persistence, Chip-"
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"\n\t\tHP hit.",
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},
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{
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.ctrnum = 165,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "IDCW_ON_DRAWER_DRAWER_HIT",
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.desc = "A directory write to the Level-1 Data or Level-1"
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"\n\t\tinstruction cache directory where the returned"
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"\n\t\tcache line was sourced from an On-Drawer Level-2"
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"\n\t\tcache using drawer level horizontal persistence,"
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"\n\t\tDrawer-HP hit.",
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},
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{
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.ctrnum = 166,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "IDCW_OFF_DRAWER_IV",
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.desc = "A directory write to the Level-1 Data or Level-1"
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"\n\t\tinstruction cache directory where the returned"
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"\n\t\tcache line was sourced from an Off-Drawer Level-2"
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"\n\t\tcache with intervention.",
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},
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{
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.ctrnum = 167,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "IDCW_OFF_DRAWER_CHIP_HIT",
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.desc = "A directory write to the Level-1 Data or Level-1"
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"\n\t\tinstruction cache directory where the returned"
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"\n\t\tcache line was sourced from an Off-Drawer Level-2"
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"\n\t\tcache using chip level horizontal persistence, Chip-"
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"\n\t\tHP hit.",
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},
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{
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.ctrnum = 168,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "IDCW_OFF_DRAWER_DRAWER_HIT",
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.desc = "A directory write to the Level-1 Data or Level-1"
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"\n\t\tInstruction cache directory where the returned"
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"\n\t\tcache line was sourced from an Off-Drawer Level-2"
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"\n\t\tcache using drawer level horizontal persistence,"
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"\n\t\tDrawer-HP hit.",
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},
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{
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.ctrnum = 169,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "ICW_REQ",
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.desc = "A directory write to the Level-1 Instruction cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tthe requestors Level-2 cache.",
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},
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{
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.ctrnum = 170,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "ICW_REQ_IV",
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.desc = "A directory write to the Level-1 Instruction cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tfrom the requestors Level-2 cache with"
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"\n\t\tintervention.",
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},
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{
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.ctrnum = 171,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "ICW_REQ_CHIP_HIT",
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.desc = "A directory write to the Level-1 Instruction cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tfrom the requestors Level-2 cache using chip level"
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"\n\t\thorizontal persistence, Chip-HP hit.",
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},
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{
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.ctrnum = 172,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "ICW_REQ_DRAWER_HIT",
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.desc = "A directory write to the Level-1 Instruction cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tfrom the requestor’s Level-2 cache using drawer"
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"\n\t\tlevel horizontal persistence, Drawer-HP hit.",
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},
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{
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.ctrnum = 173,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "ICW_ON_CHIP",
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.desc = "A directory write to the Level-1 Instruction cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tfrom an On-Chip Level-2 cache.",
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},
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{
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.ctrnum = 174,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "ICW_ON_CHIP_IV",
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.desc = "A directory write to the Level-1 Instruction cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tan On-Chip Level-2 cache with intervention.",
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},
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{
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.ctrnum = 175,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "ICW_ON_CHIP_CHIP_HIT",
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.desc = "A directory write to the Level-1 Instruction cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tfrom an On-Chip Level-2 cache using chip level"
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"\n\t\thorizontal persistence, Chip-HP hit.",
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},
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{
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.ctrnum = 176,
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.ctrset = CPUMF_CTRSET_EXTENDED,
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.name = "ICW_ON_CHIP_DRAWER_HIT",
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.desc = "A directory write to the Level-1 Instruction cache"
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"\n\t\tdirectory where the returned cache line was sourced"
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"\n\t\tfrom an On-Chip level 2 cache using drawer level"
|
||||
"\n\t\thorizontal persistence, Drawer-HP hit.",
|
||||
},
|
||||
{
|
||||
.ctrnum = 177,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "ICW_ON_MODULE",
|
||||
.desc = "A directory write to the Level-1 Instruction cache"
|
||||
"\n\t\tdirectory where the returned cache line was sourced"
|
||||
"\n\t\tfrom an On-Module Level-2 cache.",
|
||||
},
|
||||
{
|
||||
.ctrnum = 178,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "ICW_ON_DRAWER",
|
||||
.desc = "A directory write to the Level-1 Instruction cache"
|
||||
"\n\t\tdirectory where the returned cache line was sourced"
|
||||
"\n\t\tan On-Drawer Level-2 cache.",
|
||||
},
|
||||
{
|
||||
.ctrnum = 179,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "ICW_OFF_DRAWER",
|
||||
.desc = "A directory write to the Level-1 Instruction cache"
|
||||
"\n\t\tdirectory where the returned cache line was sourced"
|
||||
"\n\t\tan Off-Drawer Level-2 cache.",
|
||||
},
|
||||
{
|
||||
.ctrnum = 180,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "ICW_ON_CHIP_MEMORY",
|
||||
.desc = "A directory write to the Level-1 Instruction cache"
|
||||
"\n\t\tdirectory where the returned cache line was sourced"
|
||||
"\n\t\tfrom On-Chip memory.",
|
||||
},
|
||||
{
|
||||
.ctrnum = 181,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "ICW_ON_MODULE_MEMORY",
|
||||
.desc = "A directory write to the Level-1 Instruction cache"
|
||||
"\n\t\tdirectory where the returned cache line was sourced"
|
||||
"\n\t\tfrom On-Module memory.",
|
||||
},
|
||||
{
|
||||
.ctrnum = 182,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "ICW_ON_DRAWER_MEMORY",
|
||||
.desc = "A directory write to the Level-1 Instruction cache"
|
||||
"\n\t\tdirectory where the returned cache line was sourced"
|
||||
"\n\t\tfrom On-Drawer memory.",
|
||||
},
|
||||
{
|
||||
.ctrnum = 183,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "ICW_OFF_DRAWER_MEMORY",
|
||||
.desc = "A directory write to the Level-1 Instruction cache"
|
||||
"\n\t\tdirectory where the returned cache line was sourced"
|
||||
"\n\t\tfrom Off-Drawer memory.",
|
||||
},
|
||||
{
|
||||
.ctrnum = 224,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "BCD_DFP_EXECUTION_SLOTS",
|
||||
.desc = "Count of floating point execution slots used for"
|
||||
"\n\t\tfinished Binary Coded Decimal to Decimal Floating"
|
||||
"\n\t\tPoint conversions. Instructions: CDZT, CXZT, CZDT,"
|
||||
"\n\t\tCZXT.",
|
||||
},
|
||||
{
|
||||
.ctrnum = 225,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "VX_BCD_EXECUTION_SLOTS",
|
||||
.desc = "Count of floating point execution slots used for"
|
||||
"\n\t\tfinished vector arithmetic Binary Coded Decimal"
|
||||
"\n\t\tinstructions. Instructions: VAP, VSP, VMP, VMSP,"
|
||||
"\n\t\tVDP, VSDP, VRP, VLIP, VSRP, VPSOP, VCP, VTP, VPKZ,"
|
||||
"\n\t\tVUPKZ, VCVB, VCVBG, VCVD, VCVDG.",
|
||||
},
|
||||
{
|
||||
.ctrnum = 226,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "DECIMAL_INSTRUCTIONS",
|
||||
.desc = "Decimal instruction dispatched. Instructions: CVB,"
|
||||
"\n\t\tCVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP.",
|
||||
},
|
||||
{
|
||||
.ctrnum = 232,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "LAST_HOST_TRANSLATIONS",
|
||||
.desc = "Last Host Translation done",
|
||||
},
|
||||
{
|
||||
.ctrnum = 244,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "TX_NC_TABORT",
|
||||
.desc = "A transaction abort has occurred in a non-"
|
||||
"\n\t\tconstrained transactional-execution mode.",
|
||||
},
|
||||
{
|
||||
.ctrnum = 245,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "TX_C_TABORT_NO_SPECIAL",
|
||||
.desc = "A transaction abort has occurred in a constrained"
|
||||
"\n\t\ttransactional-execution mode and the CPU is not"
|
||||
"\n\t\tusing any special logic to allow the transaction to"
|
||||
"\n\t\tcomplete.",
|
||||
},
|
||||
{
|
||||
.ctrnum = 246,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "TX_C_TABORT_SPECIAL",
|
||||
.desc = "A transaction abort has occurred in a constrained"
|
||||
"\n\t\ttransactional-execution mode and the CPU is using"
|
||||
"\n\t\tspecial logic to allow the transaction to complete.",
|
||||
},
|
||||
{
|
||||
.ctrnum = 248,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "DFLT_ACCESS",
|
||||
.desc = "Cycles CPU spent obtaining access to Deflate unit",
|
||||
},
|
||||
{
|
||||
.ctrnum = 253,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "DFLT_CYCLES",
|
||||
.desc = "Cycles CPU is using Deflate unit",
|
||||
},
|
||||
{
|
||||
.ctrnum = 256,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "SORTL",
|
||||
.desc = "Increments by one for every SORT LISTS instruction"
|
||||
"\n\t\texecuted.",
|
||||
},
|
||||
{
|
||||
.ctrnum = 265,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "DFLT_CC",
|
||||
.desc = "Increments by one for every DEFLATE CONVERSION CALL"
|
||||
"\n\t\tinstruction executed.",
|
||||
},
|
||||
{
|
||||
.ctrnum = 266,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "DFLT_CCFINISH",
|
||||
.desc = "Increments by one for every DEFLATE CONVERSION CALL"
|
||||
"\n\t\tinstruction executed that ended in Condition Codes"
|
||||
"\n\t\t0, 1 or 2.",
|
||||
},
|
||||
{
|
||||
.ctrnum = 267,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "NNPA_INVOCATIONS",
|
||||
.desc = "Increments by one for every Neural Network"
|
||||
"\n\t\tProcessing Assist instruction executed.",
|
||||
},
|
||||
{
|
||||
.ctrnum = 268,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "NNPA_COMPLETIONS",
|
||||
.desc = "Increments by one for every Neural Network"
|
||||
"\n\t\tProcessing Assist instruction executed that ended"
|
||||
"\n\t\tin Condition Codes 0, 1 or 2.",
|
||||
},
|
||||
{
|
||||
.ctrnum = 269,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "NNPA_WAIT_LOCK",
|
||||
.desc = "Cycles CPU spent obtaining access to IBM Z"
|
||||
"\n\t\tIntegrated Accelerator for AI.",
|
||||
},
|
||||
{
|
||||
.ctrnum = 270,
|
||||
.ctrset = CPUMF_CTRSET_EXTENDED,
|
||||
.name = "NNPA_HOLD_LOCK",
|
||||
.desc = "Cycles CPU is using IBM Z Integrated Accelerator"
|
||||
"\n\t\tfor AI.",
|
||||
},
|
||||
{
|
||||
.ctrnum = 448,
|
||||
.ctrset = CPUMF_CTRSET_MT_DIAG,
|
||||
.name = "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
|
||||
.desc = "Cycle count with one thread active",
|
||||
},
|
||||
{
|
||||
.ctrnum = 449,
|
||||
.ctrset = CPUMF_CTRSET_MT_DIAG,
|
||||
.name = "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
|
||||
.desc = "Cycle count with two threads active",
|
||||
},
|
||||
};
|
||||
|
||||
/* Return the type number of the CPU Measurement facility from the sysfs file.
|
||||
* If the type number is equal to PERF_TYPE_RAW, then the prefix is 'r' to
|
||||
* specify the raw counter number by the perf tool.
|
||||
@@ -2890,6 +3470,9 @@ static struct counters *get_counter(int ctrset, size_t *len)
|
||||
*len = ARRAY_SIZE(cpumcf_z15_counters);
|
||||
read_ccerror(cp, *len);
|
||||
break;
|
||||
case UTIL_ARCH_MACHINE_TYPE_Z16:
|
||||
cp = cpumcf_z16_counters;
|
||||
*len = ARRAY_SIZE(cpumcf_z16_counters);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user