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aab339d3e3
The short descriptions for a counter in the extender counter set should be identical for all models. This patch fixes minor differences. Signed-off-by: Thomas Richter <tmricht@linux.vnet.ibm.com> Signed-off-by: Jan Höppner <hoeppner@linux.ibm.com>
358 lines
13 KiB
Plaintext
358 lines
13 KiB
Plaintext
# Counter decriptions for the
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# IBM z14 extended counter and MT-diagnostic counter set
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#
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# Notes for transactional-execution mode symbolic names:
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# TX .. transactional-execution mode
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# NC .. nonconstrained
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# C .. constrained
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#
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# Undefined counters in the extended counter set:
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# 142
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# 158-161
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# 176-223
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# 227-231
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# 233-242
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# 246-255
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# Undefined counters in the MT-diagnostic counter set:
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# 450-495
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#
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#
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# Extended Counter Set
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# ---------------------------------------------------------------------
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Counter:128 Name:L1D_RO_EXCL_WRITES
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Short-Description:L1D Read-only Exclusive Writes
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Description:
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A directory write to the Level-1 Data cache where the line was
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originally in a Read-Only state in the cache but has been updated
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to be in the Exclusive state that allows stores to the cache line
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.
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Counter:129 Name:DTLB2_WRITES
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Short-Description:DTLB2 Writes
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Description:
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A translation has been written into The Translation Lookaside
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Buffer 2 (TLB2) and the request was made by the data cache
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.
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Counter:130 Name:DTLB2_MISSES
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Short-Description:DTLB2 Misses
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Description:
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A TLB2 miss is in progress for a request made by the data cache.
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Incremented by one for every TLB2 miss in progress for the Level-1
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Data cache on this cycle
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.
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Counter:131 Name:DTLB2_HPAGE_WRITES
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Short-Description:DTLB2 One-Megabyte Page Writes
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Description:
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A translation entry was written into the Combined Region and Segment
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Table Entry array in the Level-2 TLB for a one-megabyte page or a
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Last Host Translation was done
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.
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Counter:132 Name:DTLB2_GPAGE_WRITES
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Short-Description:DTLB2 Two-Gigabyte Page Writes
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Description:
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A translation entry for a two-gigabyte page was written into the
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Level-2 TLB
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.
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Counter:133 Name:L1D_L2D_SOURCED_WRITES
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Short-Description:L1D L2D Sourced Writes
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Description:
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A directory write to the Level-1 Data cache directory where the
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returned cache line was sourced from the Level-2 Data cache
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.
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Counter:134 Name:ITLB2_WRITES
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Short-Description:ITLB2 Writes
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Description:
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A translation entry has been written into the Translation Lookaside
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Buffer 2 (TLB2) and the request was made by the instruction cache
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.
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Counter:135 Name:ITLB2_MISSES
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Short-Description:ITLB2 Misses
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Description:
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A TLB2 miss is in progress for a request made by the instruction cache.
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Incremented by one for every TLB2 miss in progress for the Level-1
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Instruction cache in a cycle
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.
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Counter:136 Name:L1I_L2I_SOURCED_WRITES
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Short-Description:L1I L2I Sourced Writes
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from the Level-2 Instruction cache
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.
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Counter:137 Name:TLB2_PTE_WRITES
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Short-Description:TLB2 PTE Writes
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Description:
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A translation entry was written into the Page Table Entry array in the
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Level-2 TLB
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.
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Counter:138 Name:TLB2_CRSTE_WRITES
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Short-Description:TLB2 CRSTE Writes
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Description:
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Translation entries were written into the Combined Region and Segment
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Table Entry array and the Page Table Entry array in the Level-2 TLB
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.
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Counter:139 Name:TLB2_ENGINES_BUSY
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Short-Description:TLB2 Engines Busy
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Description:
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The number of Level-2 TLB translation engines busy in a cycle
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.
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Counter:140 Name:TX_C_TEND
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Short-Description:Completed TEND instructions in constrained TX mode
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Description:
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A TEND instruction has completed in a constrained transactional-execution
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mode
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.
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Counter:141 Name:TX_NC_TEND
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Short-Description:Completed TEND instructions in non-constrained TX mode
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Description:
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A TEND instruction has completed in a non-constrained
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transactional-execution mode
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.
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Counter:143 Name:L1C_TLB2_MISSES
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Short-Description:L1C TLB2 Misses
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Description:
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Increments by one for any cycle where a level-1 cache or level-2 TLB miss
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is in progress
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.
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Counter:144 Name:L1D_ONCHIP_L3_SOURCED_WRITES
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Short-Description:L1D On-Chip L3 Sourced Writes
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an On-Chip Level-3 cache without intervention
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.
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Counter:145 Name:L1D_ONCHIP_MEMORY_SOURCED_WRITES
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Short-Description:L1D On-Chip Memory Sourced Writes
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from On-Chip memory
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.
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Counter:146 Name:L1D_ONCHIP_L3_SOURCED_WRITES_IV
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Short-Description:L1D On-Chip L3 Sourced Writes with Intervention
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an On-Chip Level-3 cache with intervention
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.
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Counter:147 Name:L1D_ONCLUSTER_L3_SOURCED_WRITES
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Short-Description:L1D On-Cluster L3 Sourced Writes
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from On-Cluster Level-3 cache withountervention
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.
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Counter:148 Name:L1D_ONCLUSTER_MEMORY_SOURCED_WRITES
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Short-Description:L1D On-Cluster Memory Sourced Writes
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an On-Cluster memory
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.
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Counter:149 Name:L1D_ONCLUSTER_L3_SOURCED_WRITES_IV
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Short-Description:L1D On-Cluster L3 Sourced Writes with Intervention
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an On-Cluster Level-3 cache with intervention
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.
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Counter:150 Name:L1D_OFFCLUSTER_L3_SOURCED_WRITES
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Short-Description:L1D Off-Cluster L3 Sourced Writes
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an Off-Cluster Level-3 cache without
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intervention
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.
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Counter:151 Name:L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES
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Short-Description:L1D Off-Cluster Memory Sourced Writes
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from Off-Cluster memory
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.
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Counter:152 Name:L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV
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Short-Description:L1D Off-Cluster L3 Sourced Writes with Intervention
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an Off-Cluster Level-3 cache with intervention
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.
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Counter:153 Name:L1D_OFFDRAWER_L3_SOURCED_WRITES
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Short-Description:L1D Off-Drawer L3 Sourced Writes
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an Off-Drawer Level-3 cache without
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intervention
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.
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Counter:154 Name:L1D_OFFDRAWER_MEMORY_SOURCED_WRITES
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Short-Description:L1D Off-Drawer Memory Sourced Writes
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from Off-Drawer memory
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.
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Counter:155 Name:L1D_OFFDRAWER_L3_SOURCED_WRITES_IV
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Short-Description:L1D Off-Drawer L3 Sourced Writes with Intervention
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from an Off-Drawer Level-3 cache with intervention
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.
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Counter:156 Name:L1D_ONDRAWER_L4_SOURCED_WRITES
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Short-Description:L1D On-Drawer L4 Sourced Writes
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from On-Drawer Level-4 cache
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.
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Counter:157 Name:L1D_OFFDRAWER_L4_SOURCED_WRITES
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Short-Description:L1D Off-Drawer L4 Sourced Writes
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from Off-Drawer Level-4 cache
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.
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Counter:158 Name:L1D_ONCHIP_L3_SOURCED_WRITES_RO
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Short-Description:L1D On-Chip L3 Sourced Writes read-only
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Description:
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A directory write to the Level-1 Data cache directory where the returned
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cache line was sourced from On-Chip L3 but a read-only invalidate was
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done to remove other copies of the cache line
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.
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Counter:162 Name:L1I_ONCHIP_L3_SOURCED_WRITES
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Short-Description:L1I On-Chip L3 Sourced Writes
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache ine was sourced from an On-Chip Level-3 cache without
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intervention
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.
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Counter:163 Name:L1I_ONCHIP_MEMORY_SOURCED_WRITES
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Short-Description:L1I On-Chip Memory Sourced Writes
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache ine was sourced from On-Chip memory
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.
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Counter:164 Name:L1I_ONCHIP_L3_SOURCED_WRITES_IV
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Short-Description:L1I On-Chip L3 Sourced Writes with Intervention
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache ine was sourced from an On-Chip Level-3 cache with
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intervention
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.
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Counter:165 Name:L1I_ONCLUSTER_L3_SOURCED_WRITES
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Short-Description:L1I On-Cluster L3 Sourced Writes
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from an On-Cluster Level-3 cache without
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intervention
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.
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Counter:166 Name:L1I_ONCLUSTER_MEMORY_SOURCED_WRITES
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Short-Description:L1I On-Cluster Memory Sourced Writes
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from an On-Cluster memory
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.
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Counter:167 Name:L1I_ONCLUSTER_L3_SOURCED_WRITES_IV
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Short-Description:L1I On-Cluster L3 Sourced Writes with Intervention
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from On-Cluster Level-3 cache with
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intervention
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.
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Counter:168 Name:L1I_OFFCLUSTER_L3_SOURCED_WRITES
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Short-Description:L1I Off-Cluster L3 Sourced Writes
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from an Off-Cluster Level-3 cache without
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intervention
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.
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Counter:169 Name:L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES
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Short-Description:L1I Off-Cluster Memory Sourced Writes
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from Off-Cluster memory
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.
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Counter:170 Name:L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV
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Short-Description:L1I Off-Cluster L3 Sourced Writes with Intervention
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from an Off-Cluster Level-3 cache with
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intervention
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.
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Counter:171 Name:L1I_OFFDRAWER_L3_SOURCED_WRITES
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Short-Description:L1I Off-Drawer L3 Sourced Writes
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from an Off-Drawer Level-3 cache without
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intervention
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.
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Counter:172 Name:L1I_OFFDRAWER_MEMORY_SOURCED_WRITES
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Short-Description:L1I Off-Drawer Memory Sourced Writes
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from Off-Drawer memory
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.
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Counter:173 Name:L1I_OFFDRAWER_L3_SOURCED_WRITES_IV
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Short-Description:L1I Off-Drawer L3 Sourced Writes with Intervention
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from an Off-Drawer Level-3 cache with
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intervention
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.
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Counter:174 Name:L1I_ONDRAWER_L4_SOURCED_WRITES
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Short-Description:L1I On-Drawer L4 Sourced Writes
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from On-Drawer Level-4 cache
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.
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Counter:175 Name:L1I_OFFDRAWER_L4_SOURCED_WRITES
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Short-Description:L1I Off-Drawer L4 Sourced Writes
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Description:
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A directory write to the Level-1 Instruction cache directory where the
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returned cache line was sourced from Off-Drawer Level-4 cache
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.
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Counter:224 Name:BCD_DFP_EXECUTION_SLOTS
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Short-Description:BCD DFP Execution Slots
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Description:
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Count of floating point execution slots used for finished Binary Coded
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Decimal to Decimal Floating Point conversions. Instructions: CDZT,
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CXZT, CZDT, CZXT
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.
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Counter:225 Name:VX_BCD_EXECUTION_SLOTS
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Short-Description:VX BCD Execution Slots
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Description:
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Count of floating point execution slots used for finished vector arithmetic
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Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP,
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VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG
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.
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Counter:226 Name:DECIMAL_INSTRUCTIONS
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Short-Description:Decimal Instructions
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Description:
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Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED,
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EDMK, MP, SRP, SP, ZAP
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.
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Counter:232 Name:LAST_HOST_TRANSLATIONS
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Short-Description:Last host translation done
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Description:
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Last Host Translation done
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.
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Counter:243 Name:TX_NC_TABORT
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Short-Description:Aborted transactions in non-constrained TX mode
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Description:
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A transaction abort has occurred in a non-constrained
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transactional-execution mode
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.
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Counter:244 Name:TX_C_TABORT_NO_SPECIAL
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Short-Description:Aborted transactions in constrained TX mode not using special completion logic
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Description:
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A transaction abort has occurred in a constrained transactional-execution
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mode and the CPU is not using any special logic to allow the transaction
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to complete
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.
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Counter:245 Name:TX_C_TABORT_SPECIAL
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Short-Description:Aborted transactions in constrained TX mode using special completion logic
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Description:
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A transaction abort has occurred in a constrained transactional-execution
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mode and the CPU is using special logic to allow the transaction to
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complete
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.
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#
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# MT-diagnostic counter set
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# ---------------------------------------------------------------------
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Counter:448 Name:MT_DIAG_CYCLES_ONE_THR_ACTIVE
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Short-Description:Cycle count with one thread active
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Description:
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Cycle count with one thread active
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.
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Counter:449 Name:MT_DIAG_CYCLES_TWO_THR_ACTIVE
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Short-Description:Cycle count with two threads active
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Description:
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Cycle count with two threads active
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.
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