rpm: Update spec file for version bump

Update the spec file for the rpm to the latest version.

Signed-off-by: Rob Bradford <robert.bradford@intel.com>

.github/workflows/audit.yaml

@@ -0,0 +1,15 @@
+name: Cloud Hypervisor Dependency Audit
+on:
+  pull_request:
+    paths: 
+      - '**/Cargo.toml'
+      - '**/Cargo.lock'
+jobs:
+  security_audit:
+    name: Audit
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v1
+      - uses: actions-rs/audit-check@v1
+        with:
+          token: ${{ secrets.GITHUB_TOKEN }}

.github/workflows/build.yaml

@@ -7,6 +7,7 @@ jobs:
     name: Build
     runs-on: ubuntu-latest
     strategy:
+      fail-fast: false
       matrix:
         rust:
           - stable
@@ -18,6 +19,9 @@ jobs:
     steps:
       - name: Code checkout
         uses: actions/checkout@v2
+        with:
+          fetch-depth: 0
+
       - name: Install Rust toolchain (${{ matrix.rust }})
         uses: actions-rs/toolchain@v1
         with:
@@ -25,5 +29,16 @@ jobs:
             target: ${{ matrix.target }}
             override: true
 
-      - name: Build
+      - name: Debug Check (default features)
+        run: |
+          git rev-list origin/master..$GITHUB_SHA | xargs -t -I % sh -c 'git checkout %; cargo check --all --target=${{ matrix.target }}'
+          git checkout $GITHUB_SHA
+
+      - name: Build (acpi,kvm)
+        run: cargo rustc --bin cloud-hypervisor --no-default-features --features "acpi,kvm"  -- -D warnings
+
+      - name: Build (kvm)
+        run: cargo rustc --bin cloud-hypervisor --no-default-features --features "kvm"  -- -D warnings
+        
+      - name: Release Build (default features)
         run: cargo build --all --release --target=${{ matrix.target }}

.github/workflows/cross-build.yaml

@@ -9,7 +9,7 @@ jobs:
     strategy:
       matrix:
         rust:
-          - stable
+          - 1.46.0
         target:
           - aarch64-unknown-linux-gnu
           - aarch64-unknown-linux-musl
@@ -29,4 +29,4 @@ jobs:
         with:
           use-cross: true
           command: build
-          args: --target=${{ matrix.target }} --no-default-features --features "mmio,kvm"
+          args: --target=${{ matrix.target }} --no-default-features --features "kvm"

.github/workflows/docker-image.yaml

@@ -0,0 +1,36 @@
+name: Cloud-Hypervisor's Docker image update
+
+on:
+  push:
+    branches: master
+    paths: resources/Dockerfile
+
+jobs:
+  main:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Code checkout
+        uses: actions/checkout@v2
+
+      - name: Set up QEMU
+        uses: docker/setup-qemu-action@v1
+
+      - name: Set up Docker Buildx
+        uses: docker/setup-buildx-action@v1
+
+      - name: Login to DockerHub
+        uses: docker/login-action@v1 
+        with:
+          username: ${{ secrets.DOCKERHUB_USERNAME }}
+          password: ${{ secrets.DOCKERHUB_TOKEN }}
+
+      - name: Build and push
+        uses: docker/build-push-action@v2
+        with:
+          file: ./resources/Dockerfile
+          platforms: linux/amd64,linux/arm64
+          push: true
+          tags: cloudhypervisor/dev:latest
+
+      - name: Image digest
+        run: echo ${{ steps.docker_build.outputs.digest }}

.github/workflows/fuzz-build.yaml

@@ -0,0 +1,27 @@
+name: Cloud Hypervisor Cargo Fuzz Build
+on: [pull_request, create]
+
+jobs:
+  build:
+    if: github.event_name == 'pull_request'
+    name: Cargo Fuzz Build
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        rust:
+          - nightly
+        target:
+          - x86_64-unknown-linux-gnu
+    steps:
+      - name: Code checkout
+        uses: actions/checkout@v2
+      - name: Install Rust toolchain (${{ matrix.rust }})
+        uses: actions-rs/toolchain@v1
+        with:
+            toolchain: ${{ matrix.rust }}
+            target: ${{ matrix.target }}
+            override: true
+      - name: Install Cargo fuzz
+        run: cargo install -f cargo-fuzz
+      - name: Cargo Fuzz Build
+        run: cargo fuzz build

.github/workflows/quality-aarch64.yaml

@@ -0,0 +1,34 @@
+name: Cloud Hypervisor Quality Checks
+on: [pull_request, create]
+
+jobs:
+  build:
+    if: github.event_name == 'pull_request'
+    name: Quality (clippy, rustfmt)
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        rust:
+          - stable
+        target:
+          - aarch64-unknown-linux-gnu
+    steps:
+      - name: Code checkout
+        uses: actions/checkout@v2
+      - name: Install Rust toolchain (${{ matrix.rust }})
+        uses: actions-rs/toolchain@v1
+        with:
+            toolchain: ${{ matrix.rust }}
+            target: ${{ matrix.target }}
+            override: true
+            components: rustfmt, clippy
+      - name: Install arm64 libfdt
+        run: wget http://ftp.us.debian.org/debian/pool/main/d/device-tree-compiler/libfdt-dev_1.6.0-1_arm64.deb && dpkg-deb -xv libfdt-dev_1.6.0-1_arm64.deb ./tlibfdtdev && sudo mkdir /tmmmp && mkdir target && mkdir target/debug && mkdir target/debug/deps && sudo cp ./tlibfdtdev/usr/lib/aarch64-linux-gnu/libfdt.a target/debug/deps/libfdt.a && echo "libfdt installed"
+      - name: Formatting (rustfmt)
+        run: cargo fmt -- --check
+      - name: Clippy (kvm)
+        uses: actions-rs/cargo@v1
+        with:
+          use-cross: true
+          command: clippy
+          args: --target=${{ matrix.target }} --no-default-features --features "kvm" -- -D warnings

.github/workflows/quality.yaml

@@ -0,0 +1,45 @@
+name: Cloud Hypervisor Quality Checks
+on: [pull_request, create]
+
+jobs:
+  build:
+    if: github.event_name == 'pull_request'
+    name: Quality (clippy, rustfmt)
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        rust:
+          - stable
+        target:
+          - x86_64-unknown-linux-gnu
+    steps:
+      - name: Code checkout
+        uses: actions/checkout@v2
+      - name: Install Rust toolchain (${{ matrix.rust }})
+        uses: actions-rs/toolchain@v1
+        with:
+          toolchain: ${{ matrix.rust }}
+          target: ${{ matrix.target }}
+          override: true
+          components: rustfmt, clippy
+
+      - name: Formatting (rustfmt)
+        run: cargo fmt -- --check
+
+      - name: Clippy (all features,kvm)
+        run: cargo clippy --all --all-targets --no-default-features --tests --features "common,kvm" -- -D warnings
+
+      - name: Clippy (all features,mshv)
+        run: cargo clippy --all --all-targets --no-default-features --tests --features "common,mshv" -- -D warnings
+
+      - name: Clippy (acpi,kvm)
+        run: cargo clippy --all --all-targets --no-default-features --tests --features "acpi,kvm" -- -D warnings
+
+      - name: Clippy (kvm)
+        run: cargo clippy --all --all-targets --no-default-features --tests --features "kvm" -- -D warnings
+
+      - name: Clippy (acpi,mshv)
+        run: cargo clippy --all --all-targets --no-default-features --tests --features "acpi,mshv" -- -D warnings
+
+      - name: Clippy (mshv)
+        run: cargo clippy --all --all-targets --no-default-features --tests --features "mshv" -- -D warnings

CONTRIBUTING.md

@@ -88,5 +88,5 @@ Fixes #88
 Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
 ```
 
-Then, after the correspoding PR is merged, Github will automatically close that issue when parsing the
+Then, after the corresponding PR is merged, Github will automatically close that issue when parsing the
 [commit message](https://help.github.com/articles/closing-issues-via-commit-messages/).

Cargo.toml

@@ -1,47 +1,60 @@
 [package]
 name = "cloud-hypervisor"
-version = "0.9.0"
+version = "0.12.0"
 authors = ["The Cloud Hypervisor Authors"]
 edition = "2018"
 default-run = "cloud-hypervisor"
 build = "build.rs"
+license = "LICENSE-APACHE & LICENSE-BSD-3-Clause"
+description = "Open source Virtual Machine Monitor (VMM) that runs on top of KVM"
+homepage = "https://github.com/cloud-hypervisor/cloud-hypervisor"
 
 [profile.release]
 lto = true
 
 [dependencies]
-clap = { version = "2.33.2", features = ["wrap_help"] }
+anyhow = "1.0"
+api_client = { path = "api_client" }
+clap = { version = "2.33.3", features = ["wrap_help"] }
+epoll = ">=4.0.1"
 hypervisor = { path = "hypervisor" }
-libc = "0.2.74"
+libc = "0.2.81"
 log = { version = "0.4.11", features = ["std"] }
+option_parser = { path = "option_parser" }
 seccomp = { git = "https://github.com/firecracker-microvm/firecracker", tag = "v0.22.0" }
-serde_json = "1.0.57"
-vhost_user_block = { path = "vhost_user_block"}
-vhost_user_net = { path = "vhost_user_net"}
+serde_json = "1.0.60"
+thiserror = "1.0"
 vmm = { path = "vmm" }
-vmm-sys-util = "0.6.1"
+vmm-sys-util = "0.7.0"
+wait-timeout = "0.2.0"
+vm-memory = "0.4.0"
 
-[patch.crates-io]
-vm-memory = { git = "https://github.com/cloud-hypervisor/vm-memory", branch = "ch" }
+[build-dependencies]
+clap = { version = "2.33.3", features = ["wrap_help"] }
+
+# List of patched crates
+[patch.'https://github.com/rust-vmm/vhost']
+vhost_rs = { git = "https://github.com/cloud-hypervisor/vhost", branch = "ch", package = "vhost", features = ["vhost-user-master", "vhost-user-slave"] }
 
 [dev-dependencies]
-ssh2 = "0.8.2"
+ssh2 = "0.9.0"
 dirs = "3.0.1"
 credibility = "0.1.3"
 tempdir = "0.3.7"
 lazy_static= "1.4.0"
 tempfile = "3.1.0"
-serde_json = "1.0.57"
+serde_json = "1.0.60"
 net_util = { path = "net_util" }
 
 [features]
-default = ["acpi", "pci", "cmos", "kvm"]
+default = ["acpi", "cmos", "io_uring", "kvm"]
+# Common features for all hypervisors
+common = ["acpi", "cmos", "fwdebug", "io_uring"]
 acpi = ["vmm/acpi"]
-pci = ["vmm/pci_support"]
-mmio = ["vmm/mmio_support"]
 cmos = ["vmm/cmos"]
 fwdebug = ["vmm/fwdebug"]
 kvm = ["vmm/kvm"]
+mshv = ["vmm/mshv"]
 io_uring = ["vmm/io_uring"]
 
 # Integration tests require a special environment to run in
@@ -50,6 +63,7 @@ integration_tests = []
 [workspace]
 members = [
     "acpi_tables",
+    "api_client",
     "arch",
     "arch_gen",
     "block_util",
@@ -62,7 +76,6 @@ members = [
     "qcow",
     "vhost_user_backend",
     "vhost_user_block",
-    "vhost_user_fs",
     "vhost_user_net",
     "virtio-devices",
     "vmm",

Jenkinsfile

@@ -24,31 +24,36 @@ pipeline{
 		stage ('Build') {
 			failFast true
             parallel {
-				stage ('Master build') {
-					agent { node { label 'master' } }
+				stage ('Worker build') {
+					agent { node { label 'groovy' } }
 					stages {
 						stage ('Checkout') {
 							steps {
 								checkout scm
 							}
 						}
-						stage ('Run Cargo tests') {
-							steps {
-								sh "scripts/dev_cli.sh tests --cargo"
-							}
-						}
 						stage ('Run OpenAPI tests') {
 							steps {
 								sh "scripts/run_openapi_tests.sh"
 							}
 						}
+						stage ('Run unit tests') {
+							steps {
+								sh "scripts/dev_cli.sh tests --unit"
+							}
+						}
+						stage ('Run integration tests') {
+							options {
+								timeout(time: 1, unit: 'HOURS')
+							}
+							steps {
+								sh "scripts/dev_cli.sh tests --integration"
+							}
+						}
 					}
-				}	
-				stage ('Worker build') {
-					agent { node { label 'bionic' } }
-					options {
-						timeout(time: 1, unit: 'HOURS')
-					}
+				}
+				stage ('AArch64 worker build') {
+					agent { node { label 'bionic-arm64' } }
 					stages {
 						stage ('Checkout') {
 							steps {
@@ -62,19 +67,22 @@ pipeline{
 						}
 						stage ('Run integration tests') {
 							options {
-								retry(3)
+								timeout(time: 1, unit: 'HOURS')
 							}
 							steps {
 								sh "scripts/dev_cli.sh tests --integration"
 							}
 						}
 					}
+					post {
+						always {
+							sh "sudo chown -R jenkins.jenkins ${WORKSPACE}"
+							deleteDir()
+						}
+					}
 				}
 				stage ('Worker build (musl)') {
-					agent { node { label 'bionic' } }
-					options {
-						timeout(time: 1, unit: 'HOURS')
-					}
+					agent { node { label 'groovy' } }
 					stages {
 						stage ('Checkout') {
 							steps {
@@ -88,7 +96,7 @@ pipeline{
 						}
 						stage ('Run integration tests for musl') {
 							options {
-								retry(3)
+								timeout(time: 1, unit: 'HOURS')
 							}
 							steps {
 								sh "scripts/dev_cli.sh tests --integration --libc musl"
@@ -96,6 +104,80 @@ pipeline{
 						}
 					}
 				}
+				stage ('Worker build SGX') {
+					agent { node { label 'bionic-sgx' } }
+					when { branch 'master' }
+					stages {
+						stage ('Checkout') {
+							steps {
+								checkout scm
+							}
+						}
+						stage ('Run SGX integration tests') {
+							options {
+								timeout(time: 1, unit: 'HOURS')
+							}
+							steps {
+								sh "scripts/dev_cli.sh tests --integration-sgx"
+							}
+						}
+						stage ('Run SGX integration tests for musl') {
+							options {
+								timeout(time: 1, unit: 'HOURS')
+							}
+							steps {
+								sh "scripts/dev_cli.sh tests --integration-sgx --libc musl"
+							}
+						}
+					}
+					post {
+						always {
+							sh "sudo chown -R jenkins.jenkins ${WORKSPACE}"
+							deleteDir()
+						}
+					}
+				}
+				stage ('Worker build - Windows guest') {
+					agent { node { label 'groovy-win' } }
+					stages {
+						stage ('Checkout') {
+							steps {
+								checkout scm
+							}
+						}
+						stage ('Download assets') {
+							steps {
+								sh "mkdir ${env.HOME}/workloads"
+								azureDownload(storageCredentialId: 'ch-image-store',
+											  containerName: 'private-images',
+											  includeFilesPattern: 'OVMF.fd',
+											  downloadType: 'container',
+											  downloadDirLoc: "${env.HOME}/workloads")
+								azureDownload(storageCredentialId: 'ch-image-store',
+											  containerName: 'private-images',
+											  includeFilesPattern: 'windows-server-2019.raw',
+											  downloadType: 'container',
+											  downloadDirLoc: "${env.HOME}/workloads")
+							}
+						}
+						stage ('Run Windows guest integration tests') {
+							options {
+								timeout(time: 1, unit: 'HOURS')
+							}
+							steps {
+								sh "scripts/dev_cli.sh tests --integration-windows"
+							}
+						}
+						stage ('Run Windows guest integration tests for musl') {
+							options {
+								timeout(time: 1, unit: 'HOURS')
+							}
+							steps {
+								sh "scripts/dev_cli.sh tests --integration-windows --libc musl"
+							}
+						}
+					}
+				}
 			}
 		}
 	}

README.md

@@ -1,36 +1,34 @@
 [![Build Status](https://travis-ci.com/cloud-hypervisor/cloud-hypervisor.svg?branch=master)](https://travis-ci.com/cloud-hypervisor/cloud-hypervisor)
 
-1. [What is Cloud Hypervisor?](#1-what-is-cloud-hypervisor)
-   * [Requirements](#requirements)
-	 + [High Level](#high-level)
-     + [Architectures](#architectures)
-	 + [Guest OS](#guest-os)
-2. [Getting Started](#2-getting-started)
-   * [Clone and build](#clone-and-build)
-   * [Run](#run)
-	 + [Cloud image](#cloud-image)
-	 + [Custom kernel and disk image](#custom-kernel-and-disk-image)
-		 - [Building your kernel](#building-your-kernel)
-		 - [Disk image](#disk-image)
-		 - [Booting the guest VM](#booting-the-guest-vm)
-3. [Status](#2-status)
-	* [Device Model](#device-model)
-	* [TODO](#todo)
-4. [rust-vmm dependency](#4-rust-vmm-dependency)
-	* [Firecracker and crosvm](#firecracker-and-crosvm)
-5. [Community](#5-community)
-	* [Contribute](#contribute)
-	* [Join us](#join-us)
-6. [Security](#6-security)
+- [1. What is Cloud Hypervisor?](#1-what-is-cloud-hypervisor)
+  - [Objectives](#objectives)
+    - [High Level](#high-level)
+    - [Architectures](#architectures)
+    - [Guest OS](#guest-os)
+- [2. Getting Started](#2-getting-started)
+  - [Clone and build](#clone-and-build)
+    - [Containerized builds and tests](#containerized-builds-and-tests)
+  - [Run](#run)
+    - [Cloud image](#cloud-image)
+    - [Custom kernel and disk image](#custom-kernel-and-disk-image)
+      - [Building your kernel](#building-your-kernel)
+      - [Disk image](#disk-image)
+      - [Booting the guest VM](#booting-the-guest-vm)
+- [3. Status](#3-status)
+  - [Hot Plug](#hot-plug)
+  - [Device Model](#device-model)
+  - [TODO](#todo)
+- [4. `rust-vmm` project dependency](#4-rust-vmm-project-dependency)
+  - [Firecracker and crosvm](#firecracker-and-crosvm)
+- [5. Community](#5-community)
+  - [Contribute](#contribute)
+  - [Join us](#join-us)
 
 # 1. What is Cloud Hypervisor?
 
-**This project is an experiment and should not be used with production workloads.**
-
 Cloud Hypervisor is an open source Virtual Machine Monitor (VMM) that runs on top of [KVM](https://www.kernel.org/doc/Documentation/virtual/kvm/api.txt).
 The project focuses on exclusively running modern, cloud workloads, on top of a limited set of hardware architectures and platforms.
-Cloud workloads refers to those that are usually run by customers inside a cloud provider. For our purposes this means modern
-Linux* distributions with most I/O handled by paravirtualised devices (i.e. virtio), no requirement for legacy devices and recent CPUs and KVM.
+Cloud workloads refers to those that are usually run by customers inside a cloud provider. For our purposes this means modern operating systems with most I/O handled by paravirtualised devices (i.e. virtio), no requirement for legacy devices, and 64-bit CPUs.
 
 Cloud Hypervisor is implemented in [Rust](https://www.rust-lang.org/) and is based on the [rust-vmm](https://github.com/rust-vmm) crates.
 
@@ -38,27 +36,24 @@ Cloud Hypervisor is implemented in [Rust](https://www.rust-lang.org/) and is bas
 
 ### High Level
 
-* KVM and KVM only based
-* Minimal emulation
-* Low latency
-* Low memory footprint
-* Low complexity
-* High performance
-* Small attack surface
-* 64-bit support only
-* Build time configurable CPU, memory, PCI and NVDIMM hotplug
-* Machine to machine migration
+- KVM based
+- Minimal emulation
+- Low latency
+- Low memory footprint
+- Low complexity
+- High performance
+- Small attack surface
+- 64-bit support only
+- CPU, memory, PCI hotplug
+- Machine to machine migration
 
 ### Architectures
 
-`cloud-hypervisor` only supports the `x86-64` CPU architecture for now.
-
-We're planning to add support for the `AArch64` architecture in the future.
+Cloud Hypervisor supports the `x86-64` and `AArch64` architectures. There are some small differences in functionality between the two architectures (see [#1125](https://github.com/cloud-hypervisor/cloud-hypervisor/issues/1125)).
 
 ### Guest OS
-* `64-bit Linux`
 
-Support for *modern* 64-bit Windows guest is being evaluated.
+Cloud Hypervisor supports `64-bit Linux` with support for _modern_ 64-bit Windows guests currently under development.
 
 # 2. Getting Started
 
@@ -69,6 +64,23 @@ $ export CLOUDH=$HOME/cloud-hypervisor
 $ mkdir $CLOUDH
 ```
 
+## Install prerequisites
+
+You need to install some prerequisite packages in order to build and test Cloud Hypervisor.
+Here, all the steps are based on Ubuntu, for other Linux distributions please replace the
+package manager and package name.
+
+```shell
+# Install git
+$ sudo apt install git
+# Install rust tool chain
+$ curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh
+# Install build-essential
+$ sudo apt install build-essential
+# If you want to build statically linked binary please add musl target
+$ rustup target add x86_64-unknown-linux-musl
+```
+
 ## Clone and build
 
 First you need to clone and build the cloud-hypervisor repo:
@@ -82,6 +94,8 @@ $ cargo build --release
 # We need to give the cloud-hypervisor binary the NET_ADMIN capabilities for it to set TAP interfaces up on the host.
 $ sudo setcap cap_net_admin+ep ./target/release/cloud-hypervisor
 
+# If you want to build statically linked binary
+$ cargo build --release --target=x86_64-unknown-linux-musl --all
 $ popd
 ```
 
@@ -121,8 +135,8 @@ You can run a guest VM by either using an existing cloud image or booting into y
 
 ### Cloud image
 
-`cloud-hypervisor` supports booting disk images containing all needed
-components to run cloud workloads, a.k.a. cloud images.  To do that we rely on
+Cloud Hypervisor supports booting disk images containing all needed
+components to run cloud workloads, a.k.a. cloud images. To do that we rely on
 the [Rust Hypervisor
 Firmware](https://github.com/cloud-hypervisor/rust-hypervisor-firmware) project to provide
 an ELF
@@ -157,8 +171,7 @@ Multiple arguments can be given to the `--disk` parameter.
 
 #### Building your kernel
 
-`cloud-hypervisor` also supports direct kernel boot into a `vmlinux` ELF kernel
-image. In order to support virtio-fs and virtio-iommu we have our own development branch. You are of course able to use your own kernel but these instructions will continue with the version that we develop and test against.
+Cloud Hypervisor also supports direct kernel boot into a `vmlinux` ELF kernel or `bzImage`. In order to support virtio-fs and virtio-iommu we have our own development branch. You are of course able to use your own kernel but these instructions will continue with the version that we develop and test against.
 
 To build the kernel:
 
@@ -228,51 +241,52 @@ $ ./cloud-hypervisor/target/release/cloud-hypervisor \
 
 # 3. Status
 
-`cloud-hypervisor` is in a very early, pre-alpha stage. Use at your own risk!
+Cloud Hypervisor is under active development. No API or feature stability is guaranteed.
 
 As of 2020-07-02, the following cloud images are supported:
-* [Ubuntu Bionic](https://cloud-images.ubuntu.com/bionic/current/) (cloudimg)
-* [Ubuntu Focal](https://cloud-images.ubuntu.com/focal/current/) (cloudimg)
 
-Direct kernel boot to userspace should work with most rootfs.
+- [Ubuntu Bionic](https://cloud-images.ubuntu.com/bionic/current/) (cloudimg)
+- [Ubuntu Focal](https://cloud-images.ubuntu.com/focal/current/) (cloudimg)
+
+Direct kernel boot to userspace should work with a rootfs from most distributions.
 
 ## Hot Plug
 
-This [document](https://github.com/cloud-hypervisor/cloud-hypervisor/blob/master/docs/hotplug.md) details how to add devices to
-a running VM. Currently only CPU hot plug is supported.
+Cloud Hypervisor supports hotplug of CPUs, passthrough devices (VFIO), `virtio-{net,block,pmem,fs,vsock}` and memory resizing. This [document](https://github.com/cloud-hypervisor/cloud-hypervisor/blob/master/docs/hotplug.md) details how to add devices to
+a running VM.
 
 ## Device Model
 
-Follow this [documentation](https://github.com/cloud-hypervisor/cloud-hypervisor/blob/master/docs/device_model.md).
+Details of the device model can be found in this [documentation](https://github.com/cloud-hypervisor/cloud-hypervisor/blob/master/docs/device_model.md).
 
 ## TODO
 
-We are not tracking the `cloud-hypervisor` TODO list from a specific git tracked file but through
+We are not tracking the Cloud Hypervisor TODO list from a specific git tracked file but through
 [github issues](https://github.com/cloud-hypervisor/cloud-hypervisor/issues/new) instead.
 
 # 4. `rust-vmm` project dependency
 
 In order to satisfy the design goal of having a high-performance, security-focused hypervisor the decision
 was made to use the [Rust](https://www.rust-lang.org/) programming language.
-The language's strong focus on memory and thread safety makes it an ideal candidate for implementing VMMs
+The language's strong focus on memory and thread safety makes it an ideal candidate for implementing VMMs.
 
-Instead of implementing the VMM components from scratch, `cloud-hypervisor` is importing the [rust-vmm](https://github.com/rust-vmm)
+Instead of implementing the VMM components from scratch, Cloud Hypervisor is importing the [rust-vmm](https://github.com/rust-vmm)
 crates, and sharing code and architecture together with other VMMs like e.g. Amazon's [Firecracker](https://firecracker-microvm.github.io/)
 and Google's [crosvm](https://chromium.googlesource.com/chromiumos/platform/crosvm/).
 
-`cloud-hypervisor` embraces the rust-vmm project goals, which is to be able to share and re-use
-as many virtualization crates as possible. As such, the `cloud-hypervisor` relationship with the rust-vmm
+Cloud Hypervisor embraces the rust-vmm project goals, which is to be able to share and re-use
+as many virtualization crates as possible. As such, the Cloud Hypervisor relationship with the rust-vmm
 project is twofold:
 
 1. It will use as much of the rust-vmm code as possible. Any new rust-vmm crate that's relevant to the project
    goals will be integrated as soon as possible.
-2. As it is likely that the rust-vmm project will lack some of the features that `cloud-hypervisor` needs (e.g. ACPI,
-   VFIO, vhost-user, etc), we will be using the `cloud-hypervisor` VMM to implement and test them, and contribute them
+2. As it is likely that the rust-vmm project will lack some of the features that Cloud Hypervisor needs (e.g. ACPI,
+   VFIO, vhost-user, etc), we will be using the Cloud Hypervisor VMM to implement and test them, and contribute them
    back to the rust-vmm project.
 
 ## Firecracker and crosvm
 
-A large part of the `cloud-hypervisor` code is based on either the Firecracker or the crosvm projects implementations.
+A large part of the Cloud Hypervisor code is based on either the Firecracker or the crosvm projects implementations.
 Both of these are VMMs written in Rust with a focus on safety and security, like Cloud Hypervisor.
 
 However we want to emphasize that the Cloud Hypervisor project is neither a fork nor a reimplementation of any of those
@@ -303,27 +317,3 @@ etc, are all equal and welcome means of contribution. See the [CONTRIBUTING](CON
 
 Get an [invite to our Slack channel](https://join.slack.com/t/cloud-hypervisor/shared_invite/enQtNjY3MTE3MDkwNDQ4LWQ1MTA1ZDVmODkwMWQ1MTRhYzk4ZGNlN2UwNTI3ZmFlODU0OTcwOWZjMTkwZDExYWE3YjFmNzgzY2FmNDAyMjI)
 and [join us on Slack](https://cloud-hypervisor.slack.com/).
-
-# 6. Security
-
-**Reporting a Potential Security Vulnerability**: If you have discovered
-potential security vulnerability in this project, please send an e-mail to
-secure@intel.com. For issues related to Intel Products, please visit
-https://security-center.intel.com.
-
-It is important to include the following details:
-  - The projects and versions affected
-  - Detailed description of the vulnerability
-  - Information on known exploits
-
-Vulnerability information is extremely sensitive. Please encrypt all security
-vulnerability reports using our *PGP key*
-
-A member of the Intel Product Security Team will review your e-mail and
-contact you to to collaborate on resolving the issue. For more information on
-how Intel works to resolve security issues, see: *Vulnerability Handling
-Guidelines*
-
-PGP Key: https://www.intel.com/content/www/us/en/security-center/pgp-public-key.html
-
-Vulnerability Handling Guidelines: https://www.intel.com/content/www/us/en/security-center/vulnerability-handling-guidelines.html

acpi_tables/Cargo.toml

@@ -5,5 +5,5 @@ authors = ["The Cloud Hypervisor Authors"]
 edition = "2018"
 
 [dependencies]
-vm-memory = "0.2.1"
+vm-memory = "0.4.0"
 

api_client/Cargo.toml

@@ -0,0 +1,5 @@
+[package]
+name = "api_client"
+version = "0.1.0"
+authors = ["The Cloud Hypervisor Authors"]
+edition = "2018"

api_client/src/lib.rs

@@ -0,0 +1,175 @@
+// Copyright © 2020 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+
+use std::fmt;
+use std::io::{Read, Write};
+
+#[derive(Debug)]
+pub enum Error {
+    Socket(std::io::Error),
+    StatusCodeParsing(std::num::ParseIntError),
+    MissingProtocol,
+    ContentLengthParsing(std::num::ParseIntError),
+    ServerResponse(StatusCode, Option<String>),
+}
+
+impl fmt::Display for Error {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        use Error::*;
+        match self {
+            Socket(e) => write!(f, "Error writing to or reading from HTTP socket: {}", e),
+            StatusCodeParsing(e) => write!(f, "Error parsing HTTP status code: {}", e),
+            MissingProtocol => write!(f, "HTTP output is missing protocol statement"),
+            ContentLengthParsing(e) => write!(f, "Error parsing HTTP Content-Length field: {}", e),
+            ServerResponse(s, o) => {
+                if let Some(o) = o {
+                    write!(f, "Server responded with an error: {:?}: {}", s, o)
+                } else {
+                    write!(f, "Server responded with an error: {:?}", s)
+                }
+            }
+        }
+    }
+}
+
+#[derive(Clone, Copy, Debug)]
+pub enum StatusCode {
+    Continue,
+    OK,
+    NoContent,
+    BadRequest,
+    NotFound,
+    InternalServerError,
+    NotImplemented,
+    Unknown,
+}
+
+impl StatusCode {
+    fn from_raw(code: usize) -> StatusCode {
+        match code {
+            100 => StatusCode::Continue,
+            200 => StatusCode::OK,
+            204 => StatusCode::NoContent,
+            400 => StatusCode::BadRequest,
+            404 => StatusCode::NotFound,
+            500 => StatusCode::InternalServerError,
+            501 => StatusCode::NotImplemented,
+            _ => StatusCode::Unknown,
+        }
+    }
+
+    fn parse(code: &str) -> Result<StatusCode, Error> {
+        Ok(StatusCode::from_raw(
+            code.trim().parse().map_err(Error::StatusCodeParsing)?,
+        ))
+    }
+
+    fn is_server_error(self) -> bool {
+        !matches!(
+            self,
+            StatusCode::OK | StatusCode::Continue | StatusCode::NoContent
+        )
+    }
+}
+
+fn get_header<'a>(res: &'a str, header: &'a str) -> Option<&'a str> {
+    let header_str = format!("{}: ", header);
+    if let Some(o) = res.find(&header_str) {
+        Some(&res[o + header_str.len()..o + res[o..].find('\r').unwrap()])
+    } else {
+        None
+    }
+}
+
+fn get_status_code(res: &str) -> Result<StatusCode, Error> {
+    if let Some(o) = res.find("HTTP/1.1") {
+        Ok(StatusCode::parse(
+            &res[o + "HTTP/1.1 ".len()..res[o..].find('\r').unwrap()],
+        )?)
+    } else {
+        Err(Error::MissingProtocol)
+    }
+}
+
+fn parse_http_response(socket: &mut dyn Read) -> Result<Option<String>, Error> {
+    let mut res = String::new();
+    let mut body_offset = None;
+    let mut content_length: Option<usize> = None;
+    loop {
+        let mut bytes = vec![0; 256];
+        let count = socket.read(&mut bytes).map_err(Error::Socket)?;
+        res.push_str(std::str::from_utf8(&bytes[0..count]).unwrap());
+
+        // End of headers
+        if let Some(o) = res.find("\r\n\r\n") {
+            body_offset = Some(o + "\r\n\r\n".len());
+
+            // With all headers available we can see if there is any body
+            content_length = if let Some(length) = get_header(&res, "Content-Length") {
+                Some(length.trim().parse().map_err(Error::ContentLengthParsing)?)
+            } else {
+                None
+            };
+
+            if content_length.is_none() {
+                break;
+            }
+        }
+
+        if let Some(body_offset) = body_offset {
+            if let Some(content_length) = content_length {
+                if res.len() >= content_length + body_offset {
+                    break;
+                }
+            }
+        }
+    }
+    let body_string = content_length.and(Some(String::from(&res[body_offset.unwrap()..])));
+    let status_code = get_status_code(&res)?;
+
+    if status_code.is_server_error() {
+        Err(Error::ServerResponse(status_code, body_string))
+    } else {
+        Ok(body_string)
+    }
+}
+
+pub fn simple_api_command<T: Read + Write>(
+    socket: &mut T,
+    method: &str,
+    c: &str,
+    request_body: Option<&str>,
+) -> Result<(), Error> {
+    socket
+        .write_all(
+            format!(
+                "{} /api/v1/vm.{} HTTP/1.1\r\nHost: localhost\r\nAccept: */*\r\n",
+                method, c
+            )
+            .as_bytes(),
+        )
+        .map_err(Error::Socket)?;
+
+    if let Some(request_body) = request_body {
+        socket
+            .write_all(format!("Content-Length: {}\r\n", request_body.len()).as_bytes())
+            .map_err(Error::Socket)?;
+    }
+
+    socket.write_all(b"\r\n").map_err(Error::Socket)?;
+
+    if let Some(request_body) = request_body {
+        socket
+            .write_all(request_body.as_bytes())
+            .map_err(Error::Socket)?;
+    }
+
+    socket.flush().map_err(Error::Socket)?;
+
+    if let Some(body) = parse_http_response(socket)? {
+        println!("{}", body);
+    }
+    Ok(())
+}

arch/Cargo.toml

@@ -11,9 +11,13 @@ acpi = ["acpi_tables"]
 anyhow = "1.0"
 byteorder = "1.3.4"
 hypervisor = { path = "../hypervisor" }
-libc = "0.2.74"
+libc = "0.2.81"
 log = "0.4.11"
-vm-memory = { version = "0.2.1", features = ["backend-mmap"] }
+serde = {version = ">=1.0.27", features = ["rc"] }
+serde_derive = ">=1.0.27"
+serde_json = ">=1.0.9"
+vm-memory = { version = "0.4.0", features = ["backend-mmap"] }
+vm-migration = { path = "../vm-migration" }
 acpi_tables = { path = "../acpi_tables", optional = true }
 arch_gen = { path = "../arch_gen" }
 

arch/src/aarch64/fdt.rs

@@ -90,16 +90,16 @@ pub enum Error {
 type Result<T> = result::Result<T, Error>;
 
 /// Creates the flattened device tree for this aarch64 VM.
-pub fn create_fdt<T: DeviceInfoForFDT + Clone + Debug>(
+pub fn create_fdt<T: DeviceInfoForFDT + Clone + Debug, S: ::std::hash::BuildHasher>(
     guest_mem: &GuestMemoryMmap,
     cmdline: &CStr,
     vcpu_mpidr: Vec<u64>,
-    device_info: &HashMap<(DeviceType, String), T>,
-    gic_device: &Box<dyn GICDevice>,
+    device_info: &HashMap<(DeviceType, String), T, S>,
+    gic_device: &dyn GICDevice,
     initrd: &Option<InitramfsConfig>,
-    pci_space_address: &Option<(u64, u64)>,
+    pci_space_address: &(u64, u64),
 ) -> Result<Vec<u8>> {
-    // Alocate stuff necessary for the holding the blob.
+    // Allocate stuff necessary for the holding the blob.
     let mut fdt = vec![0; FDT_MAX_SIZE];
 
     allocate_fdt(&mut fdt)?;
@@ -126,9 +126,7 @@ pub fn create_fdt<T: DeviceInfoForFDT + Clone + Debug>(
     create_clock_node(&mut fdt)?;
     create_psci_node(&mut fdt)?;
     create_devices_node(&mut fdt, device_info)?;
-    if let Some((pci_device_base, pci_device_size)) = pci_space_address {
-        create_pci_nodes(&mut fdt, *pci_device_base, *pci_device_size)?;
-    }
+    create_pci_nodes(&mut fdt, pci_space_address.0, pci_space_address.1)?;
 
     // End Header node.
     append_end_node(&mut fdt)?;
@@ -311,7 +309,7 @@ fn generate_prop64(cells: &[u64]) -> Vec<u8> {
 }
 
 // Following are the auxiliary function for creating the different nodes that we append to our FDT.
-fn create_cpu_nodes(fdt: &mut Vec<u8>, vcpu_mpidr: &Vec<u64>) -> Result<()> {
+fn create_cpu_nodes(fdt: &mut Vec<u8>, vcpu_mpidr: &[u64]) -> Result<()> {
     // See https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/arm/cpus.yaml.
     append_begin_node(fdt, "cpus")?;
     // As per documentation, on ARM v8 64-bit systems value should be set to 2.
@@ -319,7 +317,7 @@ fn create_cpu_nodes(fdt: &mut Vec<u8>, vcpu_mpidr: &Vec<u64>) -> Result<()> {
     append_property_u32(fdt, "#size-cells", 0x0)?;
     let num_cpus = vcpu_mpidr.len();
 
-    for cpu_index in 0..num_cpus {
+    for (cpu_index, mpidr) in vcpu_mpidr.iter().enumerate().take(num_cpus) {
         let cpu_name = format!("cpu@{:x}", cpu_index);
         append_begin_node(fdt, &cpu_name)?;
         append_property_string(fdt, "device_type", "cpu")?;
@@ -330,7 +328,7 @@ fn create_cpu_nodes(fdt: &mut Vec<u8>, vcpu_mpidr: &Vec<u64>) -> Result<()> {
         }
         // Set the field to first 24 bits of the MPIDR - Multiprocessor Affinity Register.
         // See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0488c/BABHBJCI.html.
-        append_property_u64(fdt, "reg", vcpu_mpidr[cpu_index] & 0x7FFFFF)?;
+        append_property_u64(fdt, "reg", mpidr & 0x7FFFFF)?;
         append_end_node(fdt)?;
     }
     append_end_node(fdt)?;
@@ -376,7 +374,7 @@ fn create_chosen_node(
     Ok(())
 }
 
-fn create_gic_node(fdt: &mut Vec<u8>, gic_device: &Box<dyn GICDevice>) -> Result<()> {
+fn create_gic_node(fdt: &mut Vec<u8>, gic_device: &dyn GICDevice) -> Result<()> {
     let gic_reg_prop = generate_prop64(gic_device.device_properties());
 
     append_begin_node(fdt, "intc")?;
@@ -402,7 +400,7 @@ fn create_gic_node(fdt: &mut Vec<u8>, gic_device: &Box<dyn GICDevice>) -> Result
 
     if gic_device.msi_compatible() {
         append_begin_node(fdt, "msic")?;
-        append_property_string(fdt, "compatible", gic_device.msi_compatiblility())?;
+        append_property_string(fdt, "compatible", gic_device.msi_compatibility())?;
         append_property_null(fdt, "msi-controller")?;
         append_property_u32(fdt, "phandle", MSI_PHANDLE)?;
         let msi_reg_prop = generate_prop64(gic_device.msi_properties());
@@ -521,9 +519,9 @@ fn create_rtc_node<T: DeviceInfoForFDT + Clone + Debug>(
     Ok(())
 }
 
-fn create_devices_node<T: DeviceInfoForFDT + Clone + Debug>(
+fn create_devices_node<T: DeviceInfoForFDT + Clone + Debug, S: ::std::hash::BuildHasher>(
     fdt: &mut Vec<u8>,
-    dev_info: &HashMap<(DeviceType, String), T>,
+    dev_info: &HashMap<(DeviceType, String), T, S>,
 ) -> Result<()> {
     // Create one temp Vec to store all virtio devices
     let mut ordered_virtio_device: Vec<&T> = Vec::new();
@@ -539,7 +537,7 @@ fn create_devices_node<T: DeviceInfoForFDT + Clone + Debug>(
     }
 
     // Sort out virtio devices by address from low to high and insert them into fdt table.
-    ordered_virtio_device.sort_by(|a, b| a.addr().cmp(&b.addr()));
+    ordered_virtio_device.sort_by_key(|&a| a.addr());
     // Current address allocation strategy in cloud-hypervisor is: the first created device
     // will be allocated to higher address. Here we reverse the vector to make sure that
     // the older created device will appear in front of the newer created device in FDT.

arch/src/aarch64/gic/dist_regs.rs

@@ -0,0 +1,182 @@
+// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+// SPDX-License-Identifier: Apache-2.0
+
+use super::{Error, Result};
+use crate::layout::IRQ_BASE;
+use hypervisor::kvm::kvm_bindings::{
+    kvm_device_attr, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
+};
+use std::sync::Arc;
+
+/*
+ Distributor registers as detailed at page 456 from
+ https://static.docs.arm.com/ihi0069/c/IHI0069C_gic_architecture_specification.pdf.
+ Address offsets are relative to the Distributor base address defined
+by the system memory map. Unless otherwise stated in the register description,
+all GIC registers are 32-bits wide.
+ */
+const GICD_CTLR: u32 = 0x0;
+const GICD_STATUSR: u32 = 0x0010;
+const GICD_IGROUPR: u32 = 0x0080;
+const GICD_ISENABLER: u32 = 0x0100;
+const GICD_ICENABLER: u32 = 0x0180;
+const GICD_ISPENDR: u32 = 0x0200;
+const GICD_ICPENDR: u32 = 0x0280;
+const GICD_ISACTIVER: u32 = 0x0300;
+const GICD_ICACTIVER: u32 = 0x0380;
+const GICD_IPRIORITYR: u32 = 0x0400;
+const GICD_ICFGR: u32 = 0x0C00;
+const GICD_IROUTER: u32 = 0x6000;
+
+/// This is how we represent the registers of the vgic's distributor.
+/// Some of the distributor register )(i.e GICD_STATUSR) are simple
+/// registers (i.e they are associated to a 32 bit value).
+/// However, there are other registers that have variable lengths since
+/// they dedicate some of the 32 bits to some specific interrupt. So, their length
+/// depends on the number of interrupts (i.e the ones that are represented as GICD_REG<n>)
+/// in the documentation mentioned above.
+struct DistReg {
+    /// Offset from distributor address.
+    base: u32,
+    /// Bits per interrupt.
+    /// Relevant for registers that DO share IRQs.
+    bpi: u8,
+    /// Length of the register.
+    /// Relevant for registers that DO NOT share IRQs.
+    length: u16,
+}
+
+// All or at least the registers we are interested in are 32 bit, so
+// we use a constant for size(u32).
+const REG_SIZE: u8 = 4;
+
+// Creates a vgic distributor register.
+macro_rules! VGIC_DIST_REG {
+    ($base:expr, $bpi:expr, $length:expr) => {
+        DistReg {
+            base: $base,
+            bpi: $bpi,
+            length: $length,
+        }
+    };
+}
+
+// List with relevant distributor registers that we will be restoring.
+// Order is taken from qemu.
+static VGIC_DIST_REGS: &'static [DistReg] = &[
+    VGIC_DIST_REG!(GICD_STATUSR, 0, 4),
+    VGIC_DIST_REG!(GICD_ICENABLER, 1, 0),
+    VGIC_DIST_REG!(GICD_ISENABLER, 1, 0),
+    VGIC_DIST_REG!(GICD_IGROUPR, 1, 0),
+    VGIC_DIST_REG!(GICD_IROUTER, 64, 0),
+    VGIC_DIST_REG!(GICD_ICFGR, 2, 0),
+    VGIC_DIST_REG!(GICD_ICPENDR, 1, 0),
+    VGIC_DIST_REG!(GICD_ISPENDR, 1, 0),
+    VGIC_DIST_REG!(GICD_ICACTIVER, 1, 0),
+    VGIC_DIST_REG!(GICD_ISACTIVER, 1, 0),
+    VGIC_DIST_REG!(GICD_IPRIORITYR, 8, 0),
+];
+
+fn dist_attr_access(
+    gic: &Arc<dyn hypervisor::Device>,
+    offset: u32,
+    val: &u32,
+    set: bool,
+) -> Result<()> {
+    let mut gic_dist_attr = kvm_device_attr {
+        group: KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
+        attr: offset as u64,
+        addr: val as *const u32 as u64,
+        flags: 0,
+    };
+    if set {
+        gic.set_device_attr(&gic_dist_attr)
+            .map_err(Error::SetDeviceAttribute)?;
+    } else {
+        gic.get_device_attr(&mut gic_dist_attr)
+            .map_err(Error::GetDeviceAttribute)?;
+    }
+    Ok(())
+}
+
+/// Get the distributor control register.
+pub fn read_ctlr(gic: &Arc<dyn hypervisor::Device>) -> Result<u32> {
+    let val: u32 = 0;
+    dist_attr_access(gic, GICD_CTLR, &val, false)?;
+    Ok(val)
+}
+
+/// Set the distributor control register.
+pub fn write_ctlr(gic: &Arc<dyn hypervisor::Device>, val: u32) -> Result<()> {
+    dist_attr_access(gic, GICD_CTLR, &val, true)
+}
+
+fn get_interrupts_num(gic: &Arc<dyn hypervisor::Device>) -> Result<u32> {
+    let num_irq = 0;
+
+    let mut nr_irqs_attr = kvm_device_attr {
+        group: KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
+        attr: 0,
+        addr: &num_irq as *const u32 as u64,
+        flags: 0,
+    };
+    gic.get_device_attr(&mut nr_irqs_attr)
+        .map_err(Error::GetDeviceAttribute)?;
+    Ok(num_irq)
+}
+
+fn compute_reg_len(gic: &Arc<dyn hypervisor::Device>, reg: &DistReg, base: u32) -> Result<u32> {
+    let mut end = base;
+    let num_irq = get_interrupts_num(gic)?;
+    if reg.length > 0 {
+        // This is the single type register (i.e one that is not DIST_X<n>) and for which
+        // the bpi is 0.
+        // Look in the kernel for REGISTER_DESC_WITH_LENGTH.
+        end = base + reg.length as u32;
+    }
+    if reg.bpi > 0 {
+        // This is the type of register that takes into account the number of interrupts
+        // that the model has. It is also the type of register where
+        // a register relates to multiple interrupts.
+        end = base + (reg.bpi as u32 * (num_irq - IRQ_BASE) / 8);
+        if reg.bpi as u32 * (num_irq - IRQ_BASE) % 8 > 0 {
+            end += REG_SIZE as u32;
+        }
+    }
+    Ok(end)
+}
+
+/// Set distributor registers of the GIC.
+pub fn set_dist_regs(gic: &Arc<dyn hypervisor::Device>, state: &[u32]) -> Result<()> {
+    let mut idx = 0;
+
+    for dreg in VGIC_DIST_REGS {
+        let mut base = dreg.base + REG_SIZE as u32 * dreg.bpi as u32;
+        let end = compute_reg_len(gic, &dreg, base)?;
+
+        while base < end {
+            let val = state[idx];
+            dist_attr_access(gic, base, &val, true)?;
+            idx += 1;
+            base += REG_SIZE as u32;
+        }
+    }
+    Ok(())
+}
+/// Get distributor registers of the GIC.
+pub fn get_dist_regs(gic: &Arc<dyn hypervisor::Device>) -> Result<Vec<u32>> {
+    let mut state = Vec::new();
+
+    for dreg in VGIC_DIST_REGS {
+        let mut base = dreg.base + REG_SIZE as u32 * dreg.bpi as u32;
+        let end = compute_reg_len(gic, &dreg, base)?;
+
+        while base < end {
+            let val: u32 = 0;
+            dist_attr_access(gic, base, &val, false)?;
+            state.push(val);
+            base += REG_SIZE as u32;
+        }
+    }
+    Ok(state)
+}

arch/src/aarch64/gic/gicv3.rs

@@ -0,0 +1,275 @@
+// Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+// SPDX-License-Identifier: Apache-2.0
+
+pub mod kvm {
+    use crate::aarch64::gic::dist_regs::{get_dist_regs, read_ctlr, set_dist_regs, write_ctlr};
+    use crate::aarch64::gic::icc_regs::{get_icc_regs, set_icc_regs};
+    use crate::aarch64::gic::kvm::{save_pending_tables, KvmGICDevice};
+    use crate::aarch64::gic::redist_regs::{get_redist_regs, set_redist_regs};
+    use crate::aarch64::gic::GICDevice;
+    use crate::layout;
+    use anyhow::anyhow;
+    use hypervisor::kvm::kvm_bindings;
+    use std::any::Any;
+    use std::convert::TryInto;
+    use std::sync::Arc;
+    use std::{boxed::Box, result};
+    use vm_migration::{
+        Migratable, MigratableError, Pausable, Snapshot, SnapshotDataSection, Snapshottable,
+        Transportable,
+    };
+
+    /// Errors thrown while saving/restoring the GICv3.
+    #[derive(Debug)]
+    pub enum Error {
+        /// Error in saving RDIST pending tables into guest RAM.
+        SavePendingTables(crate::aarch64::gic::Error),
+        /// Error in saving GIC distributor registers.
+        SaveDistributorRegisters(crate::aarch64::gic::Error),
+        /// Error in restoring GIC distributor registers.
+        RestoreDistributorRegisters(crate::aarch64::gic::Error),
+        /// Error in saving GIC distributor control registers.
+        SaveDistributorCtrlRegisters(crate::aarch64::gic::Error),
+        /// Error in restoring GIC distributor control registers.
+        RestoreDistributorCtrlRegisters(crate::aarch64::gic::Error),
+        /// Error in saving GIC redistributor registers.
+        SaveRedistributorRegisters(crate::aarch64::gic::Error),
+        /// Error in restoring GIC redistributor registers.
+        RestoreRedistributorRegisters(crate::aarch64::gic::Error),
+        /// Error in saving GIC CPU interface registers.
+        SaveICCRegisters(crate::aarch64::gic::Error),
+        /// Error in restoring GIC CPU interface registers.
+        RestoreICCRegisters(crate::aarch64::gic::Error),
+    }
+
+    type Result<T> = result::Result<T, Error>;
+
+    pub struct KvmGICv3 {
+        /// The hypervisor agnostic device
+        device: Arc<dyn hypervisor::Device>,
+
+        /// Vector holding values of GICR_TYPER for each vCPU
+        gicr_typers: Vec<u64>,
+
+        /// GIC device properties, to be used for setting up the fdt entry
+        properties: [u64; 4],
+
+        /// Number of CPUs handled by the device
+        vcpu_count: u64,
+    }
+
+    #[derive(Serialize, Deserialize)]
+    pub struct Gicv3State {
+        dist: Vec<u32>,
+        rdist: Vec<u32>,
+        icc: Vec<u32>,
+        // special register that enables interrupts and affinity routing
+        gicd_ctlr: u32,
+    }
+
+    impl KvmGICv3 {
+        // Unfortunately bindgen omits defines that are based on other defines.
+        // See arch/arm64/include/uapi/asm/kvm.h file from the linux kernel.
+        pub const SZ_64K: u64 = 0x0001_0000;
+        const KVM_VGIC_V3_DIST_SIZE: u64 = KvmGICv3::SZ_64K;
+        const KVM_VGIC_V3_REDIST_SIZE: u64 = (2 * KvmGICv3::SZ_64K);
+
+        // Device trees specific constants
+        pub const ARCH_GIC_V3_MAINT_IRQ: u32 = 9;
+
+        /// Get the address of the GIC distributor.
+        pub fn get_dist_addr() -> u64 {
+            layout::MAPPED_IO_START - KvmGICv3::KVM_VGIC_V3_DIST_SIZE
+        }
+
+        /// Get the size of the GIC distributor.
+        pub fn get_dist_size() -> u64 {
+            KvmGICv3::KVM_VGIC_V3_DIST_SIZE
+        }
+
+        /// Get the address of the GIC redistributors.
+        pub fn get_redists_addr(vcpu_count: u64) -> u64 {
+            KvmGICv3::get_dist_addr() - KvmGICv3::get_redists_size(vcpu_count)
+        }
+
+        /// Get the size of the GIC redistributors.
+        pub fn get_redists_size(vcpu_count: u64) -> u64 {
+            vcpu_count * KvmGICv3::KVM_VGIC_V3_REDIST_SIZE
+        }
+
+        /// Save the state of GIC.
+        fn state(&self, gicr_typers: &[u64]) -> Result<Gicv3State> {
+            // Flush redistributors pending tables to guest RAM.
+            save_pending_tables(&self.device()).map_err(Error::SavePendingTables)?;
+
+            let gicd_ctlr =
+                read_ctlr(&self.device()).map_err(Error::SaveDistributorCtrlRegisters)?;
+
+            let dist_state =
+                get_dist_regs(&self.device()).map_err(Error::SaveDistributorRegisters)?;
+
+            let rdist_state = get_redist_regs(&self.device(), &gicr_typers)
+                .map_err(Error::SaveRedistributorRegisters)?;
+
+            let icc_state =
+                get_icc_regs(&self.device(), &gicr_typers).map_err(Error::SaveICCRegisters)?;
+
+            Ok(Gicv3State {
+                dist: dist_state,
+                rdist: rdist_state,
+                icc: icc_state,
+                gicd_ctlr,
+            })
+        }
+
+        /// Restore the state of GIC.
+        fn set_state(&mut self, gicr_typers: &[u64], state: &Gicv3State) -> Result<()> {
+            write_ctlr(&self.device(), state.gicd_ctlr)
+                .map_err(Error::RestoreDistributorCtrlRegisters)?;
+
+            set_dist_regs(&self.device(), &state.dist)
+                .map_err(Error::RestoreDistributorRegisters)?;
+
+            set_redist_regs(&self.device(), gicr_typers, &state.rdist)
+                .map_err(Error::RestoreRedistributorRegisters)?;
+
+            set_icc_regs(&self.device(), &gicr_typers, &state.icc)
+                .map_err(Error::RestoreICCRegisters)?;
+
+            Ok(())
+        }
+    }
+
+    impl GICDevice for KvmGICv3 {
+        fn device(&self) -> &Arc<dyn hypervisor::Device> {
+            &self.device
+        }
+
+        fn fdt_compatibility(&self) -> &str {
+            "arm,gic-v3"
+        }
+
+        fn fdt_maint_irq(&self) -> u32 {
+            KvmGICv3::ARCH_GIC_V3_MAINT_IRQ
+        }
+
+        fn device_properties(&self) -> &[u64] {
+            &self.properties
+        }
+
+        fn vcpu_count(&self) -> u64 {
+            self.vcpu_count
+        }
+
+        fn set_gicr_typers(&mut self, gicr_typers: Vec<u64>) {
+            self.gicr_typers = gicr_typers;
+        }
+
+        fn as_any_concrete_mut(&mut self) -> &mut dyn Any {
+            self
+        }
+    }
+
+    impl KvmGICDevice for KvmGICv3 {
+        fn version() -> u32 {
+            kvm_bindings::kvm_device_type_KVM_DEV_TYPE_ARM_VGIC_V3
+        }
+
+        fn create_device(
+            device: Arc<dyn hypervisor::Device>,
+            vcpu_count: u64,
+        ) -> Box<dyn GICDevice> {
+            Box::new(KvmGICv3 {
+                device,
+                gicr_typers: vec![0; vcpu_count.try_into().unwrap()],
+                properties: [
+                    KvmGICv3::get_dist_addr(),
+                    KvmGICv3::get_dist_size(),
+                    KvmGICv3::get_redists_addr(vcpu_count),
+                    KvmGICv3::get_redists_size(vcpu_count),
+                ],
+                vcpu_count,
+            })
+        }
+
+        fn init_device_attributes(
+            _vm: &Arc<dyn hypervisor::Vm>,
+            gic_device: &dyn GICDevice,
+        ) -> crate::aarch64::gic::Result<()> {
+            /* Setting up the distributor attribute.
+             We are placing the GIC below 1GB so we need to substract the size of the distributor.
+            */
+            Self::set_device_attribute(
+                gic_device.device(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ADDR,
+                u64::from(kvm_bindings::KVM_VGIC_V3_ADDR_TYPE_DIST),
+                &KvmGICv3::get_dist_addr() as *const u64 as u64,
+                0,
+            )?;
+
+            /* Setting up the redistributors' attribute.
+            We are calculating here the start of the redistributors address. We have one per CPU.
+            */
+            Self::set_device_attribute(
+                gic_device.device(),
+                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ADDR,
+                u64::from(kvm_bindings::KVM_VGIC_V3_ADDR_TYPE_REDIST),
+                &KvmGICv3::get_redists_addr(gic_device.vcpu_count()) as *const u64 as u64,
+                0,
+            )?;
+
+            Ok(())
+        }
+    }
+
+    pub const GIC_V3_SNAPSHOT_ID: &str = "gic-v3";
+    impl Snapshottable for KvmGICv3 {
+        fn id(&self) -> String {
+            GIC_V3_SNAPSHOT_ID.to_string()
+        }
+
+        fn snapshot(&mut self) -> std::result::Result<Snapshot, MigratableError> {
+            let gicr_typers = self.gicr_typers.clone();
+            let snapshot = serde_json::to_vec(&self.state(&gicr_typers).unwrap())
+                .map_err(|e| MigratableError::Snapshot(e.into()))?;
+
+            let mut gic_v3_snapshot = Snapshot::new(self.id().as_str());
+            gic_v3_snapshot.add_data_section(SnapshotDataSection {
+                id: format!("{}-section", self.id()),
+                snapshot,
+            });
+
+            Ok(gic_v3_snapshot)
+        }
+
+        fn restore(&mut self, snapshot: Snapshot) -> std::result::Result<(), MigratableError> {
+            if let Some(gic_v3_section) = snapshot
+                .snapshot_data
+                .get(&format!("{}-section", self.id()))
+            {
+                let gic_v3_state = match serde_json::from_slice(&gic_v3_section.snapshot) {
+                    Ok(state) => state,
+                    Err(error) => {
+                        return Err(MigratableError::Restore(anyhow!(
+                            "Could not deserialize GICv3 {}",
+                            error
+                        )))
+                    }
+                };
+
+                let gicr_typers = self.gicr_typers.clone();
+                return self.set_state(&gicr_typers, &gic_v3_state).map_err(|e| {
+                    MigratableError::Restore(anyhow!("Could not restore GICv3 state {:?}", e))
+                });
+            }
+
+            Err(MigratableError::Restore(anyhow!(
+                "Could not find GICv3 snapshot section"
+            )))
+        }
+    }
+
+    impl Pausable for KvmGICv3 {}
+    impl Transportable for KvmGICv3 {}
+    impl Migratable for KvmGICv3 {}
+}

arch/src/aarch64/gic/gicv3_its.rs

@@ -2,18 +2,23 @@
 // SPDX-License-Identifier: Apache-2.0
 
 pub mod kvm {
+    use std::any::Any;
+    use std::convert::TryInto;
     use std::sync::Arc;
     use std::{boxed::Box, result};
     type Result<T> = result::Result<T, Error>;
+    use crate::aarch64::gic::gicv3::kvm::KvmGICv3;
     use crate::aarch64::gic::kvm::KvmGICDevice;
     use crate::aarch64::gic::{Error, GICDevice};
-    use crate::aarch64::gicv3::kvm::KvmGICv3;
     use hypervisor::kvm::kvm_bindings;
 
     pub struct KvmGICv3ITS {
         /// The hypervisor agnostic device
         device: Arc<dyn hypervisor::Device>,
 
+        /// Vector holding values of GICR_TYPER for each vCPU
+        gicr_typers: Vec<u64>,
+
         /// GIC device properties, to be used for setting up the fdt entry
         gic_properties: [u64; 4],
 
@@ -49,7 +54,7 @@ pub mod kvm {
             true
         }
 
-        fn msi_compatiblility(&self) -> &str {
+        fn msi_compatibility(&self) -> &str {
             "arm,gic-v3-its"
         }
 
@@ -68,6 +73,14 @@ pub mod kvm {
         fn vcpu_count(&self) -> u64 {
             self.vcpu_count
         }
+
+        fn set_gicr_typers(&mut self, gicr_typers: Vec<u64>) {
+            self.gicr_typers = gicr_typers;
+        }
+
+        fn as_any_concrete_mut(&mut self) -> &mut dyn Any {
+            self
+        }
     }
 
     impl KvmGICDevice for KvmGICv3ITS {
@@ -80,7 +93,8 @@ pub mod kvm {
             vcpu_count: u64,
         ) -> Box<dyn GICDevice> {
             Box::new(KvmGICv3ITS {
-                device: device,
+                device,
+                gicr_typers: vec![0; vcpu_count.try_into().unwrap()],
                 gic_properties: [
                     KvmGICv3::get_dist_addr(),
                     KvmGICv3::get_dist_size(),
@@ -91,13 +105,13 @@ pub mod kvm {
                     KvmGICv3ITS::get_msi_addr(vcpu_count),
                     KvmGICv3ITS::get_msi_size(),
                 ],
-                vcpu_count: vcpu_count,
+                vcpu_count,
             })
         }
 
         fn init_device_attributes(
             vm: &Arc<dyn hypervisor::Vm>,
-            gic_device: &Box<dyn GICDevice>,
+            gic_device: &dyn GICDevice,
         ) -> Result<()> {
             KvmGICv3::init_device_attributes(vm, gic_device)?;
 
@@ -115,7 +129,7 @@ pub mod kvm {
                 &its_fd,
                 kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ADDR,
                 u64::from(kvm_bindings::KVM_VGIC_ITS_ADDR_TYPE),
-                &KvmGICv3ITS::get_msi_addr(u64::from(gic_device.vcpu_count())) as *const u64 as u64,
+                &KvmGICv3ITS::get_msi_addr(gic_device.vcpu_count()) as *const u64 as u64,
                 0,
             )?;
 

arch/src/aarch64/gic/icc_regs.rs

@@ -0,0 +1,196 @@
+// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+// SPDX-License-Identifier: Apache-2.0
+
+use super::{Error, Result};
+use hypervisor::kvm::kvm_bindings::{
+    kvm_device_attr, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, KVM_REG_ARM64_SYSREG_CRM_MASK,
+    KVM_REG_ARM64_SYSREG_CRM_SHIFT, KVM_REG_ARM64_SYSREG_CRN_MASK, KVM_REG_ARM64_SYSREG_CRN_SHIFT,
+    KVM_REG_ARM64_SYSREG_OP0_MASK, KVM_REG_ARM64_SYSREG_OP0_SHIFT, KVM_REG_ARM64_SYSREG_OP1_MASK,
+    KVM_REG_ARM64_SYSREG_OP1_SHIFT, KVM_REG_ARM64_SYSREG_OP2_MASK, KVM_REG_ARM64_SYSREG_OP2_SHIFT,
+};
+use std::sync::Arc;
+
+const KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT: u32 = 32;
+const KVM_DEV_ARM_VGIC_V3_MPIDR_MASK: u64 = 0xffffffff << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT as u64;
+
+const ICC_CTLR_EL1_PRIBITS_SHIFT: u32 = 8;
+const ICC_CTLR_EL1_PRIBITS_MASK: u32 = 7 << ICC_CTLR_EL1_PRIBITS_SHIFT;
+
+macro_rules! arm64_vgic_sys_reg {
+    ($name: tt, $op0: tt, $op1: tt, $crn: tt, $crm: tt, $op2: expr) => {
+        const $name: u64 = ((($op0 as u64) << KVM_REG_ARM64_SYSREG_OP0_SHIFT)
+            & KVM_REG_ARM64_SYSREG_OP0_MASK as u64)
+            | ((($op1 as u64) << KVM_REG_ARM64_SYSREG_OP1_SHIFT)
+                & KVM_REG_ARM64_SYSREG_OP1_MASK as u64)
+            | ((($crn as u64) << KVM_REG_ARM64_SYSREG_CRN_SHIFT)
+                & KVM_REG_ARM64_SYSREG_CRN_MASK as u64)
+            | ((($crm as u64) << KVM_REG_ARM64_SYSREG_CRM_SHIFT)
+                & KVM_REG_ARM64_SYSREG_CRM_MASK as u64)
+            | ((($op2 as u64) << KVM_REG_ARM64_SYSREG_OP2_SHIFT)
+                & KVM_REG_ARM64_SYSREG_OP2_MASK as u64);
+    };
+}
+
+macro_rules! SYS_ICC_AP0Rn_EL1 {
+    ($name: tt, $n: tt) => {
+        arm64_vgic_sys_reg!($name, 3, 0, 12, 8, (4 | $n));
+    };
+}
+
+macro_rules! SYS_ICC_AP1Rn_EL1 {
+    ($name: tt, $n: tt) => {
+        arm64_vgic_sys_reg!($name, 3, 0, 12, 9, $n);
+    };
+}
+
+arm64_vgic_sys_reg!(SYS_ICC_SRE_EL1, 3, 0, 12, 12, 5);
+arm64_vgic_sys_reg!(SYS_ICC_CTLR_EL1, 3, 0, 12, 12, 4);
+arm64_vgic_sys_reg!(SYS_ICC_IGRPEN0_EL1, 3, 0, 12, 12, 6);
+arm64_vgic_sys_reg!(SYS_ICC_IGRPEN1_EL1, 3, 0, 12, 12, 7);
+arm64_vgic_sys_reg!(SYS_ICC_PMR_EL1, 3, 0, 4, 6, 0);
+arm64_vgic_sys_reg!(SYS_ICC_BPR0_EL1, 3, 0, 12, 8, 3);
+arm64_vgic_sys_reg!(SYS_ICC_BPR1_EL1, 3, 0, 12, 12, 3);
+SYS_ICC_AP0Rn_EL1!(SYS_ICC_AP0R0_EL1, 0);
+SYS_ICC_AP0Rn_EL1!(SYS_ICC_AP0R1_EL1, 1);
+SYS_ICC_AP0Rn_EL1!(SYS_ICC_AP0R2_EL1, 2);
+SYS_ICC_AP0Rn_EL1!(SYS_ICC_AP0R3_EL1, 3);
+SYS_ICC_AP1Rn_EL1!(SYS_ICC_AP1R0_EL1, 0);
+SYS_ICC_AP1Rn_EL1!(SYS_ICC_AP1R1_EL1, 1);
+SYS_ICC_AP1Rn_EL1!(SYS_ICC_AP1R2_EL1, 2);
+SYS_ICC_AP1Rn_EL1!(SYS_ICC_AP1R3_EL1, 3);
+
+static VGIC_ICC_REGS: &'static [u64] = &[
+    SYS_ICC_SRE_EL1,
+    SYS_ICC_CTLR_EL1,
+    SYS_ICC_IGRPEN0_EL1,
+    SYS_ICC_IGRPEN1_EL1,
+    SYS_ICC_PMR_EL1,
+    SYS_ICC_BPR0_EL1,
+    SYS_ICC_BPR1_EL1,
+    SYS_ICC_AP0R0_EL1,
+    SYS_ICC_AP0R1_EL1,
+    SYS_ICC_AP0R2_EL1,
+    SYS_ICC_AP0R3_EL1,
+    SYS_ICC_AP1R0_EL1,
+    SYS_ICC_AP1R1_EL1,
+    SYS_ICC_AP1R2_EL1,
+    SYS_ICC_AP1R3_EL1,
+];
+
+fn icc_attr_access(
+    gic: &Arc<dyn hypervisor::Device>,
+    offset: u64,
+    typer: u64,
+    val: &u32,
+    set: bool,
+) -> Result<()> {
+    let mut gic_icc_attr = kvm_device_attr {
+        group: KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
+        attr: ((typer & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) | offset), // this needs the mpidr
+        addr: val as *const u32 as u64,
+        flags: 0,
+    };
+    if set {
+        #[allow(clippy::unnecessary_mut_passed)]
+        gic.set_device_attr(&mut gic_icc_attr)
+            .map_err(Error::SetDeviceAttribute)?;
+    } else {
+        gic.get_device_attr(&mut gic_icc_attr)
+            .map_err(Error::GetDeviceAttribute)?;
+    }
+    Ok(())
+}
+
+/// Get ICC registers.
+pub fn get_icc_regs(gic: &Arc<dyn hypervisor::Device>, gicr_typer: &[u64]) -> Result<Vec<u32>> {
+    let mut state: Vec<u32> = Vec::new();
+    // We need this for the ICC_AP<m>R<n>_EL1 registers.
+    let mut num_priority_bits = 0;
+
+    for ix in gicr_typer {
+        let i = *ix;
+        for icc_offset in VGIC_ICC_REGS {
+            let val = 0;
+            if *icc_offset == SYS_ICC_CTLR_EL1 {
+                // calculate priority bits by reading the ctrl_el1 register.
+                icc_attr_access(gic, *icc_offset, i, &val, false)?;
+                // The priority bits are found in the ICC_CTLR_EL1 register (bits from  10:8).
+                // See page 194 from https://static.docs.arm.com/ihi0069/c/IHI0069C_gic_
+                // architecture_specification.pdf.
+                // Citation:
+                // "Priority bits. Read-only and writes are ignored. The number of priority bits
+                // implemented, minus one."
+                num_priority_bits =
+                    ((val & ICC_CTLR_EL1_PRIBITS_MASK) >> ICC_CTLR_EL1_PRIBITS_SHIFT) + 1;
+                state.push(val);
+            }
+            // As per ARMv8 documentation: https://static.docs.arm.com/ihi0069/c/IHI0069C_
+            // gic_architecture_specification.pdf
+            // page 178,
+            // ICC_AP0R1_EL1 is only implemented in implementations that support 6 or more bits of
+            // priority.
+            // ICC_AP0R2_EL1 and ICC_AP0R3_EL1 are only implemented in implementations that support
+            // 7 bits of priority.
+            else if *icc_offset == SYS_ICC_AP0R1_EL1 || *icc_offset == SYS_ICC_AP1R1_EL1 {
+                if num_priority_bits >= 6 {
+                    icc_attr_access(gic, *icc_offset, i, &val, false)?;
+                    state.push(val);
+                }
+            } else if *icc_offset == SYS_ICC_AP0R2_EL1
+                || *icc_offset == SYS_ICC_AP0R3_EL1
+                || *icc_offset == SYS_ICC_AP1R2_EL1
+                || *icc_offset == SYS_ICC_AP1R3_EL1
+            {
+                if num_priority_bits == 7 {
+                    icc_attr_access(gic, *icc_offset, i, &val, false)?;
+                    state.push(val);
+                }
+            } else {
+                icc_attr_access(gic, *icc_offset, i, &val, false)?;
+                state.push(val);
+            }
+        }
+    }
+    Ok(state)
+}
+
+/// Set ICC registers.
+pub fn set_icc_regs(
+    gic: &Arc<dyn hypervisor::Device>,
+    gicr_typer: &[u64],
+    state: &[u32],
+) -> Result<()> {
+    let mut num_priority_bits = 0;
+    let mut idx = 0;
+    for ix in gicr_typer {
+        let i = *ix;
+        for icc_offset in VGIC_ICC_REGS {
+            if *icc_offset == SYS_ICC_CTLR_EL1 {
+                let ctrl_el1 = state[idx];
+                num_priority_bits =
+                    ((ctrl_el1 & ICC_CTLR_EL1_PRIBITS_MASK) >> ICC_CTLR_EL1_PRIBITS_SHIFT) + 1;
+            }
+            if *icc_offset == SYS_ICC_AP0R1_EL1 || *icc_offset == SYS_ICC_AP1R1_EL1 {
+                if num_priority_bits >= 6 {
+                    icc_attr_access(gic, *icc_offset, i, &state[idx], true)?;
+                    idx += 1;
+                }
+                continue;
+            }
+            if *icc_offset == SYS_ICC_AP0R2_EL1
+                || *icc_offset == SYS_ICC_AP0R3_EL1
+                || *icc_offset == SYS_ICC_AP1R2_EL1
+                || *icc_offset == SYS_ICC_AP1R3_EL1
+            {
+                if num_priority_bits == 7 {
+                    icc_attr_access(gic, *icc_offset, i, &state[idx], true)?;
+                    idx += 1;
+                }
+                continue;
+            }
+            icc_attr_access(gic, *icc_offset, i, &state[idx], true)?;
+            idx += 1;
+        }
+    }
+    Ok(())
+}

arch/src/aarch64/gic/mod.rs

@@ -1,6 +1,16 @@
 // Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 // SPDX-License-Identifier: Apache-2.0
 
+pub mod dist_regs;
+pub mod gicv3;
+pub mod gicv3_its;
+pub mod icc_regs;
+pub mod redist_regs;
+
+pub use self::dist_regs::{get_dist_regs, read_ctlr, set_dist_regs, write_ctlr};
+pub use self::icc_regs::{get_icc_regs, set_icc_regs};
+pub use self::redist_regs::{get_redist_regs, set_redist_regs};
+use std::any::Any;
 use std::result;
 use std::sync::Arc;
 
@@ -11,10 +21,12 @@ pub enum Error {
     CreateGIC(hypervisor::HypervisorVmError),
     /// Error while setting device attributes for the GIC.
     SetDeviceAttribute(hypervisor::HypervisorDeviceError),
+    /// Error while getting device attributes for the GIC.
+    GetDeviceAttribute(hypervisor::HypervisorDeviceError),
 }
 type Result<T> = result::Result<T, Error>;
 
-pub trait GICDevice {
+pub trait GICDevice: Send {
     /// Returns the hypervisor agnostic Device of the GIC device
     fn device(&self) -> &Arc<dyn hypervisor::Device>;
 
@@ -36,7 +48,7 @@ pub trait GICDevice {
     }
 
     /// Returns the MSI compatibility property of the device
-    fn msi_compatiblility(&self) -> &str {
+    fn msi_compatibility(&self) -> &str {
         ""
     }
 
@@ -44,14 +56,18 @@ pub trait GICDevice {
     fn msi_properties(&self) -> &[u64] {
         &[]
     }
+
+    /// Get the values of GICR_TYPER for each vCPU.
+    fn set_gicr_typers(&mut self, gicr_typers: Vec<u64>);
+
+    /// Downcast the trait object to its concrete type.
+    fn as_any_concrete_mut(&mut self) -> &mut dyn Any;
 }
 
 pub mod kvm {
     use super::GICDevice;
     use super::Result;
-    use crate::aarch64::gicv2::kvm::KvmGICv2;
-    use crate::aarch64::gicv3::kvm::KvmGICv3;
-    use crate::aarch64::gicv3_its::kvm::KvmGICv3ITS;
+    use crate::aarch64::gic::gicv3_its::kvm::KvmGICv3ITS;
     use crate::layout;
     use hypervisor::kvm::kvm_bindings;
     use std::boxed::Box;
@@ -71,7 +87,7 @@ pub mod kvm {
         /// Setup the device-specific attributes
         fn init_device_attributes(
             vm: &Arc<dyn hypervisor::Vm>,
-            gic_device: &Box<dyn GICDevice>,
+            gic_device: &dyn GICDevice,
         ) -> Result<()>;
 
         /// Initialize a GIC device
@@ -95,10 +111,10 @@ pub mod kvm {
             flags: u32,
         ) -> Result<()> {
             let attr = kvm_bindings::kvm_device_attr {
-                group: group,
-                attr: attr,
-                addr: addr,
-                flags: flags,
+                group,
+                attr,
+                addr,
+                flags,
             };
             device
                 .set_device_attr(&attr)
@@ -107,8 +123,29 @@ pub mod kvm {
             Ok(())
         }
 
+        /// Get a GIC device attribute
+        fn get_device_attribute(
+            device: &Arc<dyn hypervisor::Device>,
+            group: u32,
+            attr: u64,
+            addr: u64,
+            flags: u32,
+        ) -> Result<()> {
+            let mut attr = kvm_bindings::kvm_device_attr {
+                group,
+                attr,
+                addr,
+                flags,
+            };
+            device
+                .get_device_attr(&mut attr)
+                .map_err(super::Error::GetDeviceAttribute)?;
+
+            Ok(())
+        }
+
         /// Finalize the setup of a GIC device
-        fn finalize_device(gic_device: &Box<dyn GICDevice>) -> Result<()> {
+        fn finalize_device(gic_device: &dyn GICDevice) -> Result<()> {
             /* We need to tell the kernel how many irqs to support with this vgic.
              * See the `layout` module for details.
              */
@@ -137,38 +174,38 @@ pub mod kvm {
         }
 
         /// Method to initialize the GIC device
+        #[allow(clippy::new_ret_no_self)]
         fn new(vm: &Arc<dyn hypervisor::Vm>, vcpu_count: u64) -> Result<Box<dyn GICDevice>> {
             let vgic_fd = Self::init_device(vm)?;
 
             let device = Self::create_device(vgic_fd, vcpu_count);
 
-            Self::init_device_attributes(vm, &device)?;
+            Self::init_device_attributes(vm, &*device)?;
 
-            Self::finalize_device(&device)?;
+            Self::finalize_device(&*device)?;
 
             Ok(device)
         }
     }
 
-    /// Create a GIC device.
+    /// Create a GICv3-ITS device.
     ///
-    /// It will try to create by default a GICv3 device. If that fails it will try
-    /// to fall-back to a GICv2 device.
-    pub fn create_gic(
-        vm: &Arc<dyn hypervisor::Vm>,
-        vcpu_count: u64,
-        its_required: bool,
-    ) -> Result<Box<dyn GICDevice>> {
-        if its_required {
-            KvmGICv3ITS::new(vm, vcpu_count)
-        } else {
-            KvmGICv3ITS::new(vm, vcpu_count).or_else(|_| {
-                debug!("Failed to create GICv3-ITS, will try GICv3 instead.");
-                KvmGICv3::new(vm, vcpu_count).or_else(|_| {
-                    debug!("Failed to create GICv3, will try GICv2 instead.");
-                    KvmGICv2::new(vm, vcpu_count)
-                })
-            })
-        }
+    pub fn create_gic(vm: &Arc<dyn hypervisor::Vm>, vcpu_count: u64) -> Result<Box<dyn GICDevice>> {
+        debug!("creating a GICv3-ITS");
+        KvmGICv3ITS::new(vm, vcpu_count)
+    }
+
+    /// Function that saves RDIST pending tables into guest RAM.
+    ///
+    /// The tables get flushed to guest RAM whenever the VM gets stopped.
+    pub fn save_pending_tables(gic: &Arc<dyn hypervisor::Device>) -> Result<()> {
+        let init_gic_attr = kvm_bindings::kvm_device_attr {
+            group: kvm_bindings::KVM_DEV_ARM_VGIC_GRP_CTRL,
+            attr: u64::from(kvm_bindings::KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES),
+            addr: 0,
+            flags: 0,
+        };
+        gic.set_device_attr(&init_gic_attr)
+            .map_err(super::Error::SetDeviceAttribute)
     }
 }

arch/src/aarch64/gic/redist_regs.rs

@@ -0,0 +1,179 @@
+// Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+// SPDX-License-Identifier: Apache-2.0
+
+use super::{Error, Result};
+use hypervisor::kvm::kvm_bindings::{kvm_device_attr, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS};
+use std::sync::Arc;
+
+// Relevant redistributor registers that we want to save/restore.
+const GICR_CTLR: u32 = 0x0000;
+const GICR_STATUSR: u32 = 0x0010;
+const GICR_WAKER: u32 = 0x0014;
+const GICR_PROPBASER: u32 = 0x0070;
+const GICR_PENDBASER: u32 = 0x0078;
+
+/* SGI and PPI Redistributor registers, offsets from RD_base */
+/*
+ * Redistributor frame offsets from RD_base which is actually SZ_
+ */
+const GICR_SGI_OFFSET: u32 = 0x0001_0000;
+const GICR_IGROUPR0: u32 = GICR_SGI_OFFSET + 0x0080;
+const GICR_ICENABLER0: u32 = GICR_SGI_OFFSET + 0x0180;
+const GICR_ISENABLER0: u32 = GICR_SGI_OFFSET + 0x0100;
+const GICR_ISPENDR0: u32 = GICR_SGI_OFFSET + 0x0200;
+const GICR_ICPENDR0: u32 = GICR_SGI_OFFSET + 0x0280;
+const GICR_ISACTIVER0: u32 = GICR_SGI_OFFSET + 0x0300;
+const GICR_ICACTIVER0: u32 = GICR_SGI_OFFSET + 0x0380;
+const GICR_IPRIORITYR0: u32 = GICR_SGI_OFFSET + 0x0400;
+const GICR_ICFGR0: u32 = GICR_SGI_OFFSET + 0x0C00;
+
+const KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT: u32 = 32;
+const KVM_DEV_ARM_VGIC_V3_MPIDR_MASK: u64 = 0xffffffff << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT as u64;
+
+/// This is how we represent the registers of a distributor.
+/// It is relrvant their offset from the base address of the
+/// distributor.
+/// Each register has a different number
+/// of bits_per_irq and is therefore variable length.
+/// First 32 interrupts (0-32) are private to each CPU (SGIs and PPIs).
+/// and so we save the first irq to identify between the type of the interrupt
+/// that the respective register deals with.
+struct RdistReg {
+    /// Offset from distributor address.
+    base: u32,
+    /// Length of the register.
+    length: u8,
+}
+
+// All or at least the registers we are interested in are 32 bit, so
+// we use a constant for size(u32).
+const REG_SIZE: u8 = 4;
+
+// Creates a vgic redistributor register.
+macro_rules! VGIC_RDIST_REG {
+    ($base:expr, $len:expr) => {
+        RdistReg {
+            base: $base,
+            length: $len,
+        }
+    };
+}
+
+// List with relevant distributor registers that we will be restoring.
+static VGIC_RDIST_REGS: &'static [RdistReg] = &[
+    VGIC_RDIST_REG!(GICR_CTLR, 4),
+    VGIC_RDIST_REG!(GICR_STATUSR, 4),
+    VGIC_RDIST_REG!(GICR_WAKER, 4),
+    VGIC_RDIST_REG!(GICR_PROPBASER, 8),
+    VGIC_RDIST_REG!(GICR_PENDBASER, 8),
+];
+
+// List with relevant distributor registers that we will be restoring.
+static VGIC_SGI_REGS: &'static [RdistReg] = &[
+    VGIC_RDIST_REG!(GICR_IGROUPR0, 4),
+    VGIC_RDIST_REG!(GICR_ICENABLER0, 4),
+    VGIC_RDIST_REG!(GICR_ISENABLER0, 4),
+    VGIC_RDIST_REG!(GICR_ICFGR0, 8),
+    VGIC_RDIST_REG!(GICR_ICPENDR0, 4),
+    VGIC_RDIST_REG!(GICR_ISPENDR0, 4),
+    VGIC_RDIST_REG!(GICR_ICACTIVER0, 4),
+    VGIC_RDIST_REG!(GICR_ISACTIVER0, 4),
+    VGIC_RDIST_REG!(GICR_IPRIORITYR0, 32),
+];
+
+fn redist_attr_access(
+    gic: &Arc<dyn hypervisor::Device>,
+    offset: u32,
+    typer: u64,
+    val: &u32,
+    set: bool,
+) -> Result<()> {
+    let mut gic_dist_attr = kvm_device_attr {
+        group: KVM_DEV_ARM_VGIC_GRP_REDIST_REGS,
+        attr: (typer & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) | (offset as u64), // this needs the mpidr
+        addr: val as *const u32 as u64,
+        flags: 0,
+    };
+    if set {
+        #[allow(clippy::unnecessary_mut_passed)]
+        gic.set_device_attr(&mut gic_dist_attr)
+            .map_err(Error::SetDeviceAttribute)?;
+    } else {
+        gic.get_device_attr(&mut gic_dist_attr)
+            .map_err(Error::GetDeviceAttribute)?;
+    }
+    Ok(())
+}
+
+fn access_redists_aux(
+    gic: &Arc<dyn hypervisor::Device>,
+    gicr_typer: &[u64],
+    state: &mut Vec<u32>,
+    reg_list: &'static [RdistReg],
+    idx: &mut usize,
+    set: bool,
+) -> Result<()> {
+    for i in gicr_typer {
+        for rdreg in reg_list {
+            let mut base = rdreg.base;
+            let end = base + rdreg.length as u32;
+
+            while base < end {
+                let mut val = 0;
+                if set {
+                    val = state[*idx];
+                    redist_attr_access(gic, base, *i, &val, true)?;
+                    *idx += 1;
+                } else {
+                    redist_attr_access(gic, base, *i, &val, false)?;
+                    state.push(val);
+                }
+                base += REG_SIZE as u32;
+            }
+        }
+    }
+    Ok(())
+}
+
+/// Get redistributor registers.
+pub fn get_redist_regs(gic: &Arc<dyn hypervisor::Device>, gicr_typer: &[u64]) -> Result<Vec<u32>> {
+    let mut state = Vec::new();
+    let mut idx: usize = 0;
+    access_redists_aux(
+        gic,
+        &gicr_typer,
+        &mut state,
+        VGIC_RDIST_REGS,
+        &mut idx,
+        false,
+    )?;
+
+    access_redists_aux(gic, &gicr_typer, &mut state, VGIC_SGI_REGS, &mut idx, false)?;
+    Ok(state)
+}
+
+/// Set redistributor registers.
+pub fn set_redist_regs(
+    gic: &Arc<dyn hypervisor::Device>,
+    gicr_typer: &[u64],
+    state: &[u32],
+) -> Result<()> {
+    let mut idx: usize = 0;
+    let mut mut_state = state.to_owned();
+    access_redists_aux(
+        gic,
+        gicr_typer,
+        &mut mut_state,
+        VGIC_RDIST_REGS,
+        &mut idx,
+        true,
+    )?;
+    access_redists_aux(
+        gic,
+        gicr_typer,
+        &mut mut_state,
+        VGIC_SGI_REGS,
+        &mut idx,
+        true,
+    )
+}

arch/src/aarch64/gicv2.rs

@@ -1,124 +0,0 @@
-// Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
-// SPDX-License-Identifier: Apache-2.0
-
-pub mod kvm {
-    use crate::aarch64::gic::kvm::KvmGICDevice;
-    use crate::aarch64::gic::{Error, GICDevice};
-    use std::{boxed::Box, result};
-    type Result<T> = result::Result<T, Error>;
-    use crate::layout;
-    use hypervisor::kvm::kvm_bindings;
-    use std::sync::Arc;
-
-    /// Represent a GIC v2 device
-    pub struct KvmGICv2 {
-        /// The hypervisor agnostic device
-        device: Arc<dyn hypervisor::Device>,
-
-        /// GIC device properties, to be used for setting up the fdt entry
-        properties: [u64; 4],
-
-        /// Number of CPUs handled by the device
-        vcpu_count: u64,
-    }
-
-    impl KvmGICv2 {
-        // Unfortunately bindgen omits defines that are based on other defines.
-        // See arch/arm64/include/uapi/asm/kvm.h file from the linux kernel.
-        const KVM_VGIC_V2_DIST_SIZE: u64 = 0x1000;
-        const KVM_VGIC_V2_CPU_SIZE: u64 = 0x2000;
-
-        // Device trees specific constants
-        const ARCH_GIC_V2_MAINT_IRQ: u32 = 8;
-
-        /// Get the address of the GICv2 distributor.
-        const fn get_dist_addr() -> u64 {
-            layout::MAPPED_IO_START - KvmGICv2::KVM_VGIC_V2_DIST_SIZE
-        }
-
-        /// Get the size of the GIC_v2 distributor.
-        const fn get_dist_size() -> u64 {
-            KvmGICv2::KVM_VGIC_V2_DIST_SIZE
-        }
-
-        /// Get the address of the GIC_v2 CPU.
-        const fn get_cpu_addr() -> u64 {
-            KvmGICv2::get_dist_addr() - KvmGICv2::KVM_VGIC_V2_CPU_SIZE
-        }
-
-        /// Get the size of the GIC_v2 CPU.
-        const fn get_cpu_size() -> u64 {
-            KvmGICv2::KVM_VGIC_V2_CPU_SIZE
-        }
-    }
-
-    impl GICDevice for KvmGICv2 {
-        fn device(&self) -> &Arc<dyn hypervisor::Device> {
-            &self.device
-        }
-
-        fn device_properties(&self) -> &[u64] {
-            &self.properties
-        }
-
-        fn fdt_compatibility(&self) -> &str {
-            "arm,gic-400"
-        }
-
-        fn fdt_maint_irq(&self) -> u32 {
-            KvmGICv2::ARCH_GIC_V2_MAINT_IRQ
-        }
-
-        fn vcpu_count(&self) -> u64 {
-            self.vcpu_count
-        }
-    }
-
-    impl KvmGICDevice for KvmGICv2 {
-        fn version() -> u32 {
-            kvm_bindings::kvm_device_type_KVM_DEV_TYPE_ARM_VGIC_V2
-        }
-
-        fn create_device(
-            device: Arc<dyn hypervisor::Device>,
-            vcpu_count: u64,
-        ) -> Box<dyn GICDevice> {
-            Box::new(KvmGICv2 {
-                device: device,
-                properties: [
-                    KvmGICv2::get_dist_addr(),
-                    KvmGICv2::get_dist_size(),
-                    KvmGICv2::get_cpu_addr(),
-                    KvmGICv2::get_cpu_size(),
-                ],
-                vcpu_count: vcpu_count,
-            })
-        }
-
-        fn init_device_attributes(
-            _vm: &Arc<dyn hypervisor::Vm>,
-            gic_device: &Box<dyn GICDevice>,
-        ) -> Result<()> {
-            /* Setting up the distributor attribute.
-            We are placing the GIC below 1GB so we need to substract the size of the distributor. */
-            Self::set_device_attribute(
-                gic_device.device(),
-                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ADDR,
-                u64::from(kvm_bindings::KVM_VGIC_V2_ADDR_TYPE_DIST),
-                &KvmGICv2::get_dist_addr() as *const u64 as u64,
-                0,
-            )?;
-
-            /* Setting up the CPU attribute. */
-            Self::set_device_attribute(
-                gic_device.device(),
-                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ADDR,
-                u64::from(kvm_bindings::KVM_VGIC_V2_ADDR_TYPE_CPU),
-                &KvmGICv2::get_cpu_addr() as *const u64 as u64,
-                0,
-            )?;
-
-            Ok(())
-        }
-    }
-}

arch/src/aarch64/gicv3.rs

@@ -1,128 +0,0 @@
-// Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
-// SPDX-License-Identifier: Apache-2.0
-
-pub mod kvm {
-    use crate::aarch64::gic::kvm::KvmGICDevice;
-    use crate::aarch64::gic::{Error, GICDevice};
-    use crate::layout;
-    use hypervisor::kvm::kvm_bindings;
-    use std::sync::Arc;
-    use std::{boxed::Box, result};
-    type Result<T> = result::Result<T, Error>;
-
-    pub struct KvmGICv3 {
-        /// The hypervisor agnostic device
-        device: Arc<dyn hypervisor::Device>,
-
-        /// GIC device properties, to be used for setting up the fdt entry
-        properties: [u64; 4],
-
-        /// Number of CPUs handled by the device
-        vcpu_count: u64,
-    }
-
-    impl KvmGICv3 {
-        // Unfortunately bindgen omits defines that are based on other defines.
-        // See arch/arm64/include/uapi/asm/kvm.h file from the linux kernel.
-        pub const SZ_64K: u64 = 0x0001_0000;
-        const KVM_VGIC_V3_DIST_SIZE: u64 = KvmGICv3::SZ_64K;
-        const KVM_VGIC_V3_REDIST_SIZE: u64 = (2 * KvmGICv3::SZ_64K);
-
-        // Device trees specific constants
-        pub const ARCH_GIC_V3_MAINT_IRQ: u32 = 9;
-
-        /// Get the address of the GIC distributor.
-        pub fn get_dist_addr() -> u64 {
-            layout::MAPPED_IO_START - KvmGICv3::KVM_VGIC_V3_DIST_SIZE
-        }
-
-        /// Get the size of the GIC distributor.
-        pub fn get_dist_size() -> u64 {
-            KvmGICv3::KVM_VGIC_V3_DIST_SIZE
-        }
-
-        /// Get the address of the GIC redistributors.
-        pub fn get_redists_addr(vcpu_count: u64) -> u64 {
-            KvmGICv3::get_dist_addr() - KvmGICv3::get_redists_size(vcpu_count)
-        }
-
-        /// Get the size of the GIC redistributors.
-        pub fn get_redists_size(vcpu_count: u64) -> u64 {
-            vcpu_count * KvmGICv3::KVM_VGIC_V3_REDIST_SIZE
-        }
-    }
-
-    impl GICDevice for KvmGICv3 {
-        fn device(&self) -> &Arc<dyn hypervisor::Device> {
-            &self.device
-        }
-
-        fn fdt_compatibility(&self) -> &str {
-            "arm,gic-v3"
-        }
-
-        fn fdt_maint_irq(&self) -> u32 {
-            KvmGICv3::ARCH_GIC_V3_MAINT_IRQ
-        }
-
-        fn device_properties(&self) -> &[u64] {
-            &self.properties
-        }
-
-        fn vcpu_count(&self) -> u64 {
-            self.vcpu_count
-        }
-    }
-
-    impl KvmGICDevice for KvmGICv3 {
-        fn version() -> u32 {
-            kvm_bindings::kvm_device_type_KVM_DEV_TYPE_ARM_VGIC_V3
-        }
-
-        fn create_device(
-            device: Arc<dyn hypervisor::Device>,
-            vcpu_count: u64,
-        ) -> Box<dyn GICDevice> {
-            Box::new(KvmGICv3 {
-                device: device,
-                properties: [
-                    KvmGICv3::get_dist_addr(),
-                    KvmGICv3::get_dist_size(),
-                    KvmGICv3::get_redists_addr(vcpu_count),
-                    KvmGICv3::get_redists_size(vcpu_count),
-                ],
-                vcpu_count: vcpu_count,
-            })
-        }
-
-        fn init_device_attributes(
-            _vm: &Arc<dyn hypervisor::Vm>,
-            gic_device: &Box<dyn GICDevice>,
-        ) -> Result<()> {
-            /* Setting up the distributor attribute.
-             We are placing the GIC below 1GB so we need to substract the size of the distributor.
-            */
-            Self::set_device_attribute(
-                gic_device.device(),
-                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ADDR,
-                u64::from(kvm_bindings::KVM_VGIC_V3_ADDR_TYPE_DIST),
-                &KvmGICv3::get_dist_addr() as *const u64 as u64,
-                0,
-            )?;
-
-            /* Setting up the redistributors' attribute.
-            We are calculating here the start of the redistributors address. We have one per CPU.
-            */
-            Self::set_device_attribute(
-                gic_device.device(),
-                kvm_bindings::KVM_DEV_ARM_VGIC_GRP_ADDR,
-                u64::from(kvm_bindings::KVM_VGIC_V3_ADDR_TYPE_REDIST),
-                &KvmGICv3::get_redists_addr(u64::from(gic_device.vcpu_count())) as *const u64
-                    as u64,
-                0,
-            )?;
-
-            Ok(())
-        }
-    }
-}

arch/src/aarch64/layout.rs

@@ -37,13 +37,13 @@
 //           |                                                               |
 // 144 M     +---------------------------------------------------------------|
 //           |                                                               |
-//           |                    Reserverd (now GIC is here)                |
+//           |                    Reserved (now GIC is here)                 |
 //           |                                                               |
 // 0GB       +---------------------------------------------------------------+
 //
 //
 
-use vm_memory::{GuestAddress, GuestUsize};
+use vm_memory::GuestAddress;
 
 /// Below this address will reside the GIC, above this address will reside the MMIO devices.
 pub const MAPPED_IO_START: u64 = 0x0900_0000;
@@ -61,7 +61,7 @@ pub const MEM_32BIT_DEVICES_SIZE: u64 = 0x3000_0000;
 
 /// PCI MMCONFIG space (start: after the device space at 1 GiB, length: 256MiB)
 pub const PCI_MMCONFIG_START: GuestAddress = GuestAddress(0x4000_0000);
-pub const PCI_MMCONFIG_SIZE: GuestUsize = 256 << 20;
+pub const PCI_MMCONFIG_SIZE: u64 = 256 << 20;
 
 /// Start of RAM on 64 bit ARM.
 pub const RAM_64BIT_START: u64 = 0x8000_0000;

arch/src/aarch64/mod.rs

@@ -6,9 +6,6 @@
 pub mod fdt;
 /// Module for the global interrupt controller configuration.
 pub mod gic;
-mod gicv2;
-mod gicv3;
-mod gicv3_its;
 /// Layout for this aarch64 system.
 pub mod layout;
 /// Logic for configuring aarch64 registers.
@@ -17,7 +14,7 @@ pub mod regs;
 pub use self::fdt::DeviceInfoForFDT;
 use crate::DeviceType;
 use crate::RegionType;
-use hypervisor::kvm::kvm_bindings;
+use aarch64::gic::GICDevice;
 use std::collections::HashMap;
 use std::ffi::CStr;
 use std::fmt::Debug;
@@ -42,11 +39,8 @@ pub enum Error {
     /// Error configuring the general purpose registers
     REGSConfiguration(regs::Error),
 
-    /// Error fetching prefered target
-    VcpuArmPreferredTarget(hypervisor::HypervisorVmError),
-
-    /// Error doing Vcpu Init on Arm.
-    VcpuArmInit(hypervisor::HypervisorCpuError),
+    /// Error configuring the MPIDR register
+    VcpuRegMPIDR(hypervisor::HypervisorCpuError),
 }
 
 impl From<Error> for super::Error {
@@ -67,23 +61,10 @@ pub struct EntryPoint {
 pub fn configure_vcpu(
     fd: &Arc<dyn hypervisor::Vcpu>,
     id: u8,
-    vm: &Arc<dyn hypervisor::Vm>,
     kernel_entry_point: Option<EntryPoint>,
     vm_memory: &GuestMemoryAtomic<GuestMemoryMmap>,
+    _phys_bits: u8,
 ) -> super::Result<u64> {
-    let mut kvi: kvm_bindings::kvm_vcpu_init = kvm_bindings::kvm_vcpu_init::default();
-
-    // This reads back the kernel's preferred target type.
-    vm.get_preferred_target(&mut kvi)
-        .map_err(Error::VcpuArmPreferredTarget)?;
-    // We already checked that the capability is supported.
-    kvi.features[0] |= 1 << kvm_bindings::KVM_ARM_VCPU_PSCI_0_2;
-    // Non-boot cpus are powered off initially.
-    if id > 0 {
-        kvi.features[0] |= 1 << kvm_bindings::KVM_ARM_VCPU_POWER_OFF;
-    }
-
-    fd.vcpu_init(&kvi).map_err(Error::VcpuArmInit)?;
     if let Some(kernel_entry_point) = kernel_entry_point {
         regs::setup_regs(
             fd,
@@ -94,7 +75,7 @@ pub fn configure_vcpu(
         .map_err(Error::REGSConfiguration)?;
     }
 
-    let mpidr = regs::read_mpidr(fd).map_err(Error::REGSConfiguration)?;
+    let mpidr = fd.read_mpidr().map_err(Error::VcpuRegMPIDR)?;
     Ok(mpidr)
 }
 
@@ -136,34 +117,31 @@ pub fn arch_memory_regions(size: GuestUsize) -> Vec<(GuestAddress, usize, Region
 ///
 /// * `guest_mem` - The memory to be used by the guest.
 /// * `num_cpus` - Number of virtual CPUs the guest will have.
-pub fn configure_system<T: DeviceInfoForFDT + Clone + Debug>(
+#[allow(clippy::too_many_arguments)]
+pub fn configure_system<T: DeviceInfoForFDT + Clone + Debug, S: ::std::hash::BuildHasher>(
     vm: &Arc<dyn hypervisor::Vm>,
     guest_mem: &GuestMemoryMmap,
     cmdline_cstring: &CStr,
     vcpu_count: u64,
     vcpu_mpidr: Vec<u64>,
-    device_info: &HashMap<(DeviceType, String), T>,
+    device_info: &HashMap<(DeviceType, String), T, S>,
     initrd: &Option<super::InitramfsConfig>,
-    pci_space_address: &Option<(u64, u64)>,
-) -> super::Result<()> {
-    // If pci_space_address is present, it means PCI devices are used ("pci" feature enabled).
-    // Then GITv3-ITS is required for MSI messaging.
-    // Otherwise ("mmio" feature enabled), any version of GIC is OK.
-    let gic_device = gic::kvm::create_gic(vm, vcpu_count, pci_space_address.is_some())
-        .map_err(Error::SetupGIC)?;
+    pci_space_address: &(u64, u64),
+) -> super::Result<Box<dyn GICDevice>> {
+    let gic_device = gic::kvm::create_gic(vm, vcpu_count).map_err(Error::SetupGIC)?;
 
     fdt::create_fdt(
         guest_mem,
         cmdline_cstring,
         vcpu_mpidr,
         device_info,
-        &gic_device,
+        &*gic_device,
         initrd,
         pci_space_address,
     )
     .map_err(Error::SetupFDT)?;
 
-    Ok(())
+    Ok(gic_device)
 }
 
 /// Returns the memory address where the initramfs could be loaded.
@@ -209,10 +187,10 @@ fn get_fdt_addr(mem: &GuestMemoryMmap) -> u64 {
 pub fn get_host_cpu_phys_bits() -> u8 {
     // The value returned here is used to determine the physical address space size
     // for a VM (IPA size).
-    // In recent kernel versions, the maxium IPA size supported by the host can be
+    // In recent kernel versions, the maximum IPA size supported by the host can be
     // known by querying cap KVM_CAP_ARM_VM_IPA_SIZE. And the IPA size for a
     // guest can be configured smaller.
-    // But in Cloud-Hypervisor we simply use the maxium value for the VM.
+    // But in Cloud-Hypervisor we simply use the maximum value for the VM.
     // Reference https://lwn.net/Articles/766767/.
     //
     // The correct way to query KVM_CAP_ARM_VM_IPA_SIZE is via rust-vmm/kvm-ioctls,

arch/src/aarch64/regs.rs

@@ -7,12 +7,9 @@
 
 use super::get_fdt_addr;
 use hypervisor::kvm::kvm_bindings::{
-    user_pt_regs, KVM_REG_ARM64, KVM_REG_ARM64_SYSREG, KVM_REG_ARM64_SYSREG_CRM_MASK,
-    KVM_REG_ARM64_SYSREG_CRM_SHIFT, KVM_REG_ARM64_SYSREG_CRN_MASK, KVM_REG_ARM64_SYSREG_CRN_SHIFT,
-    KVM_REG_ARM64_SYSREG_OP0_MASK, KVM_REG_ARM64_SYSREG_OP0_SHIFT, KVM_REG_ARM64_SYSREG_OP1_MASK,
-    KVM_REG_ARM64_SYSREG_OP1_SHIFT, KVM_REG_ARM64_SYSREG_OP2_MASK, KVM_REG_ARM64_SYSREG_OP2_SHIFT,
-    KVM_REG_ARM_CORE, KVM_REG_SIZE_U64,
+    kvm_regs, user_pt_regs, KVM_REG_ARM64, KVM_REG_ARM_CORE, KVM_REG_SIZE_U64,
 };
+use hypervisor::{arm64_core_reg_id, offset__of};
 use std::sync::Arc;
 use std::{mem, result};
 use vm_memory::GuestMemoryMmap;
@@ -38,80 +35,6 @@ const PSR_D_BIT: u64 = 0x0000_0200;
 // Taken from arch/arm64/kvm/inject_fault.c.
 const PSTATE_FAULT_BITS_64: u64 = PSR_MODE_EL1h | PSR_A_BIT | PSR_F_BIT | PSR_I_BIT | PSR_D_BIT;
 
-// Following are macros that help with getting the ID of a aarch64 core register.
-// The core register are represented by the user_pt_regs structure. Look for it in
-// arch/arm64/include/uapi/asm/ptrace.h.
-
-// This macro gets the offset of a structure (i.e `str`) member (i.e `field`) without having
-// an instance of that structure.
-// It uses a null pointer to retrieve the offset to the field.
-// Inspired by C solution: `#define offsetof(str, f) ((size_t)(&((str *)0)->f))`.
-// Doing `offset__of!(user_pt_regs, pstate)` in our rust code will trigger the following:
-// unsafe { &(*(0 as *const user_pt_regs)).pstate as *const _ as usize }
-// The dereference expression produces an lvalue, but that lvalue is not actually read from,
-// we're just doing pointer math on it, so in theory, it should safe.
-macro_rules! offset__of {
-    ($str:ty, $field:ident) => {
-        unsafe { &(*(0 as *const $str)).$field as *const _ as usize }
-    };
-}
-
-macro_rules! arm64_core_reg {
-    ($reg: tt) => {
-        // As per `kvm_arm_copy_reg_indices`, the id of a core register can be obtained like this:
-        // `const u64 core_reg = KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | i`, where i is obtained with:
-        // `for (i = 0; i < sizeof(struct kvm_regs) / sizeof(__u32); i++) {`
-        // We are using here `user_pt_regs` since this structure contains the core register and it is at
-        // the start of `kvm_regs`.
-        // struct kvm_regs {
-        //	struct user_pt_regs regs;	/* sp = sp_el0 */
-        //
-        //	__u64	sp_el1;
-        //	__u64	elr_el1;
-        //
-        //	__u64	spsr[KVM_NR_SPSR];
-        //
-        //	struct user_fpsimd_state fp_regs;
-        //};
-        // struct user_pt_regs {
-        //	__u64		regs[31];
-        //	__u64		sp;
-        //	__u64		pc;
-        //	__u64		pstate;
-        //};
-        // In our implementation we need: pc, pstate and user_pt_regs->regs[0].
-        KVM_REG_ARM64 as u64
-            | KVM_REG_SIZE_U64 as u64
-            | u64::from(KVM_REG_ARM_CORE)
-            | ((offset__of!(user_pt_regs, $reg) / mem::size_of::<u32>()) as u64)
-    };
-}
-
-// This macro computes the ID of a specific ARM64 system register similar to how
-// the kernel C macro does.
-// https://elixir.bootlin.com/linux/v4.20.17/source/arch/arm64/include/uapi/asm/kvm.h#L203
-macro_rules! arm64_sys_reg {
-    ($name: tt, $op0: tt, $op1: tt, $crn: tt, $crm: tt, $op2: tt) => {
-        const $name: u64 = KVM_REG_ARM64 as u64
-            | KVM_REG_SIZE_U64 as u64
-            | KVM_REG_ARM64_SYSREG as u64
-            | ((($op0 as u64) << KVM_REG_ARM64_SYSREG_OP0_SHIFT)
-                & KVM_REG_ARM64_SYSREG_OP0_MASK as u64)
-            | ((($op1 as u64) << KVM_REG_ARM64_SYSREG_OP1_SHIFT)
-                & KVM_REG_ARM64_SYSREG_OP1_MASK as u64)
-            | ((($crn as u64) << KVM_REG_ARM64_SYSREG_CRN_SHIFT)
-                & KVM_REG_ARM64_SYSREG_CRN_MASK as u64)
-            | ((($crm as u64) << KVM_REG_ARM64_SYSREG_CRM_SHIFT)
-                & KVM_REG_ARM64_SYSREG_CRM_MASK as u64)
-            | ((($op2 as u64) << KVM_REG_ARM64_SYSREG_OP2_SHIFT)
-                & KVM_REG_ARM64_SYSREG_OP2_MASK as u64);
-    };
-}
-
-// Constant imported from the Linux kernel:
-// https://elixir.bootlin.com/linux/v4.20.17/source/arch/arm64/include/asm/sysreg.h#L135
-arm64_sys_reg!(MPIDR_EL1, 3, 0, 0, 0, 5);
-
 /// Configure core registers for a given CPU.
 ///
 /// # Arguments
@@ -126,31 +49,33 @@ pub fn setup_regs(
     boot_ip: u64,
     mem: &GuestMemoryMmap,
 ) -> Result<()> {
+    let kreg_off = offset__of!(kvm_regs, regs);
+
     // Get the register index of the PSTATE (Processor State) register.
-    vcpu.set_one_reg(arm64_core_reg!(pstate), PSTATE_FAULT_BITS_64)
-        .map_err(Error::SetCoreRegister)?;
+    let pstate = offset__of!(user_pt_regs, pstate) + kreg_off;
+    vcpu.set_reg(
+        arm64_core_reg_id!(KVM_REG_SIZE_U64, pstate),
+        PSTATE_FAULT_BITS_64,
+    )
+    .map_err(Error::SetCoreRegister)?;
 
     // Other vCPUs are powered off initially awaiting PSCI wakeup.
     if cpu_id == 0 {
         // Setting the PC (Processor Counter) to the current program address (kernel address).
-        vcpu.set_one_reg(arm64_core_reg!(pc), boot_ip)
+        let pc = offset__of!(user_pt_regs, pc) + kreg_off;
+        vcpu.set_reg(arm64_core_reg_id!(KVM_REG_SIZE_U64, pc), boot_ip as u64)
             .map_err(Error::SetCoreRegister)?;
 
         // Last mandatory thing to set -> the address pointing to the FDT (also called DTB).
         // "The device tree blob (dtb) must be placed on an 8-byte boundary and must
         // not exceed 2 megabytes in size." -> https://www.kernel.org/doc/Documentation/arm64/booting.txt.
         // We are choosing to place it the end of DRAM. See `get_fdt_addr`.
-        vcpu.set_one_reg(arm64_core_reg!(regs), get_fdt_addr(mem) as u64)
-            .map_err(Error::SetCoreRegister)?;
+        let regs0 = offset__of!(user_pt_regs, regs) + kreg_off;
+        vcpu.set_reg(
+            arm64_core_reg_id!(KVM_REG_SIZE_U64, regs0),
+            get_fdt_addr(mem) as u64,
+        )
+        .map_err(Error::SetCoreRegister)?;
     }
     Ok(())
 }
-
-/// Read the MPIDR - Multiprocessor Affinity Register.
-///
-/// # Arguments
-///
-/// * `vcpu` - Structure for the VCPU that holds the VCPU's fd.
-pub fn read_mpidr(vcpu: &Arc<dyn hypervisor::Vcpu>) -> Result<u64> {
-    vcpu.get_one_reg(MPIDR_EL1).map_err(Error::GetSysRegister)
-}

arch/src/lib.rs

@@ -14,6 +14,7 @@
     clippy::cast_ptr_alignment
 )]
 
+extern crate anyhow;
 extern crate byteorder;
 extern crate hypervisor;
 extern crate libc;
@@ -23,7 +24,13 @@ extern crate log;
 extern crate acpi_tables;
 extern crate arch_gen;
 extern crate linux_loader;
+extern crate serde;
 extern crate vm_memory;
+extern crate vm_migration;
+#[cfg(target_arch = "aarch64")]
+#[macro_use]
+extern crate serde_derive;
+extern crate serde_json;
 
 use std::fmt;
 use std::result;

arch/src/x86_64/layout.rs

@@ -7,7 +7,7 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE-BSD-3-Clause file.
 
-use vm_memory::{GuestAddress, GuestUsize};
+use vm_memory::GuestAddress;
 
 /*
 
@@ -81,22 +81,22 @@ pub const HIGH_RAM_START: GuestAddress = GuestAddress(0x100000);
 
 // ** 32-bit reserved area (start: 3GiB, length: 1GiB) **
 pub const MEM_32BIT_RESERVED_START: GuestAddress = GuestAddress(0xc000_0000);
-pub const MEM_32BIT_RESERVED_SIZE: GuestUsize = 1024 << 20;
+pub const MEM_32BIT_RESERVED_SIZE: u64 = 1024 << 20;
 
 // == Fixed constants within the "32-bit reserved" range ==
 
 // Sub range: 32-bit PCI devices (start: 3GiB, length: 640Mib)
 pub const MEM_32BIT_DEVICES_START: GuestAddress = MEM_32BIT_RESERVED_START;
-pub const MEM_32BIT_DEVICES_SIZE: GuestUsize = 640 << 20;
+pub const MEM_32BIT_DEVICES_SIZE: u64 = 640 << 20;
 
 // PCI MMCONFIG space (start: after the device space, length: 256MiB)
 pub const PCI_MMCONFIG_START: GuestAddress =
     GuestAddress(MEM_32BIT_DEVICES_START.0 + MEM_32BIT_DEVICES_SIZE);
-pub const PCI_MMCONFIG_SIZE: GuestUsize = 256 << 20;
+pub const PCI_MMCONFIG_SIZE: u64 = 256 << 20;
 
 // IOAPIC
 pub const IOAPIC_START: GuestAddress = GuestAddress(0xfec0_0000);
-pub const IOAPIC_SIZE: GuestUsize = 0x20;
+pub const IOAPIC_SIZE: u64 = 0x20;
 
 // APIC
 pub const APIC_START: GuestAddress = GuestAddress(0xfee0_0000);

arch/src/x86_64/mod.rs

@@ -7,10 +7,8 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE-BSD-3-Clause file.
 use std::sync::Arc;
-mod gdt;
 pub mod interrupts;
 pub mod layout;
-#[cfg(not(feature = "acpi"))]
 mod mptable;
 pub mod regs;
 use crate::InitramfsConfig;
@@ -26,6 +24,7 @@ use vm_memory::{
     GuestMemoryMmap, GuestMemoryRegion, GuestUsize,
 };
 mod smbios;
+use std::arch::x86_64;
 
 #[derive(Debug, Copy, Clone)]
 pub enum BootProtocol {
@@ -141,7 +140,7 @@ unsafe impl ByteValued for BootParamsWrapper {}
 pub enum Error {
     /// Invalid e820 setup params.
     E820Configuration,
-    #[cfg(not(feature = "acpi"))]
+
     /// Error writing MP table to memory.
     MpTableSetup(mptable::Error),
 
@@ -174,6 +173,9 @@ pub enum Error {
 
     /// Missing SGX_LC CPU feature
     MissingSgxLaunchControlFeature,
+
+    // Error populating Cpuid
+    PopulatingCpuid,
 }
 
 impl From<Error> for super::Error {
@@ -333,13 +335,95 @@ pub fn configure_vcpu(
     kernel_entry_point: Option<EntryPoint>,
     vm_memory: &GuestMemoryAtomic<GuestMemoryMmap>,
     cpuid: CpuId,
+    kvm_hyperv: bool,
+    phys_bits: u8,
 ) -> super::Result<()> {
     let mut cpuid = cpuid;
     CpuidPatch::set_cpuid_reg(&mut cpuid, 0xb, None, CpuidReg::EDX, u32::from(id));
     CpuidPatch::set_cpuid_reg(&mut cpuid, 0x1f, None, CpuidReg::EDX, u32::from(id));
+
+    if kvm_hyperv {
+        // Remove conflicting entries
+        cpuid.retain(|c| c.function != 0x4000_0000);
+        cpuid.retain(|c| c.function != 0x4000_0001);
+
+        // See "Hypervisor Top Level Functional Specification" for details
+        // Compliance with "Hv#1" requires leaves up to 0x4000_000a
+        cpuid
+            .push(CpuIdEntry {
+                function: 0x40000000,
+                eax: 0x4000000a, // Maximum cpuid leaf
+                ebx: 0x756e694c, // "Linu"
+                ecx: 0x564b2078, // "x KV"
+                edx: 0x7648204d, // "M Hv"
+                ..Default::default()
+            })
+            .map_err(|_| Error::PopulatingCpuid)?;
+        cpuid
+            .push(CpuIdEntry {
+                function: 0x40000001,
+                eax: 0x31237648, // "Hv#1"
+                ..Default::default()
+            })
+            .map_err(|_| Error::PopulatingCpuid)?;
+        cpuid
+            .push(CpuIdEntry {
+                function: 0x40000002,
+                eax: 0x3839,  // "Build number"
+                ebx: 0xa0000, // "Version"
+                ..Default::default()
+            })
+            .map_err(|_| Error::PopulatingCpuid)?;
+        cpuid
+            .push(CpuIdEntry {
+                function: 0x4000_0003,
+                eax: 1 << 1 // AccessPartitionReferenceCounter
+                   | 1 << 2 // AccessSynicRegs
+                   | 1 << 3 // AccessSyntheticTimerRegs
+                   | 1 << 9, // AccessPartitionReferenceTsc
+                ..Default::default()
+            })
+            .map_err(|_| Error::PopulatingCpuid)?;
+        for i in 0x4000_0004..=0x4000_000a {
+            cpuid
+                .push(CpuIdEntry {
+                    function: i,
+                    ..Default::default()
+                })
+                .map_err(|_| Error::PopulatingCpuid)?;
+        }
+    }
+
+    // Copy CPU identification string
+    for i in 0x8000_0002..=0x8000_0004 {
+        cpuid.retain(|c| c.function != i);
+        let leaf = unsafe { x86_64::__cpuid(i) };
+        cpuid
+            .push(CpuIdEntry {
+                function: i,
+                eax: leaf.eax,
+                ebx: leaf.ebx,
+                ecx: leaf.ecx,
+                edx: leaf.edx,
+                ..Default::default()
+            })
+            .map_err(|_| Error::PopulatingCpuid)?;
+    }
+
+    // Set CPU physical bits
+    for entry in cpuid.as_mut_slice().iter_mut() {
+        if entry.function == 0x8000_0008 {
+            entry.eax = (entry.eax & 0xffff_ff00) | (phys_bits as u32 & 0xff);
+        }
+    }
+
     fd.set_cpuid2(&cpuid)
         .map_err(|e| Error::SetSupportedCpusFailed(e.into()))?;
 
+    if kvm_hyperv {
+        fd.enable_hyperv_synic().unwrap();
+    }
+
     regs::setup_msrs(fd).map_err(Error::MSRSConfiguration)?;
     if let Some(kernel_entry_point) = kernel_entry_point {
         // Safe to unwrap because this method is called after the VM is configured
@@ -426,11 +510,12 @@ pub fn configure_system(
     boot_prot: BootProtocol,
     sgx_epc_region: Option<SgxEpcRegion>,
 ) -> super::Result<()> {
-    smbios::setup_smbios(guest_mem).map_err(Error::SmbiosSetup)?;
+    let size = smbios::setup_smbios(guest_mem).map_err(Error::SmbiosSetup)?;
 
-    // Note that this puts the mptable at the last 1k of Linux's 640k base RAM
-    #[cfg(not(feature = "acpi"))]
-    mptable::setup_mptable(guest_mem, _num_cpus).map_err(Error::MpTableSetup)?;
+    // Place the MP table after the SMIOS table aligned to 16 bytes
+    let offset = GuestAddress(layout::SMBIOS_START).unchecked_add(size);
+    let offset = GuestAddress((offset.0 + 16) & !0xf);
+    mptable::setup_mptable(offset, guest_mem, _num_cpus).map_err(Error::MpTableSetup)?;
 
     // Check that the RAM is not smaller than the RSDP start address
     if let Some(rsdp_addr) = rsdp_addr {
@@ -747,7 +832,6 @@ pub fn initramfs_load_addr(
 }
 
 pub fn get_host_cpu_phys_bits() -> u8 {
-    use std::arch::x86_64;
     unsafe {
         let leaf = x86_64::__cpuid(0x8000_0000);
 
@@ -907,7 +991,7 @@ mod tests {
     #[test]
     fn test_system_configuration() {
         let no_vcpus = 4;
-        let gm = GuestMemoryMmap::from_ranges(&vec![(GuestAddress(0), 0x10000)]).unwrap();
+        let gm = GuestMemoryMmap::from_ranges(&[(GuestAddress(0), 0x10000)]).unwrap();
         let config_err = configure_system(
             &gm,
             GuestAddress(0),

arch/src/x86_64/mptable.rs

@@ -13,8 +13,10 @@ use std::slice;
 use libc::c_char;
 
 use arch_gen::x86::mpspec;
-use layout::{APIC_START, IOAPIC_START, MPTABLE_START};
-use vm_memory::{Address, ByteValued, Bytes, GuestMemory, GuestMemoryError, GuestMemoryMmap};
+use layout::{APIC_START, HIGH_RAM_START, IOAPIC_START};
+use vm_memory::{
+    Address, ByteValued, Bytes, GuestAddress, GuestMemory, GuestMemoryError, GuestMemoryMmap,
+};
 
 // This is a workaround to the Rust enforcement specifying that any implementation of a foreign
 // trait (in this case `ByteValued`) where:
@@ -121,16 +123,21 @@ fn compute_mp_size(num_cpus: u8) -> usize {
 }
 
 /// Performs setup of the MP table for the given `num_cpus`.
-pub fn setup_mptable(mem: &GuestMemoryMmap, num_cpus: u8) -> Result<()> {
+pub fn setup_mptable(offset: GuestAddress, mem: &GuestMemoryMmap, num_cpus: u8) -> Result<()> {
     if num_cpus as u32 > MAX_SUPPORTED_CPUS {
         return Err(Error::TooManyCpus);
     }
 
     // Used to keep track of the next base pointer into the MP table.
-    let mut base_mp = MPTABLE_START;
+    let mut base_mp = offset;
 
     let mp_size = compute_mp_size(num_cpus);
 
+    if offset.unchecked_add(mp_size as u64) >= HIGH_RAM_START {
+        warn!("Skipping mptable creation due to insufficient space");
+        return Ok(());
+    }
+
     let mut checksum: u8 = 0;
     let ioapicid: u8 = num_cpus + 1;
 
@@ -280,6 +287,7 @@ pub fn setup_mptable(mem: &GuestMemoryMmap, num_cpus: u8) -> Result<()> {
 #[cfg(test)]
 mod tests {
     use super::*;
+    use layout::MPTABLE_START;
     use vm_memory::{GuestAddress, GuestUsize};
 
     fn table_entry_size(type_: u8) -> usize {
@@ -299,7 +307,7 @@ mod tests {
         let mem =
             GuestMemoryMmap::from_ranges(&[(MPTABLE_START, compute_mp_size(num_cpus))]).unwrap();
 
-        setup_mptable(&mem, num_cpus).unwrap();
+        setup_mptable(MPTABLE_START, &mem, num_cpus).unwrap();
     }
 
     #[test]
@@ -308,7 +316,7 @@ mod tests {
         let mem = GuestMemoryMmap::from_ranges(&[(MPTABLE_START, compute_mp_size(num_cpus) - 1)])
             .unwrap();
 
-        assert!(setup_mptable(&mem, num_cpus).is_err());
+        assert!(setup_mptable(MPTABLE_START, &mem, num_cpus).is_err());
     }
 
     #[test]
@@ -317,7 +325,7 @@ mod tests {
         let mem =
             GuestMemoryMmap::from_ranges(&[(MPTABLE_START, compute_mp_size(num_cpus))]).unwrap();
 
-        setup_mptable(&mem, num_cpus).unwrap();
+        setup_mptable(MPTABLE_START, &mem, num_cpus).unwrap();
 
         let mpf_intel: MpfIntelWrapper = mem.read_obj(MPTABLE_START).unwrap();
 
@@ -333,7 +341,7 @@ mod tests {
         let mem =
             GuestMemoryMmap::from_ranges(&[(MPTABLE_START, compute_mp_size(num_cpus))]).unwrap();
 
-        setup_mptable(&mem, num_cpus).unwrap();
+        setup_mptable(MPTABLE_START, &mem, num_cpus).unwrap();
 
         let mpf_intel: MpfIntelWrapper = mem.read_obj(MPTABLE_START).unwrap();
         let mpc_offset = GuestAddress(mpf_intel.0.physptr as GuestUsize);
@@ -367,7 +375,7 @@ mod tests {
         .unwrap();
 
         for i in 0..MAX_SUPPORTED_CPUS as u8 {
-            setup_mptable(&mem, i).unwrap();
+            setup_mptable(MPTABLE_START, &mem, i).unwrap();
 
             let mpf_intel: MpfIntelWrapper = mem.read_obj(MPTABLE_START).unwrap();
             let mpc_offset = GuestAddress(mpf_intel.0.physptr as GuestUsize);
@@ -400,7 +408,7 @@ mod tests {
         let mem =
             GuestMemoryMmap::from_ranges(&[(MPTABLE_START, compute_mp_size(cpus as u8))]).unwrap();
 
-        let result = setup_mptable(&mem, cpus as u8);
+        let result = setup_mptable(MPTABLE_START, &mem, cpus as u8);
         assert!(result.is_err());
     }
 }

arch/src/x86_64/regs.rs

@@ -9,8 +9,9 @@
 use std::sync::Arc;
 use std::{mem, result};
 
-use super::gdt::{gdt_entry, segment_from_gdt};
 use super::BootProtocol;
+use hypervisor::arch::x86::gdt::{gdt_entry, segment_from_gdt};
+use hypervisor::arch::x86::regs::*;
 use hypervisor::x86_64::{FpuState, SpecialRegisters, StandardRegisters};
 use layout::{
     BOOT_GDT_START, BOOT_IDT_START, PDE_START, PDPTE_START, PML4_START, PML5_START, PVH_INFO_START,
@@ -134,14 +135,6 @@ pub fn setup_sregs(
 
 const BOOT_GDT_MAX: usize = 4;
 
-const EFER_LMA: u64 = 0x400;
-const EFER_LME: u64 = 0x100;
-
-const X86_CR0_PE: u64 = 0x1;
-const X86_CR0_PG: u64 = 0x80000000;
-const X86_CR4_PAE: u64 = 0x20;
-const X86_CR4_LA57: u64 = 0x1000;
-
 fn write_gdt_table(table: &[u64], guest_mem: &GuestMemoryMmap) -> Result<()> {
     let boot_gdt_addr = BOOT_GDT_START;
     for (index, entry) in table.iter().enumerate() {
@@ -209,12 +202,12 @@ pub fn configure_segments_and_sregs(
 
     match boot_prot {
         BootProtocol::PvhBoot => {
-            sregs.cr0 = X86_CR0_PE;
+            sregs.cr0 = CR0_PE;
             sregs.cr4 = 0;
         }
         BootProtocol::LinuxBoot => {
             /* 64-bit protected mode */
-            sregs.cr0 |= X86_CR0_PE;
+            sregs.cr0 |= CR0_PE;
             sregs.efer |= EFER_LME | EFER_LMA;
         }
     }
@@ -230,7 +223,7 @@ pub fn setup_page_tables(mem: &GuestMemoryMmap, sregs: &mut SpecialRegisters) ->
             .map_err(Error::WritePML5Address)?;
 
         sregs.cr3 = PML5_START.raw_value();
-        sregs.cr4 |= X86_CR4_LA57;
+        sregs.cr4 |= CR4_LA57;
     } else {
         sregs.cr3 = PML4_START.raw_value();
     }
@@ -250,8 +243,8 @@ pub fn setup_page_tables(mem: &GuestMemoryMmap, sregs: &mut SpecialRegisters) ->
             .map_err(Error::WritePDEAddress)?;
     }
 
-    sregs.cr4 |= X86_CR4_PAE;
-    sregs.cr0 |= X86_CR0_PG;
+    sregs.cr4 |= CR4_PAE;
+    sregs.cr0 |= CR0_PG;
 
     Ok(())
 }
@@ -264,7 +257,7 @@ mod tests {
     use vm_memory::{GuestAddress, GuestMemoryMmap};
 
     fn create_guest_mem() -> GuestMemoryMmap {
-        GuestMemoryMmap::from_ranges(&vec![(GuestAddress(0), 0x10000)]).unwrap()
+        GuestMemoryMmap::from_ranges(&[(GuestAddress(0), 0x10000)]).unwrap()
     }
 
     fn read_u64(gm: &GuestMemoryMmap, offset: GuestAddress) -> u64 {
@@ -301,7 +294,7 @@ mod tests {
         assert_eq!(0, sregs.tr.base);
         assert_eq!(0xffffffff, sregs.tr.limit);
         assert_eq!(0, sregs.tr.avl);
-        assert_eq!(X86_CR0_PE, sregs.cr0);
+        assert_eq!(CR0_PE, sregs.cr0);
         assert_eq!(EFER_LME | EFER_LMA, sregs.efer);
 
         configure_segments_and_sregs(&gm, &mut sregs, BootProtocol::PvhBoot).unwrap();
@@ -331,7 +324,7 @@ mod tests {
         assert_eq!(0x67, sregs.tr.limit);
         assert_eq!(0xb, sregs.tr.type_);
         assert_eq!(0, sregs.tr.avl);
-        assert_eq!(X86_CR0_PE, sregs.cr0);
+        assert_eq!(CR0_PE, sregs.cr0);
         assert_eq!(0, sregs.cr4);
     }
 
@@ -358,7 +351,7 @@ mod tests {
         } else {
             assert_eq!(PML4_START.raw_value(), sregs.cr3);
         }
-        assert_eq!(X86_CR4_PAE, sregs.cr4);
-        assert_eq!(X86_CR0_PG, sregs.cr0);
+        assert_eq!(CR4_PAE, sregs.cr4);
+        assert_eq!(CR0_PG, sregs.cr0);
     }
 }

arch/src/x86_64/smbios.rs

@@ -161,7 +161,7 @@ fn write_string(
     Ok(curptr)
 }
 
-pub fn setup_smbios(mem: &GuestMemoryMmap) -> Result<()> {
+pub fn setup_smbios(mem: &GuestMemoryMmap) -> Result<u64> {
     let physptr = GuestAddress(SMBIOS_START)
         .checked_add(mem::size_of::<Smbios30Entrypoint>() as u64)
         .ok_or(Error::NotEnoughMemory)?;
@@ -224,7 +224,7 @@ pub fn setup_smbios(mem: &GuestMemoryMmap) -> Result<()> {
             .map_err(|_| Error::WriteSmbiosEp)?;
     }
 
-    Ok(())
+    Ok(curptr.unchecked_offset_from(physptr))
 }
 
 #[cfg(test)]

arch_gen/src/x86/mpspec.rs

@@ -67,7 +67,7 @@ fn bindgen_test_layout_mpf_intel() {
         concat!("Alignment of ", stringify!(mpf_intel))
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpf_intel)).signature as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpf_intel>()).signature as *const _ as usize },
         0usize,
         concat!(
             "Alignment of field: ",
@@ -77,7 +77,7 @@ fn bindgen_test_layout_mpf_intel() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpf_intel)).physptr as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpf_intel>()).physptr as *const _ as usize },
         4usize,
         concat!(
             "Alignment of field: ",
@@ -87,7 +87,7 @@ fn bindgen_test_layout_mpf_intel() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpf_intel)).length as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpf_intel>()).length as *const _ as usize },
         8usize,
         concat!(
             "Alignment of field: ",
@@ -97,7 +97,7 @@ fn bindgen_test_layout_mpf_intel() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpf_intel)).specification as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpf_intel>()).specification as *const _ as usize },
         9usize,
         concat!(
             "Alignment of field: ",
@@ -107,7 +107,7 @@ fn bindgen_test_layout_mpf_intel() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpf_intel)).checksum as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpf_intel>()).checksum as *const _ as usize },
         10usize,
         concat!(
             "Alignment of field: ",
@@ -117,7 +117,7 @@ fn bindgen_test_layout_mpf_intel() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpf_intel)).feature1 as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpf_intel>()).feature1 as *const _ as usize },
         11usize,
         concat!(
             "Alignment of field: ",
@@ -127,7 +127,7 @@ fn bindgen_test_layout_mpf_intel() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpf_intel)).feature2 as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpf_intel>()).feature2 as *const _ as usize },
         12usize,
         concat!(
             "Alignment of field: ",
@@ -137,7 +137,7 @@ fn bindgen_test_layout_mpf_intel() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpf_intel)).feature3 as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpf_intel>()).feature3 as *const _ as usize },
         13usize,
         concat!(
             "Alignment of field: ",
@@ -147,7 +147,7 @@ fn bindgen_test_layout_mpf_intel() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpf_intel)).feature4 as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpf_intel>()).feature4 as *const _ as usize },
         14usize,
         concat!(
             "Alignment of field: ",
@@ -157,7 +157,7 @@ fn bindgen_test_layout_mpf_intel() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpf_intel)).feature5 as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpf_intel>()).feature5 as *const _ as usize },
         15usize,
         concat!(
             "Alignment of field: ",
@@ -200,7 +200,7 @@ fn bindgen_test_layout_mpc_table() {
         concat!("Alignment of ", stringify!(mpc_table))
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_table)).signature as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_table>()).signature as *const _ as usize },
         0usize,
         concat!(
             "Alignment of field: ",
@@ -210,7 +210,7 @@ fn bindgen_test_layout_mpc_table() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_table)).length as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_table>()).length as *const _ as usize },
         4usize,
         concat!(
             "Alignment of field: ",
@@ -220,7 +220,7 @@ fn bindgen_test_layout_mpc_table() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_table)).spec as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_table>()).spec as *const _ as usize },
         6usize,
         concat!(
             "Alignment of field: ",
@@ -230,7 +230,7 @@ fn bindgen_test_layout_mpc_table() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_table)).checksum as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_table>()).checksum as *const _ as usize },
         7usize,
         concat!(
             "Alignment of field: ",
@@ -240,7 +240,7 @@ fn bindgen_test_layout_mpc_table() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_table)).oem as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_table>()).oem as *const _ as usize },
         8usize,
         concat!(
             "Alignment of field: ",
@@ -250,7 +250,7 @@ fn bindgen_test_layout_mpc_table() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_table)).productid as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_table>()).productid as *const _ as usize },
         16usize,
         concat!(
             "Alignment of field: ",
@@ -260,7 +260,7 @@ fn bindgen_test_layout_mpc_table() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_table)).oemptr as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_table>()).oemptr as *const _ as usize },
         28usize,
         concat!(
             "Alignment of field: ",
@@ -270,7 +270,7 @@ fn bindgen_test_layout_mpc_table() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_table)).oemsize as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_table>()).oemsize as *const _ as usize },
         32usize,
         concat!(
             "Alignment of field: ",
@@ -280,7 +280,7 @@ fn bindgen_test_layout_mpc_table() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_table)).oemcount as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_table>()).oemcount as *const _ as usize },
         34usize,
         concat!(
             "Alignment of field: ",
@@ -290,7 +290,7 @@ fn bindgen_test_layout_mpc_table() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_table)).lapic as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_table>()).lapic as *const _ as usize },
         36usize,
         concat!(
             "Alignment of field: ",
@@ -300,7 +300,7 @@ fn bindgen_test_layout_mpc_table() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_table)).reserved as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_table>()).reserved as *const _ as usize },
         40usize,
         concat!(
             "Alignment of field: ",
@@ -339,7 +339,7 @@ fn bindgen_test_layout_mpc_cpu() {
         concat!("Alignment of ", stringify!(mpc_cpu))
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_cpu)).type_ as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_cpu>()).type_ as *const _ as usize },
         0usize,
         concat!(
             "Alignment of field: ",
@@ -349,7 +349,7 @@ fn bindgen_test_layout_mpc_cpu() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_cpu)).apicid as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_cpu>()).apicid as *const _ as usize },
         1usize,
         concat!(
             "Alignment of field: ",
@@ -359,7 +359,7 @@ fn bindgen_test_layout_mpc_cpu() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_cpu)).apicver as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_cpu>()).apicver as *const _ as usize },
         2usize,
         concat!(
             "Alignment of field: ",
@@ -369,7 +369,7 @@ fn bindgen_test_layout_mpc_cpu() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_cpu)).cpuflag as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_cpu>()).cpuflag as *const _ as usize },
         3usize,
         concat!(
             "Alignment of field: ",
@@ -379,7 +379,7 @@ fn bindgen_test_layout_mpc_cpu() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_cpu)).cpufeature as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_cpu>()).cpufeature as *const _ as usize },
         4usize,
         concat!(
             "Alignment of field: ",
@@ -389,7 +389,7 @@ fn bindgen_test_layout_mpc_cpu() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_cpu)).featureflag as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_cpu>()).featureflag as *const _ as usize },
         8usize,
         concat!(
             "Alignment of field: ",
@@ -399,7 +399,7 @@ fn bindgen_test_layout_mpc_cpu() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_cpu)).reserved as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_cpu>()).reserved as *const _ as usize },
         12usize,
         concat!(
             "Alignment of field: ",
@@ -434,7 +434,7 @@ fn bindgen_test_layout_mpc_bus() {
         concat!("Alignment of ", stringify!(mpc_bus))
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_bus)).type_ as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_bus>()).type_ as *const _ as usize },
         0usize,
         concat!(
             "Alignment of field: ",
@@ -444,7 +444,7 @@ fn bindgen_test_layout_mpc_bus() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_bus)).busid as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_bus>()).busid as *const _ as usize },
         1usize,
         concat!(
             "Alignment of field: ",
@@ -454,7 +454,7 @@ fn bindgen_test_layout_mpc_bus() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_bus)).bustype as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_bus>()).bustype as *const _ as usize },
         2usize,
         concat!(
             "Alignment of field: ",
@@ -491,7 +491,7 @@ fn bindgen_test_layout_mpc_ioapic() {
         concat!("Alignment of ", stringify!(mpc_ioapic))
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_ioapic)).type_ as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_ioapic>()).type_ as *const _ as usize },
         0usize,
         concat!(
             "Alignment of field: ",
@@ -501,7 +501,7 @@ fn bindgen_test_layout_mpc_ioapic() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_ioapic)).apicid as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_ioapic>()).apicid as *const _ as usize },
         1usize,
         concat!(
             "Alignment of field: ",
@@ -511,7 +511,7 @@ fn bindgen_test_layout_mpc_ioapic() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_ioapic)).apicver as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_ioapic>()).apicver as *const _ as usize },
         2usize,
         concat!(
             "Alignment of field: ",
@@ -521,7 +521,7 @@ fn bindgen_test_layout_mpc_ioapic() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_ioapic)).flags as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_ioapic>()).flags as *const _ as usize },
         3usize,
         concat!(
             "Alignment of field: ",
@@ -531,7 +531,7 @@ fn bindgen_test_layout_mpc_ioapic() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_ioapic)).apicaddr as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_ioapic>()).apicaddr as *const _ as usize },
         4usize,
         concat!(
             "Alignment of field: ",
@@ -570,7 +570,7 @@ fn bindgen_test_layout_mpc_intsrc() {
         concat!("Alignment of ", stringify!(mpc_intsrc))
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_intsrc)).type_ as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_intsrc>()).type_ as *const _ as usize },
         0usize,
         concat!(
             "Alignment of field: ",
@@ -580,7 +580,7 @@ fn bindgen_test_layout_mpc_intsrc() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_intsrc)).irqtype as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_intsrc>()).irqtype as *const _ as usize },
         1usize,
         concat!(
             "Alignment of field: ",
@@ -590,7 +590,7 @@ fn bindgen_test_layout_mpc_intsrc() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_intsrc)).irqflag as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_intsrc>()).irqflag as *const _ as usize },
         2usize,
         concat!(
             "Alignment of field: ",
@@ -600,7 +600,7 @@ fn bindgen_test_layout_mpc_intsrc() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_intsrc)).srcbus as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_intsrc>()).srcbus as *const _ as usize },
         4usize,
         concat!(
             "Alignment of field: ",
@@ -610,7 +610,7 @@ fn bindgen_test_layout_mpc_intsrc() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_intsrc)).srcbusirq as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_intsrc>()).srcbusirq as *const _ as usize },
         5usize,
         concat!(
             "Alignment of field: ",
@@ -620,7 +620,7 @@ fn bindgen_test_layout_mpc_intsrc() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_intsrc)).dstapic as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_intsrc>()).dstapic as *const _ as usize },
         6usize,
         concat!(
             "Alignment of field: ",
@@ -630,7 +630,7 @@ fn bindgen_test_layout_mpc_intsrc() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_intsrc)).dstirq as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_intsrc>()).dstirq as *const _ as usize },
         7usize,
         concat!(
             "Alignment of field: ",
@@ -674,7 +674,7 @@ fn bindgen_test_layout_mpc_lintsrc() {
         concat!("Alignment of ", stringify!(mpc_lintsrc))
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_lintsrc)).type_ as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_lintsrc>()).type_ as *const _ as usize },
         0usize,
         concat!(
             "Alignment of field: ",
@@ -684,7 +684,7 @@ fn bindgen_test_layout_mpc_lintsrc() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_lintsrc)).irqtype as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_lintsrc>()).irqtype as *const _ as usize },
         1usize,
         concat!(
             "Alignment of field: ",
@@ -694,7 +694,7 @@ fn bindgen_test_layout_mpc_lintsrc() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_lintsrc)).irqflag as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_lintsrc>()).irqflag as *const _ as usize },
         2usize,
         concat!(
             "Alignment of field: ",
@@ -704,7 +704,7 @@ fn bindgen_test_layout_mpc_lintsrc() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_lintsrc)).srcbusid as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_lintsrc>()).srcbusid as *const _ as usize },
         4usize,
         concat!(
             "Alignment of field: ",
@@ -714,7 +714,7 @@ fn bindgen_test_layout_mpc_lintsrc() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_lintsrc)).srcbusirq as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_lintsrc>()).srcbusirq as *const _ as usize },
         5usize,
         concat!(
             "Alignment of field: ",
@@ -724,7 +724,7 @@ fn bindgen_test_layout_mpc_lintsrc() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_lintsrc)).destapic as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_lintsrc>()).destapic as *const _ as usize },
         6usize,
         concat!(
             "Alignment of field: ",
@@ -734,7 +734,7 @@ fn bindgen_test_layout_mpc_lintsrc() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_lintsrc)).destapiclint as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_lintsrc>()).destapiclint as *const _ as usize },
         7usize,
         concat!(
             "Alignment of field: ",
@@ -771,7 +771,7 @@ fn bindgen_test_layout_mpc_oemtable() {
         concat!("Alignment of ", stringify!(mpc_oemtable))
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_oemtable)).signature as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_oemtable>()).signature as *const _ as usize },
         0usize,
         concat!(
             "Alignment of field: ",
@@ -781,7 +781,7 @@ fn bindgen_test_layout_mpc_oemtable() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_oemtable)).length as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_oemtable>()).length as *const _ as usize },
         4usize,
         concat!(
             "Alignment of field: ",
@@ -791,7 +791,7 @@ fn bindgen_test_layout_mpc_oemtable() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_oemtable)).rev as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_oemtable>()).rev as *const _ as usize },
         6usize,
         concat!(
             "Alignment of field: ",
@@ -801,7 +801,7 @@ fn bindgen_test_layout_mpc_oemtable() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_oemtable)).checksum as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_oemtable>()).checksum as *const _ as usize },
         7usize,
         concat!(
             "Alignment of field: ",
@@ -811,7 +811,7 @@ fn bindgen_test_layout_mpc_oemtable() {
         )
     );
     assert_eq!(
-        unsafe { &(*(0 as *const mpc_oemtable)).mpc as *const _ as usize },
+        unsafe { &(*std::ptr::null::<mpc_oemtable>()).mpc as *const _ as usize },
         8usize,
         concat!(
             "Alignment of field: ",

block_util/Cargo.toml

@@ -9,13 +9,13 @@ default = []
 io_uring = []
 
 [dependencies]
-io-uring = { git = "https://github.com/tokio-rs/io-uring.git", branch = "0.4" }
-libc = "0.2.74"
+io-uring = ">=0.4.0"
+libc = "0.2.81"
 log = "0.4.11"
 serde = ">=1.0.27"
 serde_derive = ">=1.0.27"
 serde_json = ">=1.0.9"
 virtio-bindings = { version = "0.1", features = ["virtio-v5_0_0"]}
-vm-memory = { version = "0.2.1", features = ["backend-mmap", "backend-atomic"] }
+vm-memory = { version = "0.4.0", features = ["backend-mmap", "backend-atomic"] }
 vm-virtio = { path = "../vm-virtio" }
 vmm-sys-util = ">=0.3.1"

block_util/src/lib.rs

@@ -14,13 +14,15 @@ extern crate log;
 extern crate serde_derive;
 
 #[cfg(feature = "io_uring")]
-use io_uring::{opcode, IoUring, Probe};
+use io_uring::Probe;
+use io_uring::{opcode, squeue, IoUring};
 use serde::ser::{Serialize, SerializeStruct, Serializer};
 use std::cmp;
 use std::io::{self, Read, Seek, SeekFrom, Write};
 use std::os::linux::fs::MetadataExt;
 #[cfg(feature = "io_uring")]
-use std::os::unix::io::{AsRawFd, RawFd};
+use std::os::unix::io::AsRawFd;
+use std::os::unix::io::RawFd;
 use std::path::PathBuf;
 use std::result;
 use virtio_bindings::bindings::virtio_blk::*;
@@ -50,6 +52,8 @@ pub enum Error {
     GetFileMetadata,
     /// The requested operation would cause a seek beyond disk end.
     InvalidOffset,
+    /// The requested operation does not support multiple descriptors.
+    TooManyDescriptors,
 }
 
 fn build_device_id(disk_path: &PathBuf) -> result::Result<String, Error> {
@@ -147,8 +151,7 @@ fn sector(mem: &GuestMemoryMmap, desc_addr: GuestAddress) -> result::Result<u64,
 pub struct Request {
     pub request_type: RequestType,
     pub sector: u64,
-    pub data_addr: GuestAddress,
-    pub data_len: u32,
+    pub data_descriptors: Vec<(GuestAddress, u32)>,
     pub status_addr: GuestAddress,
     pub writeback: bool,
 }
@@ -166,15 +169,13 @@ impl Request {
         let mut req = Request {
             request_type: request_type(&mem, avail_desc.addr)?,
             sector: sector(&mem, avail_desc.addr)?,
-            data_addr: GuestAddress(0),
-            data_len: 0,
+            data_descriptors: Vec::new(),
             status_addr: GuestAddress(0),
             writeback: true,
         };
 
-        let data_desc;
         let status_desc;
-        let desc = avail_desc
+        let mut desc = avail_desc
             .next_descriptor()
             .ok_or(Error::DescriptorChainTooShort)?;
 
@@ -185,23 +186,22 @@ impl Request {
                 return Err(Error::DescriptorChainTooShort);
             }
         } else {
-            data_desc = desc;
-            status_desc = data_desc
-                .next_descriptor()
-                .ok_or(Error::DescriptorChainTooShort)?;
-
-            if data_desc.is_write_only() && req.request_type == RequestType::Out {
-                return Err(Error::UnexpectedWriteOnlyDescriptor);
+            while desc.has_next() {
+                if desc.is_write_only() && req.request_type == RequestType::Out {
+                    return Err(Error::UnexpectedWriteOnlyDescriptor);
+                }
+                if !desc.is_write_only() && req.request_type == RequestType::In {
+                    return Err(Error::UnexpectedReadOnlyDescriptor);
+                }
+                if !desc.is_write_only() && req.request_type == RequestType::GetDeviceID {
+                    return Err(Error::UnexpectedReadOnlyDescriptor);
+                }
+                req.data_descriptors.push((desc.addr, desc.len));
+                desc = desc
+                    .next_descriptor()
+                    .ok_or(Error::DescriptorChainTooShort)?;
             }
-            if !data_desc.is_write_only() && req.request_type == RequestType::In {
-                return Err(Error::UnexpectedReadOnlyDescriptor);
-            }
-            if !data_desc.is_write_only() && req.request_type == RequestType::GetDeviceID {
-                return Err(Error::UnexpectedReadOnlyDescriptor);
-            }
-
-            req.data_addr = data_desc.addr;
-            req.data_len = data_desc.len;
+            status_desc = desc;
         }
 
         // The status MUST always be writable.
@@ -226,47 +226,48 @@ impl Request {
         mem: &GuestMemoryMmap,
         disk_id: &Vec<u8>,
     ) -> result::Result<u32, ExecuteError> {
-        let mut top: u64 = u64::from(self.data_len) / SECTOR_SIZE;
-        if u64::from(self.data_len) % SECTOR_SIZE != 0 {
-            top += 1;
-        }
-        top = top
-            .checked_add(self.sector)
-            .ok_or(ExecuteError::BadRequest(Error::InvalidOffset))?;
-        if top > disk_nsectors {
-            return Err(ExecuteError::BadRequest(Error::InvalidOffset));
-        }
-
         disk.seek(SeekFrom::Start(self.sector << SECTOR_SHIFT))
             .map_err(ExecuteError::Seek)?;
+        let mut len = 0;
+        for (data_addr, data_len) in &self.data_descriptors {
+            let mut top: u64 = u64::from(*data_len) / SECTOR_SIZE;
+            if u64::from(*data_len) % SECTOR_SIZE != 0 {
+                top += 1;
+            }
+            top = top
+                .checked_add(self.sector)
+                .ok_or(ExecuteError::BadRequest(Error::InvalidOffset))?;
+            if top > disk_nsectors {
+                return Err(ExecuteError::BadRequest(Error::InvalidOffset));
+            }
 
-        match self.request_type {
-            RequestType::In => {
-                mem.read_exact_from(self.data_addr, disk, self.data_len as usize)
-                    .map_err(ExecuteError::Read)?;
-                return Ok(self.data_len);
-            }
-            RequestType::Out => {
-                mem.write_all_to(self.data_addr, disk, self.data_len as usize)
-                    .map_err(ExecuteError::Write)?;
-                if !self.writeback {
-                    disk.flush().map_err(ExecuteError::Flush)?;
+            match self.request_type {
+                RequestType::In => {
+                    mem.read_exact_from(*data_addr, disk, *data_len as usize)
+                        .map_err(ExecuteError::Read)?;
+                    len += data_len;
                 }
-            }
-            RequestType::Flush => disk.flush().map_err(ExecuteError::Flush)?,
-            RequestType::GetDeviceID => {
-                if (self.data_len as usize) < disk_id.len() {
-                    return Err(ExecuteError::BadRequest(Error::InvalidOffset));
+                RequestType::Out => {
+                    mem.write_all_to(*data_addr, disk, *data_len as usize)
+                        .map_err(ExecuteError::Write)?;
+                    if !self.writeback {
+                        disk.flush().map_err(ExecuteError::Flush)?;
+                    }
                 }
-                mem.write_slice(&disk_id.as_slice(), self.data_addr)
-                    .map_err(ExecuteError::Write)?;
-            }
-            RequestType::Unsupported(t) => return Err(ExecuteError::Unsupported(t)),
-        };
-        Ok(0)
+                RequestType::Flush => disk.flush().map_err(ExecuteError::Flush)?,
+                RequestType::GetDeviceID => {
+                    if (*data_len as usize) < disk_id.len() {
+                        return Err(ExecuteError::BadRequest(Error::InvalidOffset));
+                    }
+                    mem.write_slice(&disk_id.as_slice(), *data_addr)
+                        .map_err(ExecuteError::Write)?;
+                }
+                RequestType::Unsupported(t) => return Err(ExecuteError::Unsupported(t)),
+            };
+        }
+        Ok(len)
     }
 
-    #[cfg(feature = "io_uring")]
     pub fn execute_io_uring(
         &self,
         mem: &GuestMemoryMmap,
@@ -276,31 +277,37 @@ impl Request {
         disk_id: &[u8],
         user_data: u64,
     ) -> result::Result<bool, ExecuteError> {
-        let data_len = self.data_len;
         let sector = self.sector;
-        let data_addr = self.data_addr;
         let request_type = self.request_type;
-
-        let mut top: u64 = u64::from(data_len) / SECTOR_SIZE;
-        if u64::from(data_len) % SECTOR_SIZE != 0 {
-            top += 1;
-        }
-        top = top
-            .checked_add(sector)
-            .ok_or(ExecuteError::BadRequest(Error::InvalidOffset))?;
-        if top > disk_nsectors {
-            return Err(ExecuteError::BadRequest(Error::InvalidOffset));
-        }
-
-        let buf = mem
-            .get_slice(data_addr, data_len as usize)
-            .map_err(ExecuteError::GetHostAddress)?
-            .as_ptr();
-        let offset = (sector as i64) << SECTOR_SHIFT;
+        let offset = (sector << SECTOR_SHIFT) as libc::off_t;
 
         let (submitter, sq, _) = io_uring.split();
         let mut avail_sq = sq.available();
 
+        let mut iovecs = Vec::new();
+        for (data_addr, data_len) in &self.data_descriptors {
+            let mut top: u64 = u64::from(*data_len) / SECTOR_SIZE;
+            if u64::from(*data_len) % SECTOR_SIZE != 0 {
+                top += 1;
+            }
+            top = top
+                .checked_add(sector)
+                .ok_or(ExecuteError::BadRequest(Error::InvalidOffset))?;
+            if top > disk_nsectors {
+                return Err(ExecuteError::BadRequest(Error::InvalidOffset));
+            }
+
+            let buf = mem
+                .get_slice(*data_addr, *data_len as usize)
+                .map_err(ExecuteError::GetHostAddress)?
+                .as_ptr();
+            let iovec = libc::iovec {
+                iov_base: buf as *mut libc::c_void,
+                iov_len: *data_len as libc::size_t,
+            };
+            iovecs.push(iovec);
+        }
+
         // Queue operations expected to be submitted.
         match request_type {
             RequestType::In => {
@@ -308,10 +315,15 @@ impl Request {
                 // relied on vm-memory to provide the buffer address.
                 let _ = unsafe {
                     avail_sq.push(
-                        opcode::Read::new(opcode::types::Fd(disk_image_fd), buf, data_len)
-                            .offset(offset)
-                            .build()
-                            .user_data(user_data),
+                        opcode::Readv::new(
+                            opcode::types::Fd(disk_image_fd),
+                            iovecs.as_ptr(),
+                            iovecs.len() as u32,
+                        )
+                        .offset(offset)
+                        .build()
+                        .flags(squeue::Flags::ASYNC)
+                        .user_data(user_data),
                     )
                 };
             }
@@ -320,10 +332,15 @@ impl Request {
                 // relied on vm-memory to provide the buffer address.
                 let _ = unsafe {
                     avail_sq.push(
-                        opcode::Write::new(opcode::types::Fd(disk_image_fd), buf, data_len)
-                            .offset(offset)
-                            .build()
-                            .user_data(user_data),
+                        opcode::Writev::new(
+                            opcode::types::Fd(disk_image_fd),
+                            iovecs.as_ptr(),
+                            iovecs.len() as u32,
+                        )
+                        .offset(offset)
+                        .build()
+                        .flags(squeue::Flags::ASYNC)
+                        .user_data(user_data),
                     )
                 };
             }
@@ -333,11 +350,17 @@ impl Request {
                     avail_sq.push(
                         opcode::Fsync::new(opcode::types::Fd(disk_image_fd))
                             .build()
+                            .flags(squeue::Flags::ASYNC)
                             .user_data(user_data),
                     )
                 };
             }
             RequestType::GetDeviceID => {
+                let (data_addr, data_len) = if self.data_descriptors.len() == 1 {
+                    (self.data_descriptors[0].0, self.data_descriptors[0].1)
+                } else {
+                    return Err(ExecuteError::BadRequest(Error::TooManyDescriptors));
+                };
                 if (data_len as usize) < disk_id.len() {
                     return Err(ExecuteError::BadRequest(Error::InvalidOffset));
                 }
@@ -543,3 +566,8 @@ pub fn block_io_uring_is_supported() -> bool {
 
     true
 }
+
+#[cfg(not(feature = "io_uring"))]
+pub fn block_io_uring_is_supported() -> bool {
+    false
+}

build.rs

@@ -3,20 +3,25 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 
+#[macro_use(crate_version)]
+extern crate clap;
+
 use std::process::Command;
 
 fn main() {
-    let git_out = Command::new("git")
-        .args(&["describe", "--dirty"])
-        .output()
-        .expect("Expect to get git describe output");
+    let mut version = "v".to_owned() + crate_version!();
+
+    if let Ok(git_out) = Command::new("git").args(&["describe", "--dirty"]).output() {
+        if git_out.status.success() {
+            if let Ok(git_out_str) = String::from_utf8(git_out.stdout) {
+                version = git_out_str;
+            }
+        }
+    }
 
     // This println!() has a special behavior, as it will set the environment
     // variable BUILT_VERSION, so that it can be reused from the binary.
     // Particularly, this is used from src/main.rs to display the exact
     // version.
-    println!(
-        "cargo:rustc-env=BUILT_VERSION={}",
-        String::from_utf8(git_out.stdout).unwrap()
-    );
+    println!("cargo:rustc-env=BUILT_VERSION={}", version);
 }

devices/Cargo.toml

@@ -8,14 +8,14 @@ anyhow = "1.0"
 bitflags = ">=1.2.1"
 byteorder = "1.3.4"
 epoll = ">=4.0.1"
-libc = "0.2.74"
+libc = "0.2.81"
 log = "0.4.11"
 serde = {version = ">=1.0.27", features = ["rc"] }
 serde_derive = ">=1.0.27"
 serde_json = ">=1.0.9"
 vm-device = { path = "../vm-device" }
 acpi_tables = { path = "../acpi_tables", optional = true }
-vm-memory = "0.2.1"
+vm-memory = "0.4.0"
 vm-migration = { path = "../vm-migration" }
 vmm-sys-util = ">=0.3.1"
 

devices/src/acpi.rs

@@ -7,8 +7,8 @@ use acpi_tables::{aml, aml::Aml};
 use std::sync::Arc;
 use std::time::Instant;
 use vm_device::interrupt::InterruptSourceGroup;
+use vm_device::BusDevice;
 use vmm_sys_util::eventfd::EventFd;
-use BusDevice;
 use HotPlugNotificationFlags;
 
 /// A device for handling ACPI shutdown and reboot

devices/src/gic.rs

@@ -8,7 +8,6 @@ use std::sync::Arc;
 use vm_device::interrupt::{
     InterruptIndex, InterruptManager, InterruptSourceGroup, MsiIrqGroupConfig,
 };
-use vm_migration::{Migratable, MigratableError, Pausable, Snapshot, Snapshottable, Transportable};
 
 type Result<T> = result::Result<T, Error>;
 
@@ -47,8 +46,7 @@ impl Gic {
 
 impl InterruptController for Gic {
     fn enable(&self) -> Result<()> {
-        &self
-            .interrupt_source_group
+        self.interrupt_source_group
             .enable()
             .map_err(Error::EnableInterrupt)?;
         Ok(())
@@ -64,22 +62,3 @@ impl InterruptController for Gic {
         Ok(())
     }
 }
-
-const GIC_SNAPSHOT_ID: &str = "gic";
-impl Snapshottable for Gic {
-    fn id(&self) -> String {
-        GIC_SNAPSHOT_ID.to_string()
-    }
-
-    fn snapshot(&self) -> std::result::Result<Snapshot, MigratableError> {
-        unimplemented!();
-    }
-
-    fn restore(&mut self, _snapshot: Snapshot) -> std::result::Result<(), MigratableError> {
-        unimplemented!();
-    }
-}
-
-impl Pausable for Gic {}
-impl Transportable for Gic {}
-impl Migratable for Gic {}

devices/src/interrupt_controller.rs

@@ -7,8 +7,6 @@ use std::result;
 
 #[derive(Debug)]
 pub enum Error {
-    /// Invalid destination mode.
-    InvalidDestinationMode,
     /// Invalid trigger mode.
     InvalidTriggerMode,
     /// Invalid delivery mode.

devices/src/ioapic.rs

@@ -10,7 +10,6 @@
 // See https://pdos.csail.mit.edu/6.828/2016/readings/ia32/ioapic.pdf for a specification.
 
 use super::interrupt_controller::{Error, InterruptController};
-use crate::BusDevice;
 use anyhow::anyhow;
 use byteorder::{ByteOrder, LittleEndian};
 use std::result;
@@ -19,6 +18,7 @@ use vm_device::interrupt::{
     InterruptIndex, InterruptManager, InterruptSourceConfig, InterruptSourceGroup,
     MsiIrqGroupConfig, MsiIrqSourceConfig,
 };
+use vm_device::BusDevice;
 use vm_memory::GuestAddress;
 use vm_migration::{
     Migratable, MigratableError, Pausable, Snapshot, SnapshotDataSection, Snapshottable,
@@ -67,10 +67,12 @@ fn trigger_mode(entry: RedirectionTableEntry) -> u8 {
 fn interrupt_mask(entry: RedirectionTableEntry) -> u8 {
     ((entry >> 16) & 0x1u64) as u8
 }
-fn destination_field_physical(entry: RedirectionTableEntry) -> u8 {
-    ((entry >> 56) & 0xfu64) as u8
-}
-fn destination_field_logical(entry: RedirectionTableEntry) -> u8 {
+fn destination_field(entry: RedirectionTableEntry) -> u8 {
+    // When the destination mode is physical, the destination field should only
+    // be defined through bits 56-59, as defined in the IOAPIC specification.
+    // But from the APIC specification, the APIC ID is always defined on 8 bits
+    // no matter which destination mode is selected. That's why we always
+    // retrieve the destination field based on bits 56-63.
     ((entry >> 56) & 0xffu64) as u8
 }
 fn set_delivery_status(entry: &mut RedirectionTableEntry, val: u8) {
@@ -100,12 +102,6 @@ const IOWIN_OFF: u8 = 0x10;
 const IOWIN_SCALE: u8 = 0x2;
 const REG_MAX_OFFSET: u8 = IOWIN_OFF + (NUM_IOAPIC_PINS as u8 * 2) - 1;
 
-#[repr(u8)]
-enum DestinationMode {
-    Physical = 0,
-    Logical = 1,
-}
-
 #[repr(u8)]
 enum TriggerMode {
     Edge = 0,
@@ -201,15 +197,13 @@ impl Ioapic {
             })
             .map_err(Error::CreateInterruptSourceGroup)?;
 
-        interrupt_source_group
-            .enable()
-            .map_err(Error::EnableInterrupt)?;
-
+        // The IOAPIC is created with entries already masked. The guest will be
+        // in charge of unmasking them if/when necessary.
         Ok(Ioapic {
             id,
             id_reg: 0,
             reg_sel: 0,
-            reg_entries: [0; NUM_IOAPIC_PINS],
+            reg_entries: [0x10000; NUM_IOAPIC_PINS],
             used_entries: [false; NUM_IOAPIC_PINS],
             apic_address,
             interrupt_source_group,
@@ -220,6 +214,16 @@ impl Ioapic {
         debug!("IOAPIC_W reg 0x{:x}, val 0x{:x}", self.reg_sel, val);
 
         match self.reg_sel as u8 {
+            IOAPIC_REG_VERSION => {
+                if val == 0 {
+                    // Windows writes zero here (see #1791)
+                } else {
+                    error!(
+                        "IOAPIC: invalid write to version register (0x{:x}): 0x{:x}",
+                        self.reg_sel, val
+                    );
+                }
+            }
             IOAPIC_REG_ID => self.id_reg = (val >> 24) & 0xf,
             IOWIN_OFF..=REG_MAX_OFFSET => {
                 let (index, is_high_bits) = decode_irq_from_selector(self.reg_sel as u8);
@@ -241,7 +245,10 @@ impl Ioapic {
                 // Store the information this IRQ is now being used.
                 self.used_entries[index] = true;
             }
-            _ => error!("IOAPIC: invalid write to register offset"),
+            _ => error!(
+                "IOAPIC: invalid write to register offset 0x{:x}",
+                self.reg_sel
+            ),
         }
     }
 
@@ -260,7 +267,10 @@ impl Ioapic {
                 }
             }
             _ => {
-                error!("IOAPIC: invalid read from register offset");
+                error!(
+                    "IOAPIC: invalid read from register offset 0x{:x}",
+                    self.reg_sel
+                );
                 0
             }
         }
@@ -296,11 +306,7 @@ impl Ioapic {
 
         // Validate Destination Mode value, and retrieve Destination ID
         let destination_mode = destination_mode(entry);
-        let destination_id: u8 = match destination_mode {
-            x if x == DestinationMode::Physical as u8 => destination_field_physical(entry),
-            x if x == DestinationMode::Logical as u8 => destination_field_logical(entry),
-            _ => return Err(Error::InvalidDestinationMode),
-        };
+        let destination_id = destination_field(entry);
 
         // When this bit is set, the message is directed to the processor with
         // the lowest interrupt priority among processors that can receive the
@@ -405,7 +411,7 @@ impl Snapshottable for Ioapic {
         self.id.clone()
     }
 
-    fn snapshot(&self) -> std::result::Result<Snapshot, MigratableError> {
+    fn snapshot(&mut self) -> std::result::Result<Snapshot, MigratableError> {
         let snapshot =
             serde_json::to_vec(&self.state()).map_err(|e| MigratableError::Snapshot(e.into()))?;
 

devices/src/legacy/cmos.rs

@@ -5,8 +5,7 @@
 use libc::{clock_gettime, gmtime_r, time_t, timespec, tm, CLOCK_REALTIME};
 use std::cmp::min;
 use std::mem;
-
-use crate::BusDevice;
+use vm_device::BusDevice;
 
 const INDEX_MASK: u8 = 0x7f;
 const INDEX_OFFSET: u64 = 0x0;

devices/src/legacy/fwdebug.rs

@@ -7,7 +7,7 @@
 // SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
 //
 
-use BusDevice;
+use vm_device::BusDevice;
 
 /// Provides firmware debug output via I/O port controls
 #[derive(Default)]

devices/src/legacy/i8042.rs

@@ -4,7 +4,7 @@
 
 use vmm_sys_util::eventfd::EventFd;
 
-use BusDevice;
+use vm_device::BusDevice;
 
 /// A i8042 PS/2 controller that emulates just enough to shutdown the machine.
 pub struct I8042Device {

devices/src/legacy/rtc_pl031.rs

@@ -12,16 +12,15 @@ use std::fmt;
 use std::sync::Arc;
 use std::time::Instant;
 use std::{io, result};
-
-use crate::BusDevice;
 use vm_device::interrupt::InterruptSourceGroup;
+use vm_device::BusDevice;
 
 // As you can see in https://static.docs.arm.com/ddi0224/c/real_time_clock_pl031_r1p3_technical_reference_manual_DDI0224C.pdf
 // at section 3.2 Summary of RTC registers, the total size occupied by this device is 0x000 -> 0xFFC + 4 = 0x1000.
 // From 0x0 to 0x1C we have following registers:
 const RTCDR: u64 = 0x0; // Data Register.
 const RTCMR: u64 = 0x4; // Match Register.
-const RTCLR: u64 = 0x8; // Load Regiser.
+const RTCLR: u64 = 0x8; // Load Register.
 const RTCCR: u64 = 0xc; // Control Register.
 const RTCIMSC: u64 = 0x10; // Interrupt Mask Set or Clear Register.
 const RTCRIS: u64 = 0x14; // Raw Interrupt Status.

devices/src/legacy/serial.rs

@@ -5,12 +5,12 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE-BSD-3-Clause file.
 
-use crate::BusDevice;
 use anyhow::anyhow;
 use std::collections::VecDeque;
 use std::sync::Arc;
 use std::{io, result};
 use vm_device::interrupt::InterruptSourceGroup;
+use vm_device::BusDevice;
 use vm_migration::{
     Migratable, MigratableError, Pausable, Snapshot, SnapshotDataSection, Snapshottable,
     Transportable,
@@ -289,7 +289,7 @@ impl Snapshottable for Serial {
         self.id.clone()
     }
 
-    fn snapshot(&self) -> std::result::Result<Snapshot, MigratableError> {
+    fn snapshot(&mut self) -> std::result::Result<Snapshot, MigratableError> {
         let snapshot =
             serde_json::to_vec(&self.state()).map_err(|e| MigratableError::Snapshot(e.into()))?;
 
@@ -394,13 +394,13 @@ mod tests {
             Box::new(serial_out.clone()),
         );
 
-        serial.write(0, DATA as u64, &['x' as u8, 'y' as u8]);
-        serial.write(0, DATA as u64, &['a' as u8]);
-        serial.write(0, DATA as u64, &['b' as u8]);
-        serial.write(0, DATA as u64, &['c' as u8]);
+        serial.write(0, DATA as u64, &[b'x', b'y']);
+        serial.write(0, DATA as u64, &[b'a']);
+        serial.write(0, DATA as u64, &[b'b']);
+        serial.write(0, DATA as u64, &[b'c']);
         assert_eq!(
             serial_out.buf.lock().unwrap().as_slice(),
-            &['a' as u8, 'b' as u8, 'c' as u8]
+            &[b'a', b'b', b'c']
         );
     }
 
@@ -411,16 +411,14 @@ mod tests {
         let mut serial = Serial::new_out(
             String::from(SERIAL_NAME),
             Arc::new(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap()))),
-            Box::new(serial_out.clone()),
+            Box::new(serial_out),
         );
 
         // write 1 to the interrupt event fd, so that read doesn't block in case the event fd
         // counter doesn't change (for 0 it blocks)
         assert!(intr_evt.write(1).is_ok());
         serial.write(0, IER as u64, &[IER_RECV_BIT]);
-        serial
-            .queue_input_bytes(&['a' as u8, 'b' as u8, 'c' as u8])
-            .unwrap();
+        serial.queue_input_bytes(&[b'a', b'b', b'c']).unwrap();
 
         assert_eq!(intr_evt.read().unwrap(), 2);
 
@@ -433,11 +431,11 @@ mod tests {
         serial.read(0, LSR as u64, &mut data[..]);
         assert_ne!(data[0] & LSR_DATA_BIT, 0);
         serial.read(0, DATA as u64, &mut data[..]);
-        assert_eq!(data[0], 'a' as u8);
+        assert_eq!(data[0], b'a');
         serial.read(0, DATA as u64, &mut data[..]);
-        assert_eq!(data[0], 'b' as u8);
+        assert_eq!(data[0], b'b');
         serial.read(0, DATA as u64, &mut data[..]);
-        assert_eq!(data[0], 'c' as u8);
+        assert_eq!(data[0], b'c');
 
         // check if reading from the largest u8 offset returns 0
         serial.read(0, 0xff, &mut data[..]);
@@ -456,7 +454,7 @@ mod tests {
         // counter doesn't change (for 0 it blocks)
         assert!(intr_evt.write(1).is_ok());
         serial.write(0, IER as u64, &[IER_THR_BIT]);
-        serial.write(0, DATA as u64, &['a' as u8]);
+        serial.write(0, DATA as u64, &[b'a']);
 
         assert_eq!(intr_evt.read().unwrap(), 2);
         let mut data = [0u8];
@@ -496,9 +494,9 @@ mod tests {
         );
 
         serial.write(0, MCR as u64, &[MCR_LOOP_BIT as u8]);
-        serial.write(0, DATA as u64, &['a' as u8]);
-        serial.write(0, DATA as u64, &['b' as u8]);
-        serial.write(0, DATA as u64, &['c' as u8]);
+        serial.write(0, DATA as u64, &[b'a']);
+        serial.write(0, DATA as u64, &[b'b']);
+        serial.write(0, DATA as u64, &[b'c']);
 
         let mut data = [0u8];
         serial.read(0, MSR as u64, &mut data[..]);
@@ -506,11 +504,11 @@ mod tests {
         serial.read(0, MCR as u64, &mut data[..]);
         assert_eq!(data[0], MCR_LOOP_BIT as u8);
         serial.read(0, DATA as u64, &mut data[..]);
-        assert_eq!(data[0], 'a' as u8);
+        assert_eq!(data[0], b'a');
         serial.read(0, DATA as u64, &mut data[..]);
-        assert_eq!(data[0], 'b' as u8);
+        assert_eq!(data[0], b'b');
         serial.read(0, DATA as u64, &mut data[..]);
-        assert_eq!(data[0], 'c' as u8);
+        assert_eq!(data[0], b'c');
     }
 
     #[test]

devices/src/lib.rs

@@ -25,12 +25,8 @@ extern crate vmm_sys_util;
 extern crate serde_derive;
 extern crate serde_json;
 
-use std::fs::File;
-use std::io;
-
 #[cfg(feature = "acpi")]
 mod acpi;
-mod bus;
 #[cfg(target_arch = "aarch64")]
 pub mod gic;
 pub mod interrupt_controller;
@@ -40,45 +36,6 @@ pub mod legacy;
 
 #[cfg(feature = "acpi")]
 pub use self::acpi::{AcpiGEDDevice, AcpiPMTimerDevice, AcpiShutdownDevice};
-pub use self::bus::{Bus, BusDevice, Error as BusError};
-
-pub type DeviceEventT = u16;
-
-/// The payload is used to handle events where the internal state of the VirtIO device
-/// needs to be changed.
-pub enum EpollHandlerPayload {
-    /// DrivePayload(disk_image)
-    DrivePayload(File),
-    /// Events that do not need a payload.
-    Empty,
-}
-
-type Result<T> = std::result::Result<T, Error>;
-
-pub trait EpollHandler: Send {
-    fn handle_event(
-        &mut self,
-        device_event: DeviceEventT,
-        event_flags: u32,
-        payload: EpollHandlerPayload,
-    ) -> Result<()>;
-}
-
-#[derive(Debug)]
-pub enum Error {
-    FailedReadingQueue {
-        event_type: &'static str,
-        underlying: io::Error,
-    },
-    FailedReadTap,
-    FailedSignalingUsedQueue(io::Error),
-    PayloadExpected,
-    UnknownEvent {
-        device: &'static str,
-        event: DeviceEventT,
-    },
-    IoError(io::Error),
-}
 
 bitflags! {
     pub struct HotPlugNotificationFlags: u8 {

docs/api.md

@@ -12,7 +12,7 @@
         * [Reboot a Virtual Machine](#reboot-a-virtual-machine)
         * [Shut a Virtual Machine Down](#shut-a-virtual-machine-down)
     + [Command Line Interface](#command-line-interface)
-    + [REST API and CLI Architecural Relationship](#rest-api-and-cli-architectural-relationship)
+    + [REST API and CLI Architectural Relationship](#rest-api-and-cli-architectural-relationship)
   * [Internal API](#internal-api)
     + [Goals and Design](#goals-and-design)
   * [End to End Example](#end-to-end-example)
@@ -88,7 +88,8 @@ Reboot the VM                      | `/vm.reboot`        | N/A
 Pause the VM                       | `/vm.pause`         | N/A                       | N/A                      | The VM is booted
 Resume the VM                      | `/vm.resume`        | N/A                       | N/A                      | The VM is paused
 Add/remove CPUs to/from the VM     | `/vm.resize`        | `/schemas/VmResize`       | N/A                      | The VM is booted
-Remove memory from the VM          | `/vm.resize`        | `/schemas/VmResize`       | N/A                      | The VM is booted
+Add/remove memory from the VM      | `/vm.resize`        | `/schemas/VmResize`       | N/A                      | The VM is booted
+Add/remove memory from a zone      | `/vm.resize-zone`   | `/schemas/VmResizeZone`   | N/A                      | The VM is booted
 Dump the VM information            | `/vm.info`          | N/A                       | `/schemas/VmInfo`        | The VM is created
 Add VFIO PCI device to the VM      | `/vm.add-device`    | `/schemas/VmAddDevice`    | `/schemas/PciDeviceInfo` | The VM is booted
 Add disk device to the VM          | `/vm.add-disk`      | `/schemas/DiskConfig`     | `/schemas/PciDeviceInfo` | The VM is booted

docs/arm64.md

@@ -16,20 +16,10 @@ sudo apt-get install libfdt-dev
 
 ## Build
 
-For Virtio devices, you can choose MMIO or PCI as transport option.
-
-### MMIO
+Using PCI devices requires GICv3-ITS for MSI messaging. GICv3-ITS is very common in modern servers.
 
 ```bash
-cargo build --no-default-features --features mmio,kvm
-```
-
-### PCI
-
-Using PCI devices requires GICv3-ITS for MSI messaging. GICv3-ITS is very common in modern servers, but your machine happen to be old ones with GICv2(M) (like Raspberry Pi 4) or GICv3 without ITS, MMIO can still work.
-
-```bash
-cargo build --no-default-features --features pci,kvm
+cargo build --no-default-features --features kvm
 ```
 
 ## Image
@@ -51,7 +41,7 @@ To build the development container:
 ./scripts/dev_cli.sh build-container
 ```
 
-To build Cloud-hypervisor in the container: (The default option for Virtio transport is MMIO.)
+To build Cloud-hypervisor in the container:
 
 ```bash
 ./scripts/dev_cli.sh build
@@ -62,7 +52,7 @@ To build Cloud-hypervisor in the container: (The default option for Virtio trans
 Assuming you have built Cloud-hypervisor with the development container, a VM can be started with command:
 
 ```bash
-sudo build/cargo_target/aarch64-unknown-linux-gnu/debug/cloud-hypervisor --kernel kernel.bin --disk path=rootfs.ext4 --cmdline "keep_bootcon console=hvc0 reboot=k panic=1 pci=off root=/dev/vda rw" --cpus boot=4 --memory size=512M --serial file=serial.log --log-file log.log -vvv
+sudo build/cargo_target/aarch64-unknown-linux-gnu/debug/cloud-hypervisor --kernel kernel.bin --disk path=rootfs.ext4 --cmdline "keep_bootcon console=hvc0 reboot=k panic=1 root=/dev/vda rw" --cpus boot=4 --memory size=512M --serial file=serial.log --log-file log.log -vvv
 ```
 
 If the build was done out of the container, replace the binary path with `target/debug/cloud-hypervisor`.

docs/device_model.md

@@ -75,12 +75,8 @@ feature is enabled by default.
 
 ## Virtio devices
 
-For all virtio devices listed below, both `virtio-mmio` and `virtio-pci`
-transport layers are supported, `virtio-pci` being the default.
-
-Both `virtio-mmio` and `virtio-pci` can be compiled out. `virtio-pci` is
-built-in by default, and enabled by default. If both transport layers were
-built at the same time, `virtio-pci` would be the default transport layer.
+For all virtio devices listed below, only `virtio-pci` transport layer is
+supported.
 
 ### virtio-block
 

docs/fs.md

@@ -56,7 +56,7 @@ Assuming you have `focal-server-cloudimg-amd64.raw` and `custom-vmlinux.bin` on
 ```bash
 ./cloud-hypervisor \
     --cpus 4 \
-    --memory "size=512,file=/dev/shm" \
+    --memory "size=512M,shared=on" \
     --disk path=focal-server-cloudimg-amd64.raw \
     --kernel custom-vmlinux.bin \
     --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \

docs/hotplug.md

@@ -63,7 +63,7 @@ As per adding CPUs to the guest, after a reboot the VM will be running with the
 
 ## Memory Hot Plug
 
-Extra memory can be added from a runing Cloud Hypervisor instance. This is controlled by two mechanisms:
+Extra memory can be added from a running Cloud Hypervisor instance. This is controlled by two mechanisms:
 
 1. Allocating some of the guest physical address space for hotplug memory.
 2. Making a HTTP API request to the VMM to ask for a new amount of RAM to be assigned to the VM. In the case of expanding the memory for the VM the new memory will be hotplugged into the running VM, if reducing the size of the memory then change will take effect after the next reboot.

docs/intel_sgx.md

@@ -8,7 +8,7 @@ the host kernel. The required Linux and KVM changes can be found in the
 [KVM SGX Tree](https://github.com/intel/kvm-sgx).
 
 Utilizing SGX in the guest requires a kernel/OS with SGX support, e.g. a kernel
-buit using the [SGX Linux Development Tree](https://github.com/jsakkine-intel/linux-sgx.git)
+built using the [SGX Linux Development Tree](https://github.com/jsakkine-intel/linux-sgx.git)
 or the [KVM SGX Tree](https://github.com/intel/kvm-sgx). Running KVM SGX as the
 guest kernel allows nested virtualization of SGX.
 

docs/iommu.md

@@ -86,7 +86,7 @@ virtual IOMMU:
 
 ```bash
 ./cloud-hypervisor \
-    --cpus 1 \
+    --cpus boot=1 \
     --memory size=512M \
     --disk path=focal-server-cloudimg-amd64.raw,iommu=on \
     --kernel custom-bzImage \
@@ -163,8 +163,8 @@ be consumed.
 
 ```bash
 ./cloud-hypervisor \
-    --cpus 1 \
-    --memory size=8G,file=/dev/hugepages \
+    --cpus boot=1 \
+    --memory size=8G,hugepages=on \
     --disk path=focal-server-cloudimg-amd64.raw \
     --kernel custom-bzImage \
     --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw hugepagesz=2M hugepages=2048" \
@@ -180,8 +180,8 @@ passing through is `0000:00:01.0`.
 
 ```bash
 ./cloud-hypervisor \
-    --cpus 1 \
-    --memory size=8G,file=/dev/hugepages \
+    --cpus boot=1 \
+    --memory size=8G,hugepages=on \
     --disk path=focal-server-cloudimg-amd64.raw \
     --kernel custom-bzImage \
     --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw kvm-intel.nested=1 vfio_iommu_type1.allow_unsafe_interrupts rw hugepagesz=2M hugepages=2048" \
@@ -200,8 +200,8 @@ Last thing is to start the L2 guest with the huge pages memory backend.
 
 ```bash
 ./cloud-hypervisor \
-    --cpus 1 \
-    --memory size=4G,file=/dev/hugepages \
+    --cpus boot=1 \
+    --memory size=4G,hugepages=on \
     --disk path=focal-server-cloudimg-amd64.raw \
     --kernel custom-bzImage \
     --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \

docs/logging.md

@@ -0,0 +1,43 @@
+# Logging
+
+The target audience of this document is both:
+
+* Developers who want to understand what log level to use and when,
+* Users who want to debug issues with running their workloads in Cloud Hypervisor
+
+## Control
+
+The number of `-v` parameters passed to the `cloud-hypervisor` binary will determine the log level. Currenly the default is log messages up to `WARN:` (`warn!`) are included by default. The `--log-file` allows the log to be sent to a location other than `stderr`.
+
+## Levels
+
+### `error!()`
+
+For immediate, unrecoverable errors where it does not make sense for the execution to continue as the behaviour of the VM is considerablely impacted.
+
+Cloud Hypervisor should exit shortly after reporting this error (with a non-zero exit code). Generally this should be used during initial construction of the VM state before the virtual CPUs have begun running code.
+
+A typical situation where this might occur is when the user is using command line options that conflict with each other or is trying to use a file that is not present on the filesystem.
+
+Users should react to this error by checking their initial VM configuration.
+
+### `warn!()`
+
+A serious problem has occured but the execution of the VM can continue although some functionality might be impacted.
+
+A typical example of where this level of message should be generated is during an API call request that cannot be fulfilled.
+
+The user should investigate the meaning of this warning and take steps to ensure the correct functionality.
+
+
+### `info!()`
+
+Use `-v` to enable.
+
+This level is for the benefit of developers. It should be used for sporadic and infrequent messages. The same message should not "spam" the logs. The VM should be usable when this level of debugging is enabled and trying to use `stdin/stdout` and the logs are going to `stderr`.
+
+### `debug!()`
+
+Use `-vv` to enable.
+
+For the most verbose of logging messages. It is acceptable to "spam" the log with repeated invocations of the same message. This level of logging would be combined with `--log-file`.

docs/memory.md

@@ -0,0 +1,451 @@
+# Memory
+
+Cloud-Hypervisor has many ways to expose memory to the guest VM. This document
+aims to explain what Cloud-Hypervisor is capable of and how it can be used to
+meet the needs of very different use cases.
+
+## Basic Parameters
+
+`MemoryConfig` or what is known as `--memory` from the CLI perspective is the
+easiest way to get started with Cloud-Hypervisor.
+
+```rust
+struct MemoryConfig {
+    size: u64,
+    mergeable: bool,
+    shared: bool,
+    hugepages: bool,
+    hotplug_method: HotplugMethod,
+    hotplug_size: Option<u64>,
+    hotplugged_size: Option<u64>,
+    zones: Option<Vec<MemoryZoneConfig>>,
+}
+```
+
+```
+--memory <memory>	Memory parameters "size=<guest_memory_size>,mergeable=on|off,shared=on|off,hugepages=on|off,hotplug_method=acpi|virtio-mem,hotplug_size=<hotpluggable_memory_size>,hotplugged_size=<hotplugged_memory_size>"
+```
+
+### `size`
+
+Size of the RAM in the guest VM.
+
+This option is mandatory when using the `--memory` parameter.
+
+Value is an unsigned integer of 64 bits.
+
+_Example_
+
+```
+--memory size=1G
+```
+
+### `mergeable`
+
+Specifies if the pages from the guest RAM must be marked as _mergeable_. In
+case this option is `true` or `on`, the pages will be marked with `madvise(2)`
+to let the host kernel know which pages are eligible for being merged by the
+KSM daemon.
+
+This option can be used when trying to reach a higher density of VMs running
+on a single host, as it will reduce the amount of memory consumed by each VM.
+
+By default this option is turned off.
+
+_Example_
+
+```
+--memory size=1G,mergeable=on
+```
+
+### `shared`
+
+Specifies if the memory must be `mmap(2)` with `MAP_SHARED` flag.
+
+By sharing a memory mapping, one can share the guest RAM with other processes
+running on the host. One can use this option when running vhost-user devices
+as part of the VM device model, as they will be driven by standalone daemons
+needing access to the guest RAM content.
+
+By default this option is turned off, which results in performing `mmap(2)`
+with `MAP_PRIVATE` flag.
+
+_Example_
+
+```
+--memory size=1G,shared=on
+```
+
+### `hugepages`
+
+Specifies if the memory must be `mmap(2)` with `MAP_HUGETLB` and `MAP_HUGE_2MB`
+flags. This performs a memory mapping relying on 2MiB pages instead of the
+default 4kiB pages.
+
+By using hugepages, one can improve the overall performance of the VM, assuming
+the guest will allocate hugepages as well. Another interesting use case is VFIO
+as it speeds up the VM's boot time since the amount of IOMMU mappings are
+reduced.
+
+By default this option is turned off.
+
+_Example_
+
+```
+--memory size=1G,hugepages=on
+```
+
+### `hotplug_method`
+
+Selects the way of adding and/or removing memory to/from a booted VM.
+
+Possible values are `acpi` and `virtio-mem`. Default value is `acpi`.
+
+_Example_
+
+```
+--memory size=1G,hotplug_method=acpi
+```
+
+### `hotplug_size`
+
+Amount of memory that can be dynamically added to the VM.
+
+Value is an unsigned integer of 64 bits. A value of 0 is invalid.
+
+_Example_
+
+```
+--memory size=1G,hotplug_size=1G
+```
+
+### `hotplugged_size`
+
+Amount of memory that will be dynamically added to the VM at boot. This option
+allows for starting a VM with a certain amount of memory that can be reduced
+during runtime.
+
+This is only valid when the `hotplug_method` is `virtio-mem` as it does not
+make sense for the `acpi` use case. When using ACPI, the memory can't be
+resized after it has been extended.
+
+This option is only valid when `hotplug_size` is specified, and its value can't
+exceed the value of `hotplug_size`.
+
+Value is an unsigned integer of 64 bits. A value of 0 is invalid.
+
+_Example_
+
+```
+--memory size=1G,hotplug_method=virtio-mem,hotplug_size=1G,hotplugged_size=512M
+```
+
+## Advanced Parameters
+
+`MemoryZoneConfig` or what is known as `--memory-zone` from the CLI perspective
+is a power user parameter. It allows for a full description of the guest RAM,
+describing how every memory region is backed and exposed to the guest.
+
+```rust
+struct MemoryZoneConfig {
+    id: String,
+    size: u64,
+    file: Option<PathBuf>,
+    shared: bool,
+    hugepages: bool,
+    host_numa_node: Option<u32>,
+    hotplug_size: Option<u64>,
+    hotplugged_size: Option<u64>,
+}
+```
+
+```
+--memory-zone <memory-zone>	User defined memory zone parameters "size=<guest_memory_region_size>,file=<backing_file>,shared=on|off,hugepages=on|off,host_numa_node=<node_id>,id=<zone_identifier>,hotplug_size=<hotpluggable_memory_size>,hotplugged_size=<hotplugged_memory_size>"
+```
+
+This parameter expects one or more occurences, allowing for a list of memory
+zones to be defined. It must be used with `--memory size=0`, clearly indicating
+that the memory will be described through advanced parameters.
+
+Each zone is given a list of options which we detail through the following
+sections.
+
+### `id`
+
+Memory zone identifier. This identifier must be unique, otherwise an error will
+be returned.
+
+This option is useful when referring to a memory zone previously created. In
+particular, the `--numa` parameter can associate a memory zone to a specific
+NUMA node based on the memory zone identifier.
+
+This option is mandatory when using the `--memory-zone` parameter.
+
+Value is a string.
+
+_Example_
+
+```
+--memory size=0
+--memory-zone id=mem0,size=1G
+```
+
+### `size`
+
+Size of the memory zone.
+
+This option is mandatory when using the `--memory-zone` parameter.
+
+Value is an unsigned integer of 64 bits.
+
+_Example_
+
+```
+--memory size=0
+--memory-zone id=mem0,size=1G
+```
+
+### `file`
+
+Path to the file backing the memory zone. This can be either a file or a
+directory. In case of a file, it will be opened and used as the backing file
+for the `mmap(2)` operation. In case of a directory, a temporary file with no
+hard link on the filesystem will be created. This file will be used as the
+backing file for the `mmap(2)` operation.
+
+This option can be particularly useful when trying to back a part of the guest
+RAM with a well known file. In the context of the snapshot/restore feature, and
+if the provided path is a file, the snapshot operation will not perform any
+copy of the guest RAM content for this specific memory zone since the user has
+access to it and it would duplicate data already stored on the current
+filesystem.
+
+Value is a string.
+
+_Example_
+
+```
+--memory size=0
+--memory-zone id=mem0,size=1G,file=/foo/bar
+```
+
+### `shared`
+
+Specifies if the memory zone must be `mmap(2)` with `MAP_SHARED` flag.
+
+By sharing a memory zone mapping, one can share part of the guest RAM with
+other processes running on the host. One can use this option when running
+vhost-user devices as part of the VM device model, as they will be driven
+by standalone daemons needing access to the guest RAM content.
+
+By default this option is turned off, which result in performing `mmap(2)`
+with `MAP_PRIVATE` flag.
+
+_Example_
+
+```
+--memory size=0
+--memory-zone id=mem0,size=1G,shared=on
+```
+
+### `hugepages`
+
+Specifies if the memory zone must be `mmap(2)` with `MAP_HUGETLB` and
+`MAP_HUGE_2MB` flags. This performs a memory zone mapping relying on 2MiB
+pages instead of the default 4kiB pages.
+
+By using hugepages, one can improve the overall performance of the VM, assuming
+the guest will allocate hugepages as well. Another interesting use case is VFIO
+as it speeds up the VM's boot time since the amount of IOMMU mappings are
+reduced.
+
+By default this option is turned off.
+
+_Example_
+
+```
+--memory size=0
+--memory-zone id=mem0,size=1G,hugepages=on
+```
+
+### `host_numa_node`
+
+Node identifier of a node present on the host. This option will let the user
+pick a specific NUMA node from which the memory must be allocated. After the
+memory zone is `mmap(2)`, the NUMA policy for this memory mapping will be
+applied through `mbind(2)`, relying on the provided node identifier. If the
+node does not exist on the host, the call to `mbind(2)` will fail.
+
+This option is useful when trying to back a VM memory with a specific type of
+memory from the host. Assuming a host has two types of memory, with one slower
+than the other, each related to a distinct NUMA node, one could create a VM
+with slower memory accesses by backing the entire guest RAM from the furthest
+NUMA node on the host.
+
+This option also gives the opportunity to create a VM with non uniform memory
+accesses as one could define a first memory zone backed by fast memory, and a
+second memory zone backed by slow memory.
+
+Value is an unsigned integer of 32 bits.
+
+_Example_
+
+```
+--memory size=0
+--memory-zone id=mem0,size=1G,host_numa_node=0
+```
+
+### `hotplug_size`
+
+Amount of memory that can be dynamically added to the memory zone. Since
+`virtio-mem` is the only way of resizing a memory zone, one must specify
+the `hotplug_method=virtio-mem` to the `--memory` parameter.
+
+Value is an unsigned integer of 64 bits. A value of 0 is invalid.
+
+_Example_
+
+```
+--memory size=0,hotplug_method=virtio-mem
+--memory-zone id=mem0,size=1G,hotplug_size=1G
+```
+
+### `hotplugged_size`
+
+Amount of memory that will be dynamically added to a memory zone at VM's boot.
+This option allows for starting a VM with a certain amount of memory that can
+be reduced during runtime.
+
+This is only valid when the `hotplug_method` is `virtio-mem` as it does not
+make sense for the `acpi` use case. When using ACPI, the memory can't be
+resized after it has been extended.
+
+This option is only valid when `hotplug_size` is specified, and its value can't
+exceed the value of `hotplug_size`.
+
+Value is an unsigned integer of 64 bits. A value of 0 is invalid.
+
+_Example_
+
+```
+--memory size=0,hotplug_method=virtio-mem
+--memory-zone id=mem0,size=1G,hotplug_size=1G,hotplugged_size=512M
+```
+
+## NUMA settings
+
+`NumaConfig` or what is known as `--numa` from the CLI perspective has been
+introduced to define a guest NUMA topology. It allows for a fine description
+about the CPUs and memory ranges associated with each NUMA node. Additionally
+it allows for specifying the distance between each NUMA node.
+
+```rust
+struct NumaConfig {
+    id: u32,
+    cpus: Option<Vec<u8>>,
+    distances: Option<Vec<NumaDistance>>,
+    memory_zones: Option<Vec<String>>,
+}
+```
+
+```
+--numa <numa>	Settings related to a given NUMA node "id=<node_id>,cpus=<cpus_id>,distances=<list_of_distances_to_destination_nodes>,memory_zones=<list_of_memory_zones>"
+```
+
+### `guest_numa_id`
+
+Node identifier of a guest NUMA node. This identifier must be unique, otherwise
+an error will be returned.
+
+This option is mandatory when using the `--numa` parameter.
+
+Value is an unsigned integer of 32 bits.
+
+_Example_
+
+```
+--numa guest_numa_id=0
+```
+
+### `cpus`
+
+List of virtual CPUs attached to the guest NUMA node identified by the
+`guest_numa_id` option. This allows for describing a list of CPUs which
+must be seen by the guest as belonging to the NUMA node `guest_numa_id`.
+
+One can use this option for a fine grained description of the NUMA topology
+regarding the CPUs associated with it, which might help the guest run more
+efficiently.
+
+Multiple values can be provided to define the list. Each value is an unsigned
+integer of 8 bits.
+
+For instance, if one needs to attach all CPUs from 0 to 4 to a specific node,
+the syntax using `-` will help define a contiguous range with `cpus=0-4`. The
+same example could also be described with `cpus=0:1:2:3:4`.
+
+A combination of both `-` and `:` separators is useful when one might need to
+describe a list containing all CPUs from 0 to 99 and the CPU 255, as it could
+simply be described with `cpus=0-99:255`.
+
+_Example_
+
+```
+--cpus boot=8
+--numa guest_numa_id=0,cpus=1-3:7
+--numa guest_numa_id=1,cpus=0:4-6
+```
+
+### `distances`
+
+List of distances between the current NUMA node referred by `guest_numa_id`
+and the destination NUMA nodes listed along with distances. This option let
+the user choose the distances between guest NUMA nodes. This is important to
+provide an accurate description of the way non uniform memory accesses will
+perform in the guest.
+
+One or more tuple of two values must be provided through this option. The first
+value is an unsigned integer of 32 bits as it represents the destination NUMA
+node. The second value is an unsigned integer of 8 bits as it represents the
+distance between the current NUMA node and the destination NUMA node. The two
+values are separated by `@` (`value1@value2`), meaning the destination NUMA
+node `value1` is located at a distance of `value2`. Each tuple is separated
+from the others with `:` separator.
+
+For instance, if one wants to define 3 NUMA nodes, with each node located at
+different distances, it can be described with the following example.
+
+_Example_
+
+```
+--numa guest_numa_id=0,distances=1@15:2@25
+--numa guest_numa_id=1,distances=0@15:2@20
+--numa guest_numa_id=2,distances=0@25:1@20
+```
+
+### `memory_zones`
+
+List of memory zones attached to the guest NUMA node identified by the
+`guest_numa_id` option. This allows for describing a list of memory ranges
+which must be seen by the guest as belonging to the NUMA node `guest_numa_id`.
+
+This option can be very useful and powerful when combined with `host_numa_node`
+option from `--memory-zone` parameter as it allows for creating a VM with non
+uniform memory accesses, and let the guest know about it. It allows for
+exposing memory zones through different NUMA nodes, which can help the guest
+workload run more efficiently.
+
+Multiple values can be provided to define the list. Each value is a string
+referring to an existing memory zone identifier. Values are separated from
+each other with the `:` separator.
+
+_Example_
+
+```
+--memory size=0
+--memory-zone id=mem0,size=1G
+--memory-zone id=mem1,size=1G
+--memory-zone id=mem2,size=1G
+--numa guest_numa_id=0,memory_zones=mem0:mem2
+--numa guest_numa_id=1,memory_zones=mem1
+```

docs/networking.md

@@ -1,6 +1,6 @@
 # How to use networking
 
-cloud-hypervisor can emulate one or more virtual network interfaces, represented at the hypervisor host by [tap devices](https://www.kernel.org/doc/Documentation/networking/tuntap.txt). This guide briefly describes, in a manual and distribution neutral way, how to setup and use networking with cloud-hypevisor.
+cloud-hypervisor can emulate one or more virtual network interfaces, represented at the hypervisor host by [tap devices](https://www.kernel.org/doc/Documentation/networking/tuntap.txt). This guide briefly describes, in a manual and distribution neutral way, how to setup and use networking with cloud-hypervisor.
 
 ## Multiple queue support for net devices ##
 
@@ -14,7 +14,7 @@ Note:
 
 - Currently, it does not support to use ethtool to change the combined queue numbers in guest.
 - Multiple queue is enabled for vhost-user-net backend in cloud-hypervisor, however, multiple thread is not added to handle mq, thus, the performance for vhost-user-net backend is not supposed to be improved. The multiple thread will be added for backend later.
-- Performance test for vhost-user-net will be covered once vhost-user-net backend has mulitple thread supported.
+- Performance test for vhost-user-net will be covered once vhost-user-net backend has multiple thread supported.
 - Performance test for virtio-net is done by comparing 2 queue pairs with 1 queue pairs, that to run 2 iperf3 sessions in the same test environments, throughput is improved about 37%.
 
 ## Start cloud-hypervisor with net devices

docs/profiling.md

@@ -0,0 +1,45 @@
+# Profiling
+
+`perf` can be used to profile the `cloud-hypervisor` binary but it is necessary to make some modifications to the the build in order to produce a binary that gives useful results.
+
+## Building a suitable binary
+
+Modify the `Cargo.toml` file to add `debug = 1` to the `[profile.release]` block. It should look like this:
+
+```
+[profile.release]
+lto = true
+debug = 1
+```
+
+This adds the symbol information to the release binary but does not otherwise affect the performance.
+
+The binary must also be built with frame pointers included so that the call graph can be captured by the profiler.
+
+```
+$ cargo clean && RUSTFLAGS='-C force-frame-pointers=y' cargo build --release
+```
+
+## Profiling
+
+`perf` may then be used in the usual manner:
+
+e.g.
+
+```
+$ perf record -g target/release/cloud-hypervisor \
+        --kernel ~/src/linux/vmlinux \
+        --pmem file=~/workloads/focal.raw \
+        --cpus boot=1 --memory size=1G \
+        --cmdline "root=/dev/pmem0p1 console=ttyS0" \
+        --serial tty --console off \
+        --api-socket=/tmp/api1
+```
+
+For analysing the samples:
+
+```
+$ perf report -g
+```
+
+If profiling with a network device attached either the TAP device must be already created and configured or the profiling must be done as root so that the TAP device can be created.

docs/snapshot_restore.md

@@ -54,7 +54,7 @@ drwxr-xr-x 47 foo bar       4096 Jul 22 11:47 ../
 In this particular example, we can observe that 2 memory region files were
 created. That is explained by the size of the guest RAM, which is 4GiB in this
 case. Because it exceeds 3GiB (which is where we can find a ~1GiB memory hole),
-Cloud-Hypervisor needs 2 distincts memory regions to be created. Each memory
+Cloud-Hypervisor needs 2 distinct memory regions to be created. Each memory
 region's content is stored through a dedicated file, which explains why we end
 up with 2 different files, the first one containing the guest RAM range 0-3GiB
 and the second one containing the guest RAM range 3-4GiB.
@@ -63,7 +63,7 @@ and the second one containing the guest RAM range 3-4GiB.
 and state. The configuration bits are used to create a similar virtual machine
 with the correct amount of CPUs, RAM, and other expected devices. The state
 bits are used to restore each component in the state it was left before the
-snapshot occured.
+snapshot occurred.
 
 ## Restore a Cloud-Hypervisor VM
 

docs/uefi.md

@@ -0,0 +1,75 @@
+# UEFI Boot
+
+Cloud Hypervisor supports UEFI boot through the utilization of the EDK II based UEFI firmware. 
+
+## Building UEFI Firmware
+
+To avoid any unnecessary issues, it is recommended to use Ubuntu 18.04 and its default toolset. Any other compatible Linux distribution is otherwise suitable, however it is suggested to use a temporary Docker container with Ubuntu 18.04 for a quick build on an existing Linux machine.
+
+The commands below will compile an OVMF firmware suitable for Cloud Hypervisor.
+
+```shell
+sudo apt-get update
+sudo apt-get install uuid-dev nasm iasl build-essential python3-distutils git
+
+git clone https://github.com/cloud-hypervisor/edk2 -b ch
+cd edk2
+. edksetup.sh
+git submodule update --init
+
+echo "ACTIVE_PLATFORM=OvmfPkg/OvmfCh.dsc" >> Conf/target.txt
+echo "TARGET_ARCH=X64" >> Conf/target.txt
+echo "TOOL_CHAIN_TAG=GCC5" >> Conf/target.txt
+
+make -C ./BaseTools
+build
+```
+
+After the successful build, the resulting firmware binaries are available under `Build/OvmfCh/DEBUG_GCC5/FV` underneath the edk2 checkout.
+
+## Using OVMF Binaries
+
+Any UEFI capable image can be booted using the Cloud Hypervisor specific firmware. Windows guests under Cloud Hypervisor only support UEFI boot, therefore OVMF is mandatory there.
+
+To make Cloud Hypervisor use UEFI boot, pass the `OVMF.fd` file path as an argument to the `--kernel` option. The firmware file will be opened in read only mode.
+
+The same firmware can be used with Cloud Hypervisor or with QEMU. This is particularly useful if using QEMU for the preparation phase.
+
+## Building UEFI Firmware with Compatibility Support Module (CSM)
+
+CSM is a module that allows to boot legacy operating systems using the OVMF firmware. OVMF can embed a CSM build of SeaBIOS. To build the SeaBIOS with CSM support, add `CONFIG_CSM=y` to `.config` before the build. The outcome `out/Csm16.bin` is to be moved into `OvmfPkg/Csm/Csm16/Csm16.bin` before OVMF is built. Then, the OVMF build will have to be passed the `-D CSM_ENABLE` option in order to generate a legacy aware UEFI firmware. At the current stage, all the necessary patches are included in the Cloud Hypervisor specific [SeaBIOS branch](https://github.com/cloud-hypervisor/seabios/tree/ch). Taking into account the previous instructions, the modified command sequence to compile an OVMF binary with CSM support is the following one:
+
+```shell
+sudo apt-get update
+sudo apt-get install uuid-dev nasm iasl build-essential python3-distutils git
+
+git checkout https://github.com/cloud-hypervisor/seabios -b ch
+cd seabios
+make menuconfig
+# Enable `CONFIG_CSM` and `CONFIG_QEMU_HARDWARE`
+make CONFIG_CSM=y CONFIG_QEMU_HARDWARE=y
+cd ..
+
+git clone https://github.com/cloud-hypervisor/edk2 -b ch
+cd edk2
+. edksetup.sh
+git submodule update --init
+cp ../seabios/out/Csm16.bin OvmfPkg/Csm/Csm16/
+
+echo "ACTIVE_PLATFORM=OvmfPkg/OvmfCh.dsc" >> Conf/target.txt
+echo "TARGET_ARCH=X64" >> Conf/target.txt
+echo "TOOL_CHAIN_TAG=GCC5" >> Conf/target.txt
+
+make -C ./BaseTools
+build
+
+```
+
+Please note, that the CSM support has currently only been tested with Linux guests. There are no plans to provide legacy support for other OSes (e.g. Windows).
+
+# Links
+
+- [OVMF wiki](https://github.com/tianocore/tianocore.github.io/wiki/OVMF) 
+- [Cloud Hypervisor specific tree](https://github.com/cloud-hypervisor/edk2/tree/ch)
+- [Redhat OVMF Status Report](https://access.redhat.com/sites/default/files/attachments/ovmf-whtepaper-031815.pdf)
+- [SeaBIOS Build Overview](https://www.seabios.org/Build_overview#Build_as_a_UEFI_Compatibility_Support_Module_.28CSM.29)

docs/vhost-user-blk-testing.md

@@ -73,7 +73,7 @@ VMs run in client mode. They connect to the socket created by the `dpdkvhostuser
 # From the test terminal. We need to create one vhost-user-blk device for the --disk.
 ./cloud-hypervisor \
         --cpus boot=4 \
-        --memory size=1024M,hugepages=on \
+        --memory size=1024M,hugepages=on,shared=true \
         --kernel linux/arch/x86/boot/compressed/vmlinux.bin \
         --cmdline "console=ttyS0 root=/dev/vda1 rw iommu=off" \
         --disk path=images/focal-server-cloudimg-amd64.raw vhost_user=true,socket=/var/tmp/vhost.1,num_queues=4,queue_size=128 \

docs/vhost-user-net-testing.md

@@ -76,7 +76,7 @@ VMs run in client mode. They connect to the socket created by the `dpdkvhostuser
 # From one terminal. We need to give the cloud-hypervisor binary the NET_ADMIN capabilities for it to set TAP interfaces up on the host.
 ./cloud-hypervisor \
         --cpus boot=2 \
-        --memory size=512M,hugepages=on   \
+        --memory size=512M,hugepages=on,shared=true \
         --kernel vmlinux \
         --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
         --disk path=focal-server-cloudimg-amd64.raw   \
@@ -85,7 +85,7 @@ VMs run in client mode. They connect to the socket created by the `dpdkvhostuser
 # From another terminal. We need to give the cloud-hypervisor binary the NET_ADMIN capabilities for it to set TAP interfaces up on the host.
 ./cloud-hypervisor \
         --cpus boot=2 \
-        --memory size=512M,hugepages=on   \
+        --memory size=512M,hugepages=on,shared=true \
         --kernel vmlinux \
         --cmdline "console=ttyS0 console=hvc0 root=/dev/vda1 rw" \
         --disk path=focal-server-cloudimg-amd64.raw   \

docs/windows.md

@@ -0,0 +1,337 @@
+# Windows Support
+
+Starting with the release version [0.10.0](https://github.com/cloud-hypervisor/cloud-hypervisor/releases/tag/v0.10.0), Cloud Hypervisor supports Windows guests.
+
+__Requirements__
+
+- Host with KVM enabled 
+- [UEFI](uefi.md) capable Windows guest image with Virtio drivers integrated
+
+Any modern Windows Server version is compatible. Cloud Hypervisor has been successfully tested with Windows Server 2019 and Windows Server Core 2004.
+
+At the current stage, only UEFI capable Windows images are supported. This implies the presence of the OVMF firmware during the Windows installation and in any subsequent usage. BIOS boot is not supported.
+
+The subsequent sections will tell, in detail, how to prepare an appropriate Windows image.
+
+## Image Preparation
+
+### Installation using the stock Windows ISO
+
+__Prerequisites__
+
+- QEMU, version >=5.0.0 is recommended.
+- Windows installation ISO. Obtained through MSDN, Visual Studio subscription, evaluation center, etc. 
+- [VirtIO driver ISO](https://fedorapeople.org/groups/virt/virtio-win/direct-downloads/stable-virtio/)
+- Suitable [OVMF](uefi.md) firmware 
+- With the suggested image size of 30G, there should be enough free disk space to hold the installation ISO and any other necessary files
+
+This step currently requires QEMU to install Windows onto the guest. QEMU is only used at the preparation stage, the resulting image is then fully functional with Cloud Hypervisor.
+
+Preparing several command parts as these will be used in the follow up sections as well.
+
+```shell
+IMG_FILE=windows-disk.qcow
+WIN_ISO_FILE=en_windows_server_version_2004_updated_may_2020_x64_dvd_1e7f1cfa.iso
+VIRTIO_ISO_FILE=virtio-win-0.1.185.iso
+OVMF_DIR=./FV
+```
+
+Create an empty image file, `qcow` or `raw` is supported.
+```shell
+qemu-img create -f qcow2 $IMG_FILE 30G
+```
+
+Begin the Windows installation process under QEMU
+```shell
+qemu-system-x86_64 \
+	-machine q35,accel=kvm \
+	-cpu host \
+	-m 4G \
+	-bios ./$OVMF_DIR/OVMF_CODE.fd \
+	-cdrom ./$WIN_ISO_FILE \
+	-drive file=./$VIRTIO_ISO_FILE,index=0,media=cdrom
+	-drive if=none,id=root,file=./$IMG_FILE \
+	-device virtio-blk-pci,drive=root,disable-legacy=on \
+	-device virtio-net-pci,netdev=mynet0,disable-legacy=on \
+	-netdev user,id=mynet0 \
+	-vga std
+```
+
+Before the installation can proceed, point the Windows installation program to the VirtIO disk and install the necessary storage controller drivers. After that, the attached hard drive will become visible and the actual installation can commence.
+
+After the installation has completed, proceed further to the configuration section. QEMU will be needed at least once more to enable the Windows Special Administration Console (SAC) and to possibly install extra device drivers.
+
+## Image Usage
+
+The basic command to boot a Windows image. The configuration section should be checked before executing it for the first time.
+
+```shell
+cloud-hypervisor \
+	--kernel ./$OVMF_DIR/OVMF.fd \
+	--disk path=./$IMG_FILE \
+	--cpus boot=1,kvm_hyperv=on \
+	--memory size=4G \
+	--serial tty \
+	--console off \
+	--net tap=
+```
+
+It is necessary to always:
+
+- Carry the OVMF firmware in the `--kernel` option
+- Add `kvm_hyperv=on` to the `--cpus` option
+
+In cases where the host processor supports address space > 39 bits, it might be necessary to limit the address space. It can be done by appending the option `max_phys_bits=X` to the `--cpus` parameter, where `X` is the number of bits to be supported. Windows was tested to support at least 39-bit address space.
+
+To daemonize the Cloud Hypervisor process, `nohup` can be used. Some STDIO redirections might need to be done. In a simple case it is sufficient to just redirect all the output to `/dev/null`.
+
+## Image Configuration
+
+### Device Drivers
+
+After the Windows installation has finished under QEMU, there might be still devices with no drivers installed. This might happen for example, when a device was not used during the installation. In particular it is important to ensure that the VirtIO network device is setup correctly because further steps for the configuration and the usage require network in most case.
+
+Boot once more under QEMU and use the [Device Manager](https://support.microsoft.com/en-in/help/4028443/windows-10-update-drivers), to ensure all the device drivers, and especially the network card, are installed correctly. Also, as Cloud Hypervisor can introduce new devices, it is advisable to repeat the procedure while booted under Cloud Hypervisor, when the RDP access to the image is functional.
+
+### Windows Special Administration Console (SAC) enablement
+
+SAC provides a text based console access to the Windows guest. As Cloud Hypervisor doesn't implement a VGA adaptor, SAC is an important instrument for the Windows guest management.
+
+Boot the Windows image under QEMU and execute the below commands to permanently enable SAC
+
+```cmd
+bcdedit /emssettings emsport:1 emsbaudrate:115200
+bcdedit /ems on
+bcdedit /bootems on
+```
+
+Once SAC is enabled, the image can be booted under Cloud Hypervisor. The SAC prompt will show up 
+
+<pre>
+Computer is booting, SAC started and initialized.                               
+                                                                                
+Use the "ch -?" command for information about using channels.                   
+Use the "?" command for general help.                                           
+                                                                                
+                                                                                
+SAC>
+</pre>
+
+To open a console on the guest, the command sequence below can be used
+<pre>
+SAC>cmd
+The Command Prompt session was successfully launched.
+SAC>
+EVENT:   A new channel has been created.  Use "ch -?" for channel help.
+Channel: Cmd0001
+SAC>ch -si 1
+</pre>
+
+See also the [links](#Links) section for a more extended SAC documentation.
+
+## Network
+
+This section illustrates the Windows specific corner points for the VM network configuration. For the extended networking guide, including bridging for multiple VMs, follow [networking.md](networking.md).
+
+### Basic Networking
+
+As the simplest option, using `--net tap=` in the Cloud Hypervisor command line will create a `vmtapX` device on the host with the default IPv4 adress `192.168.249.1`. After SAC becomes available, the guest configuration can be set with
+
+<pre>
+SAC>i 10 192.168.249.2 255.255.255.0 192.168.249.1
+</pre> 
+
+Where `10` is the device index as shown by the `i` command.
+
+### Guest Internet Connectivity
+
+Additional steps are necessary to provide the guest with internet access.
+
+- On the guest, add the DNS server either by using `netsh` or by opening `Network and Connectivity Center` and editing the adapter properties.
+- On the host, configure the traffic forwarding. Replace the `NET_DEV` with the name of your network device.
+```shell
+NET_DEV=wlp3s0
+sysctl -w net.ipv4.ip_forward=1
+iptables -t nat -A POSTROUTING -o $NET_DEV -j MASQUERADE
+```
+
+### Remote Desktop Protocol (RDP) enablement
+
+#### Using QEMU
+  - Execute `SystemPropertiesRemote`
+  - In the properties window, choose "Allow remote connections to this computer"
+  - Click "Select Users" and add some user to the allow list
+#### Using powershell
+```powershell
+Set-ItemProperty "HKLM:\SYSTEM\CurrentControlSet\Control\Terminal Server\" -Name "fDenyTSConnections" -Value 0
+Enable-NetFirewallRule -DisplayGroup "Remote Desktop"
+Add-LocalGroupMember -Group "Remote Desktop Users" -Member someuser
+```
+ 
+Administrators can always RDP, non administrator users have to be explicitly enabled. 
+
+Once the configuration is set, RDP clients can connect to `192.168.249.2`.
+
+### SSH
+
+#### Enable using powershell
+
+```powershell
+Add-WindowsCapability -Online -Name OpenSSH.Server~~~~0.0.1.0
+Start-Service sshd
+Set-Service -Name sshd -StartupType ‘Automatic’
+```
+
+This allows for SSH login from a remote machine, for example through the `administrator` user: `ssh administrator@192.168.249.2`. For a more detailed OpenSSH guide, please follow the MSDN article from the [links](#links) section.
+
+## Debugging
+
+The Windows guest debugging process relies heavily on QEMU and [socat](http://www.dest-unreach.org/socat/). The procedure requires two Windows VMs:
+
+- A debugger VM running under QEMU.
+- A debuggee, a Windows VM that has been created in the previous steps, running under Cloud Hypervisor or QEMU.
+
+The connection between both guests happens over TCP, whereby on the guest side it is automatically translated to a COM port. Because the VMs are connected through TCP, the debugging infrastructure can be distributed over the network. The serial port, while slowly transferring data, is common enough to support a wide range of cases and tools.
+
+In this excercise, [WinDbg](https://docs.microsoft.com/en-us/windows-hardware/drivers/debugger/) is used. Any other debugger of choice with the ability to use serial connection can be used instead. 
+
+### Debugger and Debuggee
+
+#### WinDbg VM
+
+For simplicity, the debugger VM is supposed to be only running under QEMU. It will require VGA and doesn't neccessarily depend on UEFI. As an OS, it can carry any supported Windows OS where the debugger of choice can be installed. The simplest way is to follow the image preparation instructions from the previous chapter, but avoid using the OVMF firmware. It is also not required to use VirtIO drivers, whereby it might be useful in some case. Though, while creating the image file for the debugger VM, be sure to choose a sufficient disk size that counts in the need to save the corresponding debug symbols and sources.
+
+To create the debugger Windows VM, the following command can be used:
+
+```shell
+qemu-system-x86_64 \
+	-machine q35,accel=kvm \
+	-cpu host \
+	-smp 1 \
+	-m 4G \
+	-cdrom ./$WIN_ISO_FILE \
+	-drive file=./$VIRTIO_ISO_FILE,index=0,media=cdrom
+	-drive if=none,id=root,file=./windbg-disk.qcow \
+	-device virtio-blk-pci,drive=root,disable-legacy=on \
+	-device virtio-net-pci,netdev=mynet0,disable-legacy=on \
+	-netdev user,id=mynet0,net=192.168.178.0/24,host=192.168.178.1,dhcpstart=192.168.178.64,hostname=windbg-host \
+	-vga std
+```
+
+A non server Windows OS like Windows 10 can be used to carry the debugging tools in the debugger VM.
+
+#### Debuggee VM
+
+The debuggee VM is the one that we've learned to configure and run in the first section. There might be various reasons to debug. For example, there could be an issue in the Windows guest with an emulated device or an included driver. Or, we might want to develop a custom feature like a kernel driver to be available in the guest.
+
+Note, that there are several ways to debug Windows, not all of them need to be enabled at the same time. For example, if developing a kernel module, the only useful options would be to configure for the serial debugging and enable the kernel debug. In that case, any crash or misbehavior in the boot loader or kernel would be ignored. The commands below must be run as administrator on the debuggee guest VM.
+
+##### Turn On Serial Debugging
+
+This will configure the debugging to be enabled and instruct to use the serial port for it.
+
+```cmd
+bcdedit /dbgsettings serial debugport:1 baudrate:115200
+```
+
+##### Turn On Kernel Debuging
+
+```cmd
+bcdedit /debug on
+```
+
+##### Turn On Boot Loader Debug
+
+```cmd
+bcdedit /bootdebug on
+```
+
+##### Turn on boot manager debug 
+
+```cmd
+bcdedit /set {bootmgr} bootdebug on
+```
+
+##### Disable Recovery Screen On Boot Failure
+
+There could be a situation, where a crash is debugged. In such cases, the guest could be left in an inconsistent state. The default Windows behavior would be to boot into the recovery screen, however in some cases it might be not desired. To make Windows ignore failures and always proceed to booting the OS, use the command below:
+
+```cmd
+bcdedit /set {default} bootstatuspolicy ignoreallfailures
+```
+
+### Debugging Process
+
+#### Invoke the WinDbg VM
+
+```shell
+qemu-system-x86_64 \
+	-machine q35,accel=kvm \
+	-cpu host \
+	-smp 1 \
+	-m 4G \
+	-drive if=none,id=root,file=./windbg-disk.qcow \
+	-device virtio-blk-pci,drive=root,disable-legacy=on \
+	-serial tcp::4445,server,nowait \
+	-device virtio-net-pci,netdev=mynet0,disable-legacy=on \
+	-netdev user,id=mynet0,net=192.168.178.0/24,host=192.168.178.1,dhcpstart=192.168.178.64,hostname=windbg-host \
+	-vga std
+```
+
+Note, this VM has the networking enabled. It is needed, because symbols and sources might need to be fetched from a network location.
+
+Also, notice the `-serial` parameter - that's what does the magic on exposing the serial port to the guest while connecting the debugger VM with a client VM through the network. SAC/EMS needs to be disabled in the debugger VM, as otherwise the COM device might be blocked.
+
+Hereafter, WinDbg can be started using a command below:
+
+```cmd
+set _NT_DEBUG_PORT=com1
+set _NT_DEBUG_BAUD_RATE=115200
+
+windbg -v -d -k
+```
+
+Once started, WinDbg will wait for an incoming connection which is going to be initialized by the debuggee VM started in the next section.
+
+#### Invoke the Debuggee VM
+
+##### Under QEMU
+
+Essentially it would be the command like depicted in the guest preparation sections, with a few modifications:
+```shell
+qemu-system-x86_64 \
+	-machine q35,accel=kvm \
+	-cpu host \
+	-m 4G \
+	-bios ./$OVMF_DIR/OVMF_CODE.fd \
+	-cdrom ./$WIN_ISO_FILE \
+	-drive file=./$VIRTIO_ISO_FILE,index=0,media=cdrom
+	-drive if=none,id=root,file=./$IMG_FILE \
+	-device virtio-blk-pci,drive=root,disable-legacy=on \
+	-device virtio-net-pci,netdev=mynet0,disable-legacy=on \
+	-netdev user,id=mynet0 \
+	-serial tcp:127.0.0.1:4445 \
+	-vga std
+```
+
+It is to see, that `-serial` parameter is used here, to establish the connection with the debugger VM.
+
+To disable HPET, attach `--no-hpet`. To enable hypervisor reference timer, use `-cpu host,hv-time`. These and other options can be used to achieve better [Hyper-V compatibility](https://archive.fosdem.org/2019/schedule/event/vai_enlightening_kvm/attachments/slides/2860/export/events/attachments/vai_enlightening_kvm/slides/2860/vkuznets_fosdem2019_enlightening_kvm.pdf).
+
+##### Cloud Hypervisor
+
+The `socat` tool is used to establish the QEMU compatible behavior. Here as well, the Cloud Hypervisor command used to run the Windows guest is to be used. Put the command into a shell script:
+
+`socat SYSTEM:"./ch-script",openpty,raw,echo=0 TCP:localhost:4445`
+
+The reason to pack the command into the shell script is that the command might contain a comma. When using SYSTEM, the shell command can't contain `,` or `!!`.
+
+## Links
+
+- [Fedora VirtIO guide for Windows](https://docs.fedoraproject.org/en-US/quick-docs/creating-windows-virtual-machines-using-virtio-drivers/)
+- [VirtIO driver binaries](https://fedorapeople.org/groups/virt/virtio-win/direct-downloads/stable-virtio/)
+- [VirtIO driver sources](https://github.com/virtio-win/kvm-guest-drivers-windows)
+- [Emergency Management Services](https://docs.microsoft.com/en-us/previous-versions/windows/it-pro/windows-server-2003/cc787940(v=ws.10))
+- [OpenSSH server/client configuration](https://docs.microsoft.com/en-us/windows-server/administration/openssh/openssh_install_firstuse)
+- [Windows guest debugging under KVM](https://www.linux-kvm.org/page/WindowsGuestDrivers/GuestDebugging)
+- ["ENLIGHTENING" KVM](https://archive.fosdem.org/2019/schedule/event/vai_enlightening_kvm/attachments/slides/2860/export/events/attachments/vai_enlightening_kvm/slides/2860/vkuznets_fosdem2019_enlightening_kvm.pdf)

fuzz/Cargo.toml

@@ -1,4 +1,3 @@
-
 [package]
 name = "cloud-hypervisor-fuzz"
 version = "0.0.0"
@@ -13,17 +12,15 @@ cargo-fuzz = true
 libc = "0.2.72"
 libfuzzer-sys = "0.3"
 qcow = { path = "../qcow" }
+seccomp = { git = "https://github.com/firecracker-microvm/firecracker", tag = "v0.22.0" }
 virtio-devices = { path = "../virtio-devices" }
 vmm-sys-util = ">=0.3.1"
 vm-virtio = { path = "../vm-virtio" }
-vm-memory = "0.2.1"
+vm-memory = "0.4.0"
 
 [dependencies.cloud-hypervisor]
 path = ".."
 
-[patch.crates-io]
-vm-memory = { git = "https://github.com/cloud-hypervisor/vm-memory", branch = "ch" }
-
 # Prevent this from interfering with workspaces
 [workspace]
 members = ["."]

fuzz/fuzz_targets/block.rs

@@ -16,6 +16,7 @@ use virtio_devices::{Block, VirtioDevice, VirtioInterrupt, VirtioInterruptType};
 use vm_memory::{Bytes, GuestAddress, GuestMemoryAtomic, GuestMemoryMmap};
 use vm_virtio::Queue;
 use vmm_sys_util::eventfd::EventFd;
+use seccomp::SeccompAction;
 
 const MEM_SIZE: u64 = 256 * 1024 * 1024;
 const DESC_SIZE: u64 = 16; // Bytes in one virtio descriptor.
@@ -92,6 +93,7 @@ fuzz_target!(|bytes| {
         false,
         2,
         256,
+        SeccompAction::Allow,
     )
     .unwrap();
 

hypervisor/Cargo.toml

@@ -1,25 +1,40 @@
 [package]
 name = "hypervisor"
 version = "0.1.0"
-authors = ["Muminul Islam <muislam@microsoft.com>"]
+authors = ["Microsoft Authors"]
 edition = "2018"
+license = "Apache-2.0 OR BSD-3-Clause"
 
 [features]
 kvm = []
+mshv = []
 
 [dependencies]
 anyhow = "1.0"
+epoll = ">=4.0.1"
 thiserror = "1.0"
-libc = "0.2.74"
+libc = "0.2.81"
 log = "0.4.11"
 kvm-ioctls = { git = "https://github.com/cloud-hypervisor/kvm-ioctls", branch = "ch" }
 kvm-bindings = { git = "https://github.com/cloud-hypervisor/kvm-bindings", branch = "ch", features = ["with-serde", "fam-wrappers"] }
+
+mshv-bindings = {git = "https://github.com/cloud-hypervisor/mshv", branch = "master", features = ["with-serde", "fam-wrappers"] }
+mshv-ioctls = { git = "https://github.com/cloud-hypervisor/mshv", branch = "master" }
+
 serde = {version = ">=1.0.27", features = ["rc"] }
 serde_derive = ">=1.0.27"
 serde_json = ">=1.0.9"
-vm-memory = { version = "0.2.0", features = ["backend-mmap", "backend-atomic"] }
+vm-memory = { version = "0.4.0", features = ["backend-mmap", "backend-atomic"] }
 vmm-sys-util = { version = ">=0.5.0", features = ["with-serde"] }
 
 [dependencies.linux-loader]
 git = "https://github.com/rust-vmm/linux-loader"
 features = ["elf", "bzimage"]
+
+[target.'cfg(target_arch = "x86_64")'.dependencies.iced-x86]
+version = "1.9.1"
+default-features = false
+features = ["std", "decoder", "op_code_info", "instr_info", "fast_fmt"]
+
+[dev-dependencies]
+env_logger = "0.8.2"

hypervisor/src/arch/emulator/mod.rs

@@ -0,0 +1,148 @@
+//
+// Copyright © 2020 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+
+extern crate thiserror;
+
+use core::fmt::Debug;
+use std::fmt::{self, Display};
+use thiserror::Error;
+
+#[derive(Clone, Copy, Error, Debug)]
+pub struct Exception<T: Debug> {
+    vector: T,
+    ip: u64,
+    error: Option<u32>,
+    payload: Option<u64>,
+}
+
+impl<T: Debug> Display for Exception<T> {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        write!(f, "Exception {:?} at IP {:#x}", self.vector, self.ip)
+    }
+}
+
+#[derive(Error, Debug)]
+pub enum PlatformError {
+    #[error("Invalid address: {0}")]
+    InvalidAddress(#[source] anyhow::Error),
+
+    #[error("Invalid register: {0}")]
+    InvalidRegister(#[source] anyhow::Error),
+
+    #[error("Invalid state: {0}")]
+    InvalidState(#[source] anyhow::Error),
+
+    #[error("Memory read failure: {0}")]
+    MemoryReadFailure(#[source] anyhow::Error),
+
+    #[error("Memory write failure: {0}")]
+    MemoryWriteFailure(#[source] anyhow::Error),
+
+    #[error("Get CPU state failure: {0}")]
+    GetCpuStateFailure(#[source] anyhow::Error),
+
+    #[error("Set CPU state failure: {0}")]
+    SetCpuStateFailure(#[source] anyhow::Error),
+
+    #[error("Unmapped virtual address: {0}")]
+    UnmappedGVA(#[source] anyhow::Error),
+
+    #[error("Unsupported CPU Mode: {0}")]
+    UnsupportedCpuMode(#[source] anyhow::Error),
+
+    #[error("Invalid instruction operand: {0}")]
+    InvalidOperand(#[source] anyhow::Error),
+}
+
+#[derive(Error, Debug)]
+pub enum EmulationError<T: Debug> {
+    #[error("Unsupported instruction: {0}")]
+    UnsupportedInstruction(#[source] anyhow::Error),
+
+    #[error("Unsupported memory size: {0}")]
+    UnsupportedMemorySize(#[source] anyhow::Error),
+
+    #[error("Invalid operand: {0}")]
+    InvalidOperand(#[source] anyhow::Error),
+
+    #[error("Wrong number of operands: {0}")]
+    WrongNumberOperands(#[source] anyhow::Error),
+
+    #[error("Instruction Exception: {0}")]
+    InstructionException(Exception<T>),
+
+    #[error("Instruction fetching error: {0}")]
+    InstructionFetchingError(#[source] anyhow::Error),
+
+    #[error("Platform emulation error: {0}")]
+    PlatformEmulationError(PlatformError),
+
+    #[error(transparent)]
+    EmulationError(#[from] anyhow::Error),
+}
+
+/// The PlatformEmulator trait emulates a guest platform.
+/// It's mostly a guest resources (memory and CPU state) getter and setter.
+///
+/// A CpuState is an architecture specific type, representing a CPU state.
+/// The emulator and its instruction handlers modify a given CPU state and
+/// eventually ask the platform to commit it back through `set_cpu_state`.
+pub trait PlatformEmulator: Send + Sync {
+    type CpuState: Clone;
+
+    /// Read guest memory into a u8 slice.
+    ///
+    /// # Arguments
+    ///
+    /// * `gva` - Guest virtual address to read from.
+    /// * `data` - Data slice to read into.
+    ///
+    fn read_memory(&self, gva: u64, data: &mut [u8]) -> Result<(), PlatformError>;
+
+    /// Write a u8 slice into guest memory.
+    ///
+    /// # Arguments
+    ///
+    /// * `gva` - Guest virtual address to write into.
+    /// * `data` - Data slice to be written.
+    ///
+    fn write_memory(&mut self, gva: u64, data: &[u8]) -> Result<(), PlatformError>;
+
+    /// Get a CPU state from the guest.
+    ///
+    /// # Arguments
+    ///
+    /// * `cpu_id` - Logical CPU ID.
+    ///
+    fn cpu_state(&self, cpu_id: usize) -> Result<Self::CpuState, PlatformError>;
+
+    /// Set a guest CPU state.
+    ///
+    /// # Arguments
+    ///
+    /// * `cpu_id` - Logical CPU ID.
+    /// * `state` - State to set the CPU into.
+    ///
+    fn set_cpu_state(&self, cpu_id: usize, state: Self::CpuState) -> Result<(), PlatformError>;
+
+    /// Translate a guest virtual address into a physical one
+    ///
+    /// # Arguments
+    ///
+    /// * `gva` - Guest virtual address to translate.
+    ///
+    fn gva_to_gpa(&self, gva: u64) -> Result<u64, PlatformError>;
+
+    /// Fetch instruction bytes from memory.
+    ///
+    /// # Arguments
+    ///
+    /// * `ip` - Instruction pointer virtual address to start fetching instructions from.
+    ///
+    fn fetch(&self, ip: u64, instruction_bytes: &mut [u8]) -> Result<(), PlatformError>;
+}
+
+pub type EmulationResult<S, E> = std::result::Result<S, EmulationError<E>>;

hypervisor/src/arch/mod.rs

@@ -11,5 +11,7 @@
 // Copyright © 2020, Microsoft Corporation
 //
 
+pub mod emulator;
+
 #[cfg(target_arch = "x86_64")]
 pub mod x86;

hypervisor/src/arch/x86/emulator/instructions/cmp.rs

@@ -0,0 +1,355 @@
+//
+// Copyright © 2020 Microsoft
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#![allow(non_camel_case_types)]
+
+//
+// CMP-Compare Two Operands
+//
+
+extern crate iced_x86;
+
+use crate::arch::emulator::{EmulationError, PlatformEmulator};
+use crate::arch::x86::emulator::instructions::*;
+use crate::arch::x86::regs::*;
+use crate::arch::x86::Exception;
+
+// CMP affects OF, SF, ZF, AF, PF and CF
+const FLAGS_MASK: u64 = CF | PF | AF | ZF | SF | OF;
+
+// TODO: Switch to inline asm when that's stable. Executing CMP (or any arthimetic instructions)
+// natively and extracting RFLAGS will be much faster and make the code simpler.
+fn calc_rflags_cpazso(op0: u64, op1: u64, op_size: usize) -> u64 {
+    let op_bits = op_size * 8;
+    let msb_shift = op_bits - 1;
+    // CMP is the same as SUB.
+    let result = op0.wrapping_sub(op1);
+
+    // Carry-out vector for SUB.
+    let cout = (!op0 & op1) | ((!op0 ^ op1) & result);
+
+    let cf = ((cout >> msb_shift) & 0x1) << CF_SHIFT;
+
+    // PF only needs the least significant byte. XOR its higher 4 bits with its lower 4 bits then
+    // use the value directly.
+    let pf = ((0x9669 >> ((result ^ (result >> 4)) & 0xf)) & 0x1) << PF_SHIFT;
+
+    // AF cares about the lowest 4 bits (nibble). msb_shift is 3 in this case.
+    let af = ((cout >> 3) & 0x1) << AF_SHIFT;
+
+    let zf = if result & (!0u64 >> (63 - msb_shift)) == 0 {
+        1
+    } else {
+        0
+    } << ZF_SHIFT;
+
+    let sf = ((result >> msb_shift) & 0x1) << SF_SHIFT;
+
+    // Overflow happens when two operands have the same sign but the result has a different sign.
+    let of = ((((op0 ^ op1) & (op0 ^ result)) >> msb_shift) & 0x1) << OF_SHIFT;
+
+    cf | pf | af | zf | sf | of
+}
+
+macro_rules! cmp_rm_r {
+    ($bound:ty) => {
+        fn emulate(
+            &self,
+            insn: &Instruction,
+            state: &mut T,
+            platform: &mut dyn PlatformEmulator<CpuState = T>,
+        ) -> Result<(), EmulationError<Exception>> {
+            let op0_value = get_op(&insn, 0, std::mem::size_of::<$bound>(), state, platform)
+                .map_err(EmulationError::PlatformEmulationError)?;
+            let op1_value = get_op(&insn, 1, std::mem::size_of::<$bound>(), state, platform)
+                .map_err(EmulationError::PlatformEmulationError)?;
+
+            let cpazso = calc_rflags_cpazso(op0_value, op1_value, std::mem::size_of::<$bound>());
+
+            state.set_flags((state.flags() & !FLAGS_MASK) | cpazso);
+
+            state.set_ip(insn.ip());
+
+            Ok(())
+        }
+    };
+}
+
+macro_rules! cmp_r_rm {
+    ($bound:ty) => {
+        fn emulate(
+            &self,
+            insn: &Instruction,
+            state: &mut T,
+            platform: &mut dyn PlatformEmulator<CpuState = T>,
+        ) -> Result<(), EmulationError<Exception>> {
+            let op0_value = get_op(&insn, 0, std::mem::size_of::<$bound>(), state, platform)
+                .map_err(EmulationError::PlatformEmulationError)?;
+            let op1_value = get_op(&insn, 1, std::mem::size_of::<$bound>(), state, platform)
+                .map_err(EmulationError::PlatformEmulationError)?;
+
+            let cpazso = calc_rflags_cpazso(op0_value, op1_value, std::mem::size_of::<$bound>());
+
+            state.set_flags((state.flags() & !FLAGS_MASK) | cpazso);
+
+            state.set_ip(insn.ip());
+
+            Ok(())
+        }
+    };
+}
+
+macro_rules! cmp_rm_imm {
+    ($imm:ty, $bound:ty) => {
+        fn emulate(
+            &self,
+            insn: &Instruction,
+            state: &mut T,
+            platform: &mut dyn PlatformEmulator<CpuState = T>,
+        ) -> Result<(), EmulationError<Exception>> {
+            let op0_value = get_op(&insn, 0, std::mem::size_of::<$bound>(), state, platform)
+                .map_err(EmulationError::PlatformEmulationError)?;
+            let op1_value = get_op(&insn, 1, std::mem::size_of::<$imm>(), state, platform)
+                .map_err(EmulationError::PlatformEmulationError)?;
+
+            let cpazso = calc_rflags_cpazso(op0_value, op1_value, std::mem::size_of::<$bound>());
+
+            state.set_flags((state.flags() & !FLAGS_MASK) | cpazso);
+
+            state.set_ip(insn.ip());
+
+            Ok(())
+        }
+    };
+}
+
+pub struct Cmp_rm64_r64;
+impl<T: CpuStateManager> InstructionHandler<T> for Cmp_rm64_r64 {
+    cmp_rm_r!(u64);
+}
+
+pub struct Cmp_rm32_r32;
+impl<T: CpuStateManager> InstructionHandler<T> for Cmp_rm32_r32 {
+    cmp_rm_r!(u32);
+}
+
+pub struct Cmp_rm16_r16;
+impl<T: CpuStateManager> InstructionHandler<T> for Cmp_rm16_r16 {
+    cmp_rm_r!(u16);
+}
+
+pub struct Cmp_rm8_r8;
+impl<T: CpuStateManager> InstructionHandler<T> for Cmp_rm8_r8 {
+    cmp_rm_r!(u8);
+}
+
+pub struct Cmp_r64_rm64;
+impl<T: CpuStateManager> InstructionHandler<T> for Cmp_r64_rm64 {
+    cmp_r_rm!(u64);
+}
+
+pub struct Cmp_r32_rm32;
+impl<T: CpuStateManager> InstructionHandler<T> for Cmp_r32_rm32 {
+    cmp_r_rm!(u32);
+}
+
+pub struct Cmp_r16_rm16;
+impl<T: CpuStateManager> InstructionHandler<T> for Cmp_r16_rm16 {
+    cmp_r_rm!(u16);
+}
+
+pub struct Cmp_r8_rm8;
+impl<T: CpuStateManager> InstructionHandler<T> for Cmp_r8_rm8 {
+    cmp_r_rm!(u8);
+}
+
+pub struct Cmp_AL_imm8;
+impl<T: CpuStateManager> InstructionHandler<T> for Cmp_AL_imm8 {
+    cmp_rm_imm!(u8, u8);
+}
+
+pub struct Cmp_AX_imm16;
+impl<T: CpuStateManager> InstructionHandler<T> for Cmp_AX_imm16 {
+    cmp_rm_imm!(u16, u16);
+}
+
+pub struct Cmp_EAX_imm32;
+impl<T: CpuStateManager> InstructionHandler<T> for Cmp_EAX_imm32 {
+    cmp_rm_imm!(u32, u32);
+}
+
+pub struct Cmp_RAX_imm32;
+impl<T: CpuStateManager> InstructionHandler<T> for Cmp_RAX_imm32 {
+    cmp_rm_imm!(u32, u64);
+}
+
+pub struct Cmp_rm8_imm8;
+impl<T: CpuStateManager> InstructionHandler<T> for Cmp_rm8_imm8 {
+    cmp_rm_imm!(u8, u8);
+}
+
+pub struct Cmp_rm16_imm16;
+impl<T: CpuStateManager> InstructionHandler<T> for Cmp_rm16_imm16 {
+    cmp_rm_imm!(u16, u16);
+}
+
+pub struct Cmp_rm32_imm32;
+impl<T: CpuStateManager> InstructionHandler<T> for Cmp_rm32_imm32 {
+    cmp_rm_imm!(u32, u32);
+}
+
+pub struct Cmp_rm64_imm32;
+impl<T: CpuStateManager> InstructionHandler<T> for Cmp_rm64_imm32 {
+    cmp_rm_imm!(u32, u64);
+}
+
+pub struct Cmp_rm16_imm8;
+impl<T: CpuStateManager> InstructionHandler<T> for Cmp_rm16_imm8 {
+    cmp_rm_imm!(u8, u16);
+}
+
+pub struct Cmp_rm32_imm8;
+impl<T: CpuStateManager> InstructionHandler<T> for Cmp_rm32_imm8 {
+    cmp_rm_imm!(u8, u32);
+}
+
+pub struct Cmp_rm64_imm8;
+impl<T: CpuStateManager> InstructionHandler<T> for Cmp_rm64_imm8 {
+    cmp_rm_imm!(u8, u64);
+}
+
+#[cfg(test)]
+mod tests {
+    #![allow(unused_mut)]
+
+    use super::*;
+    use crate::arch::x86::emulator::mock_vmm::*;
+
+    #[test]
+    // cmp ah,al
+    fn test_cmp_rm8_r8_1() -> MockResult {
+        let rax: u64 = 0x0;
+        let ip: u64 = 0x1000;
+        let cpu_id = 0;
+        let insn = [0x38, 0xc4]; // cmp ah,al
+        let mut vmm = MockVMM::new(ip, vec![(Register::RAX, rax)], None);
+        assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
+
+        let rflags: u64 = vmm.cpu_state(cpu_id).unwrap().flags() & FLAGS_MASK;
+        assert_eq!(0b1000100, rflags);
+
+        Ok(())
+    }
+
+    #[test]
+    // cmp eax,100
+    fn test_cmp_rm32_imm8_1() -> MockResult {
+        let rax: u64 = 0xabcdef;
+        let ip: u64 = 0x1000;
+        let cpu_id = 0;
+        let insn = [0x83, 0xf8, 0x64]; // cmp eax,100
+        let mut vmm = MockVMM::new(ip, vec![(Register::RAX, rax)], None);
+        assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
+
+        let rflags: u64 = vmm.cpu_state(cpu_id).unwrap().flags() & FLAGS_MASK;
+        assert_eq!(0b100, rflags);
+
+        Ok(())
+    }
+
+    #[test]
+    // cmp eax,-1
+    fn test_cmp_rm32_imm8_2() -> MockResult {
+        let rax: u64 = 0xabcdef;
+        let ip: u64 = 0x1000;
+        let cpu_id = 0;
+        let insn = [0x83, 0xf8, 0xff]; // cmp eax,-1
+        let mut vmm = MockVMM::new(ip, vec![(Register::RAX, rax)], None);
+        assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
+
+        let rflags: u64 = vmm.cpu_state(cpu_id).unwrap().flags() & FLAGS_MASK;
+        assert_eq!(0b101, rflags);
+
+        Ok(())
+    }
+
+    #[test]
+    // cmp rax,rbx
+    fn test_cmp_rm64_r64() -> MockResult {
+        let rax: u64 = 0xabcdef;
+        let rbx: u64 = 0x1234;
+        let ip: u64 = 0x1000;
+        let cpu_id = 0;
+        let insn = [0x48, 0x39, 0xd8, 0x00, 0xc3]; // cmp rax,rbx + two bytes garbage
+        let mut vmm = MockVMM::new(ip, vec![(Register::RAX, rax), (Register::RBX, rbx)], None);
+        assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
+
+        let rflags: u64 = vmm.cpu_state(cpu_id).unwrap().flags() & FLAGS_MASK;
+        assert_eq!(0b100, rflags);
+
+        Ok(())
+    }
+
+    #[test]
+    fn test_cmp_64() -> MockResult {
+        let data = [
+            (0xabcdef, 0x1234, 0b100),
+            (0x0, 0x101, 0b1001_0101),
+            (0x0, 0x8000_0000_0000_0000, 0b1000_1000_0101),
+            (0x1234abcd, 0x1234abcd, 0b100_0100),
+            (0x1234abcd, 0xdeadbeef, 0b1001_0101),
+            (0xffff_ffff_ffff_ffff, 0xdeadbeef, 0b1000_0000),
+            (0xffff_ffff_ffff_ffff, 0x0, 0b1000_0100),
+        ];
+
+        for d in data.iter() {
+            let rax = d.0;
+            let rbx = d.1;
+            let insn = [0x48, 0x39, 0xd8]; // cmp rax,rbx
+            let mut vmm = MockVMM::new(
+                0x1000,
+                vec![(Register::RAX, rax), (Register::RBX, rbx)],
+                None,
+            );
+            assert!(vmm.emulate_first_insn(0, &insn).is_ok());
+
+            let rflags: u64 = vmm.cpu_state(0).unwrap().flags() & FLAGS_MASK;
+            assert_eq!(d.2, rflags);
+        }
+
+        Ok(())
+    }
+
+    #[test]
+    fn test_cmp_32() -> MockResult {
+        let data = [
+            (0xabcdef, 0x1234, 0b100),
+            (0x0, 0x101, 0b1001_0101),
+            (0x0, 0x8000_0000_0000_0000, 0b100_0100), // Same as cmp 0,0 due to truncation
+            (0x1234abcd, 0x1234abcd, 0b100_0100),
+            (0x1234abcd, 0xdeadbeef, 0b1_0101),
+            (0xffff_ffff_ffff_ffff, 0xdeadbeef, 0b0), // Same as cmp 0xffffffff,0xdeadbeef
+            (0xffff_ffff, 0x0, 0b1000_0100),
+        ];
+
+        for d in data.iter() {
+            let rax = d.0;
+            let rbx = d.1;
+            let insn = [0x39, 0xd8]; // cmp eax,ebx
+            let mut vmm = MockVMM::new(
+                0x1000,
+                vec![(Register::RAX, rax), (Register::RBX, rbx)],
+                None,
+            );
+            assert!(vmm.emulate_first_insn(0, &insn).is_ok());
+
+            let rflags: u64 = vmm.cpu_state(0).unwrap().flags() & FLAGS_MASK;
+            assert_eq!(d.2, rflags);
+        }
+
+        Ok(())
+    }
+}

hypervisor/src/arch/x86/emulator/instructions/mod.rs

@@ -0,0 +1,146 @@
+//
+// Copyright © 2020 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+
+extern crate iced_x86;
+
+use crate::arch::emulator::{EmulationError, PlatformEmulator, PlatformError};
+use crate::arch::x86::emulator::CpuStateManager;
+use crate::arch::x86::Exception;
+use iced_x86::*;
+
+pub mod cmp;
+pub mod mov;
+
+fn get_op<T: CpuStateManager>(
+    insn: &Instruction,
+    op_index: u32,
+    op_size: usize,
+    state: &mut T,
+    platform: &mut dyn PlatformEmulator<CpuState = T>,
+) -> Result<u64, PlatformError> {
+    if insn.op_count() < op_index + 1 {
+        return Err(PlatformError::InvalidOperand(anyhow!(
+            "Invalid operand {:?}",
+            op_index
+        )));
+    }
+
+    match op_size {
+        1 | 2 | 4 | 8 => {}
+        _ => {
+            return Err(PlatformError::InvalidOperand(anyhow!(
+                "Invalid operand size {:?}",
+                op_size
+            )))
+        }
+    }
+
+    let value = match insn.op_kind(op_index) {
+        OpKind::Register => state.read_reg(insn.op_register(op_index))?,
+        OpKind::Memory => {
+            let addr = memory_operand_address(insn, state, false)?;
+            let mut memory: [u8; 8] = [0; 8];
+            platform.read_memory(addr, &mut memory[0..op_size])?;
+            <u64>::from_le_bytes(memory)
+        }
+        OpKind::Immediate8 => insn.immediate8() as u64,
+        OpKind::Immediate8to16 => insn.immediate8to16() as u64,
+        OpKind::Immediate8to32 => insn.immediate8to32() as u64,
+        OpKind::Immediate8to64 => insn.immediate8to64() as u64,
+        OpKind::Immediate16 => insn.immediate16() as u64,
+        OpKind::Immediate32 => insn.immediate32() as u64,
+        OpKind::Immediate32to64 => insn.immediate32to64() as u64,
+        OpKind::Immediate64 => insn.immediate64() as u64,
+        k => return Err(PlatformError::InvalidOperand(anyhow!("{:?}", k))),
+    };
+
+    Ok(value)
+}
+
+fn set_op<T: CpuStateManager>(
+    insn: &Instruction,
+    op_index: u32,
+    op_size: usize,
+    state: &mut T,
+    platform: &mut dyn PlatformEmulator<CpuState = T>,
+    value: u64,
+) -> Result<(), PlatformError> {
+    if insn.op_count() < op_index + 1 {
+        return Err(PlatformError::InvalidOperand(anyhow!(
+            "Invalid operand {:?}",
+            op_index
+        )));
+    }
+
+    match op_size {
+        1 | 2 | 4 | 8 => {}
+        _ => {
+            return Err(PlatformError::InvalidOperand(anyhow!(
+                "Invalid operand size {:?}",
+                op_size
+            )))
+        }
+    }
+
+    match insn.op_kind(op_index) {
+        OpKind::Register => state.write_reg(insn.op_register(op_index), value)?,
+        OpKind::Memory => {
+            let addr = memory_operand_address(insn, state, true)?;
+            platform.write_memory(addr, &value.to_le_bytes()[..op_size])?;
+        }
+        k => return Err(PlatformError::InvalidOperand(anyhow!("{:?}", k))),
+    };
+
+    Ok(())
+}
+
+// Returns the linear a.k.a. virtual address for a memory operand.
+fn memory_operand_address<T: CpuStateManager>(
+    insn: &Instruction,
+    state: &T,
+    write: bool,
+) -> Result<u64, PlatformError> {
+    let mut address: u64 = 0;
+
+    if insn.memory_base() != iced_x86::Register::None {
+        let base: u64 = state.read_reg(insn.memory_base())?;
+        address += base;
+    }
+
+    if insn.memory_index() != iced_x86::Register::None {
+        let mut index: u64 = state.read_reg(insn.memory_index())?;
+        index *= insn.memory_index_scale() as u64;
+
+        address += index;
+    }
+
+    address += insn.memory_displacement() as u64;
+
+    // Translate to a linear address.
+    state.linearize(insn.memory_segment(), address, write)
+}
+
+pub trait InstructionHandler<T: CpuStateManager> {
+    fn emulate(
+        &self,
+        insn: &Instruction,
+        state: &mut T,
+        platform: &mut dyn PlatformEmulator<CpuState = T>,
+    ) -> Result<(), EmulationError<Exception>>;
+}
+
+macro_rules! insn_format {
+    ($insn:ident) => {{
+        let mut output = String::new();
+        let mut formatter = FastFormatter::new();
+        formatter
+            .options_mut()
+            .set_space_after_operand_separator(true);
+        formatter.format(&$insn, &mut output);
+
+        output
+    }};
+}

hypervisor/src/arch/x86/emulator/instructions/mov.rs

@@ -0,0 +1,563 @@
+//
+// Copyright © 2020 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#![allow(non_camel_case_types)]
+
+//
+// MOV-Move
+// SDM Volume 1, Chapter 4.3
+//   Copies the second operand (source operand) to the first operand (destination operand).
+//
+
+extern crate iced_x86;
+
+use crate::arch::emulator::{EmulationError, PlatformEmulator};
+use crate::arch::x86::emulator::instructions::*;
+use crate::arch::x86::Exception;
+
+macro_rules! mov_rm_r {
+    ($bound:ty) => {
+        fn emulate(
+            &self,
+            insn: &Instruction,
+            state: &mut T,
+            platform: &mut dyn PlatformEmulator<CpuState = T>,
+        ) -> Result<(), EmulationError<Exception>> {
+            let src_reg_value = get_op(&insn, 1, std::mem::size_of::<$bound>(), state, platform)
+                .map_err(EmulationError::PlatformEmulationError)?;
+
+            set_op(
+                &insn,
+                0,
+                std::mem::size_of::<$bound>(),
+                state,
+                platform,
+                src_reg_value,
+            )
+            .map_err(EmulationError::PlatformEmulationError)?;
+
+            state.set_ip(insn.ip());
+
+            Ok(())
+        }
+    };
+}
+
+macro_rules! mov_rm_imm {
+    ($bound:ty) => {
+        fn emulate(
+            &self,
+            insn: &Instruction,
+            state: &mut T,
+            platform: &mut dyn PlatformEmulator<CpuState = T>,
+        ) -> Result<(), EmulationError<Exception>> {
+            let imm = get_op(&insn, 1, std::mem::size_of::<$bound>(), state, platform)
+                .map_err(EmulationError::PlatformEmulationError)?;
+
+            set_op(
+                &insn,
+                0,
+                std::mem::size_of::<$bound>(),
+                state,
+                platform,
+                imm,
+            )
+            .map_err(EmulationError::PlatformEmulationError)?;
+
+            state.set_ip(insn.ip());
+
+            Ok(())
+        }
+    };
+}
+
+macro_rules! mov_r_rm {
+    ($bound:ty) => {
+        fn emulate(
+            &self,
+            insn: &Instruction,
+            state: &mut T,
+            platform: &mut dyn PlatformEmulator<CpuState = T>,
+        ) -> Result<(), EmulationError<Exception>> {
+            let src_value = get_op(&insn, 1, std::mem::size_of::<$bound>(), state, platform)
+                .map_err(EmulationError::PlatformEmulationError)?;
+
+            set_op(
+                &insn,
+                0,
+                std::mem::size_of::<$bound>(),
+                state,
+                platform,
+                src_value,
+            )
+            .map_err(EmulationError::PlatformEmulationError)?;
+
+            state.set_ip(insn.ip());
+
+            Ok(())
+        }
+    };
+}
+
+macro_rules! mov_r_imm {
+    ($bound:ty) => {
+        fn emulate(
+            &self,
+            insn: &Instruction,
+            state: &mut T,
+            platform: &mut dyn PlatformEmulator<CpuState = T>,
+        ) -> Result<(), EmulationError<Exception>> {
+            let imm = get_op(&insn, 1, std::mem::size_of::<$bound>(), state, platform)
+                .map_err(EmulationError::PlatformEmulationError)?;
+
+            set_op(
+                &insn,
+                0,
+                std::mem::size_of::<$bound>(),
+                state,
+                platform,
+                imm,
+            )
+            .map_err(EmulationError::PlatformEmulationError)?;
+
+            state.set_ip(insn.ip());
+
+            Ok(())
+        }
+    };
+}
+
+pub struct Mov_r8_rm8;
+impl<T: CpuStateManager> InstructionHandler<T> for Mov_r8_rm8 {
+    mov_r_rm!(u8);
+}
+
+pub struct Mov_r8_imm8;
+impl<T: CpuStateManager> InstructionHandler<T> for Mov_r8_imm8 {
+    mov_r_imm!(u8);
+}
+
+pub struct Mov_r16_rm16;
+impl<T: CpuStateManager> InstructionHandler<T> for Mov_r16_rm16 {
+    mov_r_rm!(u16);
+}
+
+pub struct Mov_r16_imm16;
+impl<T: CpuStateManager> InstructionHandler<T> for Mov_r16_imm16 {
+    mov_r_imm!(u16);
+}
+
+pub struct Mov_r32_rm32;
+impl<T: CpuStateManager> InstructionHandler<T> for Mov_r32_rm32 {
+    mov_r_rm!(u32);
+}
+
+pub struct Mov_r32_imm32;
+impl<T: CpuStateManager> InstructionHandler<T> for Mov_r32_imm32 {
+    mov_r_imm!(u32);
+}
+
+pub struct Mov_r64_rm64;
+impl<T: CpuStateManager> InstructionHandler<T> for Mov_r64_rm64 {
+    mov_r_rm!(u64);
+}
+
+pub struct Mov_r64_imm64;
+impl<T: CpuStateManager> InstructionHandler<T> for Mov_r64_imm64 {
+    mov_r_imm!(u64);
+}
+
+pub struct Mov_rm8_imm8;
+impl<T: CpuStateManager> InstructionHandler<T> for Mov_rm8_imm8 {
+    mov_rm_imm!(u8);
+}
+
+pub struct Mov_rm8_r8;
+impl<T: CpuStateManager> InstructionHandler<T> for Mov_rm8_r8 {
+    mov_rm_r!(u8);
+}
+
+pub struct Mov_rm16_imm16;
+impl<T: CpuStateManager> InstructionHandler<T> for Mov_rm16_imm16 {
+    mov_rm_imm!(u16);
+}
+
+pub struct Mov_rm16_r16;
+impl<T: CpuStateManager> InstructionHandler<T> for Mov_rm16_r16 {
+    mov_rm_r!(u16);
+}
+
+pub struct Mov_rm32_imm32;
+impl<T: CpuStateManager> InstructionHandler<T> for Mov_rm32_imm32 {
+    mov_rm_imm!(u32);
+}
+
+pub struct Mov_rm32_r32;
+impl<T: CpuStateManager> InstructionHandler<T> for Mov_rm32_r32 {
+    mov_rm_r!(u32);
+}
+
+pub struct Mov_rm64_imm32;
+impl<T: CpuStateManager> InstructionHandler<T> for Mov_rm64_imm32 {
+    mov_rm_imm!(u32);
+}
+
+pub struct Mov_rm64_r64;
+impl<T: CpuStateManager> InstructionHandler<T> for Mov_rm64_r64 {
+    mov_rm_r!(u64);
+}
+
+#[cfg(test)]
+mod tests {
+    #![allow(unused_mut)]
+    use super::*;
+    use crate::arch::x86::emulator::mock_vmm::*;
+
+    #[test]
+    // mov rax,rbx
+    fn test_mov_r64_r64() -> MockResult {
+        let rbx: u64 = 0x8899aabbccddeeff;
+        let ip: u64 = 0x1000;
+        let cpu_id = 0;
+        let insn = [0x48, 0x89, 0xd8];
+        let mut vmm = MockVMM::new(ip, vec![(Register::RBX, rbx)], None);
+        assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
+
+        let rax: u64 = vmm
+            .cpu_state(cpu_id)
+            .unwrap()
+            .read_reg(Register::RAX)
+            .unwrap();
+        assert_eq!(rax, rbx);
+
+        Ok(())
+    }
+
+    #[test]
+    // mov rax,0x1122334411223344
+    fn test_mov_r64_imm64() -> MockResult {
+        let imm64: u64 = 0x1122334411223344;
+        let ip: u64 = 0x1000;
+        let cpu_id = 0;
+        let insn = [0x48, 0xb8, 0x44, 0x33, 0x22, 0x11, 0x44, 0x33, 0x22, 0x11];
+        let mut vmm = MockVMM::new(ip, vec![], None);
+        assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
+
+        let rax: u64 = vmm
+            .cpu_state(cpu_id)
+            .unwrap()
+            .read_reg(Register::RAX)
+            .unwrap();
+        assert_eq!(rax, imm64);
+
+        Ok(())
+    }
+
+    #[test]
+    // mov rax, [rax+rax]
+    fn test_mov_r64_m64() -> MockResult {
+        let target_rax: u64 = 0x1234567812345678;
+        let mut rax: u64 = 0x100;
+        let ip: u64 = 0x1000;
+        let cpu_id = 0;
+        let memory: [u8; 8] = target_rax.to_le_bytes();
+        let insn = [0x48, 0x8b, 0x04, 0x00];
+        let mut vmm = MockVMM::new(ip, vec![(Register::RAX, rax)], Some((rax + rax, &memory)));
+        assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
+
+        rax = vmm
+            .cpu_state(cpu_id)
+            .unwrap()
+            .read_reg(Register::RAX)
+            .unwrap();
+        assert_eq!(rax, target_rax);
+
+        Ok(())
+    }
+
+    #[test]
+    // mov al,0x11
+    fn test_mov_r8_imm8() -> MockResult {
+        let imm8: u8 = 0x11;
+        let ip: u64 = 0x1000;
+        let cpu_id = 0;
+        let insn = [0xb0, 0x11];
+        let mut vmm = MockVMM::new(ip, vec![], None);
+        assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
+
+        let al = vmm
+            .cpu_state(cpu_id)
+            .unwrap()
+            .read_reg(Register::AL)
+            .unwrap();
+        assert_eq!(al as u8, imm8);
+
+        Ok(())
+    }
+
+    #[test]
+    // mov eax,0x11
+    fn test_mov_r32_imm8() -> MockResult {
+        let imm8: u8 = 0x11;
+        let ip: u64 = 0x1000;
+        let cpu_id = 0;
+        let insn = [0xb8, 0x11, 0x00, 0x00, 0x00];
+        let mut vmm = MockVMM::new(ip, vec![], None);
+        assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
+
+        let eax = vmm
+            .cpu_state(cpu_id)
+            .unwrap()
+            .read_reg(Register::EAX)
+            .unwrap();
+        assert_eq!(eax as u8, imm8);
+
+        Ok(())
+    }
+
+    #[test]
+    // mov rax,0x11223344
+    fn test_mov_r64_imm32() -> MockResult {
+        let imm32: u32 = 0x11223344;
+        let ip: u64 = 0x1000;
+        let cpu_id = 0;
+        let insn = [0x48, 0xc7, 0xc0, 0x44, 0x33, 0x22, 0x11];
+        let mut vmm = MockVMM::new(ip, vec![], None);
+        assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
+
+        let rax: u64 = vmm
+            .cpu_state(cpu_id)
+            .unwrap()
+            .read_reg(Register::RAX)
+            .unwrap();
+        assert_eq!(rax, imm32 as u64);
+
+        Ok(())
+    }
+
+    #[test]
+    // mov byte ptr [rax],dh
+    fn test_mov_m8_r8() -> MockResult {
+        let rax: u64 = 0x100;
+        let dh: u8 = 0x99;
+        let ip: u64 = 0x1000;
+        let cpu_id = 0;
+        let insn = [0x88, 0x30];
+        let mut vmm = MockVMM::new(
+            ip,
+            vec![(Register::RAX, rax), (Register::DH, dh.into())],
+            None,
+        );
+        assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
+
+        let mut memory: [u8; 1] = [0; 1];
+        vmm.read_memory(rax, &mut memory).unwrap();
+
+        assert_eq!(u8::from_le_bytes(memory), dh);
+
+        Ok(())
+    }
+
+    #[test]
+    // mov dword ptr [rax],esi
+    fn test_mov_m32_r32() -> MockResult {
+        let rax: u64 = 0x100;
+        let esi: u32 = 0x8899;
+        let ip: u64 = 0x1000;
+        let cpu_id = 0;
+        let insn = [0x89, 0x30];
+        let mut vmm = MockVMM::new(
+            ip,
+            vec![(Register::RAX, rax), (Register::ESI, esi.into())],
+            None,
+        );
+        assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
+
+        let mut memory: [u8; 4] = [0; 4];
+        vmm.read_memory(rax, &mut memory).unwrap();
+
+        assert_eq!(u32::from_le_bytes(memory), esi);
+
+        Ok(())
+    }
+
+    #[test]
+    // mov dword ptr [rax+0x00000001],edi
+    fn test_mov_m32imm32_r32() -> MockResult {
+        let rax: u64 = 0x100;
+        let displacement: u64 = 0x1;
+        let edi: u32 = 0x8899;
+        let ip: u64 = 0x1000;
+        let cpu_id = 0;
+        let insn = [0x89, 0x3c, 0x05, 0x01, 0x00, 0x00, 0x00];
+        let mut vmm = MockVMM::new(
+            ip,
+            vec![(Register::RAX, rax), (Register::EDI, edi.into())],
+            None,
+        );
+        assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
+
+        let mut memory: [u8; 4] = [0; 4];
+        vmm.read_memory(rax + displacement, &mut memory).unwrap();
+
+        assert_eq!(u32::from_le_bytes(memory), edi);
+
+        Ok(())
+    }
+
+    #[test]
+    // mov eax,dword ptr [rax+10h]
+    fn test_mov_r32_m32imm32() -> MockResult {
+        let rax: u64 = 0x100;
+        let displacement: u64 = 0x10;
+        let eax: u32 = 0xaabbccdd;
+        let memory: [u8; 4] = eax.to_le_bytes();
+        let ip: u64 = 0x1000;
+        let cpu_id = 0;
+        let insn = [0x8b, 0x40, 0x10];
+        let mut vmm = MockVMM::new(
+            ip,
+            vec![(Register::RAX, rax)],
+            Some((rax + displacement, &memory)),
+        );
+        assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
+
+        let new_eax = vmm
+            .cpu_state(cpu_id)
+            .unwrap()
+            .read_reg(Register::EAX)
+            .unwrap();
+        assert_eq!(new_eax, eax as u64);
+
+        Ok(())
+    }
+
+    #[test]
+    // mov al,byte ptr [rax+10h]
+    fn test_mov_r8_m32imm32() -> MockResult {
+        let rax: u64 = 0x100;
+        let displacement: u64 = 0x10;
+        let al: u8 = 0xaa;
+        let ip: u64 = 0x1000;
+        let cpu_id = 0;
+        let insn = [0x8a, 0x40, 0x10];
+        let memory: [u8; 1] = al.to_le_bytes();
+        let mut vmm = MockVMM::new(
+            ip,
+            vec![(Register::RAX, rax)],
+            Some((rax + displacement, &memory)),
+        );
+        assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
+
+        let new_al = vmm
+            .cpu_state(cpu_id)
+            .unwrap()
+            .read_reg(Register::AL)
+            .unwrap();
+        assert_eq!(new_al, al as u64);
+
+        Ok(())
+    }
+
+    #[test]
+    // mov rax, 0x100
+    // mov rbx, qword ptr [rax+10h]
+    fn test_mov_r64_imm64_and_r64_m64() -> MockResult {
+        let target_rax: u64 = 0x1234567812345678;
+        let rax: u64 = 0x100;
+        let displacement: u64 = 0x10;
+        let ip: u64 = 0x1000;
+        let cpu_id = 0;
+        let memory: [u8; 8] = target_rax.to_le_bytes();
+        let insn = [
+            0x48, 0xc7, 0xc0, 0x00, 0x01, 0x00, 0x00, // mov rax, 0x100
+            0x48, 0x8b, 0x58, 0x10, // mov rbx, qword ptr [rax+10h]
+        ];
+        let mut vmm = MockVMM::new(ip, vec![], Some((rax + displacement, &memory)));
+        assert!(vmm.emulate_insn(cpu_id, &insn, Some(2)).is_ok());
+
+        let rbx: u64 = vmm
+            .cpu_state(cpu_id)
+            .unwrap()
+            .read_reg(Register::RBX)
+            .unwrap();
+        assert_eq!(rbx, target_rax);
+
+        Ok(())
+    }
+
+    #[test]
+    // mov rax, 0x100
+    // mov rbx, qword ptr [rax+10h]
+    fn test_mov_r64_imm64_and_r64_m64_first_insn() -> MockResult {
+        let target_rax: u64 = 0x1234567812345678;
+        let rax: u64 = 0x100;
+        let displacement: u64 = 0x10;
+        let ip: u64 = 0x1000;
+        let cpu_id = 0;
+        let memory: [u8; 8] = target_rax.to_le_bytes();
+        let insn = [
+            0x48, 0xc7, 0xc0, 0x00, 0x01, 0x00, 0x00, // mov rax, 0x100
+            0x48, 0x8b, 0x58, 0x10, // mov rbx, qword ptr [rax+10h]
+        ];
+
+        let mut vmm = MockVMM::new(ip, vec![], Some((rax + displacement, &memory)));
+        // Only run the first instruction.
+        assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
+
+        assert_eq!(ip + 7 as u64, vmm.cpu_state(cpu_id).unwrap().ip());
+
+        let new_rax: u64 = vmm
+            .cpu_state(cpu_id)
+            .unwrap()
+            .read_reg(Register::RAX)
+            .unwrap();
+        assert_eq!(rax, new_rax);
+
+        Ok(())
+    }
+
+    #[test]
+    // mov rax, 0x100
+    // mov rbx, qword ptr [rax+10h]
+    // mov rax, 0x200
+    fn test_mov_r64_imm64_and_r64_m64_two_insns() -> MockResult {
+        let target_rax: u64 = 0x1234567812345678;
+        let rax: u64 = 0x100;
+        let displacement: u64 = 0x10;
+        let ip: u64 = 0x1000;
+        let cpu_id = 0;
+        let memory: [u8; 8] = target_rax.to_le_bytes();
+        let insn = [
+            0x48, 0xc7, 0xc0, 0x00, 0x01, 0x00, 0x00, // mov rax, 0x100
+            0x48, 0x8b, 0x58, 0x10, // mov rbx, qword ptr [rax+10h]
+            0x48, 0xc7, 0xc0, 0x00, 0x02, 0x00, 0x00, // mov rax, 0x200
+        ];
+
+        let mut vmm = MockVMM::new(ip, vec![], Some((rax + displacement, &memory)));
+        // Run the 2 first instructions.
+        assert!(vmm.emulate_insn(cpu_id, &insn, Some(2)).is_ok());
+
+        assert_eq!(ip + 7 + 4 as u64, vmm.cpu_state(cpu_id).unwrap().ip());
+
+        let rbx: u64 = vmm
+            .cpu_state(cpu_id)
+            .unwrap()
+            .read_reg(Register::RBX)
+            .unwrap();
+        assert_eq!(rbx, target_rax);
+
+        // Check that rax is still at 0x100
+        let new_rax: u64 = vmm
+            .cpu_state(cpu_id)
+            .unwrap()
+            .read_reg(Register::RAX)
+            .unwrap();
+        assert_eq!(rax, new_rax);
+
+        Ok(())
+    }
+}

hypervisor/src/arch/x86/emulator/mod.rs

@@ -0,0 +1,859 @@
+//
+// Copyright © 2020 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+
+extern crate iced_x86;
+
+use crate::arch::emulator::{EmulationError, EmulationResult, PlatformEmulator, PlatformError};
+use crate::arch::x86::emulator::instructions::*;
+use crate::arch::x86::regs::*;
+use crate::arch::x86::*;
+use crate::arch::x86::{Exception, SegmentRegisterOps};
+use crate::x86_64::{SegmentRegister, SpecialRegisters, StandardRegisters};
+use anyhow::Context;
+use iced_x86::*;
+
+#[macro_use]
+mod instructions;
+
+/// x86 CPU modes
+#[derive(Debug, PartialEq)]
+pub enum CpuMode {
+    /// Real mode
+    Real,
+
+    /// Virtual 8086 mode
+    Virtual8086,
+
+    /// 16-bit protected mode
+    Protected16,
+
+    /// 32-bit protected mode
+    Protected,
+
+    /// 64-bit mode, a.k.a. long mode
+    Long,
+}
+
+/// CpuStateManager manages an x86 CPU state.
+///
+/// Instruction emulation handlers get a mutable reference to
+/// a `CpuStateManager` implementation, representing the current state of the
+/// CPU they have to emulate an instruction stream against. Usually those
+/// handlers will modify the CPU state by modifying `CpuState` and it is up to
+/// the handler caller to commit those changes back by invoking a
+/// `PlatformEmulator` implementation `set_state()` method.
+///
+pub trait CpuStateManager: Clone {
+    /// Reads a CPU register.
+    ///
+    /// # Arguments
+    ///
+    /// * `reg` - A general purpose, control or debug register.
+    fn read_reg(&self, reg: Register) -> Result<u64, PlatformError>;
+
+    /// Write to a CPU register.
+    ///
+    /// # Arguments
+    ///
+    /// * `reg` - A general purpose, control or debug register.
+    /// * `val` - The value to load.
+    fn write_reg(&mut self, reg: Register, val: u64) -> Result<(), PlatformError>;
+
+    /// Reads a segment register.
+    ///
+    /// # Arguments
+    ///
+    /// * `reg` - A segment register.
+    fn read_segment(&self, reg: Register) -> Result<SegmentRegister, PlatformError>;
+
+    /// Write to a segment register.
+    ///
+    /// # Arguments
+    ///
+    /// * `reg` - A segment register.
+    /// * `segment_reg` - The segment register value to load.
+    fn write_segment(
+        &mut self,
+        reg: Register,
+        segment_reg: SegmentRegister,
+    ) -> Result<(), PlatformError>;
+
+    /// Get the CPU instruction pointer.
+    fn ip(&self) -> u64;
+
+    /// Set the CPU instruction pointer.
+    ///
+    /// # Arguments
+    ///
+    /// * `ip` - The CPU instruction pointer.
+    fn set_ip(&mut self, ip: u64);
+
+    /// Get the CPU Extended Feature Enable Register.
+    fn efer(&self) -> u64;
+
+    /// Set the CPU Extended Feature Enable Register.
+    ///
+    /// # Arguments
+    ///
+    /// * `efer` - The CPU EFER value.
+    fn set_efer(&mut self, efer: u64);
+
+    /// Get the CPU flags.
+    fn flags(&self) -> u64;
+
+    /// Set the CPU flags.
+    ///
+    /// # Arguments
+    ///
+    /// * `flags` - The CPU flags
+    fn set_flags(&mut self, flags: u64);
+
+    /// Get the CPU mode.
+    fn mode(&self) -> Result<CpuMode, PlatformError>;
+
+    /// Translate a logical (segmented) address into a linear (virtual) one.
+    ///
+    /// # Arguments
+    ///
+    /// * `segment` - Which segment to use for linearization
+    /// * `logical_addr` - The logical address to be translated
+    fn linearize(
+        &self,
+        segment: Register,
+        logical_addr: u64,
+        write: bool,
+    ) -> Result<u64, PlatformError> {
+        let segment_register = self.read_segment(segment)?;
+        let mode = self.mode()?;
+
+        match mode {
+            CpuMode::Long => {
+                // TODO Check that we got a canonical address.
+                Ok(logical_addr
+                    .checked_add(segment_register.base)
+                    .ok_or_else(|| {
+                        PlatformError::InvalidAddress(anyhow!(
+                            "Logical address {:#x} can not be linearized with segment {:#x?}",
+                            logical_addr,
+                            segment_register
+                        ))
+                    })?)
+            }
+
+            CpuMode::Protected | CpuMode::Real => {
+                let segment_type = segment_register.segment_type();
+
+                // Must not write to a read-only segment.
+                if segment_type_ro(segment_type) && write {
+                    return Err(PlatformError::InvalidAddress(anyhow!(
+                        "Can not write to a read-only segment"
+                    )));
+                }
+
+                let logical_addr = logical_addr & 0xffff_ffffu64;
+                let mut segment_limit: u32 = if segment_register.granularity() != 0 {
+                    (segment_register.limit << 12) | 0xfff
+                } else {
+                    segment_register.limit
+                };
+
+                // Expand-down segment
+                if segment_type_expand_down(segment_type) {
+                    if logical_addr >= segment_limit.into() {
+                        return Err(PlatformError::InvalidAddress(anyhow!(
+                            "{:#x} is off limits {:#x} (expand down)",
+                            logical_addr,
+                            segment_limit
+                        )));
+                    }
+
+                    if segment_register.db() != 0 {
+                        segment_limit = 0xffffffff
+                    } else {
+                        segment_limit = 0xffff
+                    }
+                }
+
+                if logical_addr > segment_limit.into() {
+                    return Err(PlatformError::InvalidAddress(anyhow!(
+                        "{:#x} is off limits {:#x}",
+                        logical_addr,
+                        segment_limit
+                    )));
+                }
+
+                Ok(logical_addr + segment_register.base)
+            }
+
+            _ => Err(PlatformError::UnsupportedCpuMode(anyhow!("{:?}", mode))),
+        }
+    }
+}
+
+const REGISTER_MASK_64: u64 = 0xffff_ffff_ffff_ffffu64;
+const REGISTER_MASK_32: u64 = 0xffff_ffffu64;
+const REGISTER_MASK_16: u64 = 0xffffu64;
+const REGISTER_MASK_8: u64 = 0xffu64;
+
+macro_rules! set_reg {
+    ($reg:expr, $mask:expr, $value:expr) => {
+        $reg = ($reg & $mask) | $value
+    };
+}
+
+#[derive(Clone, Default, Debug)]
+/// A minimal, emulated CPU state.
+///
+/// Hypervisors needing x86 emulation can choose to either use their own
+/// CPU state structures and implement the CpuStateManager interface for it,
+/// or use `EmulatorCpuState`. The latter implies creating a new state
+/// `EmulatorCpuState` instance for each platform `cpu_state()` call, which
+/// might be less efficient.
+pub struct EmulatorCpuState {
+    pub regs: StandardRegisters,
+    pub sregs: SpecialRegisters,
+}
+
+impl CpuStateManager for EmulatorCpuState {
+    fn read_reg(&self, reg: Register) -> Result<u64, PlatformError> {
+        let mut reg_value: u64 = match reg {
+            Register::RAX | Register::EAX | Register::AX | Register::AL | Register::AH => {
+                self.regs.rax
+            }
+            Register::RBX | Register::EBX | Register::BX | Register::BL | Register::BH => {
+                self.regs.rbx
+            }
+            Register::RCX | Register::ECX | Register::CX | Register::CL | Register::CH => {
+                self.regs.rcx
+            }
+            Register::RDX | Register::EDX | Register::DX | Register::DL | Register::DH => {
+                self.regs.rdx
+            }
+            Register::RSP | Register::ESP | Register::SP => self.regs.rsp,
+            Register::RBP | Register::EBP | Register::BP => self.regs.rbp,
+            Register::RSI | Register::ESI | Register::SI | Register::SIL => self.regs.rsi,
+            Register::RDI | Register::EDI | Register::DI | Register::DIL => self.regs.rdi,
+            Register::R8 | Register::R8D | Register::R8W | Register::R8L => self.regs.r8,
+            Register::R9 | Register::R9D | Register::R9W | Register::R9L => self.regs.r9,
+            Register::R10 | Register::R10D | Register::R10W | Register::R10L => self.regs.r10,
+            Register::R11 | Register::R11D | Register::R11W | Register::R11L => self.regs.r11,
+            Register::R12 | Register::R12D | Register::R12W | Register::R12L => self.regs.r12,
+            Register::R13 | Register::R13D | Register::R13W | Register::R13L => self.regs.r13,
+            Register::R14 | Register::R14D | Register::R14W | Register::R14L => self.regs.r14,
+            Register::R15 | Register::R15D | Register::R15W | Register::R15L => self.regs.r15,
+            Register::CR0 => self.sregs.cr0,
+            Register::CR2 => self.sregs.cr2,
+            Register::CR3 => self.sregs.cr3,
+            Register::CR4 => self.sregs.cr4,
+            Register::CR8 => self.sregs.cr8,
+
+            r => {
+                return Err(PlatformError::InvalidRegister(anyhow!(
+                    "read_reg invalid GPR {:?}",
+                    r
+                )))
+            }
+        };
+
+        reg_value = if reg.is_gpr64() || reg.is_cr() {
+            reg_value
+        } else if reg.is_gpr32() {
+            reg_value & REGISTER_MASK_32
+        } else if reg.is_gpr16() {
+            reg_value & REGISTER_MASK_16
+        } else if reg.is_gpr8() {
+            if reg == Register::AH
+                || reg == Register::BH
+                || reg == Register::CH
+                || reg == Register::DH
+            {
+                (reg_value >> 8) & REGISTER_MASK_8
+            } else {
+                reg_value & REGISTER_MASK_8
+            }
+        } else {
+            return Err(PlatformError::InvalidRegister(anyhow!(
+                "read_reg invalid GPR {:?}",
+                reg
+            )));
+        };
+
+        debug!("Register read: {:#x} from {:?}", reg_value, reg);
+
+        Ok(reg_value)
+    }
+
+    fn write_reg(&mut self, reg: Register, val: u64) -> Result<(), PlatformError> {
+        debug!("Register write: {:#x} to {:?}", val, reg);
+
+        // SDM Vol 1 - 3.4.1.1
+        //
+        // 8-bit and 16-bit operands generate an 8-bit or 16-bit result.
+        // The upper 56 bits or 48 bits (respectively) of the destination
+        // general-purpose register are not modified by the operation.
+        let (reg_value, mask): (u64, u64) = if reg.is_gpr64() || reg.is_cr() {
+            (val, !REGISTER_MASK_64)
+        } else if reg.is_gpr32() {
+            (val & REGISTER_MASK_32, !REGISTER_MASK_64)
+        } else if reg.is_gpr16() {
+            (val & REGISTER_MASK_16, !REGISTER_MASK_16)
+        } else if reg.is_gpr8() {
+            if reg == Register::AH
+                || reg == Register::BH
+                || reg == Register::CH
+                || reg == Register::DH
+            {
+                ((val & REGISTER_MASK_8) << 8, !(REGISTER_MASK_8 << 8))
+            } else {
+                (val & REGISTER_MASK_8, !REGISTER_MASK_8)
+            }
+        } else {
+            return Err(PlatformError::InvalidRegister(anyhow!(
+                "write_reg invalid register {:?}",
+                reg
+            )));
+        };
+
+        match reg {
+            Register::RAX | Register::EAX | Register::AX | Register::AL | Register::AH => {
+                set_reg!(self.regs.rax, mask, reg_value);
+            }
+            Register::RBX | Register::EBX | Register::BX | Register::BL | Register::BH => {
+                set_reg!(self.regs.rbx, mask, reg_value);
+            }
+            Register::RCX | Register::ECX | Register::CX | Register::CL | Register::CH => {
+                set_reg!(self.regs.rcx, mask, reg_value);
+            }
+            Register::RDX | Register::EDX | Register::DX | Register::DL | Register::DH => {
+                set_reg!(self.regs.rdx, mask, reg_value);
+            }
+            Register::RSP | Register::ESP | Register::SP => {
+                set_reg!(self.regs.rsp, mask, reg_value)
+            }
+            Register::RBP | Register::EBP | Register::BP => {
+                set_reg!(self.regs.rbp, mask, reg_value)
+            }
+            Register::RSI | Register::ESI | Register::SI | Register::SIL => {
+                set_reg!(self.regs.rsi, mask, reg_value)
+            }
+            Register::RDI | Register::EDI | Register::DI | Register::DIL => {
+                set_reg!(self.regs.rdi, mask, reg_value)
+            }
+            Register::R8 | Register::R8D | Register::R8W | Register::R8L => {
+                set_reg!(self.regs.r8, mask, reg_value)
+            }
+            Register::R9 | Register::R9D | Register::R9W | Register::R9L => {
+                set_reg!(self.regs.r9, mask, reg_value)
+            }
+            Register::R10 | Register::R10D | Register::R10W | Register::R10L => {
+                set_reg!(self.regs.r10, mask, reg_value)
+            }
+            Register::R11 | Register::R11D | Register::R11W | Register::R11L => {
+                set_reg!(self.regs.r11, mask, reg_value)
+            }
+            Register::R12 | Register::R12D | Register::R12W | Register::R12L => {
+                set_reg!(self.regs.r12, mask, reg_value)
+            }
+            Register::R13 | Register::R13D | Register::R13W | Register::R13L => {
+                set_reg!(self.regs.r13, mask, reg_value)
+            }
+            Register::R14 | Register::R14D | Register::R14W | Register::R14L => {
+                set_reg!(self.regs.r14, mask, reg_value)
+            }
+            Register::R15 | Register::R15D | Register::R15W | Register::R15L => {
+                set_reg!(self.regs.r15, mask, reg_value)
+            }
+            Register::CR0 => set_reg!(self.sregs.cr0, mask, reg_value),
+            Register::CR2 => set_reg!(self.sregs.cr2, mask, reg_value),
+            Register::CR3 => set_reg!(self.sregs.cr3, mask, reg_value),
+            Register::CR4 => set_reg!(self.sregs.cr4, mask, reg_value),
+            Register::CR8 => set_reg!(self.sregs.cr8, mask, reg_value),
+            _ => {
+                return Err(PlatformError::InvalidRegister(anyhow!(
+                    "write_reg invalid register {:?}",
+                    reg
+                )))
+            }
+        }
+
+        Ok(())
+    }
+
+    fn read_segment(&self, reg: Register) -> Result<SegmentRegister, PlatformError> {
+        if !reg.is_segment_register() {
+            return Err(PlatformError::InvalidRegister(anyhow!(
+                "read_segment {:?} is not a segment register",
+                reg
+            )));
+        }
+
+        match reg {
+            Register::CS => Ok(self.sregs.cs),
+            Register::DS => Ok(self.sregs.ds),
+            Register::ES => Ok(self.sregs.es),
+            Register::FS => Ok(self.sregs.fs),
+            Register::GS => Ok(self.sregs.gs),
+            Register::SS => Ok(self.sregs.ss),
+            r => Err(PlatformError::InvalidRegister(anyhow!(
+                "read_segment invalid register {:?}",
+                r
+            ))),
+        }
+    }
+
+    fn write_segment(
+        &mut self,
+        reg: Register,
+        segment_register: SegmentRegister,
+    ) -> Result<(), PlatformError> {
+        if !reg.is_segment_register() {
+            return Err(PlatformError::InvalidRegister(anyhow!("{:?}", reg)));
+        }
+
+        match reg {
+            Register::CS => self.sregs.cs = segment_register,
+            Register::DS => self.sregs.ds = segment_register,
+            Register::ES => self.sregs.es = segment_register,
+            Register::FS => self.sregs.fs = segment_register,
+            Register::GS => self.sregs.gs = segment_register,
+            Register::SS => self.sregs.ss = segment_register,
+            r => return Err(PlatformError::InvalidRegister(anyhow!("{:?}", r))),
+        }
+
+        Ok(())
+    }
+
+    fn ip(&self) -> u64 {
+        self.regs.rip
+    }
+
+    fn set_ip(&mut self, ip: u64) {
+        self.regs.rip = ip;
+    }
+
+    fn efer(&self) -> u64 {
+        self.sregs.efer
+    }
+
+    fn set_efer(&mut self, efer: u64) {
+        self.sregs.efer = efer
+    }
+
+    fn flags(&self) -> u64 {
+        self.regs.rflags
+    }
+
+    fn set_flags(&mut self, flags: u64) {
+        self.regs.rflags = flags;
+    }
+
+    fn mode(&self) -> Result<CpuMode, PlatformError> {
+        let efer = self.efer();
+        let cr0 = self.read_reg(Register::CR0)?;
+        let mut mode = CpuMode::Real;
+
+        if (cr0 & CR0_PE) == CR0_PE {
+            mode = CpuMode::Protected;
+        }
+
+        if (efer & EFER_LMA) == EFER_LMA {
+            if mode != CpuMode::Protected {
+                return Err(PlatformError::InvalidState(anyhow!(
+                    "Protection must be enabled in long mode"
+                )));
+            }
+
+            mode = CpuMode::Long;
+        }
+
+        Ok(mode)
+    }
+}
+
+pub struct Emulator<'a, T: CpuStateManager> {
+    platform: &'a mut dyn PlatformEmulator<CpuState = T>,
+}
+
+// Reduce repetition, see its invocation in get_handler().
+macro_rules! gen_handler_match {
+    ($value: ident, $( ($module:ident, $code:ident) ),* ) => {
+        match $value {
+            $(
+                Code::$code => Some(Box::new($module::$code)),
+            )*
+            _ => None,
+        }
+    };
+}
+
+impl<'a, T: CpuStateManager> Emulator<'a, T> {
+    pub fn new(platform: &mut dyn PlatformEmulator<CpuState = T>) -> Emulator<T> {
+        Emulator { platform }
+    }
+
+    fn get_handler(code: Code) -> Option<Box<dyn InstructionHandler<T>>> {
+        let handler: Option<Box<dyn InstructionHandler<T>>> = gen_handler_match!(
+            code,
+            // CMP
+            (cmp, Cmp_rm32_r32),
+            (cmp, Cmp_rm8_r8),
+            (cmp, Cmp_rm32_imm8),
+            (cmp, Cmp_rm64_r64),
+            // MOV
+            (mov, Mov_r8_rm8),
+            (mov, Mov_r8_imm8),
+            (mov, Mov_r16_imm16),
+            (mov, Mov_r16_rm16),
+            (mov, Mov_r32_imm32),
+            (mov, Mov_r32_rm32),
+            (mov, Mov_r64_imm64),
+            (mov, Mov_r64_rm64),
+            (mov, Mov_rm8_imm8),
+            (mov, Mov_rm8_r8),
+            (mov, Mov_rm16_imm16),
+            (mov, Mov_rm16_r16),
+            (mov, Mov_rm32_imm32),
+            (mov, Mov_rm32_r32),
+            (mov, Mov_rm64_imm32),
+            (mov, Mov_rm64_r64)
+        );
+
+        handler
+    }
+
+    fn emulate_insn_stream(
+        &mut self,
+        cpu_id: usize,
+        insn_stream: &[u8],
+        num_insn: Option<usize>,
+    ) -> EmulationResult<T, Exception> {
+        let mut state = self
+            .platform
+            .cpu_state(cpu_id)
+            .map_err(EmulationError::PlatformEmulationError)?;
+        let mut decoder = Decoder::new(64, insn_stream, DecoderOptions::NONE);
+        let mut insn = Instruction::default();
+        let mut num_insn_emulated: usize = 0;
+        let mut fetched_insn_stream: [u8; 16] = [0; 16];
+        let mut last_decoded_ip: u64 = state.ip();
+        let mut stop_emulation: bool = false;
+
+        decoder.set_ip(state.ip());
+
+        while decoder.can_decode() && !stop_emulation {
+            decoder.decode_out(&mut insn);
+
+            if decoder.last_error() == DecoderError::NoMoreBytes {
+                // The decoder is missing some bytes to decode the current
+                // instruction, for example because the instruction stream
+                // crosses a page boundary.
+                // We fetch 16 more bytes from the instruction segment,
+                // decode and emulate the failing instruction and terminate
+                // the emulation loop.
+                debug!(
+                    "Fetching {} bytes from {:#x}",
+                    fetched_insn_stream.len(),
+                    last_decoded_ip
+                );
+
+                // fetched_insn_stream is 16 bytes long, enough to contain
+                // any complete x86 instruction.
+                self.platform
+                    .fetch(last_decoded_ip, &mut fetched_insn_stream)
+                    .map_err(EmulationError::PlatformEmulationError)?;
+
+                debug!("Fetched {:x?}", fetched_insn_stream);
+
+                // Once we have the new stream, we must create a new decoder
+                // and emulate one last instruction from the last decoded IP.
+                decoder = Decoder::new(64, &fetched_insn_stream, DecoderOptions::NONE);
+                decoder.decode_out(&mut insn);
+                if decoder.last_error() != DecoderError::None {
+                    return Err(EmulationError::InstructionFetchingError(anyhow!(
+                        "{:#x?}",
+                        insn_format!(insn)
+                    )));
+                }
+
+                stop_emulation = true;
+            }
+
+            // Emulate the decoded instruction
+            Emulator::get_handler(insn.code())
+                .ok_or_else(|| {
+                    EmulationError::UnsupportedInstruction(anyhow!(
+                        "{:#x?} {:?} {:?}",
+                        insn_format!(insn),
+                        insn.mnemonic(),
+                        insn.code()
+                    ))
+                })?
+                .emulate(&insn, &mut state, self.platform)
+                .context(anyhow!("Failed to emulate {:#x?}", insn_format!(insn)))?;
+
+            last_decoded_ip = decoder.ip();
+            num_insn_emulated += 1;
+
+            if let Some(num_insn) = num_insn {
+                if num_insn_emulated >= num_insn {
+                    // Exit the decoding loop, do not decode the next instruction.
+                    stop_emulation = true;
+                }
+            }
+        }
+
+        state.set_ip(decoder.ip());
+        Ok(state)
+    }
+
+    /// Emulate all instructions from the instructions stream.
+    pub fn emulate(&mut self, cpu_id: usize, insn_stream: &[u8]) -> EmulationResult<T, Exception> {
+        self.emulate_insn_stream(cpu_id, insn_stream, None)
+    }
+
+    /// Only emulate the first instruction from the stream.
+    ///
+    /// This is useful for cases where we get readahead instruction stream
+    /// but implicitly must only emulate the first instruction, and then return
+    /// to the guest.
+    pub fn emulate_first_insn(
+        &mut self,
+        cpu_id: usize,
+        insn_stream: &[u8],
+    ) -> EmulationResult<T, Exception> {
+        self.emulate_insn_stream(cpu_id, insn_stream, Some(1))
+    }
+}
+
+#[cfg(test)]
+mod mock_vmm {
+    #![allow(unused_mut)]
+
+    extern crate env_logger;
+
+    use super::*;
+    use crate::arch::emulator::{EmulationError, PlatformEmulator};
+    use crate::arch::x86::emulator::{Emulator, EmulatorCpuState as CpuState};
+    use crate::arch::x86::gdt::{gdt_entry, segment_from_gdt};
+    use crate::arch::x86::Exception;
+    use std::sync::{Arc, Mutex};
+
+    #[derive(Debug, Clone)]
+    pub struct MockVMM {
+        memory: Vec<u8>,
+        state: Arc<Mutex<CpuState>>,
+    }
+
+    unsafe impl Sync for MockVMM {}
+
+    pub type MockResult = Result<(), EmulationError<Exception>>;
+
+    impl MockVMM {
+        pub fn new(ip: u64, regs: Vec<(Register, u64)>, memory: Option<(u64, &[u8])>) -> MockVMM {
+            let _ = env_logger::try_init();
+            let cs_reg = segment_from_gdt(gdt_entry(0xc09b, 0, 0xffffffff), 1);
+            let ds_reg = segment_from_gdt(gdt_entry(0xc093, 0, 0xffffffff), 2);
+            let mut initial_state = CpuState::default();
+            initial_state.set_ip(ip);
+            initial_state.write_segment(Register::CS, cs_reg).unwrap();
+            initial_state.write_segment(Register::DS, ds_reg).unwrap();
+            for (reg, value) in regs {
+                initial_state.write_reg(reg, value).unwrap();
+            }
+
+            let mut vmm = MockVMM {
+                memory: vec![0; 8192],
+                state: Arc::new(Mutex::new(initial_state)),
+            };
+
+            if let Some(mem) = memory {
+                vmm.write_memory(mem.0, &mem.1).unwrap();
+            }
+
+            vmm
+        }
+
+        pub fn emulate_insn(
+            &mut self,
+            cpu_id: usize,
+            insn: &[u8],
+            num_insn: Option<usize>,
+        ) -> MockResult {
+            let ip = self.cpu_state(cpu_id).unwrap().ip();
+            let mut emulator = Emulator::new(self);
+
+            let new_state = emulator.emulate_insn_stream(cpu_id, &insn, num_insn)?;
+            if num_insn.is_none() {
+                assert_eq!(ip + insn.len() as u64, new_state.ip());
+            }
+
+            self.set_cpu_state(cpu_id, new_state).unwrap();
+
+            Ok(())
+        }
+
+        pub fn emulate_first_insn(&mut self, cpu_id: usize, insn: &[u8]) -> MockResult {
+            self.emulate_insn(cpu_id, insn, Some(1))
+        }
+    }
+
+    impl PlatformEmulator for MockVMM {
+        type CpuState = CpuState;
+
+        fn read_memory(&self, gva: u64, data: &mut [u8]) -> Result<(), PlatformError> {
+            debug!(
+                "Memory read {} bytes from [{:#x} -> {:#x}]",
+                data.len(),
+                gva,
+                gva
+            );
+            data.copy_from_slice(&self.memory[gva as usize..gva as usize + data.len()]);
+            Ok(())
+        }
+
+        fn write_memory(&mut self, gva: u64, data: &[u8]) -> Result<(), PlatformError> {
+            debug!(
+                "Memory write {} bytes at [{:#x} -> {:#x}]",
+                data.len(),
+                gva,
+                gva
+            );
+            self.memory[gva as usize..gva as usize + data.len()].copy_from_slice(data);
+
+            Ok(())
+        }
+
+        fn cpu_state(&self, _cpu_id: usize) -> Result<CpuState, PlatformError> {
+            Ok(self.state.lock().unwrap().clone())
+        }
+
+        fn set_cpu_state(
+            &self,
+            _cpu_id: usize,
+            state: Self::CpuState,
+        ) -> Result<(), PlatformError> {
+            *self.state.lock().unwrap() = state;
+            Ok(())
+        }
+
+        fn gva_to_gpa(&self, gva: u64) -> Result<u64, PlatformError> {
+            Ok(gva)
+        }
+
+        fn fetch(&self, ip: u64, instruction_bytes: &mut [u8]) -> Result<(), PlatformError> {
+            let rip = self
+                .state
+                .lock()
+                .unwrap()
+                .linearize(Register::CS, ip, false)?;
+            self.read_memory(rip, instruction_bytes)
+        }
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    #![allow(unused_mut)]
+    use super::*;
+    use crate::arch::x86::emulator::mock_vmm::*;
+
+    #[test]
+    // Emulate truncated instruction stream, which should cause a fetch.
+    //
+    // mov rax, 0x1000
+    // Test with a first instruction truncated.
+    fn test_fetch_first_instruction() -> MockResult {
+        let ip: u64 = 0x1000;
+        let cpu_id = 0;
+        let memory = [
+            // Code at IP
+            0x48, 0xc7, 0xc0, 0x00, 0x10, 0x00, 0x00, // mov rax, 0x1000
+            0x48, 0x8b, 0x58, 0x10, // mov rbx, qword ptr [rax+10h]
+            // Padding
+            0x00, 0x00, 0x00, 0x00, 0x00, // Padding is all zeroes
+            // Data at IP + 0x10 (0x1234567812345678 in LE)
+            0x78, 0x56, 0x34, 0x12, 0x78, 0x56, 0x34, 0x12,
+        ];
+        let insn = [
+            // First instruction is truncated
+            0x48, 0xc7, 0xc0, 0x00, // mov rax, 0x1000 -- Missing bytes: 0x00, 0x10, 0x00, 0x00,
+        ];
+
+        let mut vmm = MockVMM::new(ip, vec![], Some((ip, &memory)));
+        assert!(vmm.emulate_insn(cpu_id, &insn, Some(2)).is_ok());
+
+        let rax: u64 = vmm
+            .cpu_state(cpu_id)
+            .unwrap()
+            .read_reg(Register::RAX)
+            .unwrap();
+        assert_eq!(rax, ip);
+
+        Ok(())
+    }
+
+    #[test]
+    // Emulate truncated instruction stream, which should cause a fetch.
+    //
+    // mov rax, 0x1000
+    // mov rbx, qword ptr [rax+10h]
+    // Test with a 2nd instruction truncated.
+    fn test_fetch_second_instruction() -> MockResult {
+        let target_rax: u64 = 0x1234567812345678;
+        let ip: u64 = 0x1000;
+        let cpu_id = 0;
+        let memory = [
+            // Code at IP
+            0x48, 0xc7, 0xc0, 0x00, 0x10, 0x00, 0x00, // mov rax, 0x1000
+            0x48, 0x8b, 0x58, 0x10, // mov rbx, qword ptr [rax+10h]
+            // Padding
+            0x00, 0x00, 0x00, 0x00, 0x00, // Padding is all zeroes
+            // Data at IP + 0x10 (0x1234567812345678 in LE)
+            0x78, 0x56, 0x34, 0x12, 0x78, 0x56, 0x34, 0x12,
+        ];
+        let insn = [
+            0x48, 0xc7, 0xc0, 0x00, 0x10, 0x00, 0x00, // mov rax, 0x1000
+            0x48, 0x8b, // Truncated mov rbx, qword ptr [rax+10h] -- missing [0x58, 0x10]
+        ];
+
+        let mut vmm = MockVMM::new(ip, vec![], Some((ip, &memory)));
+        assert!(vmm.emulate_insn(cpu_id, &insn, Some(2)).is_ok());
+
+        let rbx: u64 = vmm
+            .cpu_state(cpu_id)
+            .unwrap()
+            .read_reg(Register::RBX)
+            .unwrap();
+        assert_eq!(rbx, target_rax);
+
+        Ok(())
+    }
+
+    #[test]
+    // Emulate truncated instruction stream, which should cause a fetch.
+    //
+    // mov rax, 0x1000
+    // Test with a first instruction truncated and a bad fetched instruction.
+    // Verify that the instruction emulation returns an error.
+    fn test_fetch_bad_insn() -> MockResult {
+        let ip: u64 = 0x1000;
+        let cpu_id = 0;
+        let memory = [
+            // Code at IP
+            0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+            0xff, 0xff,
+        ];
+        let insn = [
+            // First instruction is truncated
+            0x48, 0xc7, 0xc0, 0x00, // mov rax, 0x1000 -- Missing bytes: 0x00, 0x10, 0x00, 0x00,
+        ];
+
+        let mut vmm = MockVMM::new(ip, vec![], Some((ip, &memory)));
+        assert!(vmm.emulate_first_insn(cpu_id, &insn).is_err());
+
+        Ok(())
+    }
+}

hypervisor/src/arch/x86/gdt.rs

@@ -8,7 +8,7 @@
 // found in the LICENSE-BSD-3-Clause file.
 
 // For GDT details see arch/x86/include/asm/segment.h
-use hypervisor::x86_64::SegmentRegister;
+use crate::x86_64::SegmentRegister;
 
 /// Constructor for a conventional segment GDT (or LDT) entry. Derived from the kernel's segment.h.
 pub fn gdt_entry(flags: u16, base: u32, limit: u32) -> u64 {

hypervisor/src/arch/x86/mod.rs

@@ -11,6 +11,8 @@
 // Copyright © 2020, Microsoft Corporation
 //
 
+pub mod gdt;
+
 #[allow(non_upper_case_globals)]
 #[allow(non_camel_case_types)]
 #[allow(non_snake_case)]
@@ -28,9 +30,95 @@
 )]
 pub mod msr_index;
 
+pub mod emulator;
+
 // MTRR constants
 pub const MTRR_ENABLE: u64 = 0x800; // IA32_MTRR_DEF_TYPE MSR: E (MTRRs enabled) flag, bit 11
 pub const MTRR_MEM_TYPE_WB: u64 = 0x6;
 
 // IOAPIC pins
 pub const NUM_IOAPIC_PINS: usize = 24;
+
+// X86 Exceptions
+#[allow(dead_code)]
+#[derive(Clone, Debug)]
+pub enum Exception {
+    DE = 1,  // Divide Error
+    DB = 2,  // Debug Exception
+    BP = 3,  // Breakpoint
+    OF = 4,  // Overflow
+    BR = 5,  // BOUND Range Exceeded
+    UD = 6,  // Invalid/Undefined Opcode
+    NM = 7,  // No Math Coprocessor
+    DF = 8,  // Double Fault
+    TS = 10, // Invalid TSS
+    NP = 11, // Segment Not Present
+    SS = 12, // Stack Segment Fault
+    GP = 13, // General Protection
+    PF = 14, // Page Fault
+    MF = 16, // Math Fault
+    AC = 17, // Alignment Check
+    MC = 18, // Machine Check
+    XM = 19, // SIMD Floating-Point Exception
+    VE = 20, // Virtualization Exception
+    CP = 21, // Control Protection Exception
+}
+
+pub mod regs;
+
+// Abstracted segment register ops.
+// Each x86 hypervisor should implement those.
+pub trait SegmentRegisterOps {
+    // Segment type
+    fn segment_type(&self) -> u8;
+    fn set_segment_type(&mut self, val: u8);
+
+    // Descriptor Privilege Level (DPL)
+    fn dpl(&self) -> u8;
+    fn set_dpl(&mut self, val: u8);
+
+    // Granularity
+    fn granularity(&self) -> u8;
+    fn set_granularity(&mut self, val: u8);
+
+    // Memory Presence
+    fn present(&self) -> u8;
+    fn set_present(&mut self, val: u8);
+
+    // Long mode
+    fn long(&self) -> u8;
+    fn set_long(&mut self, val: u8);
+
+    // Available for system use (AVL)
+    fn avl(&self) -> u8;
+    fn set_avl(&mut self, val: u8);
+
+    // Descriptor type (System or code/data)
+    fn desc_type(&self) -> u8;
+    fn set_desc_type(&mut self, val: u8);
+
+    // D/B
+    fn db(&self) -> u8;
+    fn set_db(&mut self, val: u8);
+}
+
+// Code segment
+pub const CODE_SEGMENT_TYPE: u8 = 0x8;
+
+// Read/Write or Read/Exec segment
+pub const RWRX_SEGMENT_TYPE: u8 = 0x2;
+
+// Expand down segment
+pub const EXPAND_DOWN_SEGMENT_TYPE: u8 = 0x4;
+
+pub fn segment_type_code(t: u8) -> bool {
+    t & CODE_SEGMENT_TYPE != 0
+}
+
+pub fn segment_type_ro(t: u8) -> bool {
+    t & !RWRX_SEGMENT_TYPE == 0
+}
+
+pub fn segment_type_expand_down(t: u8) -> bool {
+    !segment_type_code(t) && (t & EXPAND_DOWN_SEGMENT_TYPE != 0)
+}

hypervisor/src/arch/x86/regs.rs

@@ -0,0 +1,32 @@
+//
+// Copyright © 2020 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+
+// EFER (technically not a register) bits
+pub const EFER_LMA: u64 = 0x400;
+pub const EFER_LME: u64 = 0x100;
+
+// CR0 bits
+pub const CR0_PE: u64 = 0x1;
+pub const CR0_PG: u64 = 0x80000000;
+
+// CR4 bits
+pub const CR4_PAE: u64 = 0x20;
+pub const CR4_LA57: u64 = 0x1000;
+
+// RFlags bits
+pub const CF_SHIFT: usize = 0;
+pub const PF_SHIFT: usize = 2;
+pub const AF_SHIFT: usize = 4;
+pub const ZF_SHIFT: usize = 6;
+pub const SF_SHIFT: usize = 7;
+pub const OF_SHIFT: usize = 11;
+
+pub const CF: u64 = 1 << CF_SHIFT;
+pub const PF: u64 = 1 << PF_SHIFT;
+pub const AF: u64 = 1 << AF_SHIFT;
+pub const ZF: u64 = 1 << ZF_SHIFT;
+pub const SF: u64 = 1 << SF_SHIFT;
+pub const OF: u64 = 1 << OF_SHIFT;

hypervisor/src/cpu.rs

@@ -10,13 +10,19 @@
 
 #[cfg(target_arch = "aarch64")]
 use crate::aarch64::VcpuInit;
-use crate::{CpuState, MpState};
-
+#[cfg(target_arch = "aarch64")]
+use crate::aarch64::{RegList, Register, StandardRegisters};
+#[cfg(target_arch = "x86_64")]
+use crate::x86_64::{CpuId, LapicState};
 #[cfg(target_arch = "x86_64")]
 use crate::x86_64::{
-    CpuId, ExtendedControlRegisters, FpuState, LapicState, MsrEntries, SpecialRegisters,
-    StandardRegisters, VcpuEvents, Xsave,
+    ExtendedControlRegisters, FpuState, MsrEntries, SpecialRegisters, StandardRegisters, VcpuEvents,
 };
+use crate::CpuState;
+#[cfg(feature = "kvm")]
+use crate::MpState;
+#[cfg(target_arch = "x86_64")]
+use crate::Xsave;
 use thiserror::Error;
 
 #[derive(Error, Debug)]
@@ -137,17 +143,61 @@ pub enum HypervisorCpuError {
     /// Setting one reg error
     ///
     #[error("Failed to init vcpu: {0}")]
-    SetOneReg(#[source] anyhow::Error),
+    SetRegister(#[source] anyhow::Error),
     ///
     /// Getting one reg error
     ///
     #[error("Failed to init vcpu: {0}")]
-    GetOneReg(#[source] anyhow::Error),
+    GetRegister(#[source] anyhow::Error),
     ///
     /// Getting guest clock paused error
     ///
     #[error("Failed to notify guest its clock was paused: {0}")]
     NotifyGuestClockPaused(#[source] anyhow::Error),
+    ///
+    /// Setting debug register error
+    ///
+    #[error("Failed to set debug registers: {0}")]
+    SetDebugRegs(#[source] anyhow::Error),
+    ///
+    /// Getting debug register error
+    ///
+    #[error("Failed to get debug registers: {0}")]
+    GetDebugRegs(#[source] anyhow::Error),
+    ///
+    /// Write to Guest Mem
+    ///
+    #[error("Failed to write to Guest Mem at: {0}")]
+    GuestMemWrite(#[source] anyhow::Error),
+    /// Enabling HyperV SynIC error
+    ///
+    #[error("Failed to enable HyperV SynIC")]
+    EnableHyperVSynIC(#[source] anyhow::Error),
+    ///
+    /// Getting AArch64 core register error
+    ///
+    #[error("Failed to get core register: {0}")]
+    GetCoreRegister(#[source] anyhow::Error),
+    ///
+    /// Setting AArch64 core register error
+    ///
+    #[error("Failed to set core register: {0}")]
+    SetCoreRegister(#[source] anyhow::Error),
+    ///
+    /// Getting AArch64 registers list error
+    ///
+    #[error("Failed to retrieve list of registers: {0}")]
+    GetRegList(#[source] anyhow::Error),
+    ///
+    /// Getting AArch64 system register error
+    ///
+    #[error("Failed to get system register: {0}")]
+    GetSysRegister(#[source] anyhow::Error),
+    ///
+    /// Setting AArch64 system register error
+    ///
+    #[error("Failed to set system register: {0}")]
+    SetSysRegister(#[source] anyhow::Error),
 }
 
 #[derive(Debug)]
@@ -162,6 +212,8 @@ pub enum VmExit<'a> {
     MmioWrite(u64 /* address */, &'a [u8]),
     Ignore,
     Reset,
+    Shutdown,
+    Hyperv,
 }
 
 ///
@@ -210,6 +262,11 @@ pub trait Vcpu: Send + Sync {
     fn set_cpuid2(&self, cpuid: &CpuId) -> Result<()>;
     #[cfg(target_arch = "x86_64")]
     ///
+    /// X86 specific call to enable HyperV SynIC
+    ///
+    fn enable_hyperv_synic(&self) -> Result<()>;
+    #[cfg(target_arch = "x86_64")]
+    ///
     /// X86 specific call to retrieve the CPUID registers.
     ///
     fn get_cpuid2(&self, num_entries: usize) -> Result<CpuId>;
@@ -233,10 +290,12 @@ pub trait Vcpu: Send + Sync {
     /// Setup the model-specific registers (MSR) for this vCPU.
     ///
     fn set_msrs(&self, msrs: &MsrEntries) -> Result<usize>;
+    #[cfg(feature = "kvm")]
     ///
     /// Returns the vcpu's current "multiprocessing state".
     ///
     fn get_mp_state(&self) -> Result<MpState>;
+    #[cfg(feature = "kvm")]
     ///
     /// Sets the vcpu's current "multiprocessing state".
     ///
@@ -273,7 +332,7 @@ pub trait Vcpu: Send + Sync {
     /// of the vcpu.
     ///
     fn set_vcpu_events(&self, events: &VcpuEvents) -> Result<()>;
-    #[cfg(target_arch = "x86_64")]
+    #[cfg(all(feature = "kvm", target_arch = "x86_64"))]
     ///
     /// Let the guest know that it has been paused, which prevents from
     /// potential soft lockups when being resumed.
@@ -288,12 +347,43 @@ pub trait Vcpu: Send + Sync {
     /// Sets the value of one register for this vCPU.
     ///
     #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
-    fn set_one_reg(&self, reg_id: u64, data: u64) -> Result<()>;
+    fn set_reg(&self, reg_id: u64, data: u64) -> Result<()>;
     ///
     /// Sets the value of one register for this vCPU.
     ///
     #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
-    fn get_one_reg(&self, reg_id: u64) -> Result<u64>;
+    fn get_reg(&self, reg_id: u64) -> Result<u64>;
+    ///
+    /// Gets a list of the guest registers that are supported for the
+    /// KVM_GET_ONE_REG/KVM_SET_ONE_REG calls.
+    ///
+    #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+    fn get_reg_list(&self, reg_list: &mut RegList) -> Result<()>;
+    ///
+    /// Save the state of the core registers.
+    ///
+    #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+    fn core_registers(&self, state: &mut StandardRegisters) -> Result<()>;
+    ///
+    /// Restore the state of the core registers.
+    ///
+    #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+    fn set_core_registers(&self, state: &StandardRegisters) -> Result<()>;
+    ///
+    /// Save the state of the system registers.
+    ///
+    #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+    fn system_registers(&self, state: &mut Vec<Register>) -> Result<()>;
+    ///
+    /// Restore the state of the system registers.
+    ///
+    #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+    fn set_system_registers(&self, state: &[Register]) -> Result<()>;
+    ///
+    /// Read the MPIDR - Multiprocessor Affinity Register.
+    ///
+    #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+    fn read_mpidr(&self) -> Result<u64>;
     ///
     /// Retrieve the vCPU state.
     /// This function is necessary to snapshot the VM
@@ -304,7 +394,6 @@ pub trait Vcpu: Send + Sync {
     /// This function is required when restoring the VM
     ///
     fn set_state(&self, state: &CpuState) -> Result<()>;
-
     ///
     /// Triggers the running of the current virtual CPU returning an exit reason.
     ///

hypervisor/src/device.rs

@@ -22,6 +22,11 @@ pub enum HypervisorDeviceError {
     ///
     #[error("Failed to set device attribute: {0}")]
     SetDeviceAttribute(#[source] anyhow::Error),
+    ///
+    /// Get device attribute error
+    ///
+    #[error("Failed to get device attribute: {0}")]
+    GetDeviceAttribute(#[source] anyhow::Error),
 }
 
 ///
@@ -37,4 +42,6 @@ pub type Result<T> = std::result::Result<T, HypervisorDeviceError>;
 pub trait Device: Send + Sync + AsRawFd {
     /// Set device attribute.
     fn set_device_attr(&self, attr: &DeviceAttr) -> Result<()>;
+    /// Get device attribute.
+    fn get_device_attr(&self, attr: &mut DeviceAttr) -> Result<()>;
 }

hypervisor/src/hypervisor.rs

@@ -9,8 +9,10 @@
 //
 use crate::vm::Vm;
 #[cfg(target_arch = "x86_64")]
-use crate::x86_64::{CpuId, MsrList};
+use crate::x86_64::CpuId;
 #[cfg(target_arch = "x86_64")]
+use crate::x86_64::MsrList;
+#[cfg(all(feature = "kvm", target_arch = "x86_64"))]
 use kvm_ioctls::Cap;
 use std::sync::Arc;
 
@@ -20,6 +22,11 @@ use thiserror::Error;
 ///
 ///
 pub enum HypervisorError {
+    ///
+    /// hypervisor creation error
+    ///
+    #[error("Failed to create the hypervisor: {0}")]
+    HypervisorCreate(#[source] anyhow::Error),
     ///
     /// Vm creation failure
     ///
@@ -46,20 +53,20 @@ pub enum HypervisorError {
     #[error("Failed to get number of max vcpus: {0}")]
     GetMaxVcpu(#[source] anyhow::Error),
     ///
-    /// Recommended Vcpu error
-    ///
-    #[error("Failed to get number of max vcpus: {0}")]
-    GetNrVcpus(#[source] anyhow::Error),
-    ///
     /// CpuId error
     ///
-    #[error("Failed to get number of max vcpus: {0}")]
+    #[error("Failed to get cpuid: {0}")]
     GetCpuId(#[source] anyhow::Error),
     ///
     /// Failed to retrieve list of MSRs.
     ///
     #[error("Failed to get the list of supported MSRs: {0}")]
     GetMsrList(#[source] anyhow::Error),
+    ///
+    /// API version is not compatible
+    ///
+    #[error("Incompatible API version")]
+    IncompatibleApiVersion,
 }
 
 ///
@@ -78,23 +85,22 @@ pub trait Hypervisor: Send + Sync {
     /// Return a hypervisor-agnostic Vm trait object
     ///
     fn create_vm(&self) -> Result<Arc<dyn Vm>>;
-    ///
-    /// Get the API version of the hypervisor
-    ///
-    fn get_api_version(&self) -> i32;
+    #[cfg(feature = "kvm")]
     ///
     /// Returns the size of the memory mapping required to use the vcpu's structures
     ///
     fn get_vcpu_mmap_size(&self) -> Result<usize>;
+    #[cfg(feature = "kvm")]
     ///
     /// Gets the recommended maximum number of VCPUs per VM.
     ///
     fn get_max_vcpus(&self) -> Result<usize>;
+    #[cfg(feature = "kvm")]
     ///
     /// Gets the recommended number of VCPUs per VM.
     ///
     fn get_nr_vcpus(&self) -> Result<usize>;
-    #[cfg(target_arch = "x86_64")]
+    #[cfg(all(feature = "kvm", target_arch = "x86_64"))]
     ///
     /// Checks if a particular `Cap` is available.
     ///
@@ -104,6 +110,7 @@ pub trait Hypervisor: Send + Sync {
     /// Get the supported CpuID
     ///
     fn get_cpuid(&self) -> Result<CpuId>;
+    #[cfg(not(feature = "mshv"))]
     ///
     /// Check particular extensions if any
     ///

hypervisor/src/kvm/aarch64/mod.rs

@@ -12,16 +12,134 @@
 /// Export generically-named wrappers of kvm-bindings for Unix-based platforms
 ///
 use crate::kvm::{KvmError, KvmResult};
-pub use kvm_bindings::kvm_vcpu_init as VcpuInit;
+use kvm_bindings::{
+    kvm_mp_state, kvm_one_reg, kvm_regs, KVM_REG_ARM64, KVM_REG_ARM64_SYSREG,
+    KVM_REG_ARM64_SYSREG_CRM_MASK, KVM_REG_ARM64_SYSREG_CRM_SHIFT, KVM_REG_ARM64_SYSREG_CRN_MASK,
+    KVM_REG_ARM64_SYSREG_CRN_SHIFT, KVM_REG_ARM64_SYSREG_OP0_MASK, KVM_REG_ARM64_SYSREG_OP0_SHIFT,
+    KVM_REG_ARM64_SYSREG_OP1_MASK, KVM_REG_ARM64_SYSREG_OP1_SHIFT, KVM_REG_ARM64_SYSREG_OP2_MASK,
+    KVM_REG_ARM64_SYSREG_OP2_SHIFT, KVM_REG_ARM_COPROC_MASK, KVM_REG_ARM_CORE, KVM_REG_SIZE_MASK,
+    KVM_REG_SIZE_U32, KVM_REG_SIZE_U64,
+};
+pub use kvm_bindings::{
+    kvm_one_reg as Register, kvm_regs as StandardRegisters, kvm_vcpu_init as VcpuInit, RegList,
+};
 use serde_derive::{Deserialize, Serialize};
 pub use {kvm_ioctls::Cap, kvm_ioctls::Kvm};
 
+// Following are macros that help with getting the ID of a aarch64 core register.
+// The core register are represented by the user_pt_regs structure. Look for it in
+// arch/arm64/include/uapi/asm/ptrace.h.
+
+// This macro gets the offset of a structure (i.e `str`) member (i.e `field`) without having
+// an instance of that structure.
+// It uses a null pointer to retrieve the offset to the field.
+// Inspired by C solution: `#define offsetof(str, f) ((size_t)(&((str *)0)->f))`.
+// Doing `offset__of!(user_pt_regs, pstate)` in our rust code will trigger the following:
+// unsafe { &(*(0 as *const user_pt_regs)).pstate as *const _ as usize }
+// The dereference expression produces an lvalue, but that lvalue is not actually read from,
+// we're just doing pointer math on it, so in theory, it should safe.
+#[macro_export]
+macro_rules! offset__of {
+    ($str:ty, $field:ident) => {
+        unsafe { &(*std::ptr::null::<$str>()).$field as *const _ as usize }
+    };
+}
+
+// Get the ID of a core register
+#[macro_export]
+macro_rules! arm64_core_reg_id {
+    ($size: tt, $offset: tt) => {
+        // The core registers of an arm64 machine are represented
+        // in kernel by the `kvm_regs` structure. This structure is a
+        // mix of 32, 64 and 128 bit fields:
+        // struct kvm_regs {
+        //     struct user_pt_regs      regs;
+        //
+        //     __u64                    sp_el1;
+        //     __u64                    elr_el1;
+        //
+        //     __u64                    spsr[KVM_NR_SPSR];
+        //
+        //     struct user_fpsimd_state fp_regs;
+        // };
+        // struct user_pt_regs {
+        //     __u64 regs[31];
+        //     __u64 sp;
+        //     __u64 pc;
+        //     __u64 pstate;
+        // };
+        // The id of a core register can be obtained like this:
+        // offset = id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE). Thus,
+        // id = KVM_REG_ARM64 | KVM_REG_SIZE_U64/KVM_REG_SIZE_U32/KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | offset
+        KVM_REG_ARM64 as u64
+            | u64::from(KVM_REG_ARM_CORE)
+            | $size
+            | (($offset / mem::size_of::<u32>()) as u64)
+    };
+}
+
+// This macro computes the ID of a specific ARM64 system register similar to how
+// the kernel C macro does.
+// https://elixir.bootlin.com/linux/v4.20.17/source/arch/arm64/include/uapi/asm/kvm.h#L203
+#[macro_export]
+macro_rules! arm64_sys_reg {
+    ($name: tt, $op0: tt, $op1: tt, $crn: tt, $crm: tt, $op2: tt) => {
+        pub const $name: u64 = KVM_REG_ARM64 as u64
+            | KVM_REG_SIZE_U64 as u64
+            | KVM_REG_ARM64_SYSREG as u64
+            | ((($op0 as u64) << KVM_REG_ARM64_SYSREG_OP0_SHIFT)
+                & KVM_REG_ARM64_SYSREG_OP0_MASK as u64)
+            | ((($op1 as u64) << KVM_REG_ARM64_SYSREG_OP1_SHIFT)
+                & KVM_REG_ARM64_SYSREG_OP1_MASK as u64)
+            | ((($crn as u64) << KVM_REG_ARM64_SYSREG_CRN_SHIFT)
+                & KVM_REG_ARM64_SYSREG_CRN_MASK as u64)
+            | ((($crm as u64) << KVM_REG_ARM64_SYSREG_CRM_SHIFT)
+                & KVM_REG_ARM64_SYSREG_CRM_MASK as u64)
+            | ((($op2 as u64) << KVM_REG_ARM64_SYSREG_OP2_SHIFT)
+                & KVM_REG_ARM64_SYSREG_OP2_MASK as u64);
+    };
+}
+
+// Constant imported from the Linux kernel:
+// https://elixir.bootlin.com/linux/v4.20.17/source/arch/arm64/include/asm/sysreg.h#L135
+arm64_sys_reg!(MPIDR_EL1, 3, 0, 0, 0, 5);
+
+/// Specifies whether a particular register is a system register or not.
+/// The kernel splits the registers on aarch64 in core registers and system registers.
+/// So, below we get the system registers by checking that they are not core registers.
+///
+/// # Arguments
+///
+/// * `regid` - The index of the register we are checking.
+pub fn is_system_register(regid: u64) -> bool {
+    if (regid & KVM_REG_ARM_COPROC_MASK as u64) == KVM_REG_ARM_CORE as u64 {
+        return false;
+    }
+
+    let size = regid & KVM_REG_SIZE_MASK;
+    if size != KVM_REG_SIZE_U32 && size != KVM_REG_SIZE_U64 {
+        panic!("Unexpected register size for system register {}", size);
+    }
+    true
+}
+
 pub fn check_required_kvm_extensions(kvm: &Kvm) -> KvmResult<()> {
     if !kvm.check_extension(Cap::SignalMsi) {
         return Err(KvmError::CapabilityMissing(Cap::SignalMsi));
     }
+    if !kvm.check_extension(Cap::OneReg) {
+        return Err(KvmError::CapabilityMissing(Cap::OneReg));
+    }
     Ok(())
 }
 
-#[derive(Clone, Serialize, Deserialize)]
-pub struct VcpuKvmState {}
+#[derive(Clone, Default, Serialize, Deserialize)]
+pub struct VcpuKvmState {
+    pub mp_state: kvm_mp_state,
+    pub core_regs: kvm_regs,
+    pub sys_regs: Vec<kvm_one_reg>,
+    // We will be using the mpidr for passing it to the VmState.
+    // The VmState will give this away for saving restoring the icc and redistributor
+    // registers.
+    pub mpidr: u64,
+}

hypervisor/src/kvm/mod.rs

@@ -8,20 +8,27 @@
 //
 //
 
+#[cfg(target_arch = "aarch64")]
+pub use crate::aarch64::{
+    check_required_kvm_extensions, is_system_register, VcpuInit, VcpuKvmState as CpuState,
+    MPIDR_EL1,
+};
+use crate::cpu;
+use crate::device;
+use crate::hypervisor;
+use crate::vm::{self, VmmOps};
+#[cfg(target_arch = "aarch64")]
+use crate::{arm64_core_reg_id, offset__of};
 use kvm_ioctls::{NoDatamatch, VcpuFd, VmFd};
+use serde_derive::{Deserialize, Serialize};
 use std::os::unix::io::{AsRawFd, RawFd};
 use std::result;
+#[cfg(target_arch = "x86_64")]
+use std::sync::atomic::{AtomicBool, Ordering};
 use std::sync::Arc;
 #[cfg(target_arch = "x86_64")]
 use vm_memory::Address;
 use vmm_sys_util::eventfd::EventFd;
-
-#[cfg(target_arch = "aarch64")]
-pub use crate::aarch64::{check_required_kvm_extensions, VcpuInit, VcpuKvmState as CpuState};
-use crate::cpu;
-use crate::device;
-use crate::hypervisor;
-use crate::vm;
 // x86_64 dependencies
 #[cfg(target_arch = "x86_64")]
 pub mod x86_64;
@@ -31,6 +38,9 @@ use x86_64::{
     check_required_kvm_extensions, FpuState, SpecialRegisters, StandardRegisters, KVM_TSS_ADDRESS,
 };
 
+#[cfg(target_arch = "aarch64")]
+use aarch64::{RegList, Register, StandardRegisters};
+
 #[cfg(target_arch = "x86_64")]
 pub use x86_64::{
     CpuId, CpuIdEntry, ExtendedControlRegisters, LapicState, MsrEntries, VcpuKvmState as CpuState,
@@ -38,7 +48,9 @@ pub use x86_64::{
 };
 
 #[cfg(target_arch = "x86_64")]
-use kvm_bindings::{kvm_enable_cap, MsrList, KVM_CAP_SPLIT_IRQCHIP};
+use kvm_bindings::{
+    kvm_enable_cap, kvm_msr_entry, MsrList, KVM_CAP_HYPERV_SYNIC, KVM_CAP_SPLIT_IRQCHIP,
+};
 
 #[cfg(target_arch = "x86_64")]
 use crate::arch::x86::NUM_IOAPIC_PINS;
@@ -46,11 +58,19 @@ use crate::arch::x86::NUM_IOAPIC_PINS;
 // aarch64 dependencies
 #[cfg(target_arch = "aarch64")]
 pub mod aarch64;
+#[cfg(target_arch = "aarch64")]
+use kvm_bindings::{
+    kvm_regs, user_fpsimd_state, user_pt_regs, KVM_NR_SPSR, KVM_REG_ARM64, KVM_REG_ARM_CORE,
+    KVM_REG_SIZE_U128, KVM_REG_SIZE_U32, KVM_REG_SIZE_U64,
+};
+#[cfg(target_arch = "aarch64")]
+use std::mem;
 
 pub use kvm_bindings;
 pub use kvm_bindings::{
     kvm_create_device, kvm_device_type_KVM_DEV_TYPE_VFIO, kvm_irq_routing, kvm_irq_routing_entry,
-    kvm_userspace_memory_region, KVM_IRQ_ROUTING_MSI, KVM_MEM_READONLY, KVM_MSI_VALID_DEVID,
+    kvm_userspace_memory_region, KVM_IRQ_ROUTING_MSI, KVM_MEM_LOG_DIRTY_PAGES, KVM_MEM_READONLY,
+    KVM_MSI_VALID_DEVID,
 };
 pub use kvm_ioctls;
 pub use kvm_ioctls::{Cap, Kvm};
@@ -66,12 +86,16 @@ pub use {
     kvm_bindings::kvm_vcpu_events as VcpuEvents, kvm_ioctls::DeviceFd, kvm_ioctls::IoEventAddress,
     kvm_ioctls::VcpuExit,
 };
+#[derive(Clone, Copy, Debug, PartialEq, Deserialize, Serialize)]
+pub struct KvmVmState {}
 
+pub use KvmVmState as VmState;
 /// Wrapper over KVM VM ioctls.
 pub struct KvmVm {
     fd: Arc<VmFd>,
     #[cfg(target_arch = "x86_64")]
     msrs: MsrEntries,
+    state: KvmVmState,
 }
 
 // Returns a `Vec<T>` with a size in bytes at least as large as `size_in_bytes`.
@@ -151,7 +175,11 @@ impl vm::Vm for KvmVm {
     ///
     /// Creates a VcpuFd object from a vcpu RawFd.
     ///
-    fn create_vcpu(&self, id: u8) -> vm::Result<Arc<dyn cpu::Vcpu>> {
+    fn create_vcpu(
+        &self,
+        id: u8,
+        vmmops: Option<Arc<Box<dyn VmmOps>>>,
+    ) -> vm::Result<Arc<dyn cpu::Vcpu>> {
         let vc = self
             .fd
             .create_vcpu(id)
@@ -160,6 +188,9 @@ impl vm::Vm for KvmVm {
             fd: vc,
             #[cfg(target_arch = "x86_64")]
             msrs: self.msrs.clone(),
+            vmmops,
+            #[cfg(target_arch = "x86_64")]
+            hyperv_synic: AtomicBool::new(false),
         };
         Ok(Arc::new(vcpu))
     }
@@ -227,13 +258,19 @@ impl vm::Vm for KvmVm {
         memory_size: u64,
         userspace_addr: u64,
         readonly: bool,
+        log_dirty_pages: bool,
     ) -> MemoryRegion {
         MemoryRegion {
             slot,
             guest_phys_addr,
             memory_size,
             userspace_addr,
-            flags: if readonly { KVM_MEM_READONLY } else { 0 },
+            flags: if readonly { KVM_MEM_READONLY } else { 0 }
+                | if log_dirty_pages {
+                    KVM_MEM_LOG_DIRTY_PAGES
+                } else {
+                    0
+                },
         }
     }
     ///
@@ -314,6 +351,27 @@ impl vm::Vm for KvmVm {
         self.create_device(&mut vfio_dev)
             .map_err(|e| vm::HypervisorVmError::CreatePassthroughDevice(e.into()))
     }
+    ///
+    /// Get the Vm state. Return VM specific data
+    ///
+    fn state(&self) -> vm::Result<VmState> {
+        Ok(self.state)
+    }
+    ///
+    /// Set the VM state
+    ///
+    fn set_state(&self, _state: VmState) -> vm::Result<()> {
+        Ok(())
+    }
+
+    ///
+    /// Get dirty pages bitmap (one bit per page)
+    ///
+    fn get_dirty_log(&self, slot: u32, memory_size: u64) -> vm::Result<Vec<u64>> {
+        self.fd
+            .get_dirty_log(slot, memory_size as usize)
+            .map_err(|e| vm::HypervisorVmError::GetDirtyLog(e.into()))
+    }
 }
 /// Wrapper over KVM system ioctls.
 pub struct KvmHypervisor {
@@ -329,6 +387,12 @@ impl KvmHypervisor {
     /// Create a hypervisor based on Kvm
     pub fn new() -> hypervisor::Result<KvmHypervisor> {
         let kvm_obj = Kvm::new().map_err(|e| hypervisor::HypervisorError::VmCreate(e.into()))?;
+        let api_version = kvm_obj.get_api_version();
+
+        if api_version != kvm_bindings::KVM_API_VERSION as i32 {
+            return Err(hypervisor::HypervisorError::IncompatibleApiVersion);
+        }
+
         Ok(KvmHypervisor { kvm: kvm_obj })
     }
 }
@@ -381,12 +445,19 @@ impl hypervisor::Hypervisor for KvmHypervisor {
                 msr_entries[pos].index = *index;
             }
 
-            Ok(Arc::new(KvmVm { fd: vm_fd, msrs }))
+            Ok(Arc::new(KvmVm {
+                fd: vm_fd,
+                msrs,
+                state: VmState {},
+            }))
         }
 
         #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
         {
-            Ok(Arc::new(KvmVm { fd: vm_fd }))
+            Ok(Arc::new(KvmVm {
+                fd: vm_fd,
+                state: VmState {},
+            }))
         }
     }
 
@@ -395,12 +466,6 @@ impl hypervisor::Hypervisor for KvmHypervisor {
         Ok(())
     }
 
-    ///
-    /// Returns the KVM API version.
-    ///
-    fn get_api_version(&self) -> i32 {
-        self.kvm.get_api_version()
-    }
     ///
     ///  Returns the size of the memory mapping required to use the vcpu's `kvm_run` structure.
     ///
@@ -452,6 +517,9 @@ pub struct KvmVcpu {
     fd: VcpuFd,
     #[cfg(target_arch = "x86_64")]
     msrs: MsrEntries,
+    vmmops: Option<Arc<Box<dyn vm::VmmOps>>>,
+    #[cfg(target_arch = "x86_64")]
+    hyperv_synic: AtomicBool,
 }
 /// Implementation of Vcpu trait for KVM
 /// Example:
@@ -460,7 +528,7 @@ pub struct KvmVcpu {
 /// let kvm = hypervisor::kvm::KvmHypervisor::new().unwrap();
 /// let hypervisor: Arc<dyn hypervisor::Hypervisor> = Arc::new(kvm);
 /// let vm = hypervisor.create_vm().expect("new VM fd creation failed");
-/// let vcpu = vm.create_vcpu(0).unwrap();
+/// let vcpu = vm.create_vcpu(0, None).unwrap();
 /// vcpu.get/set().unwrap()
 ///
 impl cpu::Vcpu for KvmVcpu {
@@ -527,6 +595,21 @@ impl cpu::Vcpu for KvmVcpu {
             .set_cpuid2(cpuid)
             .map_err(|e| cpu::HypervisorCpuError::SetCpuid(e.into()))
     }
+    #[cfg(target_arch = "x86_64")]
+    ///
+    /// X86 specific call to enable HyperV SynIC
+    ///
+    fn enable_hyperv_synic(&self) -> cpu::Result<()> {
+        // Update the information about Hyper-V SynIC being enabled and
+        // emulated as it will influence later which MSRs should be saved.
+        self.hyperv_synic.store(true, Ordering::Release);
+
+        let mut cap: kvm_enable_cap = Default::default();
+        cap.cap = KVM_CAP_HYPERV_SYNIC;
+        self.fd
+            .enable_cap(&cap)
+            .map_err(|e| cpu::HypervisorCpuError::EnableHyperVSynIC(e.into()))
+    }
     ///
     /// X86 specific call to retrieve the CPUID registers.
     ///
@@ -632,9 +715,27 @@ impl cpu::Vcpu for KvmVcpu {
         match self.fd.run() {
             Ok(run) => match run {
                 #[cfg(target_arch = "x86_64")]
-                VcpuExit::IoIn(addr, data) => Ok(cpu::VmExit::IoIn(addr, data)),
+                VcpuExit::IoIn(addr, data) => {
+                    if let Some(vmmops) = &self.vmmops {
+                        return vmmops
+                            .pio_read(addr.into(), data)
+                            .map(|_| cpu::VmExit::Ignore)
+                            .map_err(|e| cpu::HypervisorCpuError::RunVcpu(e.into()));
+                    }
+
+                    Ok(cpu::VmExit::IoIn(addr, data))
+                }
                 #[cfg(target_arch = "x86_64")]
-                VcpuExit::IoOut(addr, data) => Ok(cpu::VmExit::IoOut(addr, data)),
+                VcpuExit::IoOut(addr, data) => {
+                    if let Some(vmmops) = &self.vmmops {
+                        return vmmops
+                            .pio_write(addr.into(), data)
+                            .map(|_| cpu::VmExit::Ignore)
+                            .map_err(|e| cpu::HypervisorCpuError::RunVcpu(e.into()));
+                    }
+
+                    Ok(cpu::VmExit::IoOut(addr, data))
+                }
                 #[cfg(target_arch = "x86_64")]
                 VcpuExit::IoapicEoi(vector) => Ok(cpu::VmExit::IoapicEoi(vector)),
                 #[cfg(target_arch = "x86_64")]
@@ -642,11 +743,13 @@ impl cpu::Vcpu for KvmVcpu {
 
                 #[cfg(target_arch = "aarch64")]
                 VcpuExit::SystemEvent(event_type, flags) => {
-                    use kvm_bindings::KVM_SYSTEM_EVENT_SHUTDOWN;
+                    use kvm_bindings::{KVM_SYSTEM_EVENT_RESET, KVM_SYSTEM_EVENT_SHUTDOWN};
                     // On Aarch64, when the VM is shutdown, run() returns
                     // VcpuExit::SystemEvent with reason KVM_SYSTEM_EVENT_SHUTDOWN
-                    if event_type == KVM_SYSTEM_EVENT_SHUTDOWN {
+                    if event_type == KVM_SYSTEM_EVENT_RESET {
                         Ok(cpu::VmExit::Reset)
+                    } else if event_type == KVM_SYSTEM_EVENT_SHUTDOWN {
+                        Ok(cpu::VmExit::Shutdown)
                     } else {
                         Err(cpu::HypervisorCpuError::RunVcpu(anyhow!(
                             "Unexpected system event with type 0x{:x}, flags 0x{:x}",
@@ -656,8 +759,27 @@ impl cpu::Vcpu for KvmVcpu {
                     }
                 }
 
-                VcpuExit::MmioRead(addr, data) => Ok(cpu::VmExit::MmioRead(addr, data)),
-                VcpuExit::MmioWrite(addr, data) => Ok(cpu::VmExit::MmioWrite(addr, data)),
+                VcpuExit::MmioRead(addr, data) => {
+                    if let Some(vmmops) = &self.vmmops {
+                        return vmmops
+                            .mmio_read(addr, data)
+                            .map(|_| cpu::VmExit::Ignore)
+                            .map_err(|e| cpu::HypervisorCpuError::RunVcpu(e.into()));
+                    }
+
+                    Ok(cpu::VmExit::MmioRead(addr, data))
+                }
+                VcpuExit::MmioWrite(addr, data) => {
+                    if let Some(vmmops) = &self.vmmops {
+                        return vmmops
+                            .mmio_write(addr, data)
+                            .map(|_| cpu::VmExit::Ignore)
+                            .map_err(|e| cpu::HypervisorCpuError::RunVcpu(e.into()));
+                    }
+
+                    Ok(cpu::VmExit::MmioWrite(addr, data))
+                }
+                VcpuExit::Hyperv => Ok(cpu::VmExit::Hyperv),
 
                 r => Err(cpu::HypervisorCpuError::RunVcpu(anyhow!(
                     "Unexpected exit reason on vcpu run: {:?}",
@@ -714,19 +836,263 @@ impl cpu::Vcpu for KvmVcpu {
     /// Sets the value of one register for this vCPU.
     ///
     #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
-    fn set_one_reg(&self, reg_id: u64, data: u64) -> cpu::Result<()> {
+    fn set_reg(&self, reg_id: u64, data: u64) -> cpu::Result<()> {
         self.fd
             .set_one_reg(reg_id, data)
-            .map_err(|e| cpu::HypervisorCpuError::SetOneReg(e.into()))
+            .map_err(|e| cpu::HypervisorCpuError::SetRegister(e.into()))
     }
     ///
     /// Gets the value of one register for this vCPU.
     ///
     #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
-    fn get_one_reg(&self, reg_id: u64) -> cpu::Result<u64> {
+    fn get_reg(&self, reg_id: u64) -> cpu::Result<u64> {
         self.fd
             .get_one_reg(reg_id)
-            .map_err(|e| cpu::HypervisorCpuError::GetOneReg(e.into()))
+            .map_err(|e| cpu::HypervisorCpuError::GetRegister(e.into()))
+    }
+    ///
+    /// Gets a list of the guest registers that are supported for the
+    /// KVM_GET_ONE_REG/KVM_SET_ONE_REG calls.
+    ///
+    #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+    fn get_reg_list(&self, reg_list: &mut RegList) -> cpu::Result<()> {
+        self.fd
+            .get_reg_list(reg_list)
+            .map_err(|e| cpu::HypervisorCpuError::GetRegList(e.into()))
+    }
+    ///
+    /// Save the state of the core registers.
+    ///
+    #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+    fn core_registers(&self, state: &mut StandardRegisters) -> cpu::Result<()> {
+        let mut off = offset__of!(user_pt_regs, regs);
+        // There are 31 user_pt_regs:
+        // https://elixir.free-electrons.com/linux/v4.14.174/source/arch/arm64/include/uapi/asm/ptrace.h#L72
+        // These actually are the general-purpose registers of the Armv8-a
+        // architecture (i.e x0-x30 if used as a 64bit register or w0-30 when used as a 32bit register).
+        for i in 0..31 {
+            state.regs.regs[i] = self
+                .fd
+                .get_one_reg(arm64_core_reg_id!(KVM_REG_SIZE_U64, off))
+                .map_err(|e| cpu::HypervisorCpuError::GetCoreRegister(e.into()))?;
+            off += std::mem::size_of::<u64>();
+        }
+
+        // We are now entering the "Other register" section of the ARMv8-a architecture.
+        // First one, stack pointer.
+        let off = offset__of!(user_pt_regs, sp);
+        state.regs.sp = self
+            .fd
+            .get_one_reg(arm64_core_reg_id!(KVM_REG_SIZE_U64, off))
+            .map_err(|e| cpu::HypervisorCpuError::GetCoreRegister(e.into()))?;
+
+        // Second one, the program counter.
+        let off = offset__of!(user_pt_regs, pc);
+        state.regs.pc = self
+            .fd
+            .get_one_reg(arm64_core_reg_id!(KVM_REG_SIZE_U64, off))
+            .map_err(|e| cpu::HypervisorCpuError::GetCoreRegister(e.into()))?;
+
+        // Next is the processor state.
+        let off = offset__of!(user_pt_regs, pstate);
+        state.regs.pstate = self
+            .fd
+            .get_one_reg(arm64_core_reg_id!(KVM_REG_SIZE_U64, off))
+            .map_err(|e| cpu::HypervisorCpuError::GetCoreRegister(e.into()))?;
+
+        // The stack pointer associated with EL1
+        let off = offset__of!(kvm_regs, sp_el1);
+        state.sp_el1 = self
+            .fd
+            .get_one_reg(arm64_core_reg_id!(KVM_REG_SIZE_U64, off))
+            .map_err(|e| cpu::HypervisorCpuError::GetCoreRegister(e.into()))?;
+
+        // Exception Link Register for EL1, when taking an exception to EL1, this register
+        // holds the address to which to return afterwards.
+        let off = offset__of!(kvm_regs, elr_el1);
+        state.elr_el1 = self
+            .fd
+            .get_one_reg(arm64_core_reg_id!(KVM_REG_SIZE_U64, off))
+            .map_err(|e| cpu::HypervisorCpuError::GetCoreRegister(e.into()))?;
+
+        // Saved Program Status Registers, there are 5 of them used in the kernel.
+        let mut off = offset__of!(kvm_regs, spsr);
+        for i in 0..KVM_NR_SPSR as usize {
+            state.spsr[i] = self
+                .fd
+                .get_one_reg(arm64_core_reg_id!(KVM_REG_SIZE_U64, off))
+                .map_err(|e| cpu::HypervisorCpuError::GetCoreRegister(e.into()))?;
+            off += std::mem::size_of::<u64>();
+        }
+
+        // Now moving on to floting point registers which are stored in the user_fpsimd_state in the kernel:
+        // https://elixir.free-electrons.com/linux/v4.9.62/source/arch/arm64/include/uapi/asm/kvm.h#L53
+        let mut off = offset__of!(kvm_regs, fp_regs) + offset__of!(user_fpsimd_state, vregs);
+        for i in 0..32 {
+            state.fp_regs.vregs[i][0] = self
+                .fd
+                .get_one_reg(arm64_core_reg_id!(KVM_REG_SIZE_U128, off))
+                .map_err(|e| cpu::HypervisorCpuError::GetCoreRegister(e.into()))?;
+            off += mem::size_of::<u128>();
+        }
+
+        // Floating-point Status Register
+        let off = offset__of!(kvm_regs, fp_regs) + offset__of!(user_fpsimd_state, fpsr);
+        state.fp_regs.fpsr = self
+            .fd
+            .get_one_reg(arm64_core_reg_id!(KVM_REG_SIZE_U32, off))
+            .map_err(|e| cpu::HypervisorCpuError::GetCoreRegister(e.into()))?
+            as u32;
+
+        // Floating-point Control Register
+        let off = offset__of!(kvm_regs, fp_regs) + offset__of!(user_fpsimd_state, fpcr);
+        state.fp_regs.fpcr = self
+            .fd
+            .get_one_reg(arm64_core_reg_id!(KVM_REG_SIZE_U32, off))
+            .map_err(|e| cpu::HypervisorCpuError::GetCoreRegister(e.into()))?
+            as u32;
+        Ok(())
+    }
+    ///
+    /// Restore the state of the core registers.
+    ///
+    #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+    fn set_core_registers(&self, state: &StandardRegisters) -> cpu::Result<()> {
+        // The function follows the exact identical order from `state`. Look there
+        // for some additional info on registers.
+        let mut off = offset__of!(user_pt_regs, regs);
+        for i in 0..31 {
+            self.fd
+                .set_one_reg(
+                    arm64_core_reg_id!(KVM_REG_SIZE_U64, off),
+                    state.regs.regs[i],
+                )
+                .map_err(|e| cpu::HypervisorCpuError::SetCoreRegister(e.into()))?;
+            off += std::mem::size_of::<u64>();
+        }
+
+        let off = offset__of!(user_pt_regs, sp);
+        self.fd
+            .set_one_reg(arm64_core_reg_id!(KVM_REG_SIZE_U64, off), state.regs.sp)
+            .map_err(|e| cpu::HypervisorCpuError::SetCoreRegister(e.into()))?;
+
+        let off = offset__of!(user_pt_regs, pc);
+        self.fd
+            .set_one_reg(arm64_core_reg_id!(KVM_REG_SIZE_U64, off), state.regs.pc)
+            .map_err(|e| cpu::HypervisorCpuError::SetCoreRegister(e.into()))?;
+
+        let off = offset__of!(user_pt_regs, pstate);
+        self.fd
+            .set_one_reg(arm64_core_reg_id!(KVM_REG_SIZE_U64, off), state.regs.pstate)
+            .map_err(|e| cpu::HypervisorCpuError::SetCoreRegister(e.into()))?;
+
+        let off = offset__of!(kvm_regs, sp_el1);
+        self.fd
+            .set_one_reg(arm64_core_reg_id!(KVM_REG_SIZE_U64, off), state.sp_el1)
+            .map_err(|e| cpu::HypervisorCpuError::SetCoreRegister(e.into()))?;
+
+        let off = offset__of!(kvm_regs, elr_el1);
+        self.fd
+            .set_one_reg(arm64_core_reg_id!(KVM_REG_SIZE_U64, off), state.elr_el1)
+            .map_err(|e| cpu::HypervisorCpuError::SetCoreRegister(e.into()))?;
+
+        let mut off = offset__of!(kvm_regs, spsr);
+        for i in 0..KVM_NR_SPSR as usize {
+            self.fd
+                .set_one_reg(arm64_core_reg_id!(KVM_REG_SIZE_U64, off), state.spsr[i])
+                .map_err(|e| cpu::HypervisorCpuError::SetCoreRegister(e.into()))?;
+            off += std::mem::size_of::<u64>();
+        }
+
+        let mut off = offset__of!(kvm_regs, fp_regs) + offset__of!(user_fpsimd_state, vregs);
+        for i in 0..32 {
+            self.fd
+                .set_one_reg(
+                    arm64_core_reg_id!(KVM_REG_SIZE_U128, off),
+                    state.fp_regs.vregs[i][0],
+                )
+                .map_err(|e| cpu::HypervisorCpuError::SetCoreRegister(e.into()))?;
+            off += mem::size_of::<u128>();
+        }
+
+        let off = offset__of!(kvm_regs, fp_regs) + offset__of!(user_fpsimd_state, fpsr);
+        self.fd
+            .set_one_reg(
+                arm64_core_reg_id!(KVM_REG_SIZE_U32, off),
+                state.fp_regs.fpsr as u64,
+            )
+            .map_err(|e| cpu::HypervisorCpuError::SetCoreRegister(e.into()))?;
+
+        let off = offset__of!(kvm_regs, fp_regs) + offset__of!(user_fpsimd_state, fpcr);
+        self.fd
+            .set_one_reg(
+                arm64_core_reg_id!(KVM_REG_SIZE_U32, off),
+                state.fp_regs.fpcr as u64,
+            )
+            .map_err(|e| cpu::HypervisorCpuError::SetCoreRegister(e.into()))?;
+        Ok(())
+    }
+    ///
+    /// Save the state of the system registers.
+    ///
+    #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+    fn system_registers(&self, state: &mut Vec<Register>) -> cpu::Result<()> {
+        // Call KVM_GET_REG_LIST to get all registers available to the guest. For ArmV8 there are
+        // around 500 registers.
+        let mut reg_list = RegList::new(512);
+        self.fd
+            .get_reg_list(&mut reg_list)
+            .map_err(|e| cpu::HypervisorCpuError::GetRegList(e.into()))?;
+
+        // At this point reg_list should contain: core registers and system registers.
+        // The register list contains the number of registers and their ids. We will be needing to
+        // call KVM_GET_ONE_REG on each id in order to save all of them. We carve out from the list
+        // the core registers which are represented in the kernel by kvm_regs structure and for which
+        // we can calculate the id based on the offset in the structure.
+
+        reg_list.retain(|regid| *regid != 0);
+        reg_list.as_slice().to_vec().sort_unstable();
+
+        reg_list.retain(|regid| is_system_register(*regid));
+
+        // Now, for the rest of the registers left in the previously fetched register list, we are
+        // simply calling KVM_GET_ONE_REG.
+        let indices = reg_list.as_slice();
+        for (_pos, index) in indices.iter().enumerate() {
+            if _pos > 230 {
+                break;
+            }
+            state.push(kvm_bindings::kvm_one_reg {
+                id: *index,
+                addr: self
+                    .fd
+                    .get_one_reg(*index)
+                    .map_err(|e| cpu::HypervisorCpuError::GetSysRegister(e.into()))?,
+            });
+        }
+
+        Ok(())
+    }
+    ///
+    /// Restore the state of the system registers.
+    ///
+    #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+    fn set_system_registers(&self, state: &[Register]) -> cpu::Result<()> {
+        for reg in state {
+            self.fd
+                .set_one_reg(reg.id, reg.addr)
+                .map_err(|e| cpu::HypervisorCpuError::SetSysRegister(e.into()))?;
+        }
+        Ok(())
+    }
+    ///
+    /// Read the MPIDR - Multiprocessor Affinity Register.
+    ///
+    #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+    fn read_mpidr(&self) -> cpu::Result<u64> {
+        self.fd
+            .get_one_reg(MPIDR_EL1)
+            .map_err(|e| cpu::HypervisorCpuError::GetSysRegister(e.into()))
     }
     #[cfg(target_arch = "x86_64")]
     ///
@@ -763,10 +1129,11 @@ impl cpu::Vcpu for KvmVcpu {
     /// let hv: Arc<dyn hypervisor::Hypervisor> = Arc::new(kvm);
     /// let vm = hv.create_vm().expect("new VM fd creation failed");
     /// vm.enable_split_irq().unwrap();
-    /// let vcpu = vm.create_vcpu(0).unwrap();
+    /// let vcpu = vm.create_vcpu(0, None).unwrap();
     /// let state = vcpu.state().unwrap();
     /// ```
     fn state(&self) -> cpu::Result<CpuState> {
+        let cpuid = self.get_cpuid2(kvm_bindings::KVM_MAX_CPUID_ENTRIES)?;
         let mp_state = self.get_mp_state()?;
         let regs = self.get_regs()?;
         let sregs = self.get_sregs()?;
@@ -781,6 +1148,26 @@ impl cpu::Vcpu for KvmVcpu {
         // by chunks. This is the only way to make sure we try to get as many
         // MSRs as possible, even if some MSRs are not supported.
         let mut msr_entries = self.msrs.clone();
+
+        // Save extra MSRs if the Hyper-V synthetic interrupt controller is
+        // emulated.
+        if self.hyperv_synic.load(Ordering::Acquire) {
+            let hyperv_synic_msrs = vec![
+                0x40000020, 0x40000021, 0x40000080, 0x40000081, 0x40000082, 0x40000083, 0x40000084,
+                0x40000090, 0x40000091, 0x40000092, 0x40000093, 0x40000094, 0x40000095, 0x40000096,
+                0x40000097, 0x40000098, 0x40000099, 0x4000009a, 0x4000009b, 0x4000009c, 0x4000009d,
+                0x4000009f, 0x400000b0, 0x400000b1, 0x400000b2, 0x400000b3, 0x400000b4, 0x400000b5,
+                0x400000b6, 0x400000b7,
+            ];
+            for index in hyperv_synic_msrs {
+                let msr = kvm_msr_entry {
+                    index,
+                    ..Default::default()
+                };
+                msr_entries.push(msr).unwrap();
+            }
+        }
+
         let expected_num_msrs = msr_entries.as_fam_struct_ref().nmsrs as usize;
         let num_msrs = self.get_msrs(&mut msr_entries)?;
         let msrs = if num_msrs != expected_num_msrs {
@@ -826,6 +1213,7 @@ impl cpu::Vcpu for KvmVcpu {
         let vcpu_events = self.get_vcpu_events()?;
 
         Ok(CpuState {
+            cpuid,
             msrs,
             vcpu_events,
             regs,
@@ -837,9 +1225,19 @@ impl cpu::Vcpu for KvmVcpu {
             mp_state,
         })
     }
+    ///
+    /// Get the current AArch64 CPU state
+    ///
     #[cfg(target_arch = "aarch64")]
     fn state(&self) -> cpu::Result<CpuState> {
-        unimplemented!();
+        let mut state = CpuState::default();
+        // Get this vCPUs multiprocessing state.
+        state.mp_state = self.get_mp_state()?;
+        self.core_registers(&mut state.core_regs)?;
+        self.system_registers(&mut state.sys_regs)?;
+        state.mpidr = self.read_mpidr()?;
+
+        Ok(state)
     }
     #[cfg(target_arch = "x86_64")]
     ///
@@ -877,11 +1275,12 @@ impl cpu::Vcpu for KvmVcpu {
     /// let hv: Arc<dyn hypervisor::Hypervisor> = Arc::new(kvm);
     /// let vm = hv.create_vm().expect("new VM fd creation failed");
     /// vm.enable_split_irq().unwrap();
-    /// let vcpu = vm.create_vcpu(0).unwrap();
+    /// let vcpu = vm.create_vcpu(0, None).unwrap();
     /// let state = vcpu.state().unwrap();
     /// vcpu.set_state(&state).unwrap();
     /// ```
     fn set_state(&self, state: &CpuState) -> cpu::Result<()> {
+        self.set_cpuid2(&state.cpuid)?;
         self.set_mp_state(state.mp_state)?;
         self.set_regs(&state.regs)?;
         self.set_sregs(&state.sregs)?;
@@ -923,9 +1322,15 @@ impl cpu::Vcpu for KvmVcpu {
 
         Ok(())
     }
-    #[allow(unused_variables)]
+    ///
+    /// Restore the previously saved AArch64 CPU state
+    ///
     #[cfg(target_arch = "aarch64")]
     fn set_state(&self, state: &CpuState) -> cpu::Result<()> {
+        self.set_core_registers(&state.core_regs)?;
+        self.set_system_registers(&state.sys_regs)?;
+        self.set_mp_state(state.mp_state)?;
+
         Ok(())
     }
 }
@@ -944,6 +1349,14 @@ impl device::Device for KvmDevice {
             .set_device_attr(attr)
             .map_err(|e| device::HypervisorDeviceError::SetDeviceAttribute(e.into()))
     }
+    ///
+    /// Get device attribute
+    ///
+    fn get_device_attr(&self, attr: &mut DeviceAttr) -> device::Result<()> {
+        self.fd
+            .get_device_attr(attr)
+            .map_err(|e| device::HypervisorDeviceError::GetDeviceAttribute(e.into()))
+    }
 }
 
 impl AsRawFd for KvmDevice {

hypervisor/src/kvm/x86_64/mod.rs

@@ -10,7 +10,7 @@
 
 use vm_memory::GuestAddress;
 
-use crate::arch::x86::{msr_index, MTRR_ENABLE, MTRR_MEM_TYPE_WB};
+use crate::arch::x86::{msr_index, SegmentRegisterOps, MTRR_ENABLE, MTRR_MEM_TYPE_WB};
 use crate::kvm::{Cap, Kvm, KvmError, KvmResult};
 use serde_derive::{Deserialize, Serialize};
 
@@ -28,6 +28,71 @@ pub use {
     kvm_bindings::KVM_CPUID_FLAG_SIGNIFCANT_INDEX as CPUID_FLAG_VALID_INDEX,
 };
 
+impl SegmentRegisterOps for SegmentRegister {
+    fn segment_type(&self) -> u8 {
+        self.type_
+    }
+    fn set_segment_type(&mut self, val: u8) {
+        self.type_ = val;
+    }
+
+    fn dpl(&self) -> u8 {
+        self.dpl
+    }
+
+    fn set_dpl(&mut self, val: u8) {
+        self.dpl = val;
+    }
+
+    fn present(&self) -> u8 {
+        self.present
+    }
+
+    fn set_present(&mut self, val: u8) {
+        self.present = val;
+    }
+
+    fn long(&self) -> u8 {
+        self.l
+    }
+
+    fn set_long(&mut self, val: u8) {
+        self.l = val;
+    }
+
+    fn avl(&self) -> u8 {
+        self.avl
+    }
+
+    fn set_avl(&mut self, val: u8) {
+        self.avl = val;
+    }
+
+    fn desc_type(&self) -> u8 {
+        self.s
+    }
+
+    fn set_desc_type(&mut self, val: u8) {
+        self.s = val;
+    }
+
+    fn granularity(&self) -> u8 {
+        self.g
+    }
+
+    fn set_granularity(&mut self, val: u8) {
+        self.g = val;
+    }
+
+    fn db(&self) -> u8 {
+        self.db
+    }
+
+    fn set_db(&mut self, val: u8) {
+        self.db = val;
+    }
+}
+
 pub const KVM_TSS_ADDRESS: GuestAddress = GuestAddress(0xfffb_d000);
 
 macro_rules! msr {
@@ -85,6 +150,7 @@ pub fn check_required_kvm_extensions(kvm: &Kvm) -> KvmResult<()> {
 }
 #[derive(Clone, Serialize, Deserialize)]
 pub struct VcpuKvmState {
+    pub cpuid: CpuId,
     pub msrs: MsrEntries,
     pub vcpu_events: VcpuEvents,
     pub regs: StandardRegisters,

hypervisor/src/lib.rs

@@ -20,6 +20,7 @@
 
 #[macro_use]
 extern crate anyhow;
+#[cfg(target_arch = "x86_64")]
 #[macro_use]
 extern crate log;
 extern crate serde;
@@ -27,9 +28,14 @@ extern crate serde_derive;
 extern crate serde_json;
 extern crate thiserror;
 
+#[cfg(feature = "kvm")]
 /// KVM implementation module
 pub mod kvm;
 
+/// Microsoft Hypervisor implementation module
+#[cfg(all(feature = "mshv", target_arch = "x86_64"))]
+pub mod mshv;
+
 /// Hypevisor related module
 pub mod hypervisor;
 
@@ -48,13 +54,20 @@ mod device;
 pub use crate::hypervisor::{Hypervisor, HypervisorError};
 pub use cpu::{HypervisorCpuError, Vcpu, VmExit};
 pub use device::{Device, HypervisorDeviceError};
+#[cfg(feature = "kvm")]
 pub use kvm::*;
+#[cfg(all(feature = "mshv", target_arch = "x86_64"))]
+pub use mshv::*;
 pub use vm::{DataMatch, HypervisorVmError, Vm};
 
 use std::sync::Arc;
+
 pub fn new() -> std::result::Result<Arc<dyn Hypervisor>, HypervisorError> {
     #[cfg(feature = "kvm")]
     let hv = kvm::KvmHypervisor::new()?;
 
+    #[cfg(feature = "mshv")]
+    let hv = mshv::MshvHypervisor::new()?;
+
     Ok(Arc::new(hv))
 }

hypervisor/src/mshv/x86_64/mod.rs

@@ -0,0 +1,148 @@
+// Copyright © 2019 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause
+//
+// Copyright © 2020, Microsoft Corporation
+//
+// Copyright 2018-2019 CrowdStrike, Inc.
+//
+//
+
+use crate::arch::x86::{msr_index, SegmentRegisterOps, MTRR_ENABLE, MTRR_MEM_TYPE_WB};
+use serde_derive::{Deserialize, Serialize};
+///
+/// Export generically-named wrappers of mshv_bindings for Unix-based platforms
+///
+pub use {
+    mshv_bindings::mshv_user_mem_region as MemoryRegion, mshv_bindings::msr_entry as MsrEntry,
+    mshv_bindings::CpuId, mshv_bindings::DebugRegisters,
+    mshv_bindings::FloatingPointUnit as FpuState, mshv_bindings::LapicState,
+    mshv_bindings::MsrList, mshv_bindings::Msrs as MsrEntries, mshv_bindings::Msrs,
+    mshv_bindings::SegmentRegister, mshv_bindings::SpecialRegisters,
+    mshv_bindings::StandardRegisters, mshv_bindings::VcpuEvents, mshv_bindings::XSave as Xsave,
+    mshv_bindings::Xcrs as ExtendedControlRegisters,
+};
+
+#[derive(Clone, Serialize, Deserialize)]
+pub struct VcpuMshvState {
+    pub msrs: MsrEntries,
+    pub vcpu_events: VcpuEvents,
+    pub regs: StandardRegisters,
+    pub sregs: SpecialRegisters,
+    pub fpu: FpuState,
+    pub xcrs: ExtendedControlRegisters,
+    pub lapic: LapicState,
+    pub dbg: DebugRegisters,
+    pub xsave: Xsave,
+}
+
+pub struct CreateDevice {}
+pub struct DeviceAttr {}
+pub struct IrqRouting {}
+pub enum VcpuExit {}
+pub struct MpState {}
+
+#[derive(Eq, PartialEq, Hash, Clone, Debug, Copy)]
+pub enum IoEventAddress {
+    /// Representation of an programmable I/O address.
+    Pio(u64),
+    /// Representation of an memory mapped I/O address.
+    Mmio(u64),
+}
+macro_rules! msr {
+    ($msr:expr) => {
+        MsrEntry {
+            index: $msr,
+            data: 0x0,
+            ..Default::default()
+        }
+    };
+}
+macro_rules! msr_data {
+    ($msr:expr, $data:expr) => {
+        MsrEntry {
+            index: $msr,
+            data: $data,
+            ..Default::default()
+        }
+    };
+}
+
+impl SegmentRegisterOps for SegmentRegister {
+    fn segment_type(&self) -> u8 {
+        self.type_
+    }
+    fn set_segment_type(&mut self, val: u8) {
+        self.type_ = val;
+    }
+
+    fn dpl(&self) -> u8 {
+        self.dpl
+    }
+
+    fn set_dpl(&mut self, val: u8) {
+        self.dpl = val;
+    }
+
+    fn present(&self) -> u8 {
+        self.present
+    }
+
+    fn set_present(&mut self, val: u8) {
+        self.present = val;
+    }
+
+    fn long(&self) -> u8 {
+        self.l
+    }
+
+    fn set_long(&mut self, val: u8) {
+        self.l = val;
+    }
+
+    fn avl(&self) -> u8 {
+        self.avl
+    }
+
+    fn set_avl(&mut self, val: u8) {
+        self.avl = val;
+    }
+
+    fn desc_type(&self) -> u8 {
+        self.s
+    }
+
+    fn set_desc_type(&mut self, val: u8) {
+        self.s = val;
+    }
+
+    fn granularity(&self) -> u8 {
+        self.g
+    }
+
+    fn set_granularity(&mut self, val: u8) {
+        self.g = val;
+    }
+
+    fn db(&self) -> u8 {
+        self.db
+    }
+
+    fn set_db(&mut self, val: u8) {
+        self.db = val;
+    }
+}
+
+pub fn boot_msr_entries() -> MsrEntries {
+    MsrEntries::from_entries(&[
+        msr!(msr_index::MSR_IA32_SYSENTER_CS),
+        msr!(msr_index::MSR_IA32_SYSENTER_ESP),
+        msr!(msr_index::MSR_IA32_SYSENTER_EIP),
+        msr!(msr_index::MSR_STAR),
+        msr!(msr_index::MSR_CSTAR),
+        msr!(msr_index::MSR_LSTAR),
+        msr!(msr_index::MSR_KERNEL_GS_BASE),
+        msr!(msr_index::MSR_SYSCALL_MASK),
+        msr!(msr_index::MSR_IA32_TSC),
+    ])
+}

hypervisor/src/vm.rs

@@ -12,9 +12,16 @@
 use crate::aarch64::VcpuInit;
 use crate::cpu::Vcpu;
 use crate::device::Device;
-#[cfg(target_arch = "x86_64")]
+#[cfg(all(feature = "kvm", target_arch = "x86_64"))]
 use crate::ClockData;
-use crate::{CreateDevice, IoEventAddress, IrqRoutingEntry, MemoryRegion};
+#[cfg(feature = "kvm")]
+use crate::CreateDevice;
+#[cfg(feature = "mshv")]
+use crate::HvState as VmState;
+#[cfg(feature = "kvm")]
+use crate::KvmVmState as VmState;
+use crate::{IoEventAddress, IrqRoutingEntry, MemoryRegion};
+#[cfg(feature = "kvm")]
 use kvm_ioctls::Cap;
 use std::sync::Arc;
 use thiserror::Error;
@@ -23,6 +30,7 @@ use vmm_sys_util::eventfd::EventFd;
 ///
 /// I/O events data matches (32 or 64 bits).
 ///
+#[derive(Debug)]
 pub enum DataMatch {
     DataMatch32(u32),
     DataMatch64(u64),
@@ -116,6 +124,45 @@ pub enum HypervisorVmError {
     ///
     #[error("Failed to create passthrough device: {0}")]
     CreatePassthroughDevice(#[source] anyhow::Error),
+    /// Write to Guest memory
+    ///
+    #[error("Failed to write to guest memory: {0}")]
+    GuestMemWrite(#[source] anyhow::Error),
+    ///
+    /// Read Guest memory
+    ///
+    #[error("Failed to read guest memory: {0}")]
+    GuestMemRead(#[source] anyhow::Error),
+    ///
+    /// Read from MMIO Bus
+    ///
+    #[error("Failed to read from MMIO Bus: {0}")]
+    MmioBusRead(#[source] anyhow::Error),
+    ///
+    /// Write to MMIO Bus
+    ///
+    #[error("Failed to write to MMIO Bus: {0}")]
+    MmioBusWrite(#[source] anyhow::Error),
+    ///
+    /// Read from IO Bus
+    ///
+    #[error("Failed to read from IO Bus: {0}")]
+    IoBusRead(#[source] anyhow::Error),
+    ///
+    /// Write to IO Bus
+    ///
+    #[error("Failed to write to IO Bus: {0}")]
+    IoBusWrite(#[source] anyhow::Error),
+    ///
+    /// Get dirty log error
+    ///
+    #[error("Failed to get dirty log: {0}")]
+    GetDirtyLog(#[source] anyhow::Error),
+    ///
+    /// Assert virtual interrupt error
+    ///
+    #[error("Failed to assert virtual Interrupt: {0}")]
+    AsserttVirtualInterrupt(#[source] anyhow::Error),
 }
 ///
 /// Result type for returning from a function
@@ -138,7 +185,7 @@ pub trait Vm: Send + Sync {
     /// Unregister an event that will, when signaled, trigger the `gsi` IRQ.
     fn unregister_irqfd(&self, fd: &EventFd, gsi: u32) -> Result<()>;
     /// Creates a new KVM vCPU file descriptor and maps the memory corresponding
-    fn create_vcpu(&self, id: u8) -> Result<Arc<dyn Vcpu>>;
+    fn create_vcpu(&self, id: u8, vmmops: Option<Arc<Box<dyn VmmOps>>>) -> Result<Arc<dyn Vcpu>>;
     /// Registers an event to be signaled whenever a certain address is written to.
     fn register_ioevent(
         &self,
@@ -158,9 +205,11 @@ pub trait Vm: Send + Sync {
         memory_size: u64,
         userspace_addr: u64,
         readonly: bool,
+        log_dirty_pages: bool,
     ) -> MemoryRegion;
     /// Creates/modifies a guest physical memory slot.
     fn set_user_memory_region(&self, user_memory_region: MemoryRegion) -> Result<()>;
+    #[cfg(feature = "kvm")]
     /// Creates an emulated device in the kernel.
     fn create_device(&self, device: &mut CreateDevice) -> Result<Arc<dyn Device>>;
     /// Returns the preferred CPU target type which can be emulated by KVM on underlying host.
@@ -170,13 +219,31 @@ pub trait Vm: Send + Sync {
     #[cfg(target_arch = "x86_64")]
     fn enable_split_irq(&self) -> Result<()>;
     /// Retrieve guest clock.
-    #[cfg(target_arch = "x86_64")]
+    #[cfg(all(feature = "kvm", target_arch = "x86_64"))]
     fn get_clock(&self) -> Result<ClockData>;
     /// Set guest clock.
-    #[cfg(target_arch = "x86_64")]
+    #[cfg(all(feature = "kvm", target_arch = "x86_64"))]
     fn set_clock(&self, data: &ClockData) -> Result<()>;
+    #[cfg(feature = "kvm")]
     /// Checks if a particular `Cap` is available.
     fn check_extension(&self, c: Cap) -> bool;
     /// Create a device that is used for passthrough
     fn create_passthrough_device(&self) -> Result<Arc<dyn Device>>;
+    /// Get the Vm state. Return VM specific data
+    fn state(&self) -> Result<VmState>;
+    /// Set the VM state
+    fn set_state(&self, state: VmState) -> Result<()>;
+    /// Get dirty pages bitmap
+    fn get_dirty_log(&self, slot: u32, memory_size: u64) -> Result<Vec<u64>>;
+}
+
+pub trait VmmOps: Send + Sync {
+    fn guest_mem_write(&self, buf: &[u8], gpa: u64) -> Result<usize>;
+    fn guest_mem_read(&self, buf: &mut [u8], gpa: u64) -> Result<usize>;
+    fn mmio_read(&self, addr: u64, data: &mut [u8]) -> Result<()>;
+    fn mmio_write(&self, addr: u64, data: &[u8]) -> Result<()>;
+    #[cfg(target_arch = "x86_64")]
+    fn pio_read(&self, addr: u64, data: &mut [u8]) -> Result<()>;
+    #[cfg(target_arch = "x86_64")]
+    fn pio_write(&self, addr: u64, data: &[u8]) -> Result<()>;
 }

net_util/Cargo.toml

@@ -5,17 +5,17 @@ authors = ["The Chromium OS Authors"]
 
 [dependencies]
 epoll = ">=4.0.1"
-libc = "0.2.74"
+libc = "0.2.81"
 log = "0.4.11"
 net_gen = { path = "../net_gen" }
 rand = "0.7.3"
-serde = "1.0.114"
+serde = "1.0.118"
 virtio-bindings = "0.1.0"
-vm-memory = { version = "0.2.1", features = ["backend-mmap", "backend-atomic"] }
+vm-memory = { version = "0.4.0", features = ["backend-mmap", "backend-atomic"] }
 vm-virtio = { path = "../vm-virtio" }
 vmm-sys-util = ">=0.3.1"
 
 [dev-dependencies]
 lazy_static = "1.3.0"
-pnet = "0.26.0"
-serde_json = "1.0.57"
+pnet = "0.27.2"
+serde_json = "1.0.60"

option_parser/src/lib.rs

@@ -143,6 +143,7 @@ impl FromStr for Toggle {
 
 pub struct ByteSized(pub u64);
 
+#[derive(Debug)]
 pub enum ByteSizedParseError {
     InvalidValue(String),
 }
@@ -170,3 +171,99 @@ impl FromStr for ByteSized {
         }))
     }
 }
+
+pub struct IntegerList(pub Vec<u64>);
+
+pub enum IntegerListParseError {
+    InvalidValue(String),
+}
+
+impl FromStr for IntegerList {
+    type Err = IntegerListParseError;
+
+    fn from_str(s: &str) -> std::result::Result<Self, Self::Err> {
+        let mut integer_list = Vec::new();
+        let ranges_list: Vec<&str> = s.trim().split(':').collect();
+
+        for range in ranges_list.iter() {
+            let items: Vec<&str> = range.split('-').collect();
+
+            if items.len() > 2 {
+                return Err(IntegerListParseError::InvalidValue((*range).to_string()));
+            }
+
+            let start_range = items[0]
+                .parse::<u64>()
+                .map_err(|_| IntegerListParseError::InvalidValue(items[0].to_owned()))?;
+
+            integer_list.push(start_range);
+
+            if items.len() == 2 {
+                let end_range = items[1]
+                    .parse::<u64>()
+                    .map_err(|_| IntegerListParseError::InvalidValue(items[1].to_owned()))?;
+                if start_range >= end_range {
+                    return Err(IntegerListParseError::InvalidValue((*range).to_string()));
+                }
+
+                for i in start_range..end_range {
+                    integer_list.push(i + 1);
+                }
+            }
+        }
+
+        Ok(IntegerList(integer_list))
+    }
+}
+
+pub struct TupleTwoIntegers(pub Vec<(u64, u64)>);
+
+pub enum TupleTwoIntegersParseError {
+    InvalidValue(String),
+}
+
+impl FromStr for TupleTwoIntegers {
+    type Err = TupleTwoIntegersParseError;
+
+    fn from_str(s: &str) -> std::result::Result<Self, Self::Err> {
+        let mut list = Vec::new();
+        let tuples_list: Vec<&str> = s.trim().split(':').collect();
+
+        for tuple in tuples_list.iter() {
+            let items: Vec<&str> = tuple.split('@').collect();
+
+            if items.len() != 2 {
+                return Err(TupleTwoIntegersParseError::InvalidValue(
+                    (*tuple).to_string(),
+                ));
+            }
+
+            let item1 = items[0]
+                .parse::<u64>()
+                .map_err(|_| TupleTwoIntegersParseError::InvalidValue(items[0].to_owned()))?;
+            let item2 = items[1]
+                .parse::<u64>()
+                .map_err(|_| TupleTwoIntegersParseError::InvalidValue(items[1].to_owned()))?;
+
+            list.push((item1, item2));
+        }
+
+        Ok(TupleTwoIntegers(list))
+    }
+}
+
+pub struct StringList(pub Vec<String>);
+
+pub enum StringListParseError {
+    InvalidValue(String),
+}
+
+impl FromStr for StringList {
+    type Err = StringListParseError;
+
+    fn from_str(s: &str) -> std::result::Result<Self, Self::Err> {
+        let string_list: Vec<String> = s.trim().split(':').map(|e| e.to_owned()).collect();
+
+        Ok(StringList(string_list))
+    }
+}

pci/Cargo.toml

@@ -7,18 +7,17 @@ edition = "2018"
 [dependencies]
 anyhow = "1.0"
 byteorder = "1.3.4"
-devices = { path = "../devices" }
 hypervisor = { path = "../hypervisor" }
 vfio-ioctls = { git = "https://github.com/cloud-hypervisor/vfio-ioctls", branch = "ch" }
 vmm-sys-util = ">=0.3.1"
-libc = "0.2.74"
+libc = "0.2.81"
 log = "0.4.11"
 serde = {version = ">=1.0.27", features = ["rc"] }
 serde_derive = ">=1.0.27"
 serde_json = ">=1.0.9"
 vm-allocator = { path = "../vm-allocator" }
 vm-device = { path = "../vm-device" }
-vm-memory = "0.2.1"
+vm-memory = "0.4.0"
 vm-migration = { path = "../vm-migration" }
 
 [dependencies.vfio-bindings]

pci/src/bus.rs

@@ -7,11 +7,11 @@ use crate::configuration::{
 };
 use crate::device::{DeviceRelocation, Error as PciDeviceError, PciDevice};
 use byteorder::{ByteOrder, LittleEndian};
-use devices::BusDevice;
 use std::any::Any;
 use std::collections::HashMap;
 use std::ops::DerefMut;
 use std::sync::{Arc, Mutex};
+use vm_device::{Bus, BusDevice};
 use vm_memory::{Address, GuestAddress, GuestUsize};
 
 const VENDOR_ID_INTEL: u16 = 0x8086;
@@ -26,9 +26,9 @@ pub enum PciRootError {
     /// Could not allocate an IRQ number.
     AllocateIrq,
     /// Could not add a device to the port io bus.
-    PioInsert(devices::BusError),
+    PioInsert(vm_device::BusError),
     /// Could not add a device to the mmio bus.
-    MmioInsert(devices::BusError),
+    MmioInsert(vm_device::BusError),
     /// Could not find an available device slot on the PCI bus.
     NoPciDeviceSlotAvailable,
     /// Invalid PCI device identifier provided.
@@ -110,8 +110,8 @@ impl PciBus {
     pub fn register_mapping(
         &self,
         dev: Arc<Mutex<dyn BusDevice>>,
-        #[cfg(target_arch = "x86_64")] io_bus: &devices::Bus,
-        mmio_bus: &devices::Bus,
+        #[cfg(target_arch = "x86_64")] io_bus: &Bus,
+        mmio_bus: &Bus,
         bars: Vec<(GuestAddress, GuestUsize, PciBarRegionType)>,
     ) -> Result<()> {
         for (address, size, type_) in bars {

pci/src/configuration.rs

@@ -64,7 +64,7 @@ impl PciClassCode {
     }
 }
 
-/// A PCI sublcass. Each class in `PciClassCode` can specify a unique set of subclasses. This trait
+/// A PCI subclass. Each class in `PciClassCode` can specify a unique set of subclasses. This trait
 /// is implemented by each subclass. It allows use of a trait object to generate configurations.
 pub trait PciSubclass {
     /// Convert this subclass to the value used in the PCI specification.
@@ -570,7 +570,7 @@ impl PciConfiguration {
         let end_addr = config
             .addr
             .checked_add(config.size - 1)
-            .ok_or_else(|| Error::BarAddressInvalid(config.addr, config.size))?;
+            .ok_or(Error::BarAddressInvalid(config.addr, config.size))?;
         match config.region_type {
             PciBarRegionType::Memory32BitRegion | PciBarRegionType::IORegion => {
                 if end_addr > u64::from(u32::max_value()) {
@@ -642,7 +642,7 @@ impl PciConfiguration {
         let end_addr = config
             .addr
             .checked_add(config.size - 1)
-            .ok_or_else(|| Error::RomBarAddressInvalid(config.addr, config.size))?;
+            .ok_or(Error::RomBarAddressInvalid(config.addr, config.size))?;
 
         if end_addr > u64::from(u32::max_value()) {
             return Err(Error::RomBarAddressInvalid(config.addr, config.size));
@@ -698,7 +698,7 @@ impl PciConfiguration {
         };
         let end_offset = cap_offset
             .checked_add(total_len)
-            .ok_or_else(|| Error::CapabilitySpaceFull(total_len))?;
+            .ok_or(Error::CapabilitySpaceFull(total_len))?;
         if end_offset > CAPABILITY_MAX_OFFSET {
             return Err(Error::CapabilitySpaceFull(total_len));
         }
@@ -889,7 +889,7 @@ impl Snapshottable for PciConfiguration {
         String::from("pci_configuration")
     }
 
-    fn snapshot(&self) -> std::result::Result<Snapshot, MigratableError> {
+    fn snapshot(&mut self) -> std::result::Result<Snapshot, MigratableError> {
         let snapshot =
             serde_json::to_vec(&self.state()).map_err(|e| MigratableError::Snapshot(e.into()))?;
 

pci/src/device.rs

@@ -3,11 +3,11 @@
 // found in the LICENSE-BSD-3-Clause file.
 
 use crate::configuration::{self, PciBarRegionType};
-use devices::BusDevice;
 use std::any::Any;
 use std::fmt::{self, Display};
 use std::{self, io, result};
 use vm_allocator::SystemAllocator;
+use vm_device::BusDevice;
 use vm_memory::{GuestAddress, GuestUsize};
 
 #[derive(Debug)]

pci/src/lib.rs

@@ -5,7 +5,6 @@
 //! Implements pci devices and busses.
 #[macro_use]
 extern crate log;
-extern crate devices;
 extern crate hypervisor;
 extern crate serde;
 #[macro_use]

pci/src/msix.rs

@@ -56,7 +56,7 @@ impl Default for MsixTableEntry {
             msg_addr_lo: 0,
             msg_addr_hi: 0,
             msg_data: 0,
-            vector_ctl: 0,
+            vector_ctl: 0x1,
         }
     }
 }
@@ -97,7 +97,7 @@ impl MsixConfig {
             pba_entries,
             devid,
             interrupt_source_group,
-            masked: false,
+            masked: true,
             enabled: false,
         }
     }
@@ -158,7 +158,7 @@ impl MsixConfig {
         self.masked = ((reg >> FUNCTION_MASK_BIT) & 1u16) == 1u16;
         self.enabled = ((reg >> MSIX_ENABLE_BIT) & 1u16) == 1u16;
 
-        // Update KVM routes
+        // Update interrupt routing
         if old_masked != self.masked || old_enabled != self.enabled {
             if self.enabled && !self.masked {
                 for (idx, table_entry) in self.table_entries.iter().enumerate() {
@@ -185,12 +185,6 @@ impl MsixConfig {
                         error!("Failed unmasking vector: {:?}", e);
                     }
                 }
-
-                if !old_enabled || old_masked {
-                    if let Err(e) = self.interrupt_source_group.enable() {
-                        error!("Failed enabling irq_fd: {:?}", e);
-                    }
-                }
             } else if old_enabled || !old_masked {
                 if let Err(e) = self.interrupt_source_group.disable() {
                     error!("Failed disabling irq_fd: {:?}", e);
@@ -437,7 +431,7 @@ impl Snapshottable for MsixConfig {
         String::from("msix_config")
     }
 
-    fn snapshot(&self) -> std::result::Result<Snapshot, MigratableError> {
+    fn snapshot(&mut self) -> std::result::Result<Snapshot, MigratableError> {
         let snapshot =
             serde_json::to_vec(&self.state()).map_err(|e| MigratableError::Snapshot(e.into()))?;
 

pci/src/vfio.rs

@@ -3,7 +3,6 @@
 // SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause
 //
 
-extern crate devices;
 extern crate vm_allocator;
 
 use crate::{
@@ -12,7 +11,6 @@ use crate::{
     PciDevice, PciDeviceError, PciHeaderType, PciSubclass, MSIX_TABLE_ENTRY_SIZE,
 };
 use byteorder::{ByteOrder, LittleEndian};
-use devices::BusDevice;
 use std::any::Any;
 use std::ops::Deref;
 use std::os::unix::io::AsRawFd;
@@ -25,6 +23,7 @@ use vm_allocator::SystemAllocator;
 use vm_device::interrupt::{
     InterruptIndex, InterruptManager, InterruptSourceGroup, MsiIrqGroupConfig,
 };
+use vm_device::BusDevice;
 use vm_memory::{
     Address, GuestAddress, GuestAddressSpace, GuestMemoryAtomic, GuestMemoryMmap, GuestRegionMmap,
     GuestUsize,
@@ -61,7 +60,7 @@ impl fmt::Display for VfioPciError {
             VfioPciError::MapRegionGuest(e) => {
                 write!(f, "failed to map VFIO PCI region into guest: {}", e)
             }
-            VfioPciError::SetGsiRouting(e) => write!(f, "failed to set GSI routes for KVM: {}", e),
+            VfioPciError::SetGsiRouting(e) => write!(f, "failed to set GSI routes: {}", e),
             VfioPciError::MsiNotConfigured => write!(f, "MSI interrupt not yet configured"),
             VfioPciError::MsixNotConfigured => write!(f, "MSI-X interrupt not yet configured"),
             VfioPciError::UpdateMemory(e) => write!(f, "failed to update memory: {}", e),
@@ -222,9 +221,9 @@ impl Interrupt {
 }
 
 #[derive(Copy, Clone)]
-struct MmioRegion {
-    start: GuestAddress,
-    length: GuestUsize,
+pub struct MmioRegion {
+    pub start: GuestAddress,
+    pub length: GuestUsize,
     type_: PciBarRegionType,
     index: u32,
     mem_slot: Option<u32>,
@@ -504,12 +503,9 @@ impl VfioPciDevice {
     ///
     /// # Arguments
     ///
-    /// * `vm` - The KVM VM file descriptor. It is used to set the VFIO MMIO regions
-    ///          as KVM user memory regions.
-    /// * `mem_slot` - The KVM memory slot to set the user memopry regions.
-    /// # Return value
-    ///
-    /// This function returns the updated KVM memory slot id.
+    /// * `vm` - The VM object. It is used to set the VFIO MMIO regions
+    ///          as user memory regions.
+    /// * `mem_slot` - The closure to return a memory slot.
     pub fn map_mmio_regions<F>(&mut self, vm: &Arc<dyn hypervisor::Vm>, mem_slot: F) -> Result<()>
     where
         F: Fn() -> u32,
@@ -565,6 +561,7 @@ impl VfioPciDevice {
                     mmap_size as u64,
                     host_addr as u64,
                     false,
+                    false,
                 );
 
                 vm.set_user_memory_region(mem_region)
@@ -587,20 +584,18 @@ impl VfioPciDevice {
             {
                 let (mmap_offset, _) = self.device.get_region_mmap(region.index);
 
-                // Remove region from KVM
-                let kvm_region = self.vm.make_user_memory_region(
+                // Remove region
+                let r = self.vm.make_user_memory_region(
                     mem_slot,
                     region.start.raw_value() + mmap_offset,
                     0,
                     host_addr as u64,
                     false,
+                    false,
                 );
 
-                if let Err(e) = self.vm.set_user_memory_region(kvm_region) {
-                    error!(
-                        "Could not remove the userspace memory region from KVM: {}",
-                        e
-                    );
+                if let Err(e) = self.vm.set_user_memory_region(r) {
+                    error!("Could not remove the userspace memory region: {}", e);
                 }
 
                 let ret = unsafe { libc::munmap(host_addr as *mut libc::c_void, mmap_size) };
@@ -620,6 +615,10 @@ impl VfioPciDevice {
             .extend_dma_map(new_region)
             .map_err(VfioPciError::UpdateMemory)
     }
+
+    pub fn mmio_regions(&self) -> Vec<MmioRegion> {
+        self.mmio_regions.clone()
+    }
 }
 
 impl Drop for VfioPciDevice {
@@ -721,20 +720,17 @@ impl PciDevice for VfioPciDevice {
 
             // Is this an IO BAR?
             let io_bar = if bar_id != VFIO_PCI_ROM_REGION_INDEX {
-                match lsb_flag & PCI_CONFIG_IO_BAR {
-                    PCI_CONFIG_IO_BAR => true,
-                    _ => false,
-                }
+                matches!(lsb_flag & PCI_CONFIG_IO_BAR, PCI_CONFIG_IO_BAR)
             } else {
                 false
             };
 
             // Is this a 64-bit BAR?
             let is_64bit_bar = if bar_id != VFIO_PCI_ROM_REGION_INDEX {
-                match lsb_flag & PCI_CONFIG_MEMORY_BAR_64BIT {
-                    PCI_CONFIG_MEMORY_BAR_64BIT => true,
-                    _ => false,
-                }
+                matches!(
+                    lsb_flag & PCI_CONFIG_MEMORY_BAR_64BIT,
+                    PCI_CONFIG_MEMORY_BAR_64BIT
+                )
             } else {
                 false
             };
@@ -758,7 +754,7 @@ impl PciDevice for VfioPciDevice {
                     // The address needs to be 4 bytes aligned.
                     bar_addr = allocator
                         .allocate_io_addresses(None, region_size, Some(0x4))
-                        .ok_or_else(|| PciDeviceError::IoAllocationFailed(region_size))?;
+                        .ok_or(PciDeviceError::IoAllocationFailed(region_size))?;
                 }
                 #[cfg(target_arch = "aarch64")]
                 unimplemented!()
@@ -791,8 +787,8 @@ impl PciDevice for VfioPciDevice {
 
                 // We need to allocate a guest MMIO address range for that BAR.
                 // In case the BAR is mappable directly, this means it might be
-                // set as KVM user memory region, which expects to deal with 4K
-                // pages. Therefore, the aligment has to be set accordingly.
+                // set as user memory region, which expects to deal with 4K
+                // pages. Therefore, the alignment has to be set accordingly.
                 let bar_alignment = if (bar_id == VFIO_PCI_ROM_REGION_INDEX)
                     || (self.device.get_region_flags(bar_id) & VFIO_REGION_INFO_FLAG_MMAP != 0)
                 {
@@ -805,11 +801,11 @@ impl PciDevice for VfioPciDevice {
                 if is_64bit_bar {
                     bar_addr = allocator
                         .allocate_mmio_addresses(None, region_size, Some(bar_alignment))
-                        .ok_or_else(|| PciDeviceError::IoAllocationFailed(region_size))?;
+                        .ok_or(PciDeviceError::IoAllocationFailed(region_size))?;
                 } else {
                     bar_addr = allocator
                         .allocate_mmio_hole_addresses(None, region_size, Some(bar_alignment))
-                        .ok_or_else(|| PciDeviceError::IoAllocationFailed(region_size))?;
+                        .ok_or(PciDeviceError::IoAllocationFailed(region_size))?;
                 }
             }
 
@@ -1015,26 +1011,28 @@ impl PciDevice for VfioPciDevice {
                     if let Some(host_addr) = region.host_addr {
                         let (mmap_offset, mmap_size) = self.device.get_region_mmap(region.index);
 
-                        // Remove old region from KVM
+                        // Remove old region
                         let old_mem_region = self.vm.make_user_memory_region(
                             mem_slot,
                             old_base + mmap_offset,
                             0,
                             host_addr as u64,
                             false,
+                            false,
                         );
 
                         self.vm
                             .set_user_memory_region(old_mem_region)
                             .map_err(|e| io::Error::new(io::ErrorKind::Other, e))?;
 
-                        // Insert new region to KVM
+                        // Insert new region
                         let new_mem_region = self.vm.make_user_memory_region(
                             mem_slot,
                             new_base + mmap_offset,
                             mmap_size as u64,
                             host_addr as u64,
                             false,
+                            false,
                         );
 
                         self.vm

qcow/Cargo.toml

@@ -10,7 +10,7 @@ path = "src/qcow.rs"
 
 [dependencies]
 byteorder = "1.3.4"
-libc = "0.2.74"
+libc = "0.2.81"
 log = "0.4.11"
 remain = "0.2.2"
 vmm-sys-util = ">=0.3.1"

qcow/src/qcow.rs

@@ -769,11 +769,14 @@ impl QcowFile {
             let mut ref_table = vec![0; refcount_table_entries as usize];
             let mut first_free_cluster: u64 = 0;
             for refblock_addr in &mut ref_table {
-                while refcounts[first_free_cluster as usize] != 0 {
-                    first_free_cluster += 1;
+                loop {
                     if first_free_cluster >= refcounts.len() as u64 {
                         return Err(Error::NotEnoughSpaceForRefcounts);
                     }
+                    if refcounts[first_free_cluster as usize] == 0 {
+                        break;
+                    }
+                    first_free_cluster += 1;
                 }
 
                 *refblock_addr = first_free_cluster * cluster_size;
@@ -1056,7 +1059,7 @@ impl QcowFile {
             // Free the previously used cluster if one exists. Modified tables are always
             // witten to new clusters so the L1 table can be committed to disk after they
             // are and L1 never points at an invalid table.
-            // The index must be valid from when it was insterted.
+            // The index must be valid from when it was inserted.
             let addr = self.l1_table[l1_index];
             if addr != 0 {
                 self.unref_clusters.push(addr);
@@ -1354,7 +1357,7 @@ impl QcowFile {
     fn sync_caches(&mut self) -> std::io::Result<()> {
         // Write out all dirty L2 tables.
         for (l1_index, l2_table) in self.l2_cache.iter_mut().filter(|(_k, v)| v.dirty()) {
-            // The index must be valid from when we insterted it.
+            // The index must be valid from when we inserted it.
             let addr = self.l1_table[*l1_index];
             if addr != 0 {
                 self.raw_file.write_pointer_table(
@@ -1865,7 +1868,7 @@ mod tests {
     #[test]
     fn test_header_crazy_file_size_rejected() {
         let mut header = valid_header_v3();
-        &mut header[24..32].copy_from_slice(&[0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1e]);
+        header[24..32].copy_from_slice(&[0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1e]);
         with_basic_file(&header, |disk_file: RawFile| {
             QcowFile::from(disk_file).expect_err("Failed to create file.");
         });
@@ -1914,7 +1917,7 @@ mod tests {
     #[test]
     fn test_header_huge_num_refcounts() {
         let mut header = valid_header_v3();
-        &mut header[56..60].copy_from_slice(&[0x02, 0x00, 0xe8, 0xff]);
+        header[56..60].copy_from_slice(&[0x02, 0x00, 0xe8, 0xff]);
         with_basic_file(&header, |disk_file: RawFile| {
             QcowFile::from(disk_file).expect_err("Created disk with crazy refcount clusters");
         });
@@ -1923,7 +1926,7 @@ mod tests {
     #[test]
     fn test_header_huge_refcount_offset() {
         let mut header = valid_header_v3();
-        &mut header[48..56].copy_from_slice(&[0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02, 0x00]);
+        header[48..56].copy_from_slice(&[0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02, 0x00]);
         with_basic_file(&header, |disk_file: RawFile| {
             QcowFile::from(disk_file).expect_err("Created disk with crazy refcount offset");
         });
@@ -1933,11 +1936,11 @@ mod tests {
     fn write_read_start() {
         with_basic_file(&valid_header_v3(), |disk_file: RawFile| {
             let mut q = QcowFile::from(disk_file).unwrap();
-            q.write(b"test first bytes")
+            q.write_all(b"test first bytes")
                 .expect("Failed to write test string.");
             let mut buf = [0u8; 4];
             q.seek(SeekFrom::Start(0)).expect("Failed to seek.");
-            q.read(&mut buf).expect("Failed to read.");
+            q.read_exact(&mut buf).expect("Failed to read.");
             assert_eq!(&buf, b"test");
         });
     }
@@ -1948,10 +1951,10 @@ mod tests {
             let mut q = QcowFile::from(disk_file).unwrap();
             let b = [0x55u8; 0x1000];
             q.seek(SeekFrom::Start(0xfff2000)).expect("Failed to seek.");
-            q.write(&b).expect("Failed to write test string.");
+            q.write_all(&b).expect("Failed to write test string.");
             let mut buf = [0u8; 4];
             q.seek(SeekFrom::Start(0xfff2000)).expect("Failed to seek.");
-            q.read(&mut buf).expect("Failed to read.");
+            q.read_exact(&mut buf).expect("Failed to read.");
             assert_eq!(buf[0], 0x55);
         });
     }
@@ -1963,7 +1966,7 @@ mod tests {
             // Write some test data.
             let b = [0x55u8; 0x1000];
             q.seek(SeekFrom::Start(0xfff2000)).expect("Failed to seek.");
-            q.write(&b).expect("Failed to write test string.");
+            q.write_all(&b).expect("Failed to write test string.");
             // Overwrite the test data with zeroes.
             q.seek(SeekFrom::Start(0xfff2000)).expect("Failed to seek.");
             let nwritten = q.write_zeroes(0x200).expect("Failed to write zeroes.");
@@ -1971,7 +1974,7 @@ mod tests {
             // Verify that the correct part of the data was zeroed out.
             let mut buf = [0u8; 0x1000];
             q.seek(SeekFrom::Start(0xfff2000)).expect("Failed to seek.");
-            q.read(&mut buf).expect("Failed to read.");
+            q.read_exact(&mut buf).expect("Failed to read.");
             assert_eq!(buf[0], 0);
             assert_eq!(buf[0x1FF], 0);
             assert_eq!(buf[0x200], 0x55);
@@ -1989,7 +1992,7 @@ mod tests {
             // Write some test data.
             let b = [0x55u8; CHUNK_SIZE];
             q.seek(SeekFrom::Start(0)).expect("Failed to seek.");
-            q.write(&b).expect("Failed to write test string.");
+            q.write_all(&b).expect("Failed to write test string.");
             // Overwrite the full cluster with zeroes.
             q.seek(SeekFrom::Start(0)).expect("Failed to seek.");
             let nwritten = q.write_zeroes(CHUNK_SIZE).expect("Failed to write zeroes.");
@@ -1997,7 +2000,7 @@ mod tests {
             // Verify that the data was zeroed out.
             let mut buf = [0u8; CHUNK_SIZE];
             q.seek(SeekFrom::Start(0)).expect("Failed to seek.");
-            q.read(&mut buf).expect("Failed to read.");
+            q.read_exact(&mut buf).expect("Failed to read.");
             assert_eq!(buf[0], 0);
             assert_eq!(buf[CHUNK_SIZE - 1], 0);
         });
@@ -2021,7 +2024,7 @@ mod tests {
             let mut q = QcowFile::from(disk_file).unwrap();
             let mut b = [5u8; 16];
             q.seek(SeekFrom::Start(1000)).expect("Failed to seek.");
-            q.read(&mut b).expect("Failed to read.");
+            q.read_exact(&mut b).expect("Failed to read.");
             assert_eq!(0, b[0]);
             assert_eq!(0, b[15]);
         });
@@ -2394,7 +2397,7 @@ mod tests {
             for xfer in &xfers {
                 q.seek(SeekFrom::Start(xfer.addr)).expect("Failed to seek.");
                 if xfer.write {
-                    q.write(&b).expect("Failed to write.");
+                    q.write_all(&b).expect("Failed to write.");
                 } else {
                     let read_count: usize = q.read(&mut b).expect("Failed to read.");
                     assert_eq!(read_count, BUF_SIZE);

qcow/src/raw_file.rs

@@ -58,7 +58,7 @@ impl RawFile {
         }
         RawFile {
             file,
-            alignment: alignment.try_into().unwrap(),
+            alignment,
             position: 0,
         }
     }
@@ -175,7 +175,7 @@ impl Read for RawFile {
 
             self.seek(SeekFrom::Current(to_copy.try_into().unwrap()))
                 .unwrap();
-            Ok(to_copy.try_into().unwrap())
+            Ok(to_copy)
         }
     }
 }
@@ -259,7 +259,7 @@ impl Write for RawFile {
 
                 self.seek(SeekFrom::Current(to_seek.try_into().unwrap()))
                     .unwrap();
-                Ok(to_seek.try_into().unwrap())
+                Ok(to_seek)
             }
         }
     }

release-notes.md

@@ -1,12 +1,29 @@
- - [v0.8.0](#v080)
-    - [Experimental Snapshot and Restore Support](#experimental-snapshot-and-restore-support)
-    - [Experimental ARM64 Support](#experimental-arm64-support)
-    - [Support for Using 5-level Paging in Guests](#support-for-using-5-level-paging-in-guests)
-    - [Virtio Device Interrupt Suppression for Network Devices](#virtio-device-interrupt-suppression-for-network-devices)
-    - [`vhost_user_fs` Improvements](#vhost_user_fs-improvements)
-    - [Notable Bug Fixes](#notable-bug-fixes)
-    - [Command Line and API Changes](#command-line-and-api-changes)
+- [v0.12.0](#v0120)
+    - [ARM64 enhancements](#arm64-enhancements)
+    - [Removal of `vhost-user-net` and `vhost-user-block` self spawning](#removal-of-vhost-user-net-and-vhost-user-block-self-spawning)
+    - [Migration of `vhost-user-fs` backend](#migration-of-vhost-user-fs-backend)
+    - [Enhanced "info" API](#enhanced-info-api)
     - [Contributors](#contributors)
+- [v0.11.0](#v0110)
+    - [`io_uring` support by default for `virtio-block`](#io_uring-support-by-default-for-virtio-block)
+    - [Windows Guest Support](#windows-guest-support)
+    - [`vhost-user` "Self Spawning" Deprecation](#vhost-user-self-spawning-deprecation)
+    - [`virtio-mmmio` Removal](#virtio-mmmio-removal)
+    - [Snapshot/Restore support for ARM64](#snapshotrestore-support-for-arm64)
+    - [Improved Linux Boot Time](#improved-linux-boot-time)
+    - [`SIGTERM/SIGINT` Interrupt Signal Handling](#sigtermsigint-interrupt-signal-handling)
+    - [Default Log Level Changed](#default-log-level-changed)
+    - [New `--balloon` Parameter Added](#new---balloon-parameter-added)
+    - [Experimental `virtio-watchdog` Support](#experimental-virtio-watchdog-support)
+    - [Notable Bug Fixes](#notable-bug-fixes)
+    - [Contributors](#contributors-1)
+- [v0.10.0](#v0100)
+    - [`virtio-block` Support for Multiple Descriptors](#virtio-block-support-for-multiple-descriptors)
+    - [Memory Zones](#memory-zones)
+    - [`Seccomp` Sandbox Improvements](#seccomp-sandbox-improvements)
+    - [Preliminary KVM HyperV Emulation Control](#preliminary-kvm-hyperv-emulation-control)
+    - [Notable Bug Fixes](#notable-bug-fixes-1)
+    - [Contributors](#contributors-2)
 - [v0.9.0](#v090)
     - [`io_uring` Based Block Device Support](#io_uring-based-block-device-support)
     - [Block and Network Device Statistics](#block-and-network-device-statistics)
@@ -18,18 +35,18 @@
     - [Virtio Memory Ballooning Support](#virtio-memory-ballooning-support)
     - [Enhancements to ARM64 Support](#enhancements-to-arm64-support)
     - [Intel SGX Support](#intel-sgx-support)
-    - [`Seccomp` Sandbox Improvements](#seccomp-sandbox-improvements)
-    - [Notable Bug Fixes](#notable-bug-fixes)
-    - [Contributors](#contributors)
+    - [`Seccomp` Sandbox Improvements](#seccomp-sandbox-improvements-1)
+    - [Notable Bug Fixes](#notable-bug-fixes-2)
+    - [Contributors](#contributors-3)
 - [v0.8.0](#v080)
     - [Experimental Snapshot and Restore Support](#experimental-snapshot-and-restore-support)
     - [Experimental ARM64 Support](#experimental-arm64-support)
     - [Support for Using 5-level Paging in Guests](#support-for-using-5-level-paging-in-guests)
     - [Virtio Device Interrupt Suppression for Network Devices](#virtio-device-interrupt-suppression-for-network-devices)
     - [`vhost_user_fs` Improvements](#vhost_user_fs-improvements)
-    - [Notable Bug Fixes](#notable-bug-fixes-1)
+    - [Notable Bug Fixes](#notable-bug-fixes-3)
     - [Command Line and API Changes](#command-line-and-api-changes)
-    - [Contributors](#contributors-1)
+    - [Contributors](#contributors-4)
 - [v0.7.0](#v070)
     - [Block, Network, Persistent Memory (PMEM), VirtioFS and Vsock hotplug](#block-network-persistent-memory-pmem-virtiofs-and-vsock-hotplug)
     - [Alternative `libc` Support](#alternative-libc-support)
@@ -39,14 +56,14 @@
     - [`Seccomp` Sandboxing](#seccomp-sandboxing)
     - [Updated Distribution Support](#updated-distribution-support)
     - [Command Line and API Changes](#command-line-and-api-changes-1)
-    - [Contributors](#contributors-2)
+    - [Contributors](#contributors-5)
 - [v0.6.0](#v060)
     - [Directly Assigned Devices Hotplug](#directly-assigned-devices-hotplug)
     - [Shared Filesystem Improvements](#shared-filesystem-improvements)
     - [Block and Networking IO Self Offloading](#block-and-networking-io-self-offloading)
     - [Command Line Interface](#command-line-interface)
     - [PVH Boot](#pvh-boot)
-    - [Contributors](#contributors-3)
+    - [Contributors](#contributors-6)
 - [v0.5.1](#v051)
 - [v0.5.0](#v050)
     - [Virtual Machine Dynamic Resizing](#virtual-machine-dynamic-resizing)
@@ -54,7 +71,7 @@
     - [New Interrupt Management Framework](#new-interrupt-management-framework)
     - [Development Tools](#development-tools)
     - [Kata Containers Integration](#kata-containers-integration)
-    - [Contributors](#contributors-4)
+    - [Contributors](#contributors-7)
 - [v0.4.0](#v040)
     - [Dynamic virtual CPUs addition](#dynamic-virtual-cpus-addition)
     - [Programmatic firmware tables generation](#programmatic-firmware-tables-generation)
@@ -63,7 +80,7 @@
     - [Userspace IOAPIC by default](#userspace-ioapic-by-default)
     - [PCI BAR reprogramming](#pci-bar-reprogramming)
     - [New `cloud-hypervisor` organization](#new-cloud-hypervisor-organization)
-    - [Contributors](#contributors-5)
+    - [Contributors](#contributors-8)
 - [v0.3.0](#v030)
     - [Block device offloading](#block-device-offloading)
     - [Network device backend](#network-device-backend)
@@ -90,6 +107,195 @@
     - [Unit testing](#unit-testing)
     - [Integration tests parallelization](#integration-tests-parallelization)
 
+# v0.12.0
+
+This release has been tracked through the [0.12.0 project](https://github.com/cloud-hypervisor/cloud-hypervisor/projects/15).
+
+Highlights for `cloud-hypervisor` version 0.12.0 include:
+
+### ARM64 enhancements
+
+The use of `--watchdog` is now fully supported as is the ability to reboot the
+VM from within the guest when running Cloud Hypervisor on an ARM64 system.
+
+### Removal of `vhost-user-net` and `vhost-user-block` self spawning
+
+In order to use `vhost-user-net` or `vhost-user-block` backends the user is now
+responsible for starting the backend and providing the socket for the VMM to
+use. This functionality was deprecated in the last release and how now been
+removed.
+
+### Migration of `vhost-user-fs` backend
+
+The `vhost-user-fs` backend is no longer included in Cloud Hypervisor and it is
+instead hosted in [it's own
+repository](https://gitlab.com/virtio-fs/virtiofsd-rs)
+
+### Enhanced "info" API
+
+The `vm.info` HTTP API endpoint has been extended to include the details of the
+devices used by the VM including any VFIO devices used.
+
+### Contributors
+
+Many thanks to everyone who has contributed to our 0.12.0 release:
+
+* Anatol Belski <anbelski@linux.microsoft.com>
+* Julio Montes <julio.montes@intel.com>
+* Michael Zhao <michael.zhao@arm.com>
+* Muminul Islam <muislam@microsoft.com>
+* Rob Bradford <robert.bradford@intel.com>
+* Samuel Ortiz <sameo@linux.intel.com>
+* Wei Liu <liuwe@microsoft.com>
+
+# v0.11.0
+
+This release has been tracked through the [0.11.0 project](https://github.com/cloud-hypervisor/cloud-hypervisor/projects/14).
+
+Highlights for `cloud-hypervisor` version 0.11.0 include:
+
+### `io_uring` support by default for `virtio-block`
+
+Provided that the host OS supports it (Linux kernel 5.8+) then `io_uring` will
+be used for a significantly higher performance block device. 
+
+### Windows Guest Support
+
+This is the first release where we officially support Windows running as a
+guest. Full details of how to setup the image and run Cloud Hypervisor with a
+Windows guest can be found in the dedicated [Windows
+documentation](docs/windows.md).
+
+### `vhost-user` "Self Spawning" Deprecation
+
+Automatically spawning a `vhost-user-net` or `vhost-user-block` backend is now
+deprecated. Users of this functionality will receive a warning and should make
+adjustments. The functionality will be removed in the next release.
+
+### `virtio-mmmio` Removal
+
+Support for using the `virtio-mmio` transport, rather than using PCI, has been
+removed. This has been to simplify the code and significantly
+reduce the testing burden of the project.
+
+### Snapshot/Restore support for ARM64
+
+When running on the ARM64 architecture snapshot and restore has now been
+implemented.
+
+### Improved Linux Boot Time
+
+The time to boot the Linux kernel has been significantly improved by the
+identifying some areas of delays around PCI bus probing, IOAPIC programming and
+MPTABLE issues. Full details can be seen in #1728.
+
+### `SIGTERM/SIGINT` Interrupt Signal Handling
+
+When the VMM process receives the `SIGTERM` or `SIGINT` signals then it will
+trigger the VMM process to cleanly deallocate resources before exiting. The
+guest VM will not be cleanly shutdown but the VMM process will clean up its
+resources.
+
+### Default Log Level Changed
+
+The default logging level was changed to include warnings which should make it
+easier to see potential issues. New [logging
+documentation](docs/logging) was also added.
+
+### New `--balloon` Parameter Added
+
+Control of the setup of `virtio-balloon` has been moved from `--memory` to its
+own dedicated parameter. This makes it easier to add more balloon specific
+controls without overloading `--memory`.
+
+### Experimental `virtio-watchdog` Support
+
+Support for using a new `virtio-watchdog` has been added which can be used to
+have the VMM reboot the guest if the guest userspace fails to ping the
+watchdog. This is enabled with `--watchdog` and requires kernel support.
+
+### Notable Bug Fixes
+
+* MTRR bit was missing from CPUID advertised to guest
+* "Return" key could not be used under `CMD.EXE` under Windows SAC (#1170)
+* CPU identification string is now exposed to the guest
+* `virtio-pmem` with`discard_writes=on` no longer marks the guest memory as
+  read only so avoids excessive VM exits (#1795)
+* PCI device hotplug after an unplug was fixed (#1802)
+* When using the ACPI method to resize the guest memory the full reserved size
+  can be used (#1803)
+* Snapshot and restore followed by a second snapshot and restore now works
+  correctly
+* Snapshot and restore of VMs with more than 2GiB in one region now work
+  correctly
+
+### Contributors
+
+Many thanks to everyone who has contributed to our 0.11.0 release including some new faces.
+
+* Anatol Belski <anbelski@linux.microsoft.com>
+* Bo Chen <chen.bo@intel.com>
+* Daniel Verkamp <dverkamp@chromium.org>
+* Henry Wang <Henry.Wang@arm.com>
+* Hui Zhu <teawater@antfin.com>
+* Jiangbo Wu <jiangbo.wu@intel.com>
+* Josh Soref <jsoref@users.noreply.github.com>
+* Julio Montes <julio.montes@intel.com>
+* Michael Zhao <michael.zhao@arm.com>
+* Muminul Islam <muislam@microsoft.com>
+* pierwill <19642016+pierwill@users.noreply.github.com>
+* Praveen Paladugu <prapal@microsoft.com>
+* Rob Bradford <robert.bradford@intel.com>
+* Sebastien Boeuf <sebastien.boeuf@intel.com>
+* Wei Liu <liuwe@microsoft.com>
+
+
+# v0.10.0
+
+This release has been tracked through the [0.10.0 project](https://github.com/cloud-hypervisor/cloud-hypervisor/projects/13).
+
+Highlights for `cloud-hypervisor` version 0.10.0 include:
+
+### `virtio-block` Support for Multiple Descriptors
+
+Some `virtio-block` device drivers may generate requests with multiple descriptors and support has been added for those drivers.
+
+### Memory Zones
+
+Support has been added for fine grained control of memory allocation for the guest. This includes controlling the backing of sections of guest memory, assigning to specific host NUMA nodes and assigning memory and vCPUs to specific memory nodes inside the guest. Full details of this can be found in the [memory documentation](docs/memory.md).
+
+### `Seccomp` Sandbox Improvements
+
+All the remaining threads and devices are now isolated within their own `seccomp` filters. This provides a layer of sandboxing and enhances the security model of `cloud-hypervisor`.
+
+### Preliminary KVM HyperV Emulation Control
+
+A new option (`kvm_hyperv`) has been added to `--cpus` to provide an option to toggle on KVM's HyperV emulation support. This enables progress towards booting Windows without adding extra emulated devices.
+
+### Notable Bug Fixes
+
+- When using `ch-remote` to resize the VM parameter now accepts the standard sizes suffices (#1596)
+- `cloud-hypervisor` no longer panics when started with `--memory hotplug_method=virtio-mem` and no `hotplug_size` (#1564)
+- After a reboot memory can remove when using `--memory hotplug_method=virtio-mem` (#1593)
+- `--version` shows the version for released binaries (#1669)
+- Errors generated by worker threads for `virtio` devices are now printed out (#1551)
+
+### Contributors
+
+Many thanks to everyone who has contributed to our 0.10.0 release including some new faces.
+
+* Alyssa Ross <hi@alyssa.is>
+* Amey Narkhede <ameynarkhede02@gmail.com>
+* Anatol Belski <ab@php.net>
+* Bo Chen <chen.bo@intel.com>
+* Hui Zhu <teawater@antfin.com>
+* Michael Zhao <michael.zhao@arm.com>
+* Muminul Islam <muislam@microsoft.com>
+* Rob Bradford <robert.bradford@intel.com>
+* Samuel Ortiz <sameo@linux.intel.com>
+* Sebastien Boeuf <sebastien.boeuf@intel.com>
+* Wei Liu <liuwe@microsoft.com>
+
 # v0.9.0
 
 This release has been tracked through the [0.9.0 project](https://github.com/cloud-hypervisor/cloud-hypervisor/projects/12).
@@ -274,7 +480,7 @@ Highlights for `cloud-hypervisor` version 0.7.0 include:
 Further to our effort to support modifying a running guest we now support
 hotplug and unplug of the following virtio backed devices: block, network,
 pmem, virtio-fs and vsock. This functionality is available on the (default) PCI
-based tranport and is exposed through the HTTP API. The `ch-remote` utility
+based transport and is exposed through the HTTP API. The `ch-remote` utility
 provides a CLI for adding or removing these device types after the VM has
 booted. User can use the `id` parameter on the devices to choose names for
 devices to ease their removal.
@@ -390,7 +596,7 @@ When choosing to offload the paravirtualized block and networking I/O to an
 external process (through the `vhost-user` protocol), Cloud Hypervisor now
 automatically spawns its default `vhost-user-blk` and `vhost-user-net` backends
 into their own, separate processes.
-This provides a seamless parvirtualized I/O user experience for those who want
+This provides a seamless paravirtualized I/O user experience for those who want
 to run their guest I/O into separate executions contexts.
 
 ### Command Line Interface
@@ -536,7 +742,7 @@ default Cloud Hypervisor I/O architecture.
 
 ### Guest pause and resume
 
-As an initial requiremnt for enabling live migration, we added support for
+As an initial requirement for enabling live migration, we added support for
 pausing and resuming any VMM components. As an intermediate step towards live
 migration, the upcoming guest snapshotting feature will be based on the pause
 and resume capabilities.