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cpumf: Rewrite chcpumf and lscpumf in C
Rewrite lscpumf and chcpumf in C. The previous version habe been written in perl which require a lot of instructure. Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> Reviewed-by: Sumanth Korikkar <sumanthk@linux.ibm.com> Signed-off-by: Jan Höppner <hoeppner@linux.ibm.com>
This commit is contained in:
Thomas Richter
committed by
Jan Höppner
Jan Höppner
parent
71b36d17f0
commit
199b030580
@@ -1,67 +1,30 @@
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#!/usr/bin/make -f
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include ../common.mak
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TESTS := tests/
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CPUMF_DATADIR = $(TOOLS_DATADIR)/cpumf
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DATA_FILES = cpum-cf-hw-counter.map \
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cpum-cf-cfvn-1.ctr cpum-cf-cfvn-3.ctr \
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cpum-cf-csvn-12345.ctr cpum-cf-csvn-6.ctr \
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cpum-cf-extended-z10.ctr cpum-cf-extended-z196.ctr \
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cpum-cf-extended-zEC12.ctr cpum-sf-modes.ctr \
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cpum-cf-extended-z13.ctr cpum-cf-extended-z14.ctr \
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cpum-cf-extended-z15.ctr
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LIB_FILES = bin/cpumf_helper
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USRBIN_SCRIPTS = bin/lscpumf
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USRSBIN_SCRIPTS = bin/chcpumf
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BIN_FILES = lscpumf chcpumf
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MAN_FILES = lscpumf.1 chcpumf.8
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all:
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all: $(BIN_FILES)
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scripts: $(USRBIN_SCRIPTS) $(USRSBIN_SCRIPTS) $(LIB_FILES)
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chmod +x $(USRBIN_SCRIPTS) $(USRSBIN_SCRIPTS) $(LIB_FILES)
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libs = $(rootdir)/libutil/libutil.a
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check:
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lscpumf: lscpumf.o $(libs)
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chcpumf: chcpumf.o $(libs)
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install: scripts install-man
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for prg in $(USRBIN_SCRIPTS); do \
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$(INSTALL) -g $(GROUP) -o $(OWNER) -m 755 $$prg $(DESTDIR)$(USRBINDIR) ; \
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done
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for prg in $(USRSBIN_SCRIPTS); do \
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$(INSTALL) -g $(GROUP) -o $(OWNER) -m 755 $$prg $(DESTDIR)$(USRSBINDIR) ; \
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done
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test -d $(DESTDIR)$(CPUMF_DATADIR) || mkdir -p $(DESTDIR)$(CPUMF_DATADIR)
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for lib in $(LIB_FILES); do \
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$(INSTALL) -g $(GROUP) -o $(OWNER) -m 755 $$lib $(DESTDIR)$(TOOLS_LIBDIR) ; \
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done
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for data in $(DATA_FILES); do \
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$(INSTALL) -g $(GROUP) -o $(OWNER) -m 644 data/$$data $(DESTDIR)$(CPUMF_DATADIR) ; \
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install: all install-man
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$(INSTALL) -d -m 755 $(DESTDIR)$(BINDIR) $(DESTDIR)$(MANDIR)/man8
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for binf in $(BIN_FILES); do \
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$(INSTALL) -g $(GROUP) -o $(OWNER) -m 755 $$binf $(DESTDIR)$(BINDIR); \
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done
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clean:
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rm -f *.o *~ $(BIN_FILES) core
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install-man:
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for man in $(MAN_FILES); do \
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msection=`echo $$man |sed 's/.*\.\([1-9]\)$$/man\1/'` ; \
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$(INSTALL) -g $(GROUP) -o $(OWNER) -m 644 -D man/$$man $(DESTDIR)$(MANDIR)/$$msection/$$man ; \
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done
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man2pdf:
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for man in $(MAN_FILES); do \
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man -t man/$$man |ps2pdf -sPAPERSIZE=a4 - man/$${man}.pdf ; \
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done
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man2text:
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for man in $(MAN_FILES); do \
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MANWIDTH=80 LANG=C man man/$$man |col -b |expand > man/$${man}.txt ; \
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done
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clean:
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rm -f $(LIB_FILES) $(USRBIN_SCRIPTS) $(USRSBIN_SCRIPTS)
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%: %.in
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real_libdir=$(TOOLS_LIBDIR); \
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real_cpumfdatadir=$(CPUMF_DATADIR); \
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$(SED) -e "s#@lib_path@#$$real_libdir#g" \
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-e "s#@cpumfdata_path@#$$real_cpumfdatadir#g" \
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-e 's#@S390_TOOLS_RELEASE@#$(S390_TOOLS_RELEASE)#g' \
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< $< > $@
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.PHONY: all scripts install install-man man2pdf man2text clean
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.PHONY: all install clean
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@@ -1,182 +0,0 @@
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#!/usr/bin/perl -W
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#
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# chcpumf - Control CPU-measurement facilities
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#
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# Copyright IBM Corp. 2014, 2017
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#
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# s390-tools is free software; you can redistribute it and/or modify
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# it under the terms of the MIT license. See LICENSE for details.
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#
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use strict;
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use warnings;
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use File::Basename qw/fileparse/;
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use Data::Dumper;
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use Getopt::Long qw/:config no_ignore_case/;
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# Global constants
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my $CPUMF_HELPER = '@lib_path@/cpumf_helper';
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my $CPUM_SFB_SIZE = '/sys/module/kernel/parameters/cpum_sfb_size';
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# Prototypes
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sub main();
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sub show_help();
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sub show_version();
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sub do_set_sfb_size($);
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sub cpumf_set_sfb_size($);
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sub invoke_cpumf_helper($);
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sub main()
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{
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my $config = {
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# Internal data
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cpumf => {}, # CPU-MF information hash
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};
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unless (GetOptions(
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# General options for help, version, verbose,...
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"h|help" => \&show_help,
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"v|version" => \&show_version,
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"V|verbose+" => \$config->{verbose},
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# Change specific options
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"m|min=i" => \$config->{min},
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"x|max=i" => \$config->{max},
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)) {
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print STDERR "One or more options are not valid\n";
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print STDERR "Try '" . fileparse($0) .
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" --help' for more information\n";
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exit 1;
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}
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# Collect CPU-MF information
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$config->{cpumf} = invoke_cpumf_helper("-i");
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die "Failed to collect CPU-MF information: $!\n" unless $config->{cpumf};
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# Process parameters
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my $exitval = 5;
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if (defined($config->{min}) || defined($config->{max})) {
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$exitval = do_set_sfb_size($config);
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} else {
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print STDERR "You must specify a valid option\n";
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exit 1;
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}
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exit($exitval);
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}
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sub show_help()
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{
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my $prog = fileparse($0);
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print <<"EoHelp";
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Usage: chcpumf -h|-v
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chcpumf -m <num_sdb>
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chcpumf -x <num_sdb>
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Options:
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-m <num_sdb> Specifies the initial size of the sampling buffer.
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A sample-data-block (SDB) consumes about 4 kilobytes.
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-x <num_sdb> Specifies the maximum size of the sampling buffer.
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A sample-data-block (SDB) consumes about 4 kilobytes.
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-h Displays help information, then exits.
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-v Displays version information, then exits.
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For more help information, issue 'man $prog'.
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EoHelp
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exit 0;
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}
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sub show_version()
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{
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print <<'EoVersion';
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CPU-measurement facility utilities, version @S390_TOOLS_RELEASE@
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Copyright IBM Corp. 2014, 2017
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EoVersion
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exit 0;
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}
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sub cpumf_set_sfb_size($)
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{
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my @size = @{shift()};
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my $val = join ',', @size[0,1];
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my ($SFBSIZE, $rc);
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return undef unless open($SFBSIZE, '>', $CPUM_SFB_SIZE);
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# Check the return code of print and close to detect error conditions
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# reported by the device driver. Because perl might buffer data, print
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# might be successful, but close might then report the error condition.
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# So check the return code of both functions and always close the file
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# handle.
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$rc = print { $SFBSIZE } "$val\n";
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unless ($rc) {
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close($SFBSIZE);
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return $rc;
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}
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return close($SFBSIZE);
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}
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sub do_set_sfb_size($)
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{
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my $c = shift();
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my $size;
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# Check if sampling facility is available
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unless (exists $c->{cpumf}->{sf}) {
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print STDERR "No CPU-measurement sampling facility detected\n";
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return 2;
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}
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# Check if perf support is available
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unless (exists $c->{cpumf}->{sf}->{perf}) {
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print STDERR "No perf support for the CPU-measurement" .
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" sampling facility availalble\n";
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return 2;
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}
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# Optionally, change the sampling buffer sizes
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if (defined($c->{min}) || defined($c->{max})) {
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$size = invoke_cpumf_helper("--sfb-size");
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# Use current size value for zero min/max specifications
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$size->[0] = $c->{min} if defined($c->{min});
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$size->[1] = $c->{max} if defined($c->{max});
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# Validate new settings
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if ($size->[0] < 1 || $size->[1] < 1) {
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die "The specified number(s) are not valid\n";
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}
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if ($size->[0] >= $size->[1]) {
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die "The specified maximum must be greater " .
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"than the minimum\n";
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}
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# Set new sampling buffer sizes
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unless (cpumf_set_sfb_size($size)) {
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die "Failed to change sampling buffer size: $!\n";
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}
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}
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# Finally, show sampling buffer sizes
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if ($c->{verbose}) {
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$size = invoke_cpumf_helper("--sfb-size");
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print "Sampling buffer sizes:\n";
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printf " Minimum: %6u sample-data-blocks\n", $size->[0];
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printf " Maximum: %6u sample-data-blocks\n", $size->[1];
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}
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return 0;
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}
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sub invoke_cpumf_helper($)
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{
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my $parms = shift();
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my $result;
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# Call helper module
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my $output = qx"$CPUMF_HELPER $parms";
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die "Failed to run helper module for '$parms'\n" if $? >> 8;
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$result = eval "$output";
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die "Failed to parse helper module data\n" if $@;
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return $result;
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}
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&main();
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__DATA__
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__END__
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@@ -1,489 +0,0 @@
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#!/usr/bin/perl -W
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#
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# cpumf_helper - Helper module for managing CPU-measurement facilities (CPU-MF)
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#
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# Copyright IBM Corp. 2014, 2017
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#
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# s390-tools is free software; you can redistribute it and/or modify
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# it under the terms of the MIT license. See LICENSE for details.
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#
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use strict;
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use warnings;
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use Carp qw/croak/;
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use Data::Dumper;
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use Getopt::Long qw/:config no_ignore_case/;
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# Global constants
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my $SERVICE_LEVELS = '/proc/service_levels';
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my $CPUMF_DATA_DIR = '@cpumfdata_path@';
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my $CPUM_SFB_SIZE = '/sys/module/kernel/parameters/cpum_sfb_size';
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my $CPUM_SF_DBF='/sys/kernel/debug/s390dbf/cpum_sf';
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# Counter set bits (according to QUERY COUNTER INFORMATION)
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my $BASIC_SET = 0x0002;
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my $PROBLEM_STATE_SET = 0x0004;
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my $CRYPTO_SET = 0x0008;
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my $EXTENTED_SET = 0x0001;
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my $MT_DIAG_SET = 0x0020;
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my $COPROC_GRP_SET = 0x8000;
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# Public prototypes
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sub cpumf_collect_data();
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sub cpumf_get_sfb_size();
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sub cpumf_set_sfb_size($);
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sub cpumf_parse_ctrdef($;$);
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sub cpumf_load_ctrdef($;$);
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sub cpumf_get_counter_set($);
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sub cpumf_counter_set_names();
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sub cpumf_counter_set_ids();
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sub cpumf_hardware_counter_map();
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# Internal prototypes
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sub cpumf_parse_cf($$);
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sub cpumf_parse_sf($$);
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sub cpumf_get_sfb_size()
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{
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my $val = "0,0";
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my $SFBSIZE;
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if (open($SFBSIZE, '<', $CPUM_SFB_SIZE)) {
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$val = <$SFBSIZE>;
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chomp($val);
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close($SFBSIZE);
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}
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return [split /,/, $val];
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}
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sub cpumf_set_sfb_size($)
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{
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my @size = @{shift()};
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my $val = join ',', @size[0,1];
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my ($SFBSIZE, $rc);
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return undef unless open($SFBSIZE, '>', $CPUM_SFB_SIZE);
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# Check the return code of print and close to detect error conditions
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# reported by the device driver. Because perl might buffer data, print
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# might be successful, but close might then report the error condition.
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# So check the return code of both functions and always close the file
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# handle.
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$rc = print { $SFBSIZE } "$val\n";
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unless ($rc) {
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close($SFBSIZE);
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return $rc;
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}
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return close($SFBSIZE);
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}
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sub cpumf_parse_cf($$)
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{
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my ($ent, $data) = @_;
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if ($ent =~ /version=([0-9.]+) authorization=([[:xdigit:]]+)/) {
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$data->{cf} = { version => $1, auth => hex($2) };
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}
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}
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sub cpumf_parse_sf($$)
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{
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my ($ent, $data) = @_;
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# Parse common sampling facility entry
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if ($ent =~ /min_rate=(\d+) max_rate=(\d+) cpu_speed=(\d+)/) {
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$data->{sf} = {
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min_sampl_interval => $1,
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max_sampl_interval => $2,
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cpu_speed => $3,
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# This contains a list of authorized sampling modes, for
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# example, basic
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modes => {},
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};
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}
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# Parse sampling facility mode entries
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if ($ent =~ /mode=(\w+) sample_size=(\d+)/) {
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$data->{sf}->{modes}->{$1}->{sample_size} = $2;
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}
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}
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sub cpumf_collect_data()
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{
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my $SL;
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# Collect CPU-MF information from /proc/service_levels
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return undef unless open($SL, '<', $SERVICE_LEVELS);
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my @sl = <$SL>;
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chomp(@sl);
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close($SL);
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# Process CPU-MF information and build data hash
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my $data = {};
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foreach my $ent (@sl) {
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$ent =~ s/^CPU-MF: // or next;
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cpumf_parse_cf($ent, $data) if $ent =~ s/Counter facility: //;
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cpumf_parse_sf($ent, $data) if $ent =~ s/Sampling facility: //;
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}
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# Collect perf support for available facilities
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if (-e '/sys/bus/event_source/devices/cpum_cf') {
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$data->{cf}->{perf} = "cpum_cf" if exists $data->{cf};
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}
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if (-e '/sys/bus/event_source/devices/cpum_sf') {
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$data->{sf}->{perf} = "cpum_sf" if exists $data->{sf};
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}
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return $data;
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}
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# Parse the specified counter definition file and returns a hash containing
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# the parsed counter definition. The optional argument specifies a hash
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# reference to which the new definitions are added. This reference is returned.
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sub cpumf_parse_ctrdef($;$)
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{
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my $ctrdef = shift();
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my $h = @_ ? shift() : {};
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my $CTRDEF;
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return undef unless open($CTRDEF, '<', "$CPUMF_DATA_DIR/$ctrdef");
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my ($ctr, $name);
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while (my $line = <$CTRDEF>) {
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next if $line =~ /^#/;
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chomp($line);
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# Parse start of counter definition entry
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if ($line =~ m/^Counter:\s*(0x[[:xdigit:]]+|\d+)
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\s+Name:\s*([[:alnum:]_]+)$/x) {
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($ctr, $name) = ($1, $2);
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$ctr = hex($ctr) if $ctr =~ /^0x/;
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unless (length($ctr)) {
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print STDERR "Found invalid entry in counter " .
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"definition: line $.\n";
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}
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$h->{$ctr} = { name => $name || "" };
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}
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# At this point, a counter must be defined
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next unless defined($ctr);
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# Parse short description (optional)
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if ($line =~ m/^Short-Description:\s*(\S.*)?$/) {
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$h->{$ctr}->{shortdesc} = $1 || "";
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# Parse start of counter description
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} elsif ($line =~ m/^Description:\s*(\S.*)?$/) {
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$h->{$ctr}->{desc} = $1 || "";
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# Parse end of counter description
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} elsif ($line =~ m/^\.$/) {
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# Complete the counter definition
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$h->{$ctr}->{set} = cpumf_get_counter_set($ctr);
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# Trim whitespaces
|
||||
$h->{$ctr}->{shortdesc} =~ s/^\s+|\s+$//g if $h->{$ctr}->{shortdesc};
|
||||
$h->{$ctr}->{desc} =~ s/^\s+|\s+$//g if $h->{$ctr}->{desc};
|
||||
# Finally, reset counter for next entry
|
||||
$ctr = undef;
|
||||
|
||||
# Line is part of counter description (if $ctr_num is set)
|
||||
} else {
|
||||
$h->{$ctr}->{desc} .= " $line";
|
||||
}
|
||||
}
|
||||
close($CTRDEF);
|
||||
|
||||
return $h;
|
||||
}
|
||||
|
||||
# IBM System z hardware with CPU-M counter facility support
|
||||
my $system_z_hwtype_map = {
|
||||
# Machine type Description
|
||||
'' => 'Unknown hardware model',
|
||||
2097 => 'IBM System z10 EC',
|
||||
2098 => 'IBM System z10 BC',
|
||||
2817 => 'IBM zEnterprise 196',
|
||||
2818 => 'IBM zEnterprise 114',
|
||||
2827 => 'IBM zEnterprise EC12',
|
||||
2828 => 'IBM zEnterprise BC12',
|
||||
2964 => 'IBM z13',
|
||||
2965 => 'IBM z13s',
|
||||
3906 => 'IBM z14',
|
||||
3907 => 'IBM z14 ZR1',
|
||||
8561 => 'IBM z15',
|
||||
};
|
||||
|
||||
sub get_hardware_type()
|
||||
{
|
||||
my $type = "";
|
||||
my $SYSINFO;
|
||||
|
||||
return undef unless open($SYSINFO, '<', '/proc/sysinfo');
|
||||
while (my $line = <$SYSINFO>) {
|
||||
if ($line =~ m/^Type:\s*(\d+)\s*$/) {
|
||||
$type = $1;
|
||||
last;
|
||||
}
|
||||
}
|
||||
close($SYSINFO);
|
||||
return $type;
|
||||
}
|
||||
|
||||
sub get_cpum_cf_version()
|
||||
{
|
||||
my $SL;
|
||||
|
||||
my $v = {
|
||||
cfvn => 0,
|
||||
csvn => 0,
|
||||
};
|
||||
|
||||
return $v unless open($SL, '<', $SERVICE_LEVELS);
|
||||
while (my $line = <$SL>) {
|
||||
# CPU-MF: Counter facility: version=3.5
|
||||
if ($line =~ m/^CPU-MF: Counter facility: version=(\d+)\.(\d+)/) {
|
||||
$v->{cfvn} = $1; # Counter First Version Number
|
||||
$v->{csvn} = $2; # Counter Second Version Number
|
||||
last;
|
||||
}
|
||||
}
|
||||
close($SL);
|
||||
return $v
|
||||
}
|
||||
|
||||
sub cpumf_load_ctrdef($;$)
|
||||
{
|
||||
my $hw_type = shift();
|
||||
my $authorized = @_ ? shift() : 0xffff; # Counter Set authorization
|
||||
|
||||
my $ctrmap = cpumf_hardware_counter_map();
|
||||
return unless $ctrmap;
|
||||
|
||||
# Obtain CPU-MF counter facility versions
|
||||
my $version = get_cpum_cf_version();
|
||||
|
||||
# List of "generic" counter sets
|
||||
my @def = ();
|
||||
push @def, "cfvn-" . $version->{cfvn};
|
||||
if ($version->{csvn} >= 1 && $version->{csvn} <= 6) {
|
||||
push @def, "csvn-12345";
|
||||
}
|
||||
if ($version->{csvn} == 6) {
|
||||
push @def, "csvn-6";
|
||||
}
|
||||
|
||||
my $h = {};
|
||||
# Load counter set definition
|
||||
foreach my $ent (@def) {
|
||||
cpumf_parse_ctrdef($ctrmap->{$ent}, $h) or
|
||||
croak "Failed to read counter definition for $ent: $!\n";
|
||||
}
|
||||
# Load hardware model specific counter set(s)
|
||||
if ($hw_type && $ctrmap->{$hw_type}) {
|
||||
# Hardware-model specific counter sets are:
|
||||
# - Extended Counter Set
|
||||
# - MT-diagnostic Counter Set
|
||||
cpumf_parse_ctrdef($ctrmap->{$hw_type}, $h) or
|
||||
croak "Failed to read hardware-model counter definition: $!\n";
|
||||
}
|
||||
|
||||
# Remove counter sets that miss authorizations
|
||||
my @no_auth_list = ();
|
||||
foreach my $ctr (sort keys %$h) {
|
||||
push @no_auth_list, $ctr unless $h->{$ctr}->{set} & $authorized;
|
||||
}
|
||||
delete $h->{$_} foreach (@no_auth_list);
|
||||
|
||||
return $h;
|
||||
}
|
||||
|
||||
|
||||
sub cpumf_get_counter_set($)
|
||||
{
|
||||
my $ctr = shift();
|
||||
|
||||
return $BASIC_SET if $ctr < 32;
|
||||
return $PROBLEM_STATE_SET if $ctr < 64;
|
||||
return $CRYPTO_SET if $ctr < 128;
|
||||
#
|
||||
# The extended counter set ranges from
|
||||
# 128 to
|
||||
# 159 for csvn == 1
|
||||
# 175 for csvn == 2
|
||||
# 255 for csvn > 2
|
||||
# Tolerate any future counters up to
|
||||
# the MT-diagnostic counter set.
|
||||
return $EXTENTED_SET if $ctr < 448;
|
||||
#
|
||||
# The MT-diagnostic counter set ranges from
|
||||
# 448 to
|
||||
# 495 for cvsn > 3
|
||||
return $MT_DIAG_SET if $ctr <= 495;
|
||||
return 0;
|
||||
}
|
||||
|
||||
sub cpumf_counter_set_names()
|
||||
{
|
||||
return {
|
||||
# Identifier Name
|
||||
$BASIC_SET => 'Basic Counter Set',
|
||||
$PROBLEM_STATE_SET => 'Problem-State Counter Set',
|
||||
$CRYPTO_SET => 'Crypto-Activity Counter Set',
|
||||
$EXTENTED_SET => 'Extended Counter Set',
|
||||
$MT_DIAG_SET => 'MT-diagnostic Counter Set',
|
||||
$COPROC_GRP_SET => 'Coprocessor Group Counter Set',
|
||||
};
|
||||
}
|
||||
|
||||
sub cpumf_counter_set_ids()
|
||||
{
|
||||
return [$BASIC_SET, $PROBLEM_STATE_SET, $CRYPTO_SET, $EXTENTED_SET,
|
||||
$MT_DIAG_SET, $COPROC_GRP_SET];
|
||||
}
|
||||
|
||||
sub cpumf_hardware_counter_map()
|
||||
{
|
||||
my $map = do "$CPUMF_DATA_DIR/cpum-cf-hw-counter.map";
|
||||
croak "Failed to parse mapfile: $@" if $@;
|
||||
croak "Failed to read mapfile: $!" unless defined $map;
|
||||
return $map;
|
||||
}
|
||||
|
||||
my $cpumf_helper_str = <<'END_MESSAGE';
|
||||
|
||||
cpumf_helper - Helper module for managing CPU-Measurement Facilities (CPU-MF)
|
||||
|
||||
Options:
|
||||
-i, --info:
|
||||
Displays detailed information about installed and available
|
||||
CPU-measurement facilities and the related Linux support.
|
||||
|
||||
-c, --counter authorization_value
|
||||
Displays counter information for the current System z hardware.
|
||||
The authorization value provides information about the authorized
|
||||
counter sets. The value must be specified in decimal format.
|
||||
|
||||
To display all supported counters, specify C<65535> (FFFF hex).
|
||||
|
||||
To display supported counters for a particular System z hardware,
|
||||
use the --ctr-def option and specify the System z hardware type.
|
||||
|
||||
--hardware-type
|
||||
Displays the System z hardware type.
|
||||
|
||||
--ctr-def ctr-definition
|
||||
Displays detailed information about the specified counter definition.
|
||||
Valid counter definitions start with C<cfvn-> or <csvn-> followed by
|
||||
the counter first/second version number of the CPU-Measurement Counter
|
||||
Facility. To display counter information of model-specific counter
|
||||
sets, specify the System z hardware type for I<ctr-definition>.
|
||||
|
||||
--ctr-set-names
|
||||
Displays the mapping of counter set IDs to counter set names.
|
||||
The counter set IDs are numbers that are used in counter definitions.
|
||||
|
||||
--ctr-set-ids
|
||||
Displays the counter set IDs. The counter set IDs are numbers that
|
||||
match the authorization bits (see QUERY COUNTER INFORMATION).
|
||||
The output format is a list. To get the ID for a particular counter
|
||||
set, use an index number as follows:
|
||||
|
||||
0: Basic Counter Set
|
||||
1: Problem-State Counter Set
|
||||
2: Crypto-Activity Counter Set
|
||||
3: Extended Counter Set
|
||||
4: MT-diagnostic Counter Set
|
||||
5: Coprocessor Group Counter Set
|
||||
|
||||
--ctr-sf
|
||||
Displays the counter definitions for the sampling facility support.
|
||||
These counter definitions are specific to Linux perf infrastructure.
|
||||
|
||||
--sfb-size
|
||||
Displays the size of the sampling facility buffer (SFB). The minimum
|
||||
and maximum numbers are measured in units of sample-data-blocks. A
|
||||
sample-data-block uses about 4 kilobytes.
|
||||
|
||||
END_MESSAGE
|
||||
|
||||
sub cpumf_helper_main()
|
||||
{
|
||||
# Configuration settings and options
|
||||
my $conf = {
|
||||
};
|
||||
|
||||
# Parse command line option
|
||||
GetOptions(
|
||||
"i|info" => \$conf->{opt_info},
|
||||
"c|counter=i" => \$conf->{opt_ctr},
|
||||
"ctr-def=s" => \$conf->{opt_ctrdef},
|
||||
"hardware-type" => \$conf->{opt_hwtype},
|
||||
"ctr-set-names" => \$conf->{opt_ctrset_names},
|
||||
"ctr-set-ids" => \$conf->{opt_ctrset_ids},
|
||||
"sfb-size" => \$conf->{opt_sfb_size},
|
||||
"ctr-sf" => \$conf->{opt_sf_ctr},
|
||||
) or die("One or more options are not valid\n" . $cpumf_helper_str);
|
||||
|
||||
|
||||
# Setting up Data::Dumper to create parseable Perl output
|
||||
local $Data::Dumper::Purity = 1;
|
||||
local $Data::Dumper::Sortkeys = 1;
|
||||
local $Data::Dumper::Terse = 1;
|
||||
|
||||
###print STDERR "CONF: " . Dumper($conf) . "\n";
|
||||
|
||||
# Process command line options
|
||||
my $exitval = 0;
|
||||
my $result;
|
||||
if (defined($conf->{opt_info})) {
|
||||
$result = cpumf_collect_data();
|
||||
|
||||
# Display System z hardware type
|
||||
} elsif (defined($conf->{opt_hwtype})) {
|
||||
my $type = get_hardware_type();
|
||||
$result = [$type, $system_z_hwtype_map->{$type} || ""];
|
||||
|
||||
# Display counters for current System z hardware
|
||||
} elsif (defined($conf->{opt_ctr})) {
|
||||
my $type = get_hardware_type();
|
||||
$type = 0 unless $type;
|
||||
$result = cpumf_load_ctrdef($type, $conf->{opt_ctr});
|
||||
|
||||
# Display counters for a particular System z hardware type
|
||||
} elsif (defined($conf->{opt_ctrdef})) {
|
||||
my $m = cpumf_hardware_counter_map();
|
||||
if (exists $m->{$conf->{opt_ctrdef}}) {
|
||||
$result = cpumf_parse_ctrdef($m->{$conf->{opt_ctrdef}});
|
||||
} else {
|
||||
printf STDERR "Invalid counter definition\n";
|
||||
$exitval = 2;
|
||||
}
|
||||
# Display the size of the sampling facility buffer (sfb)
|
||||
} elsif (defined($conf->{opt_sfb_size})) {
|
||||
$result = cpumf_get_sfb_size();
|
||||
|
||||
# Display counter definitions for the sampling facility support (perf)
|
||||
} elsif (defined($conf->{opt_sf_ctr})) {
|
||||
$result = cpumf_parse_ctrdef('cpum-sf-modes.ctr');
|
||||
|
||||
# Display mapping of counter set IDs to counter set names
|
||||
} elsif (defined($conf->{opt_ctrset_names})) {
|
||||
$result = cpumf_counter_set_names();
|
||||
|
||||
# Display counter set IDs
|
||||
} elsif (defined($conf->{opt_ctrset_ids})) {
|
||||
$result = cpumf_counter_set_ids();
|
||||
|
||||
} else {
|
||||
die("No option specified\n" . $cpumf_helper_str);
|
||||
}
|
||||
|
||||
# Display result
|
||||
print Dumper($result) if $result;
|
||||
exit $exitval;
|
||||
}
|
||||
|
||||
&cpumf_helper_main();
|
||||
__DATA__
|
||||
__END__
|
||||
@@ -1,387 +0,0 @@
|
||||
#!/usr/bin/perl -W
|
||||
#
|
||||
# lscpumf - Display information about CPU-measurement facilities
|
||||
#
|
||||
# Copyright IBM Corp. 2014, 2017
|
||||
#
|
||||
# s390-tools is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the MIT license. See LICENSE for details.
|
||||
#
|
||||
use strict;
|
||||
use warnings;
|
||||
use Data::Dumper;
|
||||
use File::Basename qw/fileparse/;
|
||||
use Getopt::Long qw/:config no_ignore_case/;
|
||||
|
||||
# Global constants
|
||||
my $CPUMF_HELPER = '@lib_path@/cpumf_helper';
|
||||
|
||||
# Prototypes
|
||||
sub main();
|
||||
sub show_help();
|
||||
sub show_version();
|
||||
sub do_show_info($);
|
||||
sub do_show_cf($);
|
||||
sub do_show_sf($);
|
||||
sub do_show_ctr($;$);
|
||||
sub do_show_sf_events($);
|
||||
sub invoke_cpumf_helper($);
|
||||
|
||||
|
||||
sub main()
|
||||
{
|
||||
my $config = {
|
||||
# Internal data
|
||||
cpumf => {}, # CPU-MF information hash
|
||||
};
|
||||
|
||||
unless (GetOptions(
|
||||
# General options for help, version,...
|
||||
"h|help" => \&show_help,
|
||||
"v|version" => \&show_version,
|
||||
# Display options
|
||||
"i|info" => \$config->{opt_info},
|
||||
"c|list-counters" => \$config->{opt_ctr},
|
||||
"C|list-all-counters" => \$config->{opt_ctr_all},
|
||||
"s|list-sampling-events" => \$config->{opt_ctr_sf},
|
||||
)) {
|
||||
print STDERR "One or more options are not valid\n";
|
||||
print STDERR "Try '" . fileparse($0) .
|
||||
" --help' for more information\n";
|
||||
exit 1;
|
||||
}
|
||||
|
||||
# Collect CPU-MF information
|
||||
$config->{cpumf} = invoke_cpumf_helper("-i");
|
||||
die "Failed to collect CPU-MF information: $!\n" unless $config->{cpumf};
|
||||
|
||||
# Process parameters
|
||||
my $exitval = 5;
|
||||
if (defined($config->{opt_info})) {
|
||||
do_show_cf($config);
|
||||
do_show_sf($config);
|
||||
$exitval = 0;
|
||||
|
||||
} elsif (defined($config->{opt_ctr})) {
|
||||
$exitval = do_show_ctr($config);
|
||||
} elsif (defined($config->{opt_ctr_all})) {
|
||||
$exitval = do_show_ctr($config, "all")
|
||||
} elsif (defined($config->{opt_ctr_sf})) {
|
||||
$exitval = do_show_sf_events($config);
|
||||
} else {
|
||||
$exitval = do_show_info($config);
|
||||
}
|
||||
|
||||
exit($exitval);
|
||||
}
|
||||
|
||||
sub show_help()
|
||||
{
|
||||
my $prog = fileparse($0);
|
||||
|
||||
print <<"EoHelp";
|
||||
Usage: lscpumf -h|-v
|
||||
lscpumf [-i]
|
||||
lscpumf -c|-C
|
||||
|
||||
Options:
|
||||
-i Displays detailed information.
|
||||
-c Lists counters for which the LPAR is authorized.
|
||||
-C Lists counters regardless of LPAR authorization.
|
||||
-s Lists perf raw events that activate the sampling facility.
|
||||
-h Displays help information, then exits.
|
||||
-v Displays version information, then exits.
|
||||
|
||||
For more help information, issue 'man $prog'.
|
||||
EoHelp
|
||||
exit 0;
|
||||
}
|
||||
|
||||
sub show_version()
|
||||
{
|
||||
print <<'EoVersion';
|
||||
CPU-measurement facility utilities, version @S390_TOOLS_RELEASE@
|
||||
Copyright IBM Corp. 2014, 2017
|
||||
|
||||
EoVersion
|
||||
exit 0;
|
||||
}
|
||||
|
||||
sub do_show_info($)
|
||||
{
|
||||
my $c = shift();
|
||||
my $cpumf = $c->{cpumf};
|
||||
my @f = ();
|
||||
|
||||
push @f, "CPU-measurement Counter Facility" if exists $cpumf->{cf};
|
||||
push @f, "CPU-measurement Sampling Facility" if exists $cpumf->{sf};
|
||||
|
||||
if (@f) {
|
||||
print((join "\n", @f) . "\n");
|
||||
} else {
|
||||
print STDERR "No CPU-measurement facilities detected\n";
|
||||
return 2;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
sub do_show_cf($)
|
||||
{
|
||||
my $c = shift();
|
||||
|
||||
# Check if counter facility is available
|
||||
unless (exists $c->{cpumf}->{cf}) {
|
||||
print STDERR "No CPU-measurement counter facility detected\n";
|
||||
return 2;
|
||||
}
|
||||
|
||||
# Retrieve counter facility information
|
||||
my $cf = $c->{cpumf}->{cf};
|
||||
|
||||
# Create list of authorized counter sets
|
||||
my @sets = ();
|
||||
push @sets, "None" unless $cf->{auth};
|
||||
push @sets, "Crypto-Activity counter set" if $cf->{auth} & 0x8;
|
||||
push @sets, "Problem-State counter set" if $cf->{auth} & 0x4;
|
||||
push @sets, "Basic counter set" if $cf->{auth} & 0x2;
|
||||
push @sets, "Extented counter set" if $cf->{auth} & 0x1;
|
||||
push @sets, "MT-diagnostic counter set" if $cf->{auth} & 0x20;
|
||||
|
||||
print "CPU-measurement counter facility\n";
|
||||
print "-" x 74 . "\n";
|
||||
# TODO Display additional information about available conters depending
|
||||
# on the version information
|
||||
print "Version: " . $cf->{version} . "\n";
|
||||
print "\n";
|
||||
print "Authorized counter sets:\n";
|
||||
print " $_\n" foreach (sort @sets);
|
||||
printf "\nLinux perf event support: %s\n\n",
|
||||
exists $cf->{perf} ? "Yes (PMU: $cf->{perf})" : "No";
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
sub div_ceil($$)
|
||||
{
|
||||
my ($a, $b) = @_;
|
||||
return int(($a + $b - 1) / $b);
|
||||
}
|
||||
|
||||
sub humanize_bytes($;$)
|
||||
{
|
||||
my $bytes = shift();
|
||||
my @units = split //, " KMGTPEZY";
|
||||
|
||||
my $u = @_ ? shift() : 0;
|
||||
while ($bytes >= 1024 && $u <= $#units) {
|
||||
$bytes /= 1024;
|
||||
$u++;
|
||||
}
|
||||
return sprintf "%.f%sB", $bytes, $units[$u];
|
||||
}
|
||||
|
||||
sub get_sfb_details($)
|
||||
{
|
||||
my $n_sdb = shift();
|
||||
|
||||
# Calculate sampling buffer structure
|
||||
my $n_sdbt = div_ceil($n_sdb, 511);
|
||||
my $n_pages = $n_sdb + $n_sdbt;
|
||||
return [
|
||||
$n_sdb, # number of sample-data-blocks
|
||||
$n_sdbt, # number of sample-data-block-tables
|
||||
$n_pages, # number of 4K pages
|
||||
$n_pages * 4096, # size in bytes
|
||||
];
|
||||
}
|
||||
|
||||
sub do_show_sf($)
|
||||
{
|
||||
my $c = shift();
|
||||
|
||||
# Check if sampling facility is available
|
||||
unless (exists $c->{cpumf}->{sf}) {
|
||||
print STDERR "No CPU-measurement sampling facility detected\n";
|
||||
return 2;
|
||||
}
|
||||
my $sf = $c->{cpumf}->{sf};
|
||||
my $size = invoke_cpumf_helper("--sfb-size");
|
||||
|
||||
# Sampling facility information
|
||||
print "CPU-measurement sampling facility\n";
|
||||
print "-" x 74 . "\n";
|
||||
print "Sampling Interval:\n";
|
||||
printf " Minimum: %10u cycles (approx. %8u Hz)\n",
|
||||
$sf->{min_sampl_interval},
|
||||
1000000 * $sf->{cpu_speed} / $sf->{min_sampl_interval};
|
||||
printf " Maximum: %10u cycles (approx. %8u Hz)\n",
|
||||
$sf->{max_sampl_interval},
|
||||
1000000 * $sf->{cpu_speed} / $sf->{max_sampl_interval};
|
||||
print "\n";
|
||||
print "Authorized sampling modes:\n";
|
||||
foreach my $m (sort keys %{$sf->{modes}}) {
|
||||
printf " %-10s (sample size: %3u bytes)\n", $m,
|
||||
$sf->{modes}->{$m}->{sample_size};
|
||||
}
|
||||
print "\n";
|
||||
printf "\nLinux perf event support: %s\n\n",
|
||||
exists $sf->{perf} ? "Yes (PMU: $sf->{perf})" : "No";
|
||||
|
||||
# Sampling buffer settings for cpum_sf
|
||||
goto out unless exists $sf->{perf};
|
||||
|
||||
print "Current sampling buffer settings for $sf->{perf}:\n";
|
||||
printf " Basic-sampling mode\n";
|
||||
my $s = get_sfb_details($size->[0]);
|
||||
printf " Minimum: %6u sample-data-blocks (%6s)\n",
|
||||
$s->[0], humanize_bytes($s->[3]);
|
||||
$s = get_sfb_details($size->[1]);
|
||||
printf " Maximum: %6u sample-data-blocks (%6s)\n",
|
||||
$s->[0], humanize_bytes($s->[3]);
|
||||
unless (exists $sf->{modes}->{diagnostic}) {
|
||||
goto out;
|
||||
}
|
||||
|
||||
# Sampling buffer setting specific to diagnostic-sampling mode
|
||||
my $f_diag = div_ceil($sf->{modes}->{diagnostic}->{sample_size},
|
||||
$sf->{modes}->{basic}->{sample_size});
|
||||
print "\n";
|
||||
printf " Diagnostic-sampling mode (including basic-sampling)\n";
|
||||
$s = get_sfb_details($size->[0] * $f_diag);
|
||||
printf " Minimum: %6u sample-data-blocks (%6s)\n",
|
||||
$s->[0], humanize_bytes($s->[3]);
|
||||
$s = get_sfb_details($size->[1] * $f_diag);
|
||||
printf " Maximum: %6u sample-data-blocks (%6s)\n",
|
||||
$s->[0], humanize_bytes($s->[3]);
|
||||
printf " Size factor: %2u\n", $f_diag;
|
||||
out:
|
||||
return 0;
|
||||
}
|
||||
|
||||
sub print_counters($$)
|
||||
{
|
||||
my ($ctrdef, $header) = @_;
|
||||
my $set_name_map = invoke_cpumf_helper('--ctr-set-names');
|
||||
my $out = [];
|
||||
|
||||
my ($ctr_perf, $ctr_num, $set, $name, $desc);
|
||||
format PERF_CTR_FORM =
|
||||
r@<<<< @<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
||||
$ctr_perf, $name
|
||||
|
||||
^<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
||||
$desc
|
||||
^<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< ~~
|
||||
$desc
|
||||
@<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
||||
$set
|
||||
|
||||
.
|
||||
print $header;
|
||||
$~ = "PERF_CTR_FORM";
|
||||
foreach my $ctr (sort { $a <=> $b } keys %$ctrdef) {
|
||||
$ctr_perf = sprintf "%x", $ctr;
|
||||
$ctr_num = $ctr < (1 << 16) ? $ctr : "";
|
||||
$name = $ctrdef->{$ctr}->{name};
|
||||
$desc = $ctrdef->{$ctr}->{shortdesc} ?
|
||||
$ctrdef->{$ctr}->{shortdesc}
|
||||
: $ctrdef->{$ctr}->{desc};
|
||||
$desc .= ".";
|
||||
$set = $set_name_map->{$ctrdef->{$ctr}->{set}};
|
||||
if ($set) {
|
||||
$set = "Counter $ctr_num / $set.";
|
||||
} else {
|
||||
$set = "This event is not associated with a counter set.";
|
||||
}
|
||||
write;
|
||||
}
|
||||
}
|
||||
|
||||
sub do_show_ctr($;$)
|
||||
{
|
||||
my $c = shift();
|
||||
|
||||
# Check if counter facility is available
|
||||
unless (exists $c->{cpumf}->{cf}) {
|
||||
print STDERR "No CPU-measurement counter facility detected\n";
|
||||
return 2;
|
||||
}
|
||||
|
||||
# Retrieve counter authorization ("all" or authorized counters only)
|
||||
my $auth = @_ ? hex("0xFFFF") : $c->{cpumf}->{cf}->{auth};
|
||||
|
||||
# Retrieve counter information
|
||||
my $ctrs = invoke_cpumf_helper("-c $auth");
|
||||
unless ($ctrs) {
|
||||
print STDERR "No counters are available or authorized\n";
|
||||
return 3;
|
||||
}
|
||||
|
||||
# Retrieve hardware type
|
||||
my $hwtype = invoke_cpumf_helper("--hardware-type");
|
||||
my $model = length $hwtype->[1] ? "for $hwtype->[1]" : "";
|
||||
my $header = <<"EoHeader";
|
||||
Perf event counter list $model
|
||||
==============================================================================
|
||||
|
||||
Raw
|
||||
event Name Description
|
||||
------------------------------------------------------------------------------
|
||||
EoHeader
|
||||
print_counters($ctrs, $header);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
sub do_show_sf_events($)
|
||||
{
|
||||
my $c = shift();
|
||||
|
||||
# Check if sampling facility is available
|
||||
unless (exists $c->{cpumf}->{sf}) {
|
||||
print STDERR "No CPU-measurement sampling facility detected\n";
|
||||
return 2;
|
||||
}
|
||||
my $sf = $c->{cpumf}->{sf};
|
||||
my $events = invoke_cpumf_helper("--ctr-sf");
|
||||
|
||||
# Remove events with missing authorization
|
||||
delete $events->{0xB0000} unless exists $sf->{modes}->{basic};
|
||||
delete $events->{0xBD000} unless exists $sf->{modes}->{diagnostic};
|
||||
|
||||
unless ($events) {
|
||||
print STDERR "Sampling facility is not authorized\n";
|
||||
return 3;
|
||||
}
|
||||
|
||||
# Display sampling facility events (aka. counters)
|
||||
my $header = <<"EoHeader";
|
||||
Perf events for activating the sampling facility
|
||||
==============================================================================
|
||||
|
||||
Raw
|
||||
event Name Description
|
||||
------------------------------------------------------------------------------
|
||||
EoHeader
|
||||
print_counters($events, $header);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
sub invoke_cpumf_helper($)
|
||||
{
|
||||
my $parms = shift();
|
||||
my $result;
|
||||
|
||||
# Call helper module
|
||||
my $output = qx"$CPUMF_HELPER $parms";
|
||||
die "Failed to run helper module for '$parms'\n" if $? >> 8;
|
||||
$result = eval "$output";
|
||||
die "Failed to parse helper module data\n" if $@;
|
||||
|
||||
return $result;
|
||||
}
|
||||
|
||||
&main();
|
||||
__DATA__
|
||||
__END__
|
||||
214
cpumf/chcpumf.c
Normal file
214
cpumf/chcpumf.c
Normal file
@@ -0,0 +1,214 @@
|
||||
/*
|
||||
* chcpumf - Change CPU Measurement Facility Characteristics
|
||||
*
|
||||
* Copyright IBM Corp. 2020
|
||||
*
|
||||
* s390-tools is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the MIT license. See LICENSE for details.
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
#include <fcntl.h>
|
||||
#include <getopt.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/stat.h>
|
||||
|
||||
#include "lib/util_opt.h"
|
||||
#include "lib/util_prg.h"
|
||||
#include "lib/util_base.h"
|
||||
|
||||
#include "defines.h"
|
||||
|
||||
static int verbose;
|
||||
static unsigned long min_sdb, max_sdb;
|
||||
|
||||
static struct util_opt opt_vec[] = {
|
||||
UTIL_OPT_SECTION("OPTIONS"),
|
||||
{
|
||||
.option = { "min", required_argument, NULL, 'm' },
|
||||
.argument = "num_sdb",
|
||||
.desc = "Specifies the initial size of the sampling buffer.\n"
|
||||
"A sample-data-block (SDB) consumes about 4 kilobytes.",
|
||||
},
|
||||
{
|
||||
.option = { "max", required_argument, NULL, 'x' },
|
||||
.argument = "num_sdb",
|
||||
.desc = "Specifies the maximum size of the sampling buffer.\n"
|
||||
"A sample-data-block (SDB) consumes about 4 kilobytes.",
|
||||
},
|
||||
{
|
||||
.option = { "verbose", no_argument, NULL, 'V' },
|
||||
.desc = "Verbose, display new sample-data-block values.",
|
||||
},
|
||||
UTIL_OPT_HELP,
|
||||
UTIL_OPT_VERSION,
|
||||
UTIL_OPT_END
|
||||
};
|
||||
|
||||
static const struct util_prg prg = {
|
||||
.desc = "Change CPU Measurement facility charactertics",
|
||||
.copyright_vec = {
|
||||
{
|
||||
.owner = "IBM Corp.",
|
||||
.pub_first = 2020,
|
||||
.pub_last = 2020,
|
||||
},
|
||||
UTIL_PRG_COPYRIGHT_END
|
||||
}
|
||||
};
|
||||
|
||||
/* Parse tool parameters. Fill in global variables keep_case, buffersize and
|
||||
* command according to parameters. Return VMCP_OK on success, VMCP_OPT
|
||||
* in case of parameter errors. In case of --help or --version, print
|
||||
* respective text to stdout and exit. */
|
||||
static long parse_buffersize(char *string)
|
||||
{
|
||||
char *suffix;
|
||||
long bytes;
|
||||
|
||||
bytes = strtol(string, &suffix, 10);
|
||||
if (strlen(suffix) > 1)
|
||||
return -1;
|
||||
switch (*suffix) {
|
||||
case 'k':
|
||||
case 'K':
|
||||
bytes *= 1024;
|
||||
break;
|
||||
case 'm':
|
||||
case 'M':
|
||||
bytes *= 1048576;
|
||||
break;
|
||||
case '\0':
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
return bytes;
|
||||
}
|
||||
|
||||
static int read_sfb(unsigned long *min, unsigned long *max)
|
||||
{
|
||||
int rc = EXIT_SUCCESS;
|
||||
FILE *fp;
|
||||
|
||||
fp = fopen(PERF_SFB_SIZE, "r");
|
||||
if (fp == NULL) {
|
||||
linux_error(PERF_SFB_SIZE);
|
||||
return EXIT_FAILURE;
|
||||
}
|
||||
if (fscanf(fp, "%ld,%ld", min, max) != 2) {
|
||||
fprintf(stderr, "Error: Can not parse file " PERF_SFB_SIZE);
|
||||
rc = EXIT_FAILURE;
|
||||
}
|
||||
fclose(fp);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int write_sfb(unsigned long min, unsigned long max)
|
||||
{
|
||||
int rc = EXIT_SUCCESS;
|
||||
char text[64];
|
||||
size_t len;
|
||||
FILE *fp;
|
||||
|
||||
fp = fopen(PERF_SFB_SIZE, "w");
|
||||
if (fp == NULL) {
|
||||
linux_error(PERF_SFB_SIZE);
|
||||
return EXIT_FAILURE;
|
||||
}
|
||||
snprintf(text, sizeof text, "%ld,%ld", min, max);
|
||||
len = strlen(text) + 1;
|
||||
if (fwrite(text, 1, len, fp) != len) {
|
||||
linux_error(PERF_SFB_SIZE);
|
||||
rc = EXIT_FAILURE;
|
||||
}
|
||||
if (fclose(fp)) {
|
||||
linux_error(PERF_SFB_SIZE);
|
||||
rc = EXIT_FAILURE;
|
||||
}
|
||||
if (verbose)
|
||||
fprintf(stderr, "Sampling buffer sizes:\n"
|
||||
" Minimum:%7ld sample-data-blocks\n"
|
||||
" Maximum:%7ld sample-data-blocks\n",
|
||||
min, max);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int parse_args(int argc, char **argv)
|
||||
{
|
||||
int opt, action = 0;
|
||||
long new;
|
||||
|
||||
while ((opt = util_opt_getopt_long(argc, argv)) != -1) {
|
||||
switch (opt) {
|
||||
case 'h':
|
||||
util_prg_print_help();
|
||||
util_opt_print_help();
|
||||
exit(EXIT_SUCCESS);
|
||||
case 'v':
|
||||
util_prg_print_version();
|
||||
exit(EXIT_SUCCESS);
|
||||
case 'x':
|
||||
new = parse_buffersize(optarg);
|
||||
if (new < 1) {
|
||||
fprintf(stderr, "The specified number(s)"
|
||||
" are not valid\n");
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
max_sdb = new;
|
||||
action = 1;
|
||||
break;
|
||||
case 'm':
|
||||
new = parse_buffersize(optarg);
|
||||
if (new < 1) {
|
||||
fprintf(stderr, "The specified number(s)"
|
||||
" are not valid\n");
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
min_sdb = new;
|
||||
action = 1;
|
||||
break;
|
||||
case 'V':
|
||||
verbose = 1;
|
||||
break;
|
||||
case '?':
|
||||
fprintf(stderr, "One or more options are not valid\n");
|
||||
fprintf(stderr, "Try 'chcpumf --help' for more"
|
||||
" information\n");
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
}
|
||||
if (!action) {
|
||||
fprintf(stderr, "You must specify a valid option\n");
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
return action;
|
||||
}
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
int ret = EXIT_FAILURE;
|
||||
struct stat sbuf;
|
||||
|
||||
util_prg_init(&prg);
|
||||
util_opt_init(opt_vec, NULL);
|
||||
|
||||
if (stat(PERF_PATH PERF_SF, &sbuf) != 0) {
|
||||
fprintf(stderr,
|
||||
"No CPU-measurement sampling facility detected\n");
|
||||
return ret;
|
||||
}
|
||||
if (read_sfb(&min_sdb, &max_sdb))
|
||||
return ret;
|
||||
/* Overwrite min_sdb and/or max_sdb */
|
||||
parse_args(argc, argv);
|
||||
if (min_sdb >= max_sdb) {
|
||||
fprintf(stderr, "The specified maximum must be greater "
|
||||
"than the minimum\n");
|
||||
return ret;
|
||||
}
|
||||
return write_sfb(min_sdb, max_sdb);
|
||||
}
|
||||
@@ -1,60 +0,0 @@
|
||||
Counter: 0 Name:CPU_CYCLES
|
||||
Short-Description:CPU Cycles
|
||||
Description:
|
||||
Cycle Count
|
||||
.
|
||||
Counter: 1 Name:INSTRUCTIONS
|
||||
Short-Description:Instructions
|
||||
Description:
|
||||
Instruction Count
|
||||
.
|
||||
Counter: 2 Name:L1I_DIR_WRITES
|
||||
Short-Description:L1I Directory Writes
|
||||
Description:
|
||||
Level-1 I-Cache Directory Write Count
|
||||
.
|
||||
Counter: 3 Name:L1I_PENALTY_CYCLES
|
||||
Short-Description:L1I Penalty Cycles
|
||||
Description:
|
||||
Level-1 I-Cache Penalty Cycle Count
|
||||
.
|
||||
Counter: 4 Name:L1D_DIR_WRITES
|
||||
Short-Description:L1D Directory Writes
|
||||
Description:
|
||||
Level-1 D-Cache Directory Write Count
|
||||
.
|
||||
Counter: 5 Name:L1D_PENALTY_CYCLES
|
||||
Short-Description:L1D Penalty Cycles
|
||||
Description:
|
||||
Level-1 D-Cache Penalty Cycle Count
|
||||
.
|
||||
Counter: 32 Name:PROBLEM_STATE_CPU_CYCLES
|
||||
Short-Description:Problem-State CPU Cycles
|
||||
Description:
|
||||
Problem-State Cycle Count
|
||||
.
|
||||
Counter: 33 Name:PROBLEM_STATE_INSTRUCTIONS
|
||||
Short-Description:Problem-State Instructions
|
||||
Description:
|
||||
Problem-State Instruction Count
|
||||
.
|
||||
Counter: 34 Name:PROBLEM_STATE_L1I_DIR_WRITES
|
||||
Short-Description:Problem-State L1I Directory Writes
|
||||
Description:
|
||||
Problem-State Level-1 I-Cache Directory Write Count
|
||||
.
|
||||
Counter: 35 Name:PROBLEM_STATE_L1I_PENALTY_CYCLES
|
||||
Short-Description:Problem-State L1I Penalty Cycles
|
||||
Description:
|
||||
Problem-State Level-1 I-Cache Penalty Cycle Count
|
||||
.
|
||||
Counter: 36 Name:PROBLEM_STATE_L1D_DIR_WRITES
|
||||
Short-Description:Problem-State L1D Directory Writes
|
||||
Description:
|
||||
Problem-State Level-1 D-Cache Directory Write Count
|
||||
.
|
||||
Counter: 37 Name:PROBLEM_STATE_L1D_PENALTY_CYCLES
|
||||
Short-Description:Problem-State L1D Penalty Cycles
|
||||
Description:
|
||||
Problem-State Level-1 D-Cache Penalty Cycle Count
|
||||
.
|
||||
@@ -1,40 +0,0 @@
|
||||
Counter: 0 Name:CPU_CYCLES
|
||||
Short-Description:CPU Cycles
|
||||
Description:
|
||||
Cycle Count
|
||||
.
|
||||
Counter: 1 Name:INSTRUCTIONS
|
||||
Short-Description:Instructions
|
||||
Description:
|
||||
Instruction Count
|
||||
.
|
||||
Counter: 2 Name:L1I_DIR_WRITES
|
||||
Short-Description:L1I Directory Writes
|
||||
Description:
|
||||
Level-1 I-Cache Directory Write Count
|
||||
.
|
||||
Counter: 3 Name:L1I_PENALTY_CYCLES
|
||||
Short-Description:L1I Penalty Cycles
|
||||
Description:
|
||||
Level-1 I-Cache Penalty Cycle Count
|
||||
.
|
||||
Counter: 4 Name:L1D_DIR_WRITES
|
||||
Short-Description:L1D Directory Writes
|
||||
Description:
|
||||
Level-1 D-Cache Directory Write Count
|
||||
.
|
||||
Counter: 5 Name:L1D_PENALTY_CYCLES
|
||||
Short-Description:L1D Penalty Cycles
|
||||
Description:
|
||||
Level-1 D-Cache Penalty Cycle Count
|
||||
.
|
||||
Counter: 32 Name:PROBLEM_STATE_CPU_CYCLES
|
||||
Short-Description:Problem-State CPU Cycles
|
||||
Description:
|
||||
Problem-State Cycle Count
|
||||
.
|
||||
Counter: 33 Name:PROBLEM_STATE_INSTRUCTIONS
|
||||
Short-Description:Problem-State Instructions
|
||||
Description:
|
||||
Problem-State Instruction Count
|
||||
.
|
||||
@@ -1,100 +0,0 @@
|
||||
Counter: 64 Name:PRNG_FUNCTIONS
|
||||
Short-Description:PRNG Functions
|
||||
Description:
|
||||
Total number of the PRNG functions issued by the CPU
|
||||
.
|
||||
Counter: 65 Name:PRNG_CYCLES
|
||||
Short-Description:PRNG Cycles
|
||||
Description:
|
||||
Total number of CPU cycles when the DEA/AES coprocessor is busy
|
||||
performing PRNG functions issued by the CPU
|
||||
.
|
||||
Counter: 66 Name:PRNG_BLOCKED_FUNCTIONS
|
||||
Short-Description:PRNG Blocked Functions
|
||||
Description:
|
||||
Total number of the PRNG functions that are issued by the CPU and are
|
||||
blocked because the DEA/AES coprocessor is busy performing a function
|
||||
issued by another CPU
|
||||
.
|
||||
Counter: 67 Name:PRNG_BLOCKED_CYCLES
|
||||
Short-Description:PRNG Blocked Cycles
|
||||
Description:
|
||||
Total number of CPU cycles blocked for the PRNG functions issued by
|
||||
the CPU because the DEA/AES coprocessor is busy performing a function
|
||||
issued by another CPU
|
||||
.
|
||||
Counter: 68 Name:SHA_FUNCTIONS
|
||||
Short-Description:SHA Functions
|
||||
Description:
|
||||
Total number of SHA functions issued by the CPU
|
||||
.
|
||||
Counter: 69 Name:SHA_CYCLES
|
||||
Short-Description:SHA Cycles
|
||||
Description:
|
||||
Total number of CPU cycles when the SHA coprocessor is busy performing
|
||||
the SHA functions issued by the CPU
|
||||
.
|
||||
Counter: 70 Name:SHA_BLOCKED_FUNCTIONS
|
||||
Short-Description:SHA Blocked Functions
|
||||
Description:
|
||||
Total number of the SHA functions that are issued by the CPU and are
|
||||
blocked because the SHA coprocessor is busy performing a function issued
|
||||
by another CPU
|
||||
.
|
||||
Counter: 71 Name:SHA_BLOCKED_CYCLES
|
||||
Short-Description:SHA Bloced Cycles
|
||||
Description:
|
||||
Total number of CPU cycles blocked for the SHA functions issued by the
|
||||
CPU because the SHA coprocessor is busy performing a function issued
|
||||
by another CPU
|
||||
.
|
||||
Counter: 72 Name:DEA_FUNCTIONS
|
||||
Short-Description:DEA Functions
|
||||
Description:
|
||||
Total number of the DEA functions issued by the CPU
|
||||
.
|
||||
Counter: 73 Name:DEA_CYCLES
|
||||
Short-Description:DEA Cycles
|
||||
Description:
|
||||
Total number of CPU cycles when the DEA/AES coprocessor is busy
|
||||
performing the DEA functions issued by the CPU
|
||||
.
|
||||
Counter: 74 Name:DEA_BLOCKED_FUNCTIONS
|
||||
Short-Description:DEA Blocked Functions
|
||||
Description:
|
||||
Total number of the DEA functions that are issued by the CPU and are
|
||||
blocked because the DEA/AES coprocessor is busy performing a function
|
||||
issued by another CPU
|
||||
.
|
||||
Counter: 75 Name:DEA_BLOCKED_CYCLES
|
||||
Short-Description:DEA Blocked Cycles
|
||||
Description:
|
||||
Total number of CPU cycles blocked for the DEA functions issued by the
|
||||
CPU because the DEA/AES coprocessor is busy performing a function issued
|
||||
by another CPU
|
||||
.
|
||||
Counter: 76 Name:AES_FUNCTIONS
|
||||
Short-Description:AES Functions
|
||||
Description:
|
||||
Total number of AES functions issued by the CPU
|
||||
.
|
||||
Counter: 77 Name:AES_CYCLES
|
||||
Short-Description:AES Cycles
|
||||
Description:
|
||||
Total number of CPU cycles when the DEA/AES coprocessor is busy
|
||||
performing the AES functions issued by the CPU
|
||||
.
|
||||
Counter: 78 Name:AES_BLOCKED_FUNCTIONS
|
||||
Short-Description:AES Blocked Functions
|
||||
Description:
|
||||
Total number of AES functions that are issued by the CPU and are blocked
|
||||
because the DEA/AES coprocessor is busy performing a function issued
|
||||
by another CPU
|
||||
.
|
||||
Counter: 79 Name:AES_BLOCKED_CYCLES
|
||||
Short-Description:AES Blocked Cycles
|
||||
Description:
|
||||
Total number of CPU cycles blocked for the AES functions issued by the
|
||||
CPU because the DEA/AES coprocessor is busy performing a function issued
|
||||
by another CPU
|
||||
.
|
||||
@@ -1,33 +0,0 @@
|
||||
Counter: 80 Name:ECC_FUNCTION_COUNT
|
||||
Short-Description:ECC Function Count
|
||||
Description:
|
||||
This counter counts the
|
||||
total number of the elliptic-curve cryptography (ECC)
|
||||
functions issued by the CPU.
|
||||
.
|
||||
Counter: 81 Name:ECC_CYCLES_COUNT
|
||||
Short-Description:ECC Cycles Count
|
||||
Description:
|
||||
This counter counts the total
|
||||
number of CPU cycles when the ECC coprocessor is
|
||||
busy performing the elliptic-curve cryptography
|
||||
(ECC) functions issued by the CPU.
|
||||
.
|
||||
Counter: 82 Name:ECC_BLOCKED_FUNCTION_COUNT
|
||||
Short-Description:Ecc Blocked Function Count
|
||||
Description:
|
||||
This counter
|
||||
counts the total number of the elliptic-curve
|
||||
cryptography (ECC) functions that are issued by the CPU
|
||||
and are blocked because the ECC coprocessor is
|
||||
busy performing a function issued by another CPU.
|
||||
.
|
||||
Counter: 83 Name:ECC_BLOCKED_CYCLES_COUNT
|
||||
Short-Description:ECC Blocked Cycles Count
|
||||
Description:
|
||||
This counter counts
|
||||
the total number of CPU cycles blocked for the elliptic-curve
|
||||
cryptography (ECC) functions issued by the
|
||||
CPU because the ECC coprocessor is busy perform-
|
||||
ing a function issued by another CPU.
|
||||
.
|
||||
@@ -1,114 +0,0 @@
|
||||
Counter: 128 Name:L1I_L2_SOURCED_WRITES
|
||||
Short-Description:L1I L2 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 I-Cache directory where the returned
|
||||
cache line was sourced from the Level-2 (L1.5) cache
|
||||
.
|
||||
Counter: 129 Name:L1D_L2_SOURCED_WRITES
|
||||
Short-Description:L1D L2 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 D-Cache directory where the installed
|
||||
cache line was sourced from the Level-2 (L1.5) cache
|
||||
.
|
||||
Counter: 130 Name:L1I_L3_LOCAL_WRITES
|
||||
Short-Description:L1I L3 Local Writes
|
||||
Description:
|
||||
A directory write to the Level-1 I-Cache directory where the installed
|
||||
cache line was sourced from the Level-3 cache that is on the same book
|
||||
as the Instruction cache (Local L2 cache)
|
||||
.
|
||||
Counter: 131 Name:L1D_L3_LOCAL_WRITES
|
||||
Short-Description:L1D L3 Local Writes
|
||||
Description:
|
||||
A directory write to the Level-1 D-Cache directory where the installtion
|
||||
cache line was source from the Level-3 cache that is on the same book
|
||||
as the Data cache (Local L2 cache)
|
||||
.
|
||||
Counter: 132 Name:L1I_L3_REMOTE_WRITES
|
||||
Short-Description:L1I L3 Remote Writes
|
||||
Description:
|
||||
A directory write to the Level-1 I-Cache directory where the installed
|
||||
cache line was sourced from a Level-3 cache that is not on the same
|
||||
book as the Instruction cache (Remote L2 cache)
|
||||
.
|
||||
Counter: 133 Name:L1D_L3_REMOTE_WRITES
|
||||
Short-Description:L1D L3 Remote Writes
|
||||
Description:
|
||||
A directory write to the Level-1 D-Cache directory where the installed
|
||||
cache line was sourced from a Level-3 cache that is not on the same
|
||||
book as the Data cache (Remote L2 cache)
|
||||
.
|
||||
Counter: 134 Name:L1D_LMEM_SOURCED_WRITES
|
||||
Short-Description:L1D Local Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 D-Cache directory where the installed
|
||||
cache line was sourced from memory that is attached to the same book
|
||||
as the Data cache (Local Memory)
|
||||
.
|
||||
Counter: 135 Name:L1I_LMEM_SOURCED_WRITES
|
||||
Short-Description:L1I Local Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 I-Cache where the installed cache
|
||||
line was sourced from memory that is attached to the s ame book as the
|
||||
Instruction cache (Local Memory)
|
||||
.
|
||||
Counter: 136 Name:L1D_RO_EXCL_WRITES
|
||||
Short-Description:L1D Read-only Exclusive Writes
|
||||
Description:
|
||||
A directory write to the Level-1 D-Cache where the line was originally
|
||||
in a Read-Only state in the cache but has been updated to be in the
|
||||
Exclusive state that allows stores to the cache line
|
||||
.
|
||||
Counter: 137 Name:L1I_CACHELINE_INVALIDATES
|
||||
Short-Description:L1I Cacheline Invalidates
|
||||
Description:
|
||||
A cache line in the Level-1 I-Cache has been invalidated by a store on
|
||||
the same CPU as the Level-1 I-Cache
|
||||
.
|
||||
Counter: 138 Name:ITLB1_WRITES
|
||||
Short-Description:ITLB1 Writes
|
||||
Description:
|
||||
A translation entry has been written into the Level-1 Instruction
|
||||
Translation Lookaside Buffer
|
||||
.
|
||||
Counter: 139 Name:DTLB1_WRITES
|
||||
Short-Description:DTLB1 Writes
|
||||
Description:
|
||||
A translation entry has been written to the Level-1 Data Translation
|
||||
Lookaside Buffer
|
||||
.
|
||||
Counter: 140 Name:TLB2_PTE_WRITES
|
||||
Short-Description:TLB2 PTE Writes
|
||||
Description:
|
||||
A translation entry has been written to the Level-2 TLB Page Table
|
||||
Entry arrays
|
||||
.
|
||||
Counter: 141 Name:TLB2_CRSTE_WRITES
|
||||
Short-Description:TLB2 CRSTE Writes
|
||||
Description:
|
||||
A translation entry has been written to the Level-2 TLB Common Region
|
||||
Segment Table Entry arrays
|
||||
.
|
||||
Counter: 142 Name:TLB2_CRSTE_HPAGE_WRITES
|
||||
Short-Description:TLB2 CRSTE One-Megabyte Page Writes
|
||||
Description:
|
||||
A translation entry has been written to the Level-2 TLB Common Region
|
||||
Segment Table Entry arrays for a one-megabyte large page translation
|
||||
.
|
||||
Counter: 145 Name:ITLB1_MISSES
|
||||
Short-Description:ITLB1 Misses
|
||||
Description:
|
||||
Level-1 Instruction TLB miss in progress. Incremented by one for every
|
||||
cycle an ITLB1 miss is in progress
|
||||
.
|
||||
Counter: 146 Name:DTLB1_MISSES
|
||||
Short-Description:DTLB1 Misses
|
||||
Description:
|
||||
Level-1 Data TLB miss in progress. Incremented by one for every cycle
|
||||
an DTLB1 miss is in progress
|
||||
.
|
||||
Counter: 147 Name:L2C_STORES_SENT
|
||||
Short-Description:L2C Stores Sent
|
||||
Description:
|
||||
Incremented by one for every store sent to Level-2 (L1.5) cache
|
||||
.
|
||||
@@ -1,373 +0,0 @@
|
||||
# Counter decriptions for the
|
||||
# IBM z13 extended counter and MT-diagnostic counter set
|
||||
#
|
||||
# Notes for transactional-execution mode symbolic names:
|
||||
# TX .. transactional-execution mode
|
||||
# NC .. nonconstrained
|
||||
# C .. constrained
|
||||
#
|
||||
# Undefined counters in the extended counter set:
|
||||
# 142
|
||||
# 180-217
|
||||
# 221-225
|
||||
# Undefined counters in the MT-diagnostic counter set:
|
||||
# 450-495
|
||||
#
|
||||
#
|
||||
# Extended Counter Set
|
||||
# ---------------------------------------------------------------------
|
||||
Counter:128 Name:L1D_RO_EXCL_WRITES
|
||||
Short-Description:L1D Read-only Exclusive Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache where the line was
|
||||
originally in a Read-Only state in the cache but has been updated
|
||||
to be in the Exclusive state that allows stores to the cache line.
|
||||
.
|
||||
Counter:129 Name:DTLB1_WRITES
|
||||
Short-Description:DTLB1 Writes
|
||||
Description:
|
||||
A translation entry has been written to the Level-1 Data Translation
|
||||
Lookaside Buffer
|
||||
.
|
||||
Counter:130 Name:DTLB1_MISSES
|
||||
Short-Description:DTLB1 Misses
|
||||
Description:
|
||||
Level-1 Data TLB miss in progress. Incremented by one for every cycle
|
||||
a DTLB1 miss is in progress.
|
||||
.
|
||||
Counter:131 Name:DTLB1_HPAGE_WRITES
|
||||
Short-Description:DTLB1 One-Megabyte Page Writes
|
||||
Description:
|
||||
A translation entry has been written to the Level-1 Data Translation
|
||||
Lookaside Buffer for a one-megabyte page
|
||||
.
|
||||
Counter:132 Name:DTLB1_GPAGE_WRITES
|
||||
Short-Description:DTLB1 Two-Gigabyte Page Writes
|
||||
A translation entry has been written to the Level-1 Data Translation
|
||||
Lookaside Buffer for a two-gigabyte page.
|
||||
.
|
||||
Counter:133 Name:L1D_L2D_SOURCED_WRITES
|
||||
Short-Description:L1D L2D Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from the Level-2 Data cache
|
||||
.
|
||||
Counter:134 Name:ITLB1_WRITES
|
||||
Short-Description:ITLB1 Writes
|
||||
Description:
|
||||
A translation entry has been written to the Level-1 Instruction
|
||||
Translation Lookaside Buffer
|
||||
.
|
||||
Counter:135 Name:ITLB1_MISSES
|
||||
Short-Description:ITLB1 Misses
|
||||
Description:
|
||||
Level-1 Instruction TLB miss in progress. Incremented by one for every
|
||||
cycle an ITLB1 miss is in progress
|
||||
.
|
||||
Counter:136 Name:L1I_L2I_SOURCED_WRITES
|
||||
Short-Description:L1I L2I Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from the Level-2 Instruction cache
|
||||
.
|
||||
Counter:137 Name:TLB2_PTE_WRITES
|
||||
Short-Description:TLB2 PTE Writes
|
||||
Description:
|
||||
A translation entry has been written to the Level-2 TLB Page Table
|
||||
Entry arrays
|
||||
.
|
||||
Counter:138 Name:TLB2_CRSTE_HPAGE_WRITES
|
||||
Short-Description:TLB2 CRSTE One-Megabyte Page Writes
|
||||
Description:
|
||||
A translation entry has been written to the Level-2 TLB Combined Region
|
||||
Segment Table Entry arrays for a one-megabyte large page translation
|
||||
.
|
||||
Counter:139 Name:TLB2_CRSTE_WRITES
|
||||
Short-Description:TLB2 CRSTE Writes
|
||||
Description:
|
||||
A translation entry has been written to the Level-2 TLB Combined Region
|
||||
Segment Table Entry arrays
|
||||
.
|
||||
Counter:140 Name:TX_C_TEND
|
||||
Short-Description:Completed TEND instructions in constrained TX mode
|
||||
Description:
|
||||
A TEND instruction has completed in a constrained transactional-execution
|
||||
mode
|
||||
.
|
||||
Counter:141 Name:TX_NC_TEND
|
||||
Short-Description:Completed TEND instructions in non-constrained TX mode
|
||||
Description:
|
||||
A TEND instruction has completed in a non-constrained
|
||||
transactional-execution mode
|
||||
.
|
||||
Counter:143 Name:L1C_TLB1_MISSES
|
||||
Short-Description:L1C TLB1 Misses
|
||||
Description:
|
||||
Increments by one for any cycle where a Level-1 cache or Level-1 TLB miss
|
||||
is in progress.
|
||||
.
|
||||
Counter:144 Name:L1D_ONCHIP_L3_SOURCED_WRITES
|
||||
Short-Description:L1D On-Chip L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an On-Chip Level-3 cache without intervention
|
||||
.
|
||||
Counter:145 Name:L1D_ONCHIP_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1D On-Chip L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an On-Chip Level-3 cache with intervention
|
||||
.
|
||||
Counter:146 Name:L1D_ONNODE_L4_SOURCED_WRITES
|
||||
Short-Description:L1D On-Node L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an On-Node Level-4 cache
|
||||
.
|
||||
Counter:147 Name:L1D_ONNODE_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1D On-Node L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an On-Node Level-3 cache with intervention
|
||||
.
|
||||
Counter:148 Name:L1D_ONNODE_L3_SOURCED_WRITES
|
||||
Short-Description:L1D On-Node L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an On-Node Level-3 cache without intervention
|
||||
.
|
||||
Counter:149 Name:L1D_ONDRAWER_L4_SOURCED_WRITES
|
||||
Short-Description:L1D On-Drawer L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an On-Drawer Level-4 cache
|
||||
.
|
||||
Counter:150 Name:L1D_ONDRAWER_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1D On-Drawer L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an On-Drawer Level-3 cache with intervention
|
||||
.
|
||||
Counter:151 Name:L1D_ONDRAWER_L3_SOURCED_WRITES
|
||||
Short-Description:L1D On-Drawer L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an On-Drawer Level-3 cache without intervention
|
||||
.
|
||||
Counter:152 Name:L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES
|
||||
Short-Description:L1D Off-Drawer Same-Column L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an Off-Drawer Same-Column Level-4 cache
|
||||
.
|
||||
Counter:153 Name:L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1D Off-Drawer Same-Column L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an Off-Drawer Same-Column Level-3 cache with
|
||||
intervention
|
||||
.
|
||||
Counter:154 Name:L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES
|
||||
Short-Description:L1D Off-Drawer Same-Column L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an Off-Drawer Same-Column Level-3 cache
|
||||
without intervention
|
||||
.
|
||||
Counter:155 Name:L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES
|
||||
Short-Description:L1D Off-Drawer Far-Column L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an Off-Drawer Far-Column Level-4 cache
|
||||
.
|
||||
Counter:156 Name:L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1D Off-Drawer Far-Column L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an Off-Drawer Far-Column Level-3 cache with
|
||||
intervention
|
||||
.
|
||||
Counter:157 Name:L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES
|
||||
Short-Description:L1D Off-Drawer Far-Column L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an Off-Drawer Far-Column Level-3 cache
|
||||
without intervention
|
||||
.
|
||||
Counter:158 Name:L1D_ONNODE_MEM_SOURCED_WRITES
|
||||
Short-Description:L1D On-Node Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from On-Node memory
|
||||
.
|
||||
Counter:159 Name:L1D_ONDRAWER_MEM_SOURCED_WRITES
|
||||
Short-Description:L1D On-Drawer Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from On-Drawer memory
|
||||
.
|
||||
Counter:160 Name:L1D_OFFDRAWER_MEM_SOURCED_WRITES
|
||||
Short-Description:L1D Off-Drawer Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from On-Drawer memory
|
||||
.
|
||||
Counter:161 Name:L1D_ONCHIP_MEM_SOURCED_WRITES
|
||||
Short-Description:L1D On-Chip Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from On-Chip memory
|
||||
.
|
||||
Counter:162 Name:L1I_ONCHIP_L3_SOURCED_WRITES
|
||||
Short-Description:L1I On-Chip L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an On-Chip Level-3 cache without
|
||||
intervention
|
||||
.
|
||||
Counter:163 Name:L1I_ONCHIP_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1I On-Chip L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an On Chip Level-3 cache with
|
||||
intervention
|
||||
.
|
||||
Counter:164 Name:L1I_ONNODE_L4_SOURCED_WRITES
|
||||
Short-Description:L1I On-Chip L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an On-Node Level-4 cache
|
||||
.
|
||||
Counter:165 Name:L1I_ONNODE_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1I On-Node L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where
|
||||
the returned cache line was sourced from an On-Node Level-3 cache
|
||||
with intervention
|
||||
.
|
||||
Counter:166 Name:L1I_ONNODE_L3_SOURCED_WRITES
|
||||
Short-Description:L1I On-Node L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where
|
||||
the returned cache line was sourced from an On-Node Level-3 cache
|
||||
without intervention
|
||||
.
|
||||
Counter:167 Name:L1I_ONDRAWER_L4_SOURCED_WRITES
|
||||
Short-Description:L1I On-Drawer L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where
|
||||
the returned cache line was sourced from an On-Drawer Level-4 cache
|
||||
.
|
||||
Counter:168 Name:L1I_ONDRAWER_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1I On-Drawer L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where
|
||||
the returned cache line was sourced from an On-Drawer Level-3 cache
|
||||
with intervention
|
||||
.
|
||||
Counter:169 Name:L1I_ONDRAWER_L3_SOURCED_WRITES
|
||||
Short-Description:L1I On-Drawer L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where
|
||||
the returned cache line was sourced from an On-Drawer Level-3 cache
|
||||
without intervention
|
||||
.
|
||||
Counter:170 Name:L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES
|
||||
Short-Description:L1I Off-Drawer Same-Column L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where
|
||||
the returned cache line was sourced from an Off-Drawer Same-Column
|
||||
Level-4 cache
|
||||
.
|
||||
Counter:171 Name:L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1I Off-Drawer Same-Column L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where
|
||||
the returned cache line was sourced from an Off-Drawer Same-Column
|
||||
Level-3 cache with intervention
|
||||
.
|
||||
Counter:172 Name:L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES
|
||||
Short-Description:L1I Off-Drawer Same-Column L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where
|
||||
the returned cache line was sourced from an Off-Drawer Same-Column
|
||||
Level-3 cache without intervention
|
||||
.
|
||||
Counter:173 Name:L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES
|
||||
Short-Description:L1I Off-Drawer Far-Column L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where
|
||||
the returned cache line was sourced from an Off-Drawer Far-Column
|
||||
Level-4 cache
|
||||
.
|
||||
Counter:174 Name:L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1I Off-Drawer Far-Column L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where
|
||||
the returned cache line was sourced from an Off-Drawer Far-Column
|
||||
Level-3 cache with intervention
|
||||
.
|
||||
Counter:175 Name:L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES
|
||||
Short-Description:L1I Off-Drawer Far-Column L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where
|
||||
the returned cache line was sourced from an Off-Drawer Far-Column
|
||||
Level-3 cache without intervention
|
||||
.
|
||||
Counter:176 Name:L1I_ONNODE_MEM_SOURCED_WRITES
|
||||
Short-Description:L1I On-Node Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where
|
||||
the returned cache line was sourced from On-Node memory
|
||||
.
|
||||
Counter:177 Name:L1I_ONDRAWER_MEM_SOURCED_WRITES
|
||||
Short-Description:L1I On-Drawer Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where
|
||||
the returned cache line was sourced from On-Drawer memory
|
||||
.
|
||||
Counter:178 Name:L1I_OFFDRAWER_MEM_SOURCED_WRITES
|
||||
Short-Description:L1I Off-Drawer Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where
|
||||
the returned cache line was sourced from On-Drawer memory
|
||||
.
|
||||
Counter:179 Name:L1I_ONCHIP_MEM_SOURCED_WRITES
|
||||
Short-Description:L1I On-Chip Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where
|
||||
the returned cache line was sourced from On-Chip memory
|
||||
.
|
||||
Counter:218 Name:TX_NC_TABORT
|
||||
Short-Description:Aborted transactions in non-constrained TX mode
|
||||
Description:
|
||||
A transaction abort has occurred in a non-constrained
|
||||
transactional-execution mode
|
||||
.
|
||||
Counter:219 Name:TX_C_TABORT_NO_SPECIAL
|
||||
Short-Description:Aborted transactions in constrained TX mode not using special completion logic
|
||||
Description:
|
||||
A transaction abort has occurred in a constrained transactional-execution
|
||||
mode and the CPU is not using any special logic to allow the transaction
|
||||
to complete
|
||||
.
|
||||
Counter:220 Name:TX_C_TABORT_SPECIAL
|
||||
Short-Description:Aborted transactions in constrained TX mode using special completion logic
|
||||
Description:
|
||||
A transaction abort has occurred in a constrained transactional-execution
|
||||
mode and the CPU is using special logic to allow the transaction to
|
||||
complete
|
||||
.
|
||||
#
|
||||
# MT-diagnostic counter set
|
||||
# ---------------------------------------------------------------------
|
||||
Counter:448 Name:MT_DIAG_CYCLES_ONE_THR_ACTIVE
|
||||
Short-Description:Cycle count with one thread active
|
||||
Description:
|
||||
Cycle count with one thread active
|
||||
.
|
||||
Counter:449 Name:MT_DIAG_CYCLES_TWO_THR_ACTIVE
|
||||
Short-Description:Cycle count with two threads active
|
||||
Description:
|
||||
Cycle count with two threads active
|
||||
.
|
||||
@@ -1,357 +0,0 @@
|
||||
# Counter decriptions for the
|
||||
# IBM z14 extended counter and MT-diagnostic counter set
|
||||
#
|
||||
# Notes for transactional-execution mode symbolic names:
|
||||
# TX .. transactional-execution mode
|
||||
# NC .. nonconstrained
|
||||
# C .. constrained
|
||||
#
|
||||
# Undefined counters in the extended counter set:
|
||||
# 142
|
||||
# 158-161
|
||||
# 176-223
|
||||
# 227-231
|
||||
# 233-242
|
||||
# 246-255
|
||||
# Undefined counters in the MT-diagnostic counter set:
|
||||
# 450-495
|
||||
#
|
||||
#
|
||||
# Extended Counter Set
|
||||
# ---------------------------------------------------------------------
|
||||
Counter:128 Name:L1D_RO_EXCL_WRITES
|
||||
Short-Description:L1D Read-only Exclusive Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache where the line was
|
||||
originally in a Read-Only state in the cache but has been updated
|
||||
to be in the Exclusive state that allows stores to the cache line
|
||||
.
|
||||
Counter:129 Name:DTLB2_WRITES
|
||||
Short-Description:DTLB2 Writes
|
||||
Description:
|
||||
A translation has been written into The Translation Lookaside
|
||||
Buffer 2 (TLB2) and the request was made by the data cache
|
||||
.
|
||||
Counter:130 Name:DTLB2_MISSES
|
||||
Short-Description:DTLB2 Misses
|
||||
Description:
|
||||
A TLB2 miss is in progress for a request made by the data cache.
|
||||
Incremented by one for every TLB2 miss in progress for the Level-1
|
||||
Data cache on this cycle
|
||||
.
|
||||
Counter:131 Name:DTLB2_HPAGE_WRITES
|
||||
Short-Description:DTLB2 One-Megabyte Page Writes
|
||||
Description:
|
||||
A translation entry was written into the Combined Region and Segment
|
||||
Table Entry array in the Level-2 TLB for a one-megabyte page or a
|
||||
Last Host Translation was done
|
||||
.
|
||||
Counter:132 Name:DTLB2_GPAGE_WRITES
|
||||
Short-Description:DTLB2 Two-Gigabyte Page Writes
|
||||
Description:
|
||||
A translation entry for a two-gigabyte page was written into the
|
||||
Level-2 TLB
|
||||
.
|
||||
Counter:133 Name:L1D_L2D_SOURCED_WRITES
|
||||
Short-Description:L1D L2D Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the
|
||||
returned cache line was sourced from the Level-2 Data cache
|
||||
.
|
||||
Counter:134 Name:ITLB2_WRITES
|
||||
Short-Description:ITLB2 Writes
|
||||
Description:
|
||||
A translation entry has been written into the Translation Lookaside
|
||||
Buffer 2 (TLB2) and the request was made by the instruction cache
|
||||
.
|
||||
Counter:135 Name:ITLB2_MISSES
|
||||
Short-Description:ITLB2 Misses
|
||||
Description:
|
||||
A TLB2 miss is in progress for a request made by the instruction cache.
|
||||
Incremented by one for every TLB2 miss in progress for the Level-1
|
||||
Instruction cache in a cycle
|
||||
.
|
||||
Counter:136 Name:L1I_L2I_SOURCED_WRITES
|
||||
Short-Description:L1I L2I Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from the Level-2 Instruction cache
|
||||
.
|
||||
Counter:137 Name:TLB2_PTE_WRITES
|
||||
Short-Description:TLB2 PTE Writes
|
||||
Description:
|
||||
A translation entry was written into the Page Table Entry array in the
|
||||
Level-2 TLB
|
||||
.
|
||||
Counter:138 Name:TLB2_CRSTE_WRITES
|
||||
Short-Description:TLB2 CRSTE Writes
|
||||
Description:
|
||||
Translation entries were written into the Combined Region and Segment
|
||||
Table Entry array and the Page Table Entry array in the Level-2 TLB
|
||||
.
|
||||
Counter:139 Name:TLB2_ENGINES_BUSY
|
||||
Short-Description:TLB2 Engines Busy
|
||||
Description:
|
||||
The number of Level-2 TLB translation engines busy in a cycle
|
||||
.
|
||||
Counter:140 Name:TX_C_TEND
|
||||
Short-Description:Completed TEND instructions in constrained TX mode
|
||||
Description:
|
||||
A TEND instruction has completed in a constrained transactional-execution
|
||||
mode
|
||||
.
|
||||
Counter:141 Name:TX_NC_TEND
|
||||
Short-Description:Completed TEND instructions in non-constrained TX mode
|
||||
Description:
|
||||
A TEND instruction has completed in a non-constrained
|
||||
transactional-execution mode
|
||||
.
|
||||
Counter:143 Name:L1C_TLB2_MISSES
|
||||
Short-Description:L1C TLB2 Misses
|
||||
Description:
|
||||
Increments by one for any cycle where a level-1 cache or level-2 TLB miss
|
||||
is in progress
|
||||
.
|
||||
Counter:144 Name:L1D_ONCHIP_L3_SOURCED_WRITES
|
||||
Short-Description:L1D On-Chip L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an On-Chip Level-3 cache without intervention
|
||||
.
|
||||
Counter:145 Name:L1D_ONCHIP_MEMORY_SOURCED_WRITES
|
||||
Short-Description:L1D On-Chip Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from On-Chip memory
|
||||
.
|
||||
Counter:146 Name:L1D_ONCHIP_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1D On-Chip L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an On-Chip Level-3 cache with intervention
|
||||
.
|
||||
Counter:147 Name:L1D_ONCLUSTER_L3_SOURCED_WRITES
|
||||
Short-Description:L1D On-Cluster L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from On-Cluster Level-3 cache withountervention
|
||||
.
|
||||
Counter:148 Name:L1D_ONCLUSTER_MEMORY_SOURCED_WRITES
|
||||
Short-Description:L1D On-Cluster Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an On-Cluster memory
|
||||
.
|
||||
Counter:149 Name:L1D_ONCLUSTER_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1D On-Cluster L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an On-Cluster Level-3 cache with intervention
|
||||
.
|
||||
Counter:150 Name:L1D_OFFCLUSTER_L3_SOURCED_WRITES
|
||||
Short-Description:L1D Off-Cluster L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an Off-Cluster Level-3 cache without
|
||||
intervention
|
||||
.
|
||||
Counter:151 Name:L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES
|
||||
Short-Description:L1D Off-Cluster Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from Off-Cluster memory
|
||||
.
|
||||
Counter:152 Name:L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1D Off-Cluster L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an Off-Cluster Level-3 cache with intervention
|
||||
.
|
||||
Counter:153 Name:L1D_OFFDRAWER_L3_SOURCED_WRITES
|
||||
Short-Description:L1D Off-Drawer L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an Off-Drawer Level-3 cache without
|
||||
intervention
|
||||
.
|
||||
Counter:154 Name:L1D_OFFDRAWER_MEMORY_SOURCED_WRITES
|
||||
Short-Description:L1D Off-Drawer Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from Off-Drawer memory
|
||||
.
|
||||
Counter:155 Name:L1D_OFFDRAWER_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1D Off-Drawer L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an Off-Drawer Level-3 cache with intervention
|
||||
.
|
||||
Counter:156 Name:L1D_ONDRAWER_L4_SOURCED_WRITES
|
||||
Short-Description:L1D On-Drawer L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from On-Drawer Level-4 cache
|
||||
.
|
||||
Counter:157 Name:L1D_OFFDRAWER_L4_SOURCED_WRITES
|
||||
Short-Description:L1D Off-Drawer L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from Off-Drawer Level-4 cache
|
||||
.
|
||||
Counter:158 Name:L1D_ONCHIP_L3_SOURCED_WRITES_RO
|
||||
Short-Description:L1D On-Chip L3 Sourced Writes read-only
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from On-Chip L3 but a read-only invalidate was
|
||||
done to remove other copies of the cache line
|
||||
.
|
||||
Counter:162 Name:L1I_ONCHIP_L3_SOURCED_WRITES
|
||||
Short-Description:L1I On-Chip L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache ine was sourced from an On-Chip Level-3 cache without
|
||||
intervention
|
||||
.
|
||||
Counter:163 Name:L1I_ONCHIP_MEMORY_SOURCED_WRITES
|
||||
Short-Description:L1I On-Chip Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache ine was sourced from On-Chip memory
|
||||
.
|
||||
Counter:164 Name:L1I_ONCHIP_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1I On-Chip L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache ine was sourced from an On-Chip Level-3 cache with
|
||||
intervention
|
||||
.
|
||||
Counter:165 Name:L1I_ONCLUSTER_L3_SOURCED_WRITES
|
||||
Short-Description:L1I On-Cluster L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an On-Cluster Level-3 cache without
|
||||
intervention
|
||||
.
|
||||
Counter:166 Name:L1I_ONCLUSTER_MEMORY_SOURCED_WRITES
|
||||
Short-Description:L1I On-Cluster Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an On-Cluster memory
|
||||
.
|
||||
Counter:167 Name:L1I_ONCLUSTER_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1I On-Cluster L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from On-Cluster Level-3 cache with
|
||||
intervention
|
||||
.
|
||||
Counter:168 Name:L1I_OFFCLUSTER_L3_SOURCED_WRITES
|
||||
Short-Description:L1I Off-Cluster L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an Off-Cluster Level-3 cache without
|
||||
intervention
|
||||
.
|
||||
Counter:169 Name:L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES
|
||||
Short-Description:L1I Off-Cluster Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from Off-Cluster memory
|
||||
.
|
||||
Counter:170 Name:L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1I Off-Cluster L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an Off-Cluster Level-3 cache with
|
||||
intervention
|
||||
.
|
||||
Counter:171 Name:L1I_OFFDRAWER_L3_SOURCED_WRITES
|
||||
Short-Description:L1I Off-Drawer L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an Off-Drawer Level-3 cache without
|
||||
intervention
|
||||
.
|
||||
Counter:172 Name:L1I_OFFDRAWER_MEMORY_SOURCED_WRITES
|
||||
Short-Description:L1I Off-Drawer Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from Off-Drawer memory
|
||||
.
|
||||
Counter:173 Name:L1I_OFFDRAWER_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1I Off-Drawer L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an Off-Drawer Level-3 cache with
|
||||
intervention
|
||||
.
|
||||
Counter:174 Name:L1I_ONDRAWER_L4_SOURCED_WRITES
|
||||
Short-Description:L1I On-Drawer L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from On-Drawer Level-4 cache
|
||||
.
|
||||
Counter:175 Name:L1I_OFFDRAWER_L4_SOURCED_WRITES
|
||||
Short-Description:L1I Off-Drawer L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from Off-Drawer Level-4 cache
|
||||
.
|
||||
Counter:224 Name:BCD_DFP_EXECUTION_SLOTS
|
||||
Short-Description:BCD DFP Execution Slots
|
||||
Description:
|
||||
Count of floating point execution slots used for finished Binary Coded
|
||||
Decimal to Decimal Floating Point conversions. Instructions: CDZT,
|
||||
CXZT, CZDT, CZXT
|
||||
.
|
||||
Counter:225 Name:VX_BCD_EXECUTION_SLOTS
|
||||
Short-Description:VX BCD Execution Slots
|
||||
Description:
|
||||
Count of floating point execution slots used for finished vector arithmetic
|
||||
Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP,
|
||||
VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG
|
||||
.
|
||||
Counter:226 Name:DECIMAL_INSTRUCTIONS
|
||||
Short-Description:Decimal Instructions
|
||||
Description:
|
||||
Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED,
|
||||
EDMK, MP, SRP, SP, ZAP
|
||||
.
|
||||
Counter:232 Name:LAST_HOST_TRANSLATIONS
|
||||
Short-Description:Last host translation done
|
||||
Description:
|
||||
Last Host Translation done
|
||||
.
|
||||
Counter:243 Name:TX_NC_TABORT
|
||||
Short-Description:Aborted transactions in non-constrained TX mode
|
||||
Description:
|
||||
A transaction abort has occurred in a non-constrained
|
||||
transactional-execution mode
|
||||
.
|
||||
Counter:244 Name:TX_C_TABORT_NO_SPECIAL
|
||||
Short-Description:Aborted transactions in constrained TX mode not using special completion logic
|
||||
Description:
|
||||
A transaction abort has occurred in a constrained transactional-execution
|
||||
mode and the CPU is not using any special logic to allow the transaction
|
||||
to complete
|
||||
.
|
||||
Counter:245 Name:TX_C_TABORT_SPECIAL
|
||||
Short-Description:Aborted transactions in constrained TX mode using special completion logic
|
||||
Description:
|
||||
A transaction abort has occurred in a constrained transactional-execution
|
||||
mode and the CPU is using special logic to allow the transaction to
|
||||
complete
|
||||
.
|
||||
#
|
||||
# MT-diagnostic counter set
|
||||
# ---------------------------------------------------------------------
|
||||
Counter:448 Name:MT_DIAG_CYCLES_ONE_THR_ACTIVE
|
||||
Short-Description:Cycle count with one thread active
|
||||
Description:
|
||||
Cycle count with one thread active
|
||||
.
|
||||
Counter:449 Name:MT_DIAG_CYCLES_TWO_THR_ACTIVE
|
||||
Short-Description:Cycle count with two threads active
|
||||
Description:
|
||||
Cycle count with two threads active
|
||||
.
|
||||
@@ -1,376 +0,0 @@
|
||||
# Counter decriptions for the
|
||||
# IBM z14 extended counter and MT-diagnostic counter set
|
||||
#
|
||||
# Notes for transactional-execution mode symbolic names:
|
||||
# TX .. transactional-execution mode
|
||||
# NC .. nonconstrained
|
||||
# C .. constrained
|
||||
#
|
||||
# Undefined counters in the extended counter set:
|
||||
# 142
|
||||
# 158-161
|
||||
# 176-223
|
||||
# 227-231
|
||||
# 233-242
|
||||
# 246-255
|
||||
# Undefined counters in the MT-diagnostic counter set:
|
||||
# 450-495
|
||||
#
|
||||
#
|
||||
# Extended Counter Set
|
||||
# ---------------------------------------------------------------------
|
||||
Counter:128 Name:L1D_RO_EXCL_WRITES
|
||||
Short-Description:L1D Read-only Exclusive Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache where the line was
|
||||
originally in a Read-Only state in the cache but has been updated
|
||||
to be in the Exclusive state that allows stores to the cache line
|
||||
.
|
||||
Counter:129 Name:DTLB2_WRITES
|
||||
Short-Description:DTLB2 Writes
|
||||
Description:
|
||||
A translation has been written into The Translation Lookaside
|
||||
Buffer 2 (TLB2) and the request was made by the data cache
|
||||
.
|
||||
Counter:130 Name:DTLB2_MISSES
|
||||
Short-Description:DTLB2 Misses
|
||||
Description:
|
||||
A TLB2 miss is in progress for a request made by the data cache.
|
||||
Incremented by one for every TLB2 miss in progress for the Level-1
|
||||
Data cache on this cycle
|
||||
.
|
||||
Counter:131 Name:DTLB2_HPAGE_WRITES
|
||||
Short-Description:DTLB2 One-Megabyte Page Writes
|
||||
Description:
|
||||
A translation entry was written into the Combined Region and Segment
|
||||
Table Entry array in the Level-2 TLB for a one-megabyte page
|
||||
.
|
||||
Counter:132 Name:DTLB2_GPAGE_WRITES
|
||||
Short-Description:DTLB2 Two-Gigabyte Page Writes
|
||||
Description:
|
||||
A translation entry for a two-gigabyte page was written into the
|
||||
Level-2 TLB
|
||||
.
|
||||
Counter:133 Name:L1D_L2D_SOURCED_WRITES
|
||||
Short-Description:L1D L2D Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the
|
||||
returned cache line was sourced from the Level-2 Data cache
|
||||
.
|
||||
Counter:134 Name:ITLB2_WRITES
|
||||
Short-Description:ITLB2 Writes
|
||||
Description:
|
||||
A translation entry has been written into the Translation Lookaside
|
||||
Buffer 2 (TLB2) and the request was made by the instruction cache
|
||||
.
|
||||
Counter:135 Name:ITLB2_MISSES
|
||||
Short-Description:ITLB2 Misses
|
||||
Description:
|
||||
A TLB2 miss is in progress for a request made by the instruction cache.
|
||||
Incremented by one for every TLB2 miss in progress for the Level-1
|
||||
Instruction cache in a cycle
|
||||
.
|
||||
Counter:136 Name:L1I_L2I_SOURCED_WRITES
|
||||
Short-Description:L1I L2I Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from the Level-2 Instruction cache
|
||||
.
|
||||
Counter:137 Name:TLB2_PTE_WRITES
|
||||
Short-Description:TLB2 PTE Writes
|
||||
Description:
|
||||
A translation entry was written into the Page Table Entry array in the
|
||||
Level-2 TLB
|
||||
.
|
||||
Counter:138 Name:TLB2_CRSTE_WRITES
|
||||
Short-Description:TLB2 CRSTE Writes
|
||||
Description:
|
||||
Translation entries were written into the Combined Region and Segment
|
||||
Table Entry array and the Page Table Entry array in the Level-2 TLB
|
||||
.
|
||||
Counter:139 Name:TLB2_ENGINES_BUSY
|
||||
Short-Description:TLB2 Engines Busy
|
||||
Description:
|
||||
The number of Level-2 TLB translation engines busy in a cycle
|
||||
.
|
||||
Counter:140 Name:TX_C_TEND
|
||||
Short-Description:Completed TEND instructions in constrained TX mode
|
||||
Description:
|
||||
A TEND instruction has completed in a constrained transactional-execution
|
||||
mode
|
||||
.
|
||||
Counter:141 Name:TX_NC_TEND
|
||||
Short-Description:Completed TEND instructions in non-constrained TX mode
|
||||
Description:
|
||||
A TEND instruction has completed in a non-constrained
|
||||
transactional-execution mode
|
||||
.
|
||||
Counter:143 Name:L1C_TLB2_MISSES
|
||||
Short-Description:L1C TLB2 Misses
|
||||
Description:
|
||||
Increments by one for any cycle where a level-1 cache or level-2 TLB miss
|
||||
is in progress
|
||||
.
|
||||
Counter:144 Name:L1D_ONCHIP_L3_SOURCED_WRITES
|
||||
Short-Description:L1D On-Chip L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an On-Chip Level-3 cache without intervention
|
||||
.
|
||||
Counter:145 Name:L1D_ONCHIP_MEMORY_SOURCED_WRITES
|
||||
Short-Description:L1D On-Chip Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from On-Chip memory
|
||||
.
|
||||
Counter:146 Name:L1D_ONCHIP_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1D On-Chip L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an On-Chip Level-3 cache with intervention
|
||||
.
|
||||
Counter:147 Name:L1D_ONCLUSTER_L3_SOURCED_WRITES
|
||||
Short-Description:L1D On-Cluster L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from On-Cluster Level-3 cache withountervention
|
||||
.
|
||||
Counter:148 Name:L1D_ONCLUSTER_MEMORY_SOURCED_WRITES
|
||||
Short-Description:L1D On-Cluster Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an On-Cluster memory
|
||||
.
|
||||
Counter:149 Name:L1D_ONCLUSTER_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1D On-Cluster L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an On-Cluster Level-3 cache with intervention
|
||||
.
|
||||
Counter:150 Name:L1D_OFFCLUSTER_L3_SOURCED_WRITES
|
||||
Short-Description:L1D Off-Cluster L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an Off-Cluster Level-3 cache without
|
||||
intervention
|
||||
.
|
||||
Counter:151 Name:L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES
|
||||
Short-Description:L1D Off-Cluster Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from Off-Cluster memory
|
||||
.
|
||||
Counter:152 Name:L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1D Off-Cluster L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an Off-Cluster Level-3 cache with intervention
|
||||
.
|
||||
Counter:153 Name:L1D_OFFDRAWER_L3_SOURCED_WRITES
|
||||
Short-Description:L1D Off-Drawer L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an Off-Drawer Level-3 cache without
|
||||
intervention
|
||||
.
|
||||
Counter:154 Name:L1D_OFFDRAWER_MEMORY_SOURCED_WRITES
|
||||
Short-Description:L1D Off-Drawer Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from Off-Drawer memory
|
||||
.
|
||||
Counter:155 Name:L1D_OFFDRAWER_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1D Off-Drawer L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an Off-Drawer Level-3 cache with intervention
|
||||
.
|
||||
Counter:156 Name:L1D_ONDRAWER_L4_SOURCED_WRITES
|
||||
Short-Description:L1D On-Drawer L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from On-Drawer Level-4 cache
|
||||
.
|
||||
Counter:157 Name:L1D_OFFDRAWER_L4_SOURCED_WRITES
|
||||
Short-Description:L1D Off-Drawer L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from Off-Drawer Level-4 cache
|
||||
.
|
||||
Counter:158 Name:L1D_ONCHIP_L3_SOURCED_WRITES_RO
|
||||
Short-Description:L1D On-Chip L3 Sourced Writes read-only
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from On-Chip L3 but a read-only invalidate was
|
||||
done to remove other copies of the cache line
|
||||
.
|
||||
Counter:162 Name:L1I_ONCHIP_L3_SOURCED_WRITES
|
||||
Short-Description:L1I On-Chip L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache ine was sourced from an On-Chip Level-3 cache without
|
||||
intervention
|
||||
.
|
||||
Counter:163 Name:L1I_ONCHIP_MEMORY_SOURCED_WRITES
|
||||
Short-Description:L1I On-Chip Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache ine was sourced from On-Chip memory
|
||||
.
|
||||
Counter:164 Name:L1I_ONCHIP_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1I On-Chip L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache ine was sourced from an On-Chip Level-3 cache with
|
||||
intervention
|
||||
.
|
||||
Counter:165 Name:L1I_ONCLUSTER_L3_SOURCED_WRITES
|
||||
Short-Description:L1I On-Cluster L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an On-Cluster Level-3 cache without
|
||||
intervention
|
||||
.
|
||||
Counter:166 Name:L1I_ONCLUSTER_MEMORY_SOURCED_WRITES
|
||||
Short-Description:L1I On-Cluster Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an On-Cluster memory
|
||||
.
|
||||
Counter:167 Name:L1I_ONCLUSTER_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1I On-Cluster L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from On-Cluster Level-3 cache with
|
||||
intervention
|
||||
.
|
||||
Counter:168 Name:L1I_OFFCLUSTER_L3_SOURCED_WRITES
|
||||
Short-Description:L1I Off-Cluster L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an Off-Cluster Level-3 cache without
|
||||
intervention
|
||||
.
|
||||
Counter:169 Name:L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES
|
||||
Short-Description:L1I Off-Cluster Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from Off-Cluster memory
|
||||
.
|
||||
Counter:170 Name:L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1I Off-Cluster L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an Off-Cluster Level-3 cache with
|
||||
intervention
|
||||
.
|
||||
Counter:171 Name:L1I_OFFDRAWER_L3_SOURCED_WRITES
|
||||
Short-Description:L1I Off-Drawer L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an Off-Drawer Level-3 cache without
|
||||
intervention
|
||||
.
|
||||
Counter:172 Name:L1I_OFFDRAWER_MEMORY_SOURCED_WRITES
|
||||
Short-Description:L1I Off-Drawer Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from Off-Drawer memory
|
||||
.
|
||||
Counter:173 Name:L1I_OFFDRAWER_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1I Off-Drawer L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an Off-Drawer Level-3 cache with
|
||||
intervention
|
||||
.
|
||||
Counter:174 Name:L1I_ONDRAWER_L4_SOURCED_WRITES
|
||||
Short-Description:L1I On-Drawer L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from On-Drawer Level-4 cache
|
||||
.
|
||||
Counter:175 Name:L1I_OFFDRAWER_L4_SOURCED_WRITES
|
||||
Short-Description:L1I Off-Drawer L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from Off-Drawer Level-4 cache
|
||||
.
|
||||
Counter:224 Name:BCD_DFP_EXECUTION_SLOTS
|
||||
Short-Description:BCD DFP Execution Slots
|
||||
Description:
|
||||
Count of floating point execution slots used for finished Binary Coded
|
||||
Decimal to Decimal Floating Point conversions. Instructions: CDZT,
|
||||
CXZT, CZDT, CZXT
|
||||
.
|
||||
Counter:225 Name:VX_BCD_EXECUTION_SLOTS
|
||||
Short-Description:VX BCD Execution Slots
|
||||
Description:
|
||||
Count of floating point execution slots used for finished vector arithmetic
|
||||
Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP,
|
||||
VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG
|
||||
.
|
||||
Counter:226 Name:DECIMAL_INSTRUCTIONS
|
||||
Short-Description:Decimal Instructions
|
||||
Description:
|
||||
Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED,
|
||||
EDMK, MP, SRP, SP, ZAP
|
||||
.
|
||||
Counter:232 Name:LAST_HOST_TRANSLATIONS
|
||||
Short-Description:Last host translation done
|
||||
Description:
|
||||
Last Host Translation done
|
||||
.
|
||||
Counter:243 Name:TX_NC_TABORT
|
||||
Short-Description:Aborted transactions in non-constrained TX mode
|
||||
Description:
|
||||
A transaction abort has occurred in a non-constrained
|
||||
transactional-execution mode
|
||||
.
|
||||
Counter:244 Name:TX_C_TABORT_NO_SPECIAL
|
||||
Short-Description:Aborted transactions in constrained TX mode not using special completion logic
|
||||
Description:
|
||||
A transaction abort has occurred in a constrained transactional-execution
|
||||
mode and the CPU is not using any special logic to allow the transaction
|
||||
to complete
|
||||
.
|
||||
Counter:245 Name:TX_C_TABORT_SPECIAL
|
||||
Short-Description:Aborted transactions in constrained TX mode using special completion logic
|
||||
Description:
|
||||
A transaction abort has occurred in a constrained transactional-execution
|
||||
mode and the CPU is using special logic to allow the transaction to
|
||||
complete
|
||||
.
|
||||
Counter:247 Name:DFLT_ACCESS
|
||||
Short-Description:Cycles CPU spent obtaining access to Deflate unit
|
||||
Description:
|
||||
Cycles CPU spent obtaining access to Deflate unit
|
||||
.
|
||||
Counter:252 Name:DFLT_CYCLES
|
||||
Short-Description:Cycles CPU is using Deflate unit
|
||||
Description:
|
||||
Cycles CPU is using Deflate unit
|
||||
.
|
||||
Counter:264 Name:DFLT_CC
|
||||
Short-Description:Increments by one for every DEFLATE CONVERSION CALL instruction executed
|
||||
Description:
|
||||
Increments by one for every DEFLATE CONVERSION CALL instruction executed
|
||||
.
|
||||
Counter:265 Name:DFLT_CCERROR
|
||||
Short-Description:Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2
|
||||
Description:
|
||||
Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2
|
||||
.
|
||||
#
|
||||
# MT-diagnostic counter set
|
||||
# ---------------------------------------------------------------------
|
||||
Counter:448 Name:MT_DIAG_CYCLES_ONE_THR_ACTIVE
|
||||
Short-Description:Cycle count with one thread active
|
||||
Description:
|
||||
Cycle count with one thread active
|
||||
.
|
||||
Counter:449 Name:MT_DIAG_CYCLES_TWO_THR_ACTIVE
|
||||
Short-Description:Cycle count with two threads active
|
||||
Description:
|
||||
Cycle count with two threads active
|
||||
.
|
||||
@@ -1,146 +0,0 @@
|
||||
Counter: 128 Name:L1D_L2_SOURCED_WRITES
|
||||
Short-Description:L1D L2 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 D-Cache directory where the returned
|
||||
cache line was sourced from the Level-2 cache
|
||||
.
|
||||
Counter: 129 Name:L1I_L2_SOURCED_WRITES
|
||||
Short-Description:L1I L2 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 I-Cache directory where the returned
|
||||
cache line was sourced from the Level-2 cache
|
||||
.
|
||||
Counter: 130 Name:DTLB1_MISSES
|
||||
Short-Description:DTLB1 Misses
|
||||
Description:
|
||||
Level-1 Data TLB miss in progress. Incremented by one for every cycle
|
||||
a DTLB1 miss is in progress.
|
||||
.
|
||||
Counter: 131 Name:ITLB1_MISSES
|
||||
Short-Description:ITLB1 Misses
|
||||
Description:
|
||||
Level-1 Instruction TLB miss in progress. Incremented by one for every
|
||||
cycle a ITLB1 miss is in progress.
|
||||
.
|
||||
Counter: 133 Name:L2C_STORES_SENT
|
||||
Short-Description:L2C Stores Sent
|
||||
Description:
|
||||
Incremented by one for every store sent to Level-2 cache
|
||||
.
|
||||
Counter: 134 Name:L1D_OFFBOOK_L3_SOURCED_WRITES
|
||||
Short-Description:L1D Off-Book L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 D-Cache directory where the returned
|
||||
cache line was sourced from an Off Book Level-3 cache
|
||||
.
|
||||
Counter: 135 Name:L1D_ONBOOK_L4_SOURCED_WRITES
|
||||
Short-Description:L1D On-Book L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 D-Cache directory where the returned
|
||||
cache line was sourced from an On Book Level-4 cache
|
||||
.
|
||||
Counter: 136 Name:L1I_ONBOOK_L4_SOURCED_WRITES
|
||||
Short-Description:L1I On-Book L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 I-Cache directory where the returned
|
||||
cache line was sourced from an On Book Level-4 cache
|
||||
.
|
||||
Counter: 137 Name:L1D_RO_EXCL_WRITES
|
||||
Short-Description:L1D Read-only Exclusive Writes
|
||||
Description:
|
||||
A directory write to the Level-1 D-Cache where the line was originally
|
||||
in a Read-Only state in the cache but has been updated to be in the
|
||||
Exclusive state that allows stores to the cache line
|
||||
.
|
||||
Counter: 138 Name:L1D_OFFBOOK_L4_SOURCED_WRITES
|
||||
Short-Description:L1D Off-Book L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 D-Cache directory where the returned
|
||||
cache line was sourced from an Off Book Level-4 cache
|
||||
.
|
||||
Counter: 139 Name:L1I_OFFBOOK_L4_SOURCED_WRITES
|
||||
Short-Description:L1I Off-Book L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 I-Cache directory where the returned
|
||||
cache line was sourced from an Off Book Level-4 cache
|
||||
.
|
||||
Counter: 140 Name:DTLB1_HPAGE_WRITES
|
||||
Short-Description:DTLB1 One-Megabyte Page Writes
|
||||
Description:
|
||||
A translation entry has been written to the Level-1 Data Translation
|
||||
Lookaside Buffer for a one-megabyte page
|
||||
.
|
||||
Counter: 141 Name:L1D_LMEM_SOURCED_WRITES
|
||||
Short-Description:L1D Local Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 D-Cache where the installed cache line
|
||||
was sourced from memory that is attached to the same book as the Data
|
||||
cache (Local Memory)
|
||||
.
|
||||
Counter: 142 Name:L1I_LMEM_SOURCED_WRITES
|
||||
Short-Description:L1I Local Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 I-Cache where the installed cache
|
||||
line was sourced from memory that is attached to the same book as the
|
||||
Instruction cache (Local Memory)
|
||||
.
|
||||
Counter: 143 Name:L1I_OFFBOOK_L3_SOURCED_WRITES
|
||||
Short-Description:L1I Off-Book L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 I-Cache directory where the returned
|
||||
cache line was sourced from an Off Book Level-3 cache
|
||||
.
|
||||
Counter: 144 Name:DTLB1_WRITES
|
||||
Short-Description:DTLB1 Writes
|
||||
Description:
|
||||
A translation entry has been written to the Level-1 Data Translation
|
||||
Lookaside Buffer
|
||||
.
|
||||
Counter: 145 Name:ITLB1_WRITES
|
||||
Short-Description:ITLB1 Writes
|
||||
Description:
|
||||
A translation entry has been written to the Level-1 Instruction
|
||||
Translation Lookaside Buffer
|
||||
.
|
||||
Counter: 146 Name:TLB2_PTE_WRITES
|
||||
Short-Description:TLB2 PTE Writes
|
||||
Description:
|
||||
A translation entry has been written to the Level-2 TLB Page Table
|
||||
Entry arrays
|
||||
.
|
||||
Counter: 147 Name:TLB2_CRSTE_HPAGE_WRITES
|
||||
Short-Description:TLB2 CRSTE One-Megabyte Page Writes
|
||||
Description:
|
||||
A translation entry has been written to the Level-2 TLB Common Region
|
||||
Segment Table Entry arrays for a one-megabyte large page translation
|
||||
.
|
||||
Counter: 148 Name:TLB2_CRSTE_WRITES
|
||||
Short-Description:TLB2 CRSTE Writes
|
||||
Description:
|
||||
A translation entry has been written to the Level-2 TLB Common Region
|
||||
Segment Table Entry arrays
|
||||
.
|
||||
Counter: 150 Name:L1D_ONCHIP_L3_SOURCED_WRITES
|
||||
Short-Description:L1D On-Chip L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 D-Cache directory where the returned
|
||||
cache line was sourced from an On Chip Level-3 cache
|
||||
.
|
||||
Counter: 152 Name:L1D_OFFCHIP_L3_SOURCED_WRITES
|
||||
Short-Description:L1D Off-Chip L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 D-Cache directory where the returned
|
||||
cache line was sourced from an Off Chip/On Book Level-3 cache
|
||||
.
|
||||
Counter: 153 Name:L1I_ONCHIP_L3_SOURCED_WRITES
|
||||
Short-Description:L1I On-Chip L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 I-Cache directory where the returned
|
||||
cache line was sourced from an On Chip Level-3 cache
|
||||
.
|
||||
Counter: 155 Name:L1I_OFFCHIP_L3_SOURCED_WRITES
|
||||
Short-Description:L1I Off-Chip L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 I-Cache directory where the returned
|
||||
cache line was sourced from an Off Chip/On Book Level-3 cache
|
||||
.
|
||||
@@ -1,230 +0,0 @@
|
||||
Counter: 128 Name:DTLB1_MISSES
|
||||
Short-Description:DTLB1 Misses
|
||||
Description:
|
||||
Level-1 Data TLB miss in progress. Incremented by one for every cycle
|
||||
a DTLB1 miss is in progress.
|
||||
.
|
||||
Counter:129 Name:ITLB1_MISSES
|
||||
Short-Description:ITLB1 Misses
|
||||
Description:
|
||||
Level-1 Instruction TLB miss in progress. Incremented by one for every
|
||||
cycle a ITLB1 miss is in progress.
|
||||
.
|
||||
Counter:130 Name:L1D_L2I_SOURCED_WRITES
|
||||
Short-Description:L1D L2I Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from the Level-2 Instruction cache
|
||||
.
|
||||
Counter:131 Name:L1I_L2I_SOURCED_WRITES
|
||||
Short-Description:L1I L2I Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from the Level-2 Instruction cache
|
||||
.
|
||||
Counter:132 Name:L1D_L2D_SOURCED_WRITES
|
||||
Short-Description:L1D L2D Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from the Level-2 Data cache
|
||||
.
|
||||
Counter:133 Name:DTLB1_WRITES
|
||||
Short-Description:DTLB1 Writes
|
||||
Description:
|
||||
A translation entry has been written to the Level-1 Data Translation
|
||||
Lookaside Buffer
|
||||
.
|
||||
Counter:135 Name:L1D_LMEM_SOURCED_WRITES
|
||||
Short-Description:L1D Local Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache where the installed cache line
|
||||
was sourced from memory that is attached to the same book as the Data
|
||||
cache (Local Memory)
|
||||
.
|
||||
Counter:137 Name:L1I_LMEM_SOURCED_WRITES
|
||||
Short-Description:L1I Local Memory Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache where the installed cache
|
||||
line was sourced from memory that is attached to the same book as the
|
||||
Instruction cache (Local Memory)
|
||||
.
|
||||
Counter:138 Name:L1D_RO_EXCL_WRITES
|
||||
Short-Description:L1D Read-only Exclusive Writes
|
||||
Description:
|
||||
A directory write to the Level-1 D-Cache where the line was originally
|
||||
in a Read-Only state in the cache but has been updated to be in the
|
||||
Exclusive state that allows stores to the cache line
|
||||
.
|
||||
Counter:139 Name:DTLB1_HPAGE_WRITES
|
||||
Short-Description:DTLB1 One-Megabyte Page Writes
|
||||
Description:
|
||||
A translation entry has been written to the Level-1 Data Translation
|
||||
Lookaside Buffer for a one-megabyte page
|
||||
.
|
||||
Counter:140 Name:ITLB1_WRITES
|
||||
Short-Description:ITLB1 Writes
|
||||
Description:
|
||||
A translation entry has been written to the Level-1 Instruction
|
||||
Translation Lookaside Buffer
|
||||
.
|
||||
Counter:141 Name:TLB2_PTE_WRITES
|
||||
Short-Description:TLB2 PTE Writes
|
||||
Description:
|
||||
A translation entry has been written to the Level-2 TLB Page Table
|
||||
Entry arrays
|
||||
.
|
||||
Counter:142 Name:TLB2_CRSTE_HPAGE_WRITES
|
||||
Short-Description:TLB2 CRSTE One-Megabyte Page Writes
|
||||
Description:
|
||||
A translation entry has been written to the Level-2 TLB Common Region
|
||||
Segment Table Entry arrays for a one-megabyte large page translation
|
||||
.
|
||||
Counter:143 Name:TLB2_CRSTE_WRITES
|
||||
Short-Description:TLB2 CRSTE Writes
|
||||
Description:
|
||||
A translation entry has been written to the Level-2 TLB Common Region
|
||||
Segment Table Entry arrays
|
||||
.
|
||||
Counter:144 Name:L1D_ONCHIP_L3_SOURCED_WRITES
|
||||
Short-Description:L1D On-Chip L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an On Chip Level-3 cache without intervention
|
||||
.
|
||||
Counter:145 Name:L1D_OFFCHIP_L3_SOURCED_WRITES
|
||||
Short-Description:L1D Off-Chip L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an Off Chip/On Book Level-3 cache without
|
||||
intervention
|
||||
.
|
||||
Counter:146 Name:L1D_OFFBOOK_L3_SOURCED_WRITES
|
||||
Short-Description:L1D Off-Book L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an Off Book Level-3 cache without intervention
|
||||
.
|
||||
Counter:147 Name:L1D_ONBOOK_L4_SOURCED_WRITES
|
||||
Short-Description:L1D On-Book L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an On Book Level-4 cache
|
||||
.
|
||||
Counter:148 Name:L1D_OFFBOOK_L4_SOURCED_WRITES
|
||||
Short-Description:L1D Off-Book L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an Off Book Level-4 cache
|
||||
.
|
||||
#
|
||||
# Notes for the transactional-execution mode notations:
|
||||
# TX .. transactional-execution mode
|
||||
# NC .. nonconstrained
|
||||
# C .. constrained
|
||||
#
|
||||
Counter:149 Name:TX_NC_TEND
|
||||
Short-Description:Completed TEND instructions in non-constrained TX mode
|
||||
Description:
|
||||
A TEND instruction has completed in a nonconstrained
|
||||
transactional-execution mode
|
||||
.
|
||||
Counter:150 Name:L1D_ONCHIP_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1D On-Chip L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from a On Chip Level-3 cache with intervention
|
||||
.
|
||||
Counter:151 Name:L1D_OFFCHIP_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1D Off-Chip L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an Off Chip/On Book Level-3 cache with
|
||||
intervention
|
||||
.
|
||||
# XXX Remove SOURCED from L1D_OFFBOOK_L3_SOURCED_WRITES...
|
||||
Counter:152 Name:L1D_OFFBOOK_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1D Off-Book L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Data cache directory where the returned
|
||||
cache line was sourced from an Off Book Level-3 cache with intervention
|
||||
.
|
||||
Counter:153 Name:L1I_ONCHIP_L3_SOURCED_WRITES
|
||||
Short-Description:L1I On-Chip L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an On Chip Level-3 cache without
|
||||
intervention
|
||||
.
|
||||
Counter:154 Name:L1I_OFFCHIP_L3_SOURCED_WRITES
|
||||
Short-Description:L1I Off-Chip L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an Off Chip/On Book Level-3 cache
|
||||
without intervention
|
||||
.
|
||||
Counter:155 Name:L1I_OFFBOOK_L3_SOURCED_WRITES
|
||||
Short-Description:L1I Off-Book L3 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an Off Book Level-3 cache without
|
||||
intervention
|
||||
.
|
||||
Counter:156 Name:L1I_ONBOOK_L4_SOURCED_WRITES
|
||||
Short-Description:L1I On-Book L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an On Book Level-4 cache
|
||||
.
|
||||
Counter:157 Name:L1I_OFFBOOK_L4_SOURCED_WRITES
|
||||
Short-Description:L1I Off-Book L4 Sourced Writes
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an Off Book Level-4 cache
|
||||
.
|
||||
Counter:158 Name:TX_C_TEND
|
||||
Short-Description:Completed TEND instructions in constrained TX mode
|
||||
Description:
|
||||
A TEND instruction has completed in a constrained transactional-execution
|
||||
mode
|
||||
.
|
||||
Counter:159 Name:L1I_ONCHIP_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1I On-Chip L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an On Chip Level-3 cache with
|
||||
intervention
|
||||
.
|
||||
Counter:160 Name:L1I_OFFCHIP_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1I Off-Chip L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an Off Chip/On Book Level-3 cache
|
||||
with intervention
|
||||
.
|
||||
Counter:161 Name:L1I_OFFBOOK_L3_SOURCED_WRITES_IV
|
||||
Short-Description:L1I Off-Book L3 Sourced Writes with Intervention
|
||||
Description:
|
||||
A directory write to the Level-1 Instruction cache directory where the
|
||||
returned cache line was sourced from an Off Book Level-3 cache with
|
||||
intervention
|
||||
.
|
||||
Counter:177 Name:TX_NC_TABORT
|
||||
Short-Description:Aborted transactions in non-constrained TX mode
|
||||
Description:
|
||||
A transaction abort has occurred in a nonconstrained
|
||||
transactional-execution mode
|
||||
.
|
||||
Counter:178 Name:TX_C_TABORT_NO_SPECIAL
|
||||
Short-Description:Aborted transactions in constrained TX mode not using special completion logic
|
||||
Description:
|
||||
A transaction abort has occurred in a constrained transactional-execution
|
||||
mode and the CPU is not using any special logic to allow the transaction
|
||||
to complete
|
||||
.
|
||||
Counter:179 Name:TX_C_TABORT_SPECIAL
|
||||
Short-Description:Aborted transactions in constrained TX mode using special completion logic
|
||||
Description:
|
||||
A transaction abort has occurred in a constrained transactional-execution
|
||||
mode and the CPU is using special logic to allow the transaction to
|
||||
complete
|
||||
.
|
||||
@@ -1,33 +0,0 @@
|
||||
# CPU-measurement facilities
|
||||
#
|
||||
# Mapping of:
|
||||
# 1. CPU-MF counter first/second version numbers to "generic" counter
|
||||
# definitions
|
||||
# 2. IBM z Systems hardware to respective extended counter set definitions
|
||||
#
|
||||
#
|
||||
{
|
||||
# Definition # File name
|
||||
|
||||
# CFVN
|
||||
'cfvn-1' => 'cpum-cf-cfvn-1.ctr',
|
||||
'cfvn-3' => 'cpum-cf-cfvn-3.ctr',
|
||||
|
||||
# CSVN
|
||||
'csvn-12345' => 'cpum-cf-csvn-12345.ctr',
|
||||
'csvn-6' => 'cpum-cf-csvn-6.ctr',
|
||||
|
||||
# Extended counters
|
||||
2097 => 'cpum-cf-extended-z10.ctr',
|
||||
2098 => 'cpum-cf-extended-z10.ctr',
|
||||
2817 => 'cpum-cf-extended-z196.ctr',
|
||||
2818 => 'cpum-cf-extended-z196.ctr',
|
||||
2827 => 'cpum-cf-extended-zEC12.ctr',
|
||||
2828 => 'cpum-cf-extended-zEC12.ctr',
|
||||
2964 => 'cpum-cf-extended-z13.ctr',
|
||||
2965 => 'cpum-cf-extended-z13.ctr',
|
||||
3906 => 'cpum-cf-extended-z14.ctr',
|
||||
3907 => 'cpum-cf-extended-z14.ctr',
|
||||
8561 => 'cpum-cf-extended-z15.ctr',
|
||||
8562 => 'cpum-cf-extended-z15.ctr',
|
||||
};
|
||||
@@ -1,15 +0,0 @@
|
||||
# Perf raw event counter definitions for the
|
||||
# CPU-measurment sampling facility
|
||||
#
|
||||
# Basic-sampling mode
|
||||
Counter: 0xB0000 Name:SF_CYCLES_BASIC
|
||||
Short-Description:Sample CPU Cycles Using Basic-sampling Mode
|
||||
Description:
|
||||
Sample CPU cycles using basic-sampling mode
|
||||
.
|
||||
# Diagnostic-sampling mode (includes basic-sampling)
|
||||
Counter: 0xBD000 Name:SF_CYCLES_BASIC_DIAG
|
||||
Short-Description:Sample CPU Cycle Using Diagnostic-sampling Mode (not for ordinary use)
|
||||
Description:
|
||||
Sample CPU cycle using diagnostic-sampling mode (not for ordinary use)
|
||||
.
|
||||
23
cpumf/defines.h
Normal file
23
cpumf/defines.h
Normal file
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Defines for CPU Measurement Facility Characteristics
|
||||
*
|
||||
* Copyright IBM Corp. 2020
|
||||
*
|
||||
* s390-tools is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the MIT license. See LICENSE for details.
|
||||
*/
|
||||
|
||||
#ifndef DEFINES_H
|
||||
#define DEFINES_H
|
||||
|
||||
#define PERF_SFB_SIZE "/sys/module/kernel/parameters/cpum_sfb_size"
|
||||
#define PERF_PATH "/sys/bus/event_source/devices/"
|
||||
#define PERF_SF "cpum_sf"
|
||||
#define PERF_CF "cpum_cf"
|
||||
|
||||
static inline void linux_error(const char *message)
|
||||
{
|
||||
fprintf(stderr, "Error: %s: %s\n", message, strerror(errno));
|
||||
}
|
||||
|
||||
#endif
|
||||
3095
cpumf/lscpumf.c
Normal file
3095
cpumf/lscpumf.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -1,11 +1,11 @@
|
||||
\" lscpumf.1
|
||||
.\"
|
||||
.\"
|
||||
.\" Copyright IBM Corp. 2014, 2017
|
||||
.\" Copyright IBM Corp. 2014, 2020
|
||||
.\" s390-tools is free software; you can redistribute it and/or modify
|
||||
.\" it under the terms of the MIT license. See LICENSE for details.
|
||||
.\" ----------------------------------------------------------------------
|
||||
.TH lscpumf "1" "February 2014" "s390-tools" "CPU-MF management programs"
|
||||
.TH lscpumf "1" "May 2020" "s390-tools" "CPU-MF management programs"
|
||||
.
|
||||
.ds c \fBlscpumf\fP
|
||||
.
|
||||
@@ -19,8 +19,8 @@ lscpumf \- display information about CPU-measurement facilities
|
||||
.RB [ \-i | \-\-info ]
|
||||
.br
|
||||
.B lscpumf
|
||||
.RB [ \-c | \-\-list\-counters ]
|
||||
.RB [ \-C | \-\-list\-all\-counters ]
|
||||
.RB [ \-c | \-\-list\-counters ] [ \-n ]
|
||||
.RB [ \-C | \-\-list\-all\-counters ] [ \-n ]
|
||||
.RB [ \-s | \-\-list\-sampling\-events ]
|
||||
.br
|
||||
.B lscpumf
|
||||
@@ -46,12 +46,25 @@ facilities.
|
||||
Lists counters that are provided by the CPU-measurement facility, omitting
|
||||
counters for which the LPAR is not authorized. For counter measurements with
|
||||
the perf program, the raw event identifier is displayed.
|
||||
For linux version 5.5 and later the raw event identifier is
|
||||
displayed as <type>:<number>, where type is the number the CPU Measurement
|
||||
counter facility device driver was assigned to by the kernel.
|
||||
For earlier linux versions the raw event identifier is displayed as r<number>.
|
||||
.
|
||||
.TP
|
||||
.BR \-C ", " \-\-list\-all\-counters
|
||||
Lists all counters that are provided by the CPU-measurement counter facility,
|
||||
regardless of LPAR authorization. To list only those counters for which the
|
||||
LPAR is authorized, use the -c option.
|
||||
For linux version 5.5 and later the raw event identifier is
|
||||
displayed as <type>:<number>, where type is the number the CPU Measurement
|
||||
counter facility device driver was assigned to by the kernel.
|
||||
For earlier linux versions the raw event identifier is displayed as r<number>.
|
||||
.
|
||||
.TP
|
||||
.BR \-n ", " \-\-name
|
||||
.
|
||||
Display the counter name together with the raw event identifier.
|
||||
.
|
||||
.TP
|
||||
.BR \-s ", " \-\-list\-sampling\-events
|
||||
|
||||
Reference in New Issue
Block a user